1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef OTX2_COMMON_H 12 #define OTX2_COMMON_H 13 14 #include <linux/ethtool.h> 15 #include <linux/pci.h> 16 #include <linux/iommu.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/timecounter.h> 20 #include <linux/soc/marvell/octeontx2/asm.h> 21 #include <net/pkt_cls.h> 22 23 #include <mbox.h> 24 #include <npc.h> 25 #include "otx2_reg.h" 26 #include "otx2_txrx.h" 27 #include <rvu_trace.h> 28 29 /* PCI device IDs */ 30 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 31 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 32 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 33 34 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 35 36 /* PCI BAR nos */ 37 #define PCI_CFG_REG_BAR_NUM 2 38 #define PCI_MBOX_BAR_NUM 4 39 40 #define NAME_SIZE 32 41 42 enum arua_mapped_qtypes { 43 AURA_NIX_RQ, 44 AURA_NIX_SQ, 45 }; 46 47 /* NIX LF interrupts range*/ 48 #define NIX_LF_QINT_VEC_START 0x00 49 #define NIX_LF_CINT_VEC_START 0x40 50 #define NIX_LF_GINT_VEC 0x80 51 #define NIX_LF_ERR_VEC 0x81 52 #define NIX_LF_POISON_VEC 0x82 53 54 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 55 #define SEND_CQ_SKID 2000 56 57 /* RSS configuration */ 58 struct otx2_rss_ctx { 59 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 60 }; 61 62 struct otx2_rss_info { 63 u8 enable; 64 u32 flowkey_cfg; 65 u16 rss_size; 66 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 67 u8 key[RSS_HASH_KEY_SIZE]; 68 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 69 }; 70 71 /* NIX (or NPC) RX errors */ 72 enum otx2_errlvl { 73 NPC_ERRLVL_RE, 74 NPC_ERRLVL_LID_LA, 75 NPC_ERRLVL_LID_LB, 76 NPC_ERRLVL_LID_LC, 77 NPC_ERRLVL_LID_LD, 78 NPC_ERRLVL_LID_LE, 79 NPC_ERRLVL_LID_LF, 80 NPC_ERRLVL_LID_LG, 81 NPC_ERRLVL_LID_LH, 82 NPC_ERRLVL_NIX = 0x0F, 83 }; 84 85 enum otx2_errcodes_re { 86 /* NPC_ERRLVL_RE errcodes */ 87 ERRCODE_FCS = 0x7, 88 ERRCODE_FCS_RCV = 0x8, 89 ERRCODE_UNDERSIZE = 0x10, 90 ERRCODE_OVERSIZE = 0x11, 91 ERRCODE_OL2_LEN_MISMATCH = 0x12, 92 /* NPC_ERRLVL_NIX errcodes */ 93 ERRCODE_OL3_LEN = 0x10, 94 ERRCODE_OL4_LEN = 0x11, 95 ERRCODE_OL4_CSUM = 0x12, 96 ERRCODE_IL3_LEN = 0x20, 97 ERRCODE_IL4_LEN = 0x21, 98 ERRCODE_IL4_CSUM = 0x22, 99 }; 100 101 /* NIX TX stats */ 102 enum nix_stat_lf_tx { 103 TX_UCAST = 0x0, 104 TX_BCAST = 0x1, 105 TX_MCAST = 0x2, 106 TX_DROP = 0x3, 107 TX_OCTS = 0x4, 108 TX_STATS_ENUM_LAST, 109 }; 110 111 /* NIX RX stats */ 112 enum nix_stat_lf_rx { 113 RX_OCTS = 0x0, 114 RX_UCAST = 0x1, 115 RX_BCAST = 0x2, 116 RX_MCAST = 0x3, 117 RX_DROP = 0x4, 118 RX_DROP_OCTS = 0x5, 119 RX_FCS = 0x6, 120 RX_ERR = 0x7, 121 RX_DRP_BCAST = 0x8, 122 RX_DRP_MCAST = 0x9, 123 RX_DRP_L3BCAST = 0xa, 124 RX_DRP_L3MCAST = 0xb, 125 RX_STATS_ENUM_LAST, 126 }; 127 128 struct otx2_dev_stats { 129 u64 rx_bytes; 130 u64 rx_frames; 131 u64 rx_ucast_frames; 132 u64 rx_bcast_frames; 133 u64 rx_mcast_frames; 134 u64 rx_drops; 135 136 u64 tx_bytes; 137 u64 tx_frames; 138 u64 tx_ucast_frames; 139 u64 tx_bcast_frames; 140 u64 tx_mcast_frames; 141 u64 tx_drops; 142 }; 143 144 /* Driver counted stats */ 145 struct otx2_drv_stats { 146 atomic_t rx_fcs_errs; 147 atomic_t rx_oversize_errs; 148 atomic_t rx_undersize_errs; 149 atomic_t rx_csum_errs; 150 atomic_t rx_len_errs; 151 atomic_t rx_other_errs; 152 }; 153 154 struct mbox { 155 struct otx2_mbox mbox; 156 struct work_struct mbox_wrk; 157 struct otx2_mbox mbox_up; 158 struct work_struct mbox_up_wrk; 159 struct otx2_nic *pfvf; 160 void *bbuf_base; /* Bounce buffer for mbox memory */ 161 struct mutex lock; /* serialize mailbox access */ 162 int num_msgs; /* mbox number of messages */ 163 int up_num_msgs; /* mbox_up number of messages */ 164 }; 165 166 struct otx2_hw { 167 struct pci_dev *pdev; 168 struct otx2_rss_info rss_info; 169 u16 rx_queues; 170 u16 tx_queues; 171 u16 max_queues; 172 u16 pool_cnt; 173 u16 rqpool_cnt; 174 u16 sqpool_cnt; 175 176 /* NPA */ 177 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 178 u32 stack_pg_bytes; /* Size of stack page */ 179 u16 sqb_size; 180 181 /* NIX */ 182 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 183 u16 matchall_ipolicer; 184 185 /* HW settings, coalescing etc */ 186 u16 rx_chan_base; 187 u16 tx_chan_base; 188 u16 cq_qcount_wait; 189 u16 cq_ecount_wait; 190 u16 rq_skid; 191 u8 cq_time_wait; 192 193 /* Segmentation */ 194 u8 lso_tsov4_idx; 195 u8 lso_tsov6_idx; 196 u8 lso_udpv4_idx; 197 u8 lso_udpv6_idx; 198 199 /* MSI-X */ 200 u8 cint_cnt; /* CQ interrupt count */ 201 u16 npa_msixoff; /* Offset of NPA vectors */ 202 u16 nix_msixoff; /* Offset of NIX vectors */ 203 char *irq_name; 204 cpumask_var_t *affinity_mask; 205 206 /* Stats */ 207 struct otx2_dev_stats dev_stats; 208 struct otx2_drv_stats drv_stats; 209 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 210 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 211 u64 cgx_fec_corr_blks; 212 u64 cgx_fec_uncorr_blks; 213 u8 cgx_links; /* No. of CGX links present in HW */ 214 u8 lbk_links; /* No. of LBK links present in HW */ 215 #define HW_TSO 0 216 #define CN10K_MBOX 1 217 #define CN10K_LMTST 2 218 unsigned long cap_flag; 219 220 #define LMT_LINE_SIZE 128 221 #define NIX_LMTID_BASE 72 /* RX + TX + XDP */ 222 void __iomem *lmt_base; 223 u64 *npa_lmt_base; 224 u64 *nix_lmt_base; 225 }; 226 227 enum vfperm { 228 OTX2_RESET_VF_PERM, 229 OTX2_TRUSTED_VF, 230 }; 231 232 struct otx2_vf_config { 233 struct otx2_nic *pf; 234 struct delayed_work link_event_work; 235 bool intf_down; /* interface was either configured or not */ 236 u8 mac[ETH_ALEN]; 237 u16 vlan; 238 int tx_vtag_idx; 239 bool trusted; 240 }; 241 242 struct flr_work { 243 struct work_struct work; 244 struct otx2_nic *pf; 245 }; 246 247 struct refill_work { 248 struct delayed_work pool_refill_work; 249 struct otx2_nic *pf; 250 }; 251 252 struct otx2_ptp { 253 struct ptp_clock_info ptp_info; 254 struct ptp_clock *ptp_clock; 255 struct otx2_nic *nic; 256 257 struct cyclecounter cycle_counter; 258 struct timecounter time_counter; 259 }; 260 261 #define OTX2_HW_TIMESTAMP_LEN 8 262 263 struct otx2_mac_table { 264 u8 addr[ETH_ALEN]; 265 u16 mcam_entry; 266 bool inuse; 267 }; 268 269 struct otx2_flow_config { 270 u16 entry[NPC_MAX_NONCONTIG_ENTRIES]; 271 u16 *flow_ent; 272 u16 *def_ent; 273 u16 nr_flows; 274 #define OTX2_DEFAULT_FLOWCOUNT 16 275 #define OTX2_MAX_UNICAST_FLOWS 8 276 #define OTX2_MAX_VLAN_FLOWS 1 277 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 278 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \ 279 OTX2_MAX_UNICAST_FLOWS + \ 280 OTX2_MAX_VLAN_FLOWS) 281 u16 ntuple_offset; 282 u16 unicast_offset; 283 u16 rx_vlan_offset; 284 u16 vf_vlan_offset; 285 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 286 #define OTX2_VF_VLAN_RX_INDEX 0 287 #define OTX2_VF_VLAN_TX_INDEX 1 288 u16 tc_flower_offset; 289 u16 ntuple_max_flows; 290 u16 tc_max_flows; 291 struct list_head flow_list; 292 }; 293 294 struct otx2_tc_info { 295 /* hash table to store TC offloaded flows */ 296 struct rhashtable flow_table; 297 struct rhashtable_params flow_ht_params; 298 DECLARE_BITMAP(tc_entries_bitmap, OTX2_MAX_TC_FLOWS); 299 unsigned long num_entries; 300 }; 301 302 struct dev_hw_ops { 303 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); 304 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 305 int size, int qidx); 306 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 307 void (*aura_freeptr)(void *dev, int aura, u64 buf); 308 }; 309 310 struct otx2_nic { 311 void __iomem *reg_base; 312 struct net_device *netdev; 313 struct dev_hw_ops *hw_ops; 314 void *iommu_domain; 315 u16 max_frs; 316 u16 rbsize; /* Receive buffer size */ 317 318 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 319 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 320 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 321 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 322 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 323 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 324 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 325 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 326 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 327 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 328 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 329 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 330 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 331 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 332 u64 flags; 333 334 struct otx2_qset qset; 335 struct otx2_hw hw; 336 struct pci_dev *pdev; 337 struct device *dev; 338 339 /* Mbox */ 340 struct mbox mbox; 341 struct mbox *mbox_pfvf; 342 struct workqueue_struct *mbox_wq; 343 struct workqueue_struct *mbox_pfvf_wq; 344 345 u8 total_vfs; 346 u16 pcifunc; /* RVU PF_FUNC */ 347 u16 bpid[NIX_MAX_BPID_CHAN]; 348 struct otx2_vf_config *vf_configs; 349 struct cgx_link_user_info linfo; 350 351 u64 reset_count; 352 struct work_struct reset_task; 353 struct workqueue_struct *flr_wq; 354 struct flr_work *flr_wrk; 355 struct refill_work *refill_wrk; 356 struct workqueue_struct *otx2_wq; 357 struct work_struct rx_mode_work; 358 struct otx2_mac_table *mac_table; 359 360 /* Ethtool stuff */ 361 u32 msg_enable; 362 363 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 364 int nix_blkaddr; 365 /* LMTST Lines info */ 366 u16 tot_lmt_lines; 367 u16 nix_lmt_lines; 368 u32 nix_lmt_size; 369 370 struct otx2_ptp *ptp; 371 struct hwtstamp_config tstamp; 372 373 struct otx2_flow_config *flow_cfg; 374 struct otx2_tc_info tc_info; 375 unsigned long rq_bmap; 376 }; 377 378 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 379 { 380 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF; 381 } 382 383 static inline bool is_96xx_A0(struct pci_dev *pdev) 384 { 385 return (pdev->revision == 0x00) && 386 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 387 } 388 389 static inline bool is_96xx_B0(struct pci_dev *pdev) 390 { 391 return (pdev->revision == 0x01) && 392 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 393 } 394 395 /* REVID for PCIe devices. 396 * Bits 0..1: minor pass, bit 3..2: major pass 397 * bits 7..4: midr id 398 */ 399 #define PCI_REVISION_ID_96XX 0x00 400 #define PCI_REVISION_ID_95XX 0x10 401 #define PCI_REVISION_ID_LOKI 0x20 402 #define PCI_REVISION_ID_98XX 0x30 403 #define PCI_REVISION_ID_95XXMM 0x40 404 405 static inline bool is_dev_otx2(struct pci_dev *pdev) 406 { 407 u8 midr = pdev->revision & 0xF0; 408 409 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 410 midr == PCI_REVISION_ID_LOKI || midr == PCI_REVISION_ID_98XX || 411 midr == PCI_REVISION_ID_95XXMM); 412 } 413 414 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 415 { 416 struct otx2_hw *hw = &pfvf->hw; 417 418 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 419 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 420 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 421 422 __set_bit(HW_TSO, &hw->cap_flag); 423 424 if (is_96xx_A0(pfvf->pdev)) { 425 __clear_bit(HW_TSO, &hw->cap_flag); 426 427 /* Time based irq coalescing is not supported */ 428 pfvf->hw.cq_qcount_wait = 0x0; 429 430 /* Due to HW issue previous silicons required minimum 431 * 600 unused CQE to avoid CQ overflow. 432 */ 433 pfvf->hw.rq_skid = 600; 434 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 435 } 436 if (is_96xx_B0(pfvf->pdev)) 437 __clear_bit(HW_TSO, &hw->cap_flag); 438 439 if (!is_dev_otx2(pfvf->pdev)) { 440 __set_bit(CN10K_MBOX, &hw->cap_flag); 441 __set_bit(CN10K_LMTST, &hw->cap_flag); 442 } 443 } 444 445 /* Register read/write APIs */ 446 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 447 { 448 u64 blkaddr; 449 450 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 451 case BLKTYPE_NIX: 452 blkaddr = nic->nix_blkaddr; 453 break; 454 case BLKTYPE_NPA: 455 blkaddr = BLKADDR_NPA; 456 break; 457 default: 458 blkaddr = BLKADDR_RVUM; 459 break; 460 } 461 462 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 463 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 464 465 return nic->reg_base + offset; 466 } 467 468 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 469 { 470 void __iomem *addr = otx2_get_regaddr(nic, offset); 471 472 writeq(val, addr); 473 } 474 475 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 476 { 477 void __iomem *addr = otx2_get_regaddr(nic, offset); 478 479 return readq(addr); 480 } 481 482 /* Mbox bounce buffer APIs */ 483 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 484 { 485 struct otx2_mbox *otx2_mbox; 486 struct otx2_mbox_dev *mdev; 487 488 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 489 if (!mbox->bbuf_base) 490 return -ENOMEM; 491 492 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 493 * prepare all mbox messages in bounce buffer instead of directly 494 * in hw mbox memory. 495 */ 496 otx2_mbox = &mbox->mbox; 497 mdev = &otx2_mbox->dev[0]; 498 mdev->mbase = mbox->bbuf_base; 499 500 otx2_mbox = &mbox->mbox_up; 501 mdev = &otx2_mbox->dev[0]; 502 mdev->mbase = mbox->bbuf_base; 503 return 0; 504 } 505 506 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 507 { 508 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 509 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 510 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 511 struct mbox_hdr *hdr; 512 u64 msg_size; 513 514 if (mdev->mbase == hw_mbase) 515 return; 516 517 hdr = hw_mbase + mbox->rx_start; 518 msg_size = hdr->msg_size; 519 520 if (msg_size > mbox->rx_size - msgs_offset) 521 msg_size = mbox->rx_size - msgs_offset; 522 523 /* Copy mbox messages from mbox memory to bounce buffer */ 524 memcpy(mdev->mbase + mbox->rx_start, 525 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 526 } 527 528 /* With the absence of API for 128-bit IO memory access for arm64, 529 * implement required operations at place. 530 */ 531 #if defined(CONFIG_ARM64) 532 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 533 { 534 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 535 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 536 } 537 538 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 539 { 540 u64 result; 541 542 __asm__ volatile(".cpu generic+lse\n" 543 "ldadd %x[i], %x[r], [%[b]]" 544 : [r]"=r"(result), "+m"(*ptr) 545 : [i]"r"(incr), [b]"r"(ptr) 546 : "memory"); 547 return result; 548 } 549 550 #else 551 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 552 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 553 #endif 554 555 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 556 u64 *ptrs, u64 num_ptrs, 557 u64 *lmt_addr) 558 { 559 u64 size = 0, count_eot = 0; 560 u64 tar_addr, val = 0; 561 562 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 563 /* LMTID is same as AURA Id */ 564 val = (aura & 0x7FF) | BIT_ULL(63); 565 /* Set if [127:64] of last 128bit word has a valid pointer */ 566 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 567 /* Set AURA ID to free pointer */ 568 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 569 /* Target address for LMTST flush tells HW how many 128bit 570 * words are valid from NPA_LF_AURA_BATCH_FREE0. 571 * 572 * tar_addr[6:4] is LMTST size-1 in units of 128b. 573 */ 574 if (num_ptrs > 2) { 575 size = (sizeof(u64) * num_ptrs) / 16; 576 if (!count_eot) 577 size++; 578 tar_addr |= ((size - 1) & 0x7) << 4; 579 } 580 memcpy(lmt_addr, ptrs, sizeof(u64) * num_ptrs); 581 /* Perform LMTST flush */ 582 cn10k_lmt_flush(val, tar_addr); 583 } 584 585 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 586 { 587 struct otx2_nic *pfvf = dev; 588 struct otx2_pool *pool; 589 u64 ptrs[2]; 590 591 pool = &pfvf->qset.pool[aura]; 592 ptrs[1] = buf; 593 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2, pool->lmt_addr); 594 } 595 596 /* Alloc pointer from pool/aura */ 597 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 598 { 599 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf, 600 NPA_LF_AURA_OP_ALLOCX(0)); 601 u64 incr = (u64)aura | BIT_ULL(63); 602 603 return otx2_atomic64_add(incr, ptr); 604 } 605 606 /* Free pointer to a pool/aura */ 607 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 608 { 609 struct otx2_nic *pfvf = dev; 610 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 611 612 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 613 } 614 615 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 616 { 617 if (type == AURA_NIX_SQ) 618 return pfvf->hw.rqpool_cnt + idx; 619 620 /* AURA_NIX_RQ */ 621 return idx; 622 } 623 624 /* Mbox APIs */ 625 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 626 { 627 int err; 628 629 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 630 return 0; 631 otx2_mbox_msg_send(&mbox->mbox, 0); 632 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 633 if (err) 634 return err; 635 636 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 637 } 638 639 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 640 { 641 int err; 642 643 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 644 return 0; 645 otx2_mbox_msg_send(&mbox->mbox_up, devid); 646 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 647 if (err) 648 return err; 649 650 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 651 } 652 653 /* Use this API to send mbox msgs in atomic context 654 * where sleeping is not allowed 655 */ 656 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 657 { 658 int err; 659 660 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 661 return 0; 662 otx2_mbox_msg_send(&mbox->mbox, 0); 663 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 664 if (err) 665 return err; 666 667 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 668 } 669 670 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 671 static struct _req_type __maybe_unused \ 672 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 673 { \ 674 struct _req_type *req; \ 675 \ 676 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 677 &mbox->mbox, 0, sizeof(struct _req_type), \ 678 sizeof(struct _rsp_type)); \ 679 if (!req) \ 680 return NULL; \ 681 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 682 req->hdr.id = _id; \ 683 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 684 return req; \ 685 } 686 687 MBOX_MESSAGES 688 #undef M 689 690 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 691 int \ 692 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 693 struct _req_type *req, \ 694 struct _rsp_type *rsp); \ 695 696 MBOX_UP_CGX_MESSAGES 697 #undef M 698 699 /* Time to wait before watchdog kicks off */ 700 #define OTX2_TX_TIMEOUT (100 * HZ) 701 702 #define RVU_PFVF_PF_SHIFT 10 703 #define RVU_PFVF_PF_MASK 0x3F 704 #define RVU_PFVF_FUNC_SHIFT 0 705 #define RVU_PFVF_FUNC_MASK 0x3FF 706 707 static inline int rvu_get_pf(u16 pcifunc) 708 { 709 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 710 } 711 712 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 713 struct page *page, 714 size_t offset, size_t size, 715 enum dma_data_direction dir) 716 { 717 dma_addr_t iova; 718 719 iova = dma_map_page_attrs(pfvf->dev, page, 720 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 721 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 722 return (dma_addr_t)NULL; 723 return iova; 724 } 725 726 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 727 dma_addr_t addr, size_t size, 728 enum dma_data_direction dir) 729 { 730 dma_unmap_page_attrs(pfvf->dev, addr, size, 731 dir, DMA_ATTR_SKIP_CPU_SYNC); 732 } 733 734 /* MSI-X APIs */ 735 void otx2_free_cints(struct otx2_nic *pfvf, int n); 736 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 737 int otx2_set_mac_address(struct net_device *netdev, void *p); 738 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 739 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 740 void otx2_get_mac_from_af(struct net_device *netdev); 741 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 742 int otx2_config_pause_frm(struct otx2_nic *pfvf); 743 void otx2_setup_segmentation(struct otx2_nic *pfvf); 744 745 /* RVU block related APIs */ 746 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 747 int otx2_detach_resources(struct mbox *mbox); 748 int otx2_config_npa(struct otx2_nic *pfvf); 749 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 750 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 751 void otx2_aura_pool_free(struct otx2_nic *pfvf); 752 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 753 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 754 int otx2_config_nix(struct otx2_nic *pfvf); 755 int otx2_config_nix_queues(struct otx2_nic *pfvf); 756 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl); 757 int otx2_txsch_alloc(struct otx2_nic *pfvf); 758 int otx2_txschq_stop(struct otx2_nic *pfvf); 759 void otx2_sqb_flush(struct otx2_nic *pfvf); 760 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 761 dma_addr_t *dma); 762 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 763 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 764 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 765 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 766 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 767 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 768 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 769 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 770 dma_addr_t *dma); 771 772 /* RSS configuration APIs*/ 773 int otx2_rss_init(struct otx2_nic *pfvf); 774 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 775 void otx2_set_rss_key(struct otx2_nic *pfvf); 776 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 777 778 /* Mbox handlers */ 779 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 780 struct msix_offset_rsp *rsp); 781 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 782 struct npa_lf_alloc_rsp *rsp); 783 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 784 struct nix_lf_alloc_rsp *rsp); 785 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 786 struct nix_txsch_alloc_rsp *rsp); 787 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 788 struct cgx_stats_rsp *rsp); 789 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 790 struct cgx_fec_stats_rsp *rsp); 791 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 792 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 793 struct nix_bp_cfg_rsp *rsp); 794 795 /* Device stats APIs */ 796 void otx2_get_dev_stats(struct otx2_nic *pfvf); 797 void otx2_get_stats64(struct net_device *netdev, 798 struct rtnl_link_stats64 *stats); 799 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 800 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 801 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 802 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 803 void otx2_set_ethtool_ops(struct net_device *netdev); 804 void otx2vf_set_ethtool_ops(struct net_device *netdev); 805 806 int otx2_open(struct net_device *netdev); 807 int otx2_stop(struct net_device *netdev); 808 int otx2_set_real_num_queues(struct net_device *netdev, 809 int tx_queues, int rx_queues); 810 /* MCAM filter related APIs */ 811 int otx2_mcam_flow_init(struct otx2_nic *pf); 812 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf); 813 void otx2_mcam_flow_del(struct otx2_nic *pf); 814 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 815 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 816 int otx2_get_flow(struct otx2_nic *pfvf, 817 struct ethtool_rxnfc *nfc, u32 location); 818 int otx2_get_all_flows(struct otx2_nic *pfvf, 819 struct ethtool_rxnfc *nfc, u32 *rule_locs); 820 int otx2_add_flow(struct otx2_nic *pfvf, 821 struct ethtool_rxnfc *nfc); 822 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 823 int otx2_prepare_flow_request(struct ethtool_rx_flow_spec *fsp, 824 struct npc_install_flow_req *req); 825 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 826 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 827 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 828 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 829 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 830 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 831 /* tc support */ 832 int otx2_init_tc(struct otx2_nic *nic); 833 void otx2_shutdown_tc(struct otx2_nic *nic); 834 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 835 void *type_data); 836 #endif /* OTX2_COMMON_H */ 837