1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_COMMON_H 9 #define OTX2_COMMON_H 10 11 #include <linux/ethtool.h> 12 #include <linux/pci.h> 13 #include <linux/iommu.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/ptp_clock_kernel.h> 16 #include <linux/timecounter.h> 17 #include <linux/soc/marvell/octeontx2/asm.h> 18 #include <net/pkt_cls.h> 19 #include <net/devlink.h> 20 #include <linux/time64.h> 21 #include <linux/dim.h> 22 23 #include <mbox.h> 24 #include <npc.h> 25 #include "otx2_reg.h" 26 #include "otx2_txrx.h" 27 #include "otx2_devlink.h" 28 #include <rvu_trace.h> 29 30 /* PCI device IDs */ 31 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 32 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 33 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 34 35 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 36 37 /* PCI BAR nos */ 38 #define PCI_CFG_REG_BAR_NUM 2 39 #define PCI_MBOX_BAR_NUM 4 40 41 #define NAME_SIZE 32 42 43 #ifdef CONFIG_DCB 44 /* Max priority supported for PFC */ 45 #define NIX_PF_PFC_PRIO_MAX 8 46 #endif 47 48 enum arua_mapped_qtypes { 49 AURA_NIX_RQ, 50 AURA_NIX_SQ, 51 }; 52 53 /* NIX LF interrupts range*/ 54 #define NIX_LF_QINT_VEC_START 0x00 55 #define NIX_LF_CINT_VEC_START 0x40 56 #define NIX_LF_GINT_VEC 0x80 57 #define NIX_LF_ERR_VEC 0x81 58 #define NIX_LF_POISON_VEC 0x82 59 60 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 61 #define SEND_CQ_SKID 2000 62 63 #define OTX2_GET_RX_STATS(reg) \ 64 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 65 #define OTX2_GET_TX_STATS(reg) \ 66 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 67 68 struct otx2_lmt_info { 69 u64 lmt_addr; 70 u16 lmt_id; 71 }; 72 /* RSS configuration */ 73 struct otx2_rss_ctx { 74 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 75 }; 76 77 struct otx2_rss_info { 78 u8 enable; 79 u32 flowkey_cfg; 80 u16 rss_size; 81 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 82 u8 key[RSS_HASH_KEY_SIZE]; 83 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 84 }; 85 86 /* NIX (or NPC) RX errors */ 87 enum otx2_errlvl { 88 NPC_ERRLVL_RE, 89 NPC_ERRLVL_LID_LA, 90 NPC_ERRLVL_LID_LB, 91 NPC_ERRLVL_LID_LC, 92 NPC_ERRLVL_LID_LD, 93 NPC_ERRLVL_LID_LE, 94 NPC_ERRLVL_LID_LF, 95 NPC_ERRLVL_LID_LG, 96 NPC_ERRLVL_LID_LH, 97 NPC_ERRLVL_NIX = 0x0F, 98 }; 99 100 enum otx2_errcodes_re { 101 /* NPC_ERRLVL_RE errcodes */ 102 ERRCODE_FCS = 0x7, 103 ERRCODE_FCS_RCV = 0x8, 104 ERRCODE_UNDERSIZE = 0x10, 105 ERRCODE_OVERSIZE = 0x11, 106 ERRCODE_OL2_LEN_MISMATCH = 0x12, 107 /* NPC_ERRLVL_NIX errcodes */ 108 ERRCODE_OL3_LEN = 0x10, 109 ERRCODE_OL4_LEN = 0x11, 110 ERRCODE_OL4_CSUM = 0x12, 111 ERRCODE_IL3_LEN = 0x20, 112 ERRCODE_IL4_LEN = 0x21, 113 ERRCODE_IL4_CSUM = 0x22, 114 }; 115 116 /* NIX TX stats */ 117 enum nix_stat_lf_tx { 118 TX_UCAST = 0x0, 119 TX_BCAST = 0x1, 120 TX_MCAST = 0x2, 121 TX_DROP = 0x3, 122 TX_OCTS = 0x4, 123 TX_STATS_ENUM_LAST, 124 }; 125 126 /* NIX RX stats */ 127 enum nix_stat_lf_rx { 128 RX_OCTS = 0x0, 129 RX_UCAST = 0x1, 130 RX_BCAST = 0x2, 131 RX_MCAST = 0x3, 132 RX_DROP = 0x4, 133 RX_DROP_OCTS = 0x5, 134 RX_FCS = 0x6, 135 RX_ERR = 0x7, 136 RX_DRP_BCAST = 0x8, 137 RX_DRP_MCAST = 0x9, 138 RX_DRP_L3BCAST = 0xa, 139 RX_DRP_L3MCAST = 0xb, 140 RX_STATS_ENUM_LAST, 141 }; 142 143 struct otx2_dev_stats { 144 u64 rx_bytes; 145 u64 rx_frames; 146 u64 rx_ucast_frames; 147 u64 rx_bcast_frames; 148 u64 rx_mcast_frames; 149 u64 rx_drops; 150 151 u64 tx_bytes; 152 u64 tx_frames; 153 u64 tx_ucast_frames; 154 u64 tx_bcast_frames; 155 u64 tx_mcast_frames; 156 u64 tx_drops; 157 }; 158 159 /* Driver counted stats */ 160 struct otx2_drv_stats { 161 atomic_t rx_fcs_errs; 162 atomic_t rx_oversize_errs; 163 atomic_t rx_undersize_errs; 164 atomic_t rx_csum_errs; 165 atomic_t rx_len_errs; 166 atomic_t rx_other_errs; 167 }; 168 169 struct mbox { 170 struct otx2_mbox mbox; 171 struct work_struct mbox_wrk; 172 struct otx2_mbox mbox_up; 173 struct work_struct mbox_up_wrk; 174 struct otx2_nic *pfvf; 175 void *bbuf_base; /* Bounce buffer for mbox memory */ 176 struct mutex lock; /* serialize mailbox access */ 177 int num_msgs; /* mbox number of messages */ 178 int up_num_msgs; /* mbox_up number of messages */ 179 }; 180 181 struct otx2_hw { 182 struct pci_dev *pdev; 183 struct otx2_rss_info rss_info; 184 u16 rx_queues; 185 u16 tx_queues; 186 u16 xdp_queues; 187 u16 tot_tx_queues; 188 u16 max_queues; 189 u16 pool_cnt; 190 u16 rqpool_cnt; 191 u16 sqpool_cnt; 192 193 #define OTX2_DEFAULT_RBUF_LEN 2048 194 u16 rbuf_len; 195 u32 xqe_size; 196 197 /* NPA */ 198 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 199 u32 stack_pg_bytes; /* Size of stack page */ 200 u16 sqb_size; 201 202 /* NIX */ 203 u8 txschq_link_cfg_lvl; 204 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 205 u16 matchall_ipolicer; 206 u32 dwrr_mtu; 207 208 /* HW settings, coalescing etc */ 209 u16 rx_chan_base; 210 u16 tx_chan_base; 211 u16 cq_qcount_wait; 212 u16 cq_ecount_wait; 213 u16 rq_skid; 214 u8 cq_time_wait; 215 216 /* Segmentation */ 217 u8 lso_tsov4_idx; 218 u8 lso_tsov6_idx; 219 u8 lso_udpv4_idx; 220 u8 lso_udpv6_idx; 221 222 /* RSS */ 223 u8 flowkey_alg_idx; 224 225 /* MSI-X */ 226 u8 cint_cnt; /* CQ interrupt count */ 227 u16 npa_msixoff; /* Offset of NPA vectors */ 228 u16 nix_msixoff; /* Offset of NIX vectors */ 229 char *irq_name; 230 cpumask_var_t *affinity_mask; 231 232 /* Stats */ 233 struct otx2_dev_stats dev_stats; 234 struct otx2_drv_stats drv_stats; 235 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 236 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 237 u64 cgx_fec_corr_blks; 238 u64 cgx_fec_uncorr_blks; 239 u8 cgx_links; /* No. of CGX links present in HW */ 240 u8 lbk_links; /* No. of LBK links present in HW */ 241 u8 tx_link; /* Transmit channel link number */ 242 #define HW_TSO 0 243 #define CN10K_MBOX 1 244 #define CN10K_LMTST 2 245 #define CN10K_RPM 3 246 #define CN10K_PTP_ONESTEP 4 247 unsigned long cap_flag; 248 249 #define LMT_LINE_SIZE 128 250 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 251 u64 *lmt_base; 252 struct otx2_lmt_info __percpu *lmt_info; 253 }; 254 255 enum vfperm { 256 OTX2_RESET_VF_PERM, 257 OTX2_TRUSTED_VF, 258 }; 259 260 struct otx2_vf_config { 261 struct otx2_nic *pf; 262 struct delayed_work link_event_work; 263 bool intf_down; /* interface was either configured or not */ 264 u8 mac[ETH_ALEN]; 265 u16 vlan; 266 int tx_vtag_idx; 267 bool trusted; 268 }; 269 270 struct flr_work { 271 struct work_struct work; 272 struct otx2_nic *pf; 273 }; 274 275 struct refill_work { 276 struct delayed_work pool_refill_work; 277 struct otx2_nic *pf; 278 }; 279 280 /* PTPv2 originTimestamp structure */ 281 struct ptpv2_tstamp { 282 __be16 seconds_msb; /* 16 bits + */ 283 __be32 seconds_lsb; /* 32 bits = 48 bits*/ 284 __be32 nanoseconds; 285 } __packed; 286 287 struct otx2_ptp { 288 struct ptp_clock_info ptp_info; 289 struct ptp_clock *ptp_clock; 290 struct otx2_nic *nic; 291 292 struct cyclecounter cycle_counter; 293 struct timecounter time_counter; 294 295 struct delayed_work extts_work; 296 u64 last_extts; 297 u64 thresh; 298 299 struct ptp_pin_desc extts_config; 300 u64 (*convert_rx_ptp_tstmp)(u64 timestamp); 301 u64 (*convert_tx_ptp_tstmp)(u64 timestamp); 302 struct delayed_work synctstamp_work; 303 u64 tstamp; 304 u32 base_ns; 305 }; 306 307 #define OTX2_HW_TIMESTAMP_LEN 8 308 309 struct otx2_mac_table { 310 u8 addr[ETH_ALEN]; 311 u16 mcam_entry; 312 bool inuse; 313 }; 314 315 struct otx2_flow_config { 316 u16 *flow_ent; 317 u16 *def_ent; 318 u16 nr_flows; 319 #define OTX2_DEFAULT_FLOWCOUNT 16 320 #define OTX2_MAX_UNICAST_FLOWS 8 321 #define OTX2_MAX_VLAN_FLOWS 1 322 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 323 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \ 324 OTX2_MAX_UNICAST_FLOWS + \ 325 OTX2_MAX_VLAN_FLOWS) 326 u16 unicast_offset; 327 u16 rx_vlan_offset; 328 u16 vf_vlan_offset; 329 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 330 #define OTX2_VF_VLAN_RX_INDEX 0 331 #define OTX2_VF_VLAN_TX_INDEX 1 332 u16 max_flows; 333 u8 dmacflt_max_flows; 334 u32 *bmap_to_dmacindex; 335 unsigned long *dmacflt_bmap; 336 struct list_head flow_list; 337 }; 338 339 struct otx2_tc_info { 340 /* hash table to store TC offloaded flows */ 341 struct rhashtable flow_table; 342 struct rhashtable_params flow_ht_params; 343 unsigned long *tc_entries_bitmap; 344 }; 345 346 struct dev_hw_ops { 347 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); 348 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 349 int size, int qidx); 350 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 351 void (*aura_freeptr)(void *dev, int aura, u64 buf); 352 }; 353 354 struct otx2_nic { 355 void __iomem *reg_base; 356 struct net_device *netdev; 357 struct dev_hw_ops *hw_ops; 358 void *iommu_domain; 359 u16 tx_max_pktlen; 360 u16 rbsize; /* Receive buffer size */ 361 362 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 363 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 364 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 365 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 366 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 367 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 368 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 369 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 370 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 371 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 372 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 373 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 374 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 375 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 376 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 377 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15) 378 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) 379 u64 flags; 380 u64 *cq_op_addr; 381 382 struct bpf_prog *xdp_prog; 383 struct otx2_qset qset; 384 struct otx2_hw hw; 385 struct pci_dev *pdev; 386 struct device *dev; 387 388 /* Mbox */ 389 struct mbox mbox; 390 struct mbox *mbox_pfvf; 391 struct workqueue_struct *mbox_wq; 392 struct workqueue_struct *mbox_pfvf_wq; 393 394 u8 total_vfs; 395 u16 pcifunc; /* RVU PF_FUNC */ 396 u16 bpid[NIX_MAX_BPID_CHAN]; 397 struct otx2_vf_config *vf_configs; 398 struct cgx_link_user_info linfo; 399 400 /* NPC MCAM */ 401 struct otx2_flow_config *flow_cfg; 402 struct otx2_mac_table *mac_table; 403 struct otx2_tc_info tc_info; 404 405 u64 reset_count; 406 struct work_struct reset_task; 407 struct workqueue_struct *flr_wq; 408 struct flr_work *flr_wrk; 409 struct refill_work *refill_wrk; 410 struct workqueue_struct *otx2_wq; 411 struct work_struct rx_mode_work; 412 413 /* Ethtool stuff */ 414 u32 msg_enable; 415 416 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 417 int nix_blkaddr; 418 /* LMTST Lines info */ 419 struct qmem *dync_lmt; 420 u16 tot_lmt_lines; 421 u16 npa_lmt_lines; 422 u32 nix_lmt_size; 423 424 struct otx2_ptp *ptp; 425 struct hwtstamp_config tstamp; 426 427 unsigned long rq_bmap; 428 429 /* Devlink */ 430 struct otx2_devlink *dl; 431 #ifdef CONFIG_DCB 432 /* PFC */ 433 u8 pfc_en; 434 u8 *queue_to_pfc_map; 435 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 436 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX]; 437 #endif 438 439 /* napi event count. It is needed for adaptive irq coalescing. */ 440 u32 napi_events; 441 }; 442 443 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 444 { 445 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF; 446 } 447 448 static inline bool is_96xx_A0(struct pci_dev *pdev) 449 { 450 return (pdev->revision == 0x00) && 451 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 452 } 453 454 static inline bool is_96xx_B0(struct pci_dev *pdev) 455 { 456 return (pdev->revision == 0x01) && 457 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 458 } 459 460 /* REVID for PCIe devices. 461 * Bits 0..1: minor pass, bit 3..2: major pass 462 * bits 7..4: midr id 463 */ 464 #define PCI_REVISION_ID_96XX 0x00 465 #define PCI_REVISION_ID_95XX 0x10 466 #define PCI_REVISION_ID_95XXN 0x20 467 #define PCI_REVISION_ID_98XX 0x30 468 #define PCI_REVISION_ID_95XXMM 0x40 469 #define PCI_REVISION_ID_95XXO 0xE0 470 471 static inline bool is_dev_otx2(struct pci_dev *pdev) 472 { 473 u8 midr = pdev->revision & 0xF0; 474 475 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 476 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 477 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 478 } 479 480 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 481 { 482 struct otx2_hw *hw = &pfvf->hw; 483 484 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 485 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 486 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 487 488 __set_bit(HW_TSO, &hw->cap_flag); 489 490 if (is_96xx_A0(pfvf->pdev)) { 491 __clear_bit(HW_TSO, &hw->cap_flag); 492 493 /* Time based irq coalescing is not supported */ 494 pfvf->hw.cq_qcount_wait = 0x0; 495 496 /* Due to HW issue previous silicons required minimum 497 * 600 unused CQE to avoid CQ overflow. 498 */ 499 pfvf->hw.rq_skid = 600; 500 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 501 } 502 if (is_96xx_B0(pfvf->pdev)) 503 __clear_bit(HW_TSO, &hw->cap_flag); 504 505 if (!is_dev_otx2(pfvf->pdev)) { 506 __set_bit(CN10K_MBOX, &hw->cap_flag); 507 __set_bit(CN10K_LMTST, &hw->cap_flag); 508 __set_bit(CN10K_RPM, &hw->cap_flag); 509 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag); 510 } 511 } 512 513 /* Register read/write APIs */ 514 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 515 { 516 u64 blkaddr; 517 518 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 519 case BLKTYPE_NIX: 520 blkaddr = nic->nix_blkaddr; 521 break; 522 case BLKTYPE_NPA: 523 blkaddr = BLKADDR_NPA; 524 break; 525 default: 526 blkaddr = BLKADDR_RVUM; 527 break; 528 } 529 530 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 531 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 532 533 return nic->reg_base + offset; 534 } 535 536 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 537 { 538 void __iomem *addr = otx2_get_regaddr(nic, offset); 539 540 writeq(val, addr); 541 } 542 543 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 544 { 545 void __iomem *addr = otx2_get_regaddr(nic, offset); 546 547 return readq(addr); 548 } 549 550 /* Mbox bounce buffer APIs */ 551 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 552 { 553 struct otx2_mbox *otx2_mbox; 554 struct otx2_mbox_dev *mdev; 555 556 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 557 if (!mbox->bbuf_base) 558 return -ENOMEM; 559 560 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 561 * prepare all mbox messages in bounce buffer instead of directly 562 * in hw mbox memory. 563 */ 564 otx2_mbox = &mbox->mbox; 565 mdev = &otx2_mbox->dev[0]; 566 mdev->mbase = mbox->bbuf_base; 567 568 otx2_mbox = &mbox->mbox_up; 569 mdev = &otx2_mbox->dev[0]; 570 mdev->mbase = mbox->bbuf_base; 571 return 0; 572 } 573 574 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 575 { 576 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 577 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 578 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 579 struct mbox_hdr *hdr; 580 u64 msg_size; 581 582 if (mdev->mbase == hw_mbase) 583 return; 584 585 hdr = hw_mbase + mbox->rx_start; 586 msg_size = hdr->msg_size; 587 588 if (msg_size > mbox->rx_size - msgs_offset) 589 msg_size = mbox->rx_size - msgs_offset; 590 591 /* Copy mbox messages from mbox memory to bounce buffer */ 592 memcpy(mdev->mbase + mbox->rx_start, 593 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 594 } 595 596 /* With the absence of API for 128-bit IO memory access for arm64, 597 * implement required operations at place. 598 */ 599 #if defined(CONFIG_ARM64) 600 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 601 { 602 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 603 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 604 } 605 606 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 607 { 608 u64 result; 609 610 __asm__ volatile(".cpu generic+lse\n" 611 "ldadd %x[i], %x[r], [%[b]]" 612 : [r]"=r"(result), "+m"(*ptr) 613 : [i]"r"(incr), [b]"r"(ptr) 614 : "memory"); 615 return result; 616 } 617 618 #else 619 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 620 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 621 #endif 622 623 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 624 u64 *ptrs, u64 num_ptrs) 625 { 626 struct otx2_lmt_info *lmt_info; 627 u64 size = 0, count_eot = 0; 628 u64 tar_addr, val = 0; 629 630 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); 631 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 632 /* LMTID is same as AURA Id */ 633 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); 634 /* Set if [127:64] of last 128bit word has a valid pointer */ 635 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 636 /* Set AURA ID to free pointer */ 637 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 638 /* Target address for LMTST flush tells HW how many 128bit 639 * words are valid from NPA_LF_AURA_BATCH_FREE0. 640 * 641 * tar_addr[6:4] is LMTST size-1 in units of 128b. 642 */ 643 if (num_ptrs > 2) { 644 size = (sizeof(u64) * num_ptrs) / 16; 645 if (!count_eot) 646 size++; 647 tar_addr |= ((size - 1) & 0x7) << 4; 648 } 649 dma_wmb(); 650 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); 651 /* Perform LMTST flush */ 652 cn10k_lmt_flush(val, tar_addr); 653 } 654 655 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 656 { 657 struct otx2_nic *pfvf = dev; 658 u64 ptrs[2]; 659 660 ptrs[1] = buf; 661 /* Free only one buffer at time during init and teardown */ 662 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); 663 } 664 665 /* Alloc pointer from pool/aura */ 666 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 667 { 668 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf, 669 NPA_LF_AURA_OP_ALLOCX(0)); 670 u64 incr = (u64)aura | BIT_ULL(63); 671 672 return otx2_atomic64_add(incr, ptr); 673 } 674 675 /* Free pointer to a pool/aura */ 676 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 677 { 678 struct otx2_nic *pfvf = dev; 679 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 680 681 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 682 } 683 684 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 685 { 686 if (type == AURA_NIX_SQ) 687 return pfvf->hw.rqpool_cnt + idx; 688 689 /* AURA_NIX_RQ */ 690 return idx; 691 } 692 693 /* Mbox APIs */ 694 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 695 { 696 int err; 697 698 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 699 return 0; 700 otx2_mbox_msg_send(&mbox->mbox, 0); 701 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 702 if (err) 703 return err; 704 705 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 706 } 707 708 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 709 { 710 int err; 711 712 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 713 return 0; 714 otx2_mbox_msg_send(&mbox->mbox_up, devid); 715 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 716 if (err) 717 return err; 718 719 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 720 } 721 722 /* Use this API to send mbox msgs in atomic context 723 * where sleeping is not allowed 724 */ 725 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 726 { 727 int err; 728 729 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 730 return 0; 731 otx2_mbox_msg_send(&mbox->mbox, 0); 732 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 733 if (err) 734 return err; 735 736 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 737 } 738 739 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 740 static struct _req_type __maybe_unused \ 741 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 742 { \ 743 struct _req_type *req; \ 744 \ 745 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 746 &mbox->mbox, 0, sizeof(struct _req_type), \ 747 sizeof(struct _rsp_type)); \ 748 if (!req) \ 749 return NULL; \ 750 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 751 req->hdr.id = _id; \ 752 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 753 return req; \ 754 } 755 756 MBOX_MESSAGES 757 #undef M 758 759 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 760 int \ 761 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 762 struct _req_type *req, \ 763 struct _rsp_type *rsp); \ 764 765 MBOX_UP_CGX_MESSAGES 766 #undef M 767 768 /* Time to wait before watchdog kicks off */ 769 #define OTX2_TX_TIMEOUT (100 * HZ) 770 771 #define RVU_PFVF_PF_SHIFT 10 772 #define RVU_PFVF_PF_MASK 0x3F 773 #define RVU_PFVF_FUNC_SHIFT 0 774 #define RVU_PFVF_FUNC_MASK 0x3FF 775 776 static inline bool is_otx2_vf(u16 pcifunc) 777 { 778 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 779 } 780 781 static inline int rvu_get_pf(u16 pcifunc) 782 { 783 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 784 } 785 786 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 787 struct page *page, 788 size_t offset, size_t size, 789 enum dma_data_direction dir) 790 { 791 dma_addr_t iova; 792 793 iova = dma_map_page_attrs(pfvf->dev, page, 794 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 795 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 796 return (dma_addr_t)NULL; 797 return iova; 798 } 799 800 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 801 dma_addr_t addr, size_t size, 802 enum dma_data_direction dir) 803 { 804 dma_unmap_page_attrs(pfvf->dev, addr, size, 805 dir, DMA_ATTR_SKIP_CPU_SYNC); 806 } 807 808 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx) 809 { 810 #ifdef CONFIG_DCB 811 if (pfvf->pfc_alloc_status[qidx]) 812 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx]; 813 #endif 814 815 return pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 816 } 817 818 /* MSI-X APIs */ 819 void otx2_free_cints(struct otx2_nic *pfvf, int n); 820 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 821 int otx2_set_mac_address(struct net_device *netdev, void *p); 822 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 823 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 824 void otx2_get_mac_from_af(struct net_device *netdev); 825 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 826 int otx2_config_pause_frm(struct otx2_nic *pfvf); 827 void otx2_setup_segmentation(struct otx2_nic *pfvf); 828 829 /* RVU block related APIs */ 830 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 831 int otx2_detach_resources(struct mbox *mbox); 832 int otx2_config_npa(struct otx2_nic *pfvf); 833 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 834 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 835 void otx2_aura_pool_free(struct otx2_nic *pfvf); 836 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 837 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 838 int otx2_config_nix(struct otx2_nic *pfvf); 839 int otx2_config_nix_queues(struct otx2_nic *pfvf); 840 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en); 841 int otx2_txsch_alloc(struct otx2_nic *pfvf); 842 int otx2_txschq_stop(struct otx2_nic *pfvf); 843 void otx2_sqb_flush(struct otx2_nic *pfvf); 844 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 845 dma_addr_t *dma); 846 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 847 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 848 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 849 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 850 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 851 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 852 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 853 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 854 dma_addr_t *dma); 855 856 /* RSS configuration APIs*/ 857 int otx2_rss_init(struct otx2_nic *pfvf); 858 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 859 void otx2_set_rss_key(struct otx2_nic *pfvf); 860 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 861 862 /* Mbox handlers */ 863 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 864 struct msix_offset_rsp *rsp); 865 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 866 struct npa_lf_alloc_rsp *rsp); 867 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 868 struct nix_lf_alloc_rsp *rsp); 869 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 870 struct nix_txsch_alloc_rsp *rsp); 871 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 872 struct cgx_stats_rsp *rsp); 873 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 874 struct cgx_fec_stats_rsp *rsp); 875 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 876 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 877 struct nix_bp_cfg_rsp *rsp); 878 879 /* Device stats APIs */ 880 void otx2_get_dev_stats(struct otx2_nic *pfvf); 881 void otx2_get_stats64(struct net_device *netdev, 882 struct rtnl_link_stats64 *stats); 883 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 884 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 885 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 886 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 887 void otx2_set_ethtool_ops(struct net_device *netdev); 888 void otx2vf_set_ethtool_ops(struct net_device *netdev); 889 890 int otx2_open(struct net_device *netdev); 891 int otx2_stop(struct net_device *netdev); 892 int otx2_set_real_num_queues(struct net_device *netdev, 893 int tx_queues, int rx_queues); 894 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd); 895 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr); 896 897 /* MCAM filter related APIs */ 898 int otx2_mcam_flow_init(struct otx2_nic *pf); 899 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 900 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 901 void otx2_mcam_flow_del(struct otx2_nic *pf); 902 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 903 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 904 int otx2_get_flow(struct otx2_nic *pfvf, 905 struct ethtool_rxnfc *nfc, u32 location); 906 int otx2_get_all_flows(struct otx2_nic *pfvf, 907 struct ethtool_rxnfc *nfc, u32 *rule_locs); 908 int otx2_add_flow(struct otx2_nic *pfvf, 909 struct ethtool_rxnfc *nfc); 910 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 911 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 912 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 913 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 914 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 915 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 916 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 917 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx); 918 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 919 int otx2_handle_ntuple_tc_features(struct net_device *netdev, 920 netdev_features_t features); 921 int otx2_smq_flush(struct otx2_nic *pfvf, int smq); 922 923 /* tc support */ 924 int otx2_init_tc(struct otx2_nic *nic); 925 void otx2_shutdown_tc(struct otx2_nic *nic); 926 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 927 void *type_data); 928 int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic); 929 /* CGX/RPM DMAC filters support */ 930 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 931 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 932 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 933 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos); 934 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 935 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 936 937 #ifdef CONFIG_DCB 938 /* DCB support*/ 939 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable); 940 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf); 941 int otx2_dcbnl_set_ops(struct net_device *dev); 942 /* PFC support */ 943 int otx2_pfc_txschq_config(struct otx2_nic *pfvf); 944 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf); 945 int otx2_pfc_txschq_update(struct otx2_nic *pfvf); 946 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf); 947 #endif 948 #endif /* OTX2_COMMON_H */ 949