1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef OTX2_COMMON_H 12 #define OTX2_COMMON_H 13 14 #include <linux/ethtool.h> 15 #include <linux/pci.h> 16 #include <linux/iommu.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/timecounter.h> 20 #include <linux/soc/marvell/octeontx2/asm.h> 21 22 #include <mbox.h> 23 #include <npc.h> 24 #include "otx2_reg.h" 25 #include "otx2_txrx.h" 26 #include <rvu_trace.h> 27 28 /* PCI device IDs */ 29 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 30 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 31 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 32 33 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 34 35 /* PCI BAR nos */ 36 #define PCI_CFG_REG_BAR_NUM 2 37 #define PCI_MBOX_BAR_NUM 4 38 39 #define NAME_SIZE 32 40 41 enum arua_mapped_qtypes { 42 AURA_NIX_RQ, 43 AURA_NIX_SQ, 44 }; 45 46 /* NIX LF interrupts range*/ 47 #define NIX_LF_QINT_VEC_START 0x00 48 #define NIX_LF_CINT_VEC_START 0x40 49 #define NIX_LF_GINT_VEC 0x80 50 #define NIX_LF_ERR_VEC 0x81 51 #define NIX_LF_POISON_VEC 0x82 52 53 /* RSS configuration */ 54 struct otx2_rss_info { 55 u8 enable; 56 u32 flowkey_cfg; 57 u16 rss_size; 58 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 59 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 60 u8 key[RSS_HASH_KEY_SIZE]; 61 }; 62 63 /* NIX (or NPC) RX errors */ 64 enum otx2_errlvl { 65 NPC_ERRLVL_RE, 66 NPC_ERRLVL_LID_LA, 67 NPC_ERRLVL_LID_LB, 68 NPC_ERRLVL_LID_LC, 69 NPC_ERRLVL_LID_LD, 70 NPC_ERRLVL_LID_LE, 71 NPC_ERRLVL_LID_LF, 72 NPC_ERRLVL_LID_LG, 73 NPC_ERRLVL_LID_LH, 74 NPC_ERRLVL_NIX = 0x0F, 75 }; 76 77 enum otx2_errcodes_re { 78 /* NPC_ERRLVL_RE errcodes */ 79 ERRCODE_FCS = 0x7, 80 ERRCODE_FCS_RCV = 0x8, 81 ERRCODE_UNDERSIZE = 0x10, 82 ERRCODE_OVERSIZE = 0x11, 83 ERRCODE_OL2_LEN_MISMATCH = 0x12, 84 /* NPC_ERRLVL_NIX errcodes */ 85 ERRCODE_OL3_LEN = 0x10, 86 ERRCODE_OL4_LEN = 0x11, 87 ERRCODE_OL4_CSUM = 0x12, 88 ERRCODE_IL3_LEN = 0x20, 89 ERRCODE_IL4_LEN = 0x21, 90 ERRCODE_IL4_CSUM = 0x22, 91 }; 92 93 /* NIX TX stats */ 94 enum nix_stat_lf_tx { 95 TX_UCAST = 0x0, 96 TX_BCAST = 0x1, 97 TX_MCAST = 0x2, 98 TX_DROP = 0x3, 99 TX_OCTS = 0x4, 100 TX_STATS_ENUM_LAST, 101 }; 102 103 /* NIX RX stats */ 104 enum nix_stat_lf_rx { 105 RX_OCTS = 0x0, 106 RX_UCAST = 0x1, 107 RX_BCAST = 0x2, 108 RX_MCAST = 0x3, 109 RX_DROP = 0x4, 110 RX_DROP_OCTS = 0x5, 111 RX_FCS = 0x6, 112 RX_ERR = 0x7, 113 RX_DRP_BCAST = 0x8, 114 RX_DRP_MCAST = 0x9, 115 RX_DRP_L3BCAST = 0xa, 116 RX_DRP_L3MCAST = 0xb, 117 RX_STATS_ENUM_LAST, 118 }; 119 120 struct otx2_dev_stats { 121 u64 rx_bytes; 122 u64 rx_frames; 123 u64 rx_ucast_frames; 124 u64 rx_bcast_frames; 125 u64 rx_mcast_frames; 126 u64 rx_drops; 127 128 u64 tx_bytes; 129 u64 tx_frames; 130 u64 tx_ucast_frames; 131 u64 tx_bcast_frames; 132 u64 tx_mcast_frames; 133 u64 tx_drops; 134 }; 135 136 /* Driver counted stats */ 137 struct otx2_drv_stats { 138 atomic_t rx_fcs_errs; 139 atomic_t rx_oversize_errs; 140 atomic_t rx_undersize_errs; 141 atomic_t rx_csum_errs; 142 atomic_t rx_len_errs; 143 atomic_t rx_other_errs; 144 }; 145 146 struct mbox { 147 struct otx2_mbox mbox; 148 struct work_struct mbox_wrk; 149 struct otx2_mbox mbox_up; 150 struct work_struct mbox_up_wrk; 151 struct otx2_nic *pfvf; 152 void *bbuf_base; /* Bounce buffer for mbox memory */ 153 struct mutex lock; /* serialize mailbox access */ 154 int num_msgs; /* mbox number of messages */ 155 int up_num_msgs; /* mbox_up number of messages */ 156 }; 157 158 struct otx2_hw { 159 struct pci_dev *pdev; 160 struct otx2_rss_info rss_info; 161 u16 rx_queues; 162 u16 tx_queues; 163 u16 max_queues; 164 u16 pool_cnt; 165 u16 rqpool_cnt; 166 u16 sqpool_cnt; 167 168 /* NPA */ 169 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 170 u32 stack_pg_bytes; /* Size of stack page */ 171 u16 sqb_size; 172 173 /* NIX */ 174 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 175 176 /* HW settings, coalescing etc */ 177 u16 rx_chan_base; 178 u16 tx_chan_base; 179 u16 cq_qcount_wait; 180 u16 cq_ecount_wait; 181 u16 rq_skid; 182 u8 cq_time_wait; 183 184 /* Segmentation */ 185 u8 lso_tsov4_idx; 186 u8 lso_tsov6_idx; 187 u8 lso_udpv4_idx; 188 u8 lso_udpv6_idx; 189 u8 hw_tso; 190 191 /* MSI-X */ 192 u8 cint_cnt; /* CQ interrupt count */ 193 u16 npa_msixoff; /* Offset of NPA vectors */ 194 u16 nix_msixoff; /* Offset of NIX vectors */ 195 char *irq_name; 196 cpumask_var_t *affinity_mask; 197 198 /* Stats */ 199 struct otx2_dev_stats dev_stats; 200 struct otx2_drv_stats drv_stats; 201 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 202 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 203 u8 cgx_links; /* No. of CGX links present in HW */ 204 u8 lbk_links; /* No. of LBK links present in HW */ 205 }; 206 207 struct otx2_vf_config { 208 struct otx2_nic *pf; 209 struct delayed_work link_event_work; 210 bool intf_down; /* interface was either configured or not */ 211 u8 mac[ETH_ALEN]; 212 u16 vlan; 213 int tx_vtag_idx; 214 }; 215 216 struct flr_work { 217 struct work_struct work; 218 struct otx2_nic *pf; 219 }; 220 221 struct refill_work { 222 struct delayed_work pool_refill_work; 223 struct otx2_nic *pf; 224 }; 225 226 struct otx2_ptp { 227 struct ptp_clock_info ptp_info; 228 struct ptp_clock *ptp_clock; 229 struct otx2_nic *nic; 230 231 struct cyclecounter cycle_counter; 232 struct timecounter time_counter; 233 }; 234 235 #define OTX2_HW_TIMESTAMP_LEN 8 236 237 struct otx2_mac_table { 238 u8 addr[ETH_ALEN]; 239 u16 mcam_entry; 240 bool inuse; 241 }; 242 243 struct otx2_flow_config { 244 u16 entry[NPC_MAX_NONCONTIG_ENTRIES]; 245 u32 nr_flows; 246 #define OTX2_MAX_NTUPLE_FLOWS 32 247 #define OTX2_MAX_UNICAST_FLOWS 8 248 #define OTX2_MAX_VLAN_FLOWS 1 249 #define OTX2_MCAM_COUNT (OTX2_MAX_NTUPLE_FLOWS + \ 250 OTX2_MAX_UNICAST_FLOWS + \ 251 OTX2_MAX_VLAN_FLOWS) 252 u32 ntuple_offset; 253 u32 unicast_offset; 254 u32 rx_vlan_offset; 255 u32 vf_vlan_offset; 256 #define OTX2_PER_VF_VLAN_FLOWS 2 /* rx+tx per VF */ 257 #define OTX2_VF_VLAN_RX_INDEX 0 258 #define OTX2_VF_VLAN_TX_INDEX 1 259 u32 ntuple_max_flows; 260 struct list_head flow_list; 261 }; 262 263 struct otx2_nic { 264 void __iomem *reg_base; 265 struct net_device *netdev; 266 void *iommu_domain; 267 u16 max_frs; 268 u16 rbsize; /* Receive buffer size */ 269 270 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 271 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 272 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 273 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 274 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 275 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 276 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 277 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 278 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 279 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 280 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 281 u64 flags; 282 283 struct otx2_qset qset; 284 struct otx2_hw hw; 285 struct pci_dev *pdev; 286 struct device *dev; 287 288 /* Mbox */ 289 struct mbox mbox; 290 struct mbox *mbox_pfvf; 291 struct workqueue_struct *mbox_wq; 292 struct workqueue_struct *mbox_pfvf_wq; 293 294 u8 total_vfs; 295 u16 pcifunc; /* RVU PF_FUNC */ 296 u16 bpid[NIX_MAX_BPID_CHAN]; 297 struct otx2_vf_config *vf_configs; 298 struct cgx_link_user_info linfo; 299 300 u64 reset_count; 301 struct work_struct reset_task; 302 struct workqueue_struct *flr_wq; 303 struct flr_work *flr_wrk; 304 struct refill_work *refill_wrk; 305 struct workqueue_struct *otx2_wq; 306 struct work_struct rx_mode_work; 307 struct otx2_mac_table *mac_table; 308 309 /* Ethtool stuff */ 310 u32 msg_enable; 311 312 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 313 int nix_blkaddr; 314 315 struct otx2_ptp *ptp; 316 struct hwtstamp_config tstamp; 317 318 struct otx2_flow_config *flow_cfg; 319 }; 320 321 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 322 { 323 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF; 324 } 325 326 static inline bool is_96xx_A0(struct pci_dev *pdev) 327 { 328 return (pdev->revision == 0x00) && 329 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 330 } 331 332 static inline bool is_96xx_B0(struct pci_dev *pdev) 333 { 334 return (pdev->revision == 0x01) && 335 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 336 } 337 338 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 339 { 340 struct otx2_hw *hw = &pfvf->hw; 341 342 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 343 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 344 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 345 346 hw->hw_tso = true; 347 348 if (is_96xx_A0(pfvf->pdev)) { 349 hw->hw_tso = false; 350 351 /* Time based irq coalescing is not supported */ 352 pfvf->hw.cq_qcount_wait = 0x0; 353 354 /* Due to HW issue previous silicons required minimum 355 * 600 unused CQE to avoid CQ overflow. 356 */ 357 pfvf->hw.rq_skid = 600; 358 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 359 } 360 } 361 362 /* Register read/write APIs */ 363 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 364 { 365 u64 blkaddr; 366 367 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 368 case BLKTYPE_NIX: 369 blkaddr = nic->nix_blkaddr; 370 break; 371 case BLKTYPE_NPA: 372 blkaddr = BLKADDR_NPA; 373 break; 374 default: 375 blkaddr = BLKADDR_RVUM; 376 break; 377 } 378 379 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 380 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 381 382 return nic->reg_base + offset; 383 } 384 385 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 386 { 387 void __iomem *addr = otx2_get_regaddr(nic, offset); 388 389 writeq(val, addr); 390 } 391 392 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 393 { 394 void __iomem *addr = otx2_get_regaddr(nic, offset); 395 396 return readq(addr); 397 } 398 399 /* Mbox bounce buffer APIs */ 400 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 401 { 402 struct otx2_mbox *otx2_mbox; 403 struct otx2_mbox_dev *mdev; 404 405 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 406 if (!mbox->bbuf_base) 407 return -ENOMEM; 408 409 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 410 * prepare all mbox messages in bounce buffer instead of directly 411 * in hw mbox memory. 412 */ 413 otx2_mbox = &mbox->mbox; 414 mdev = &otx2_mbox->dev[0]; 415 mdev->mbase = mbox->bbuf_base; 416 417 otx2_mbox = &mbox->mbox_up; 418 mdev = &otx2_mbox->dev[0]; 419 mdev->mbase = mbox->bbuf_base; 420 return 0; 421 } 422 423 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 424 { 425 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 426 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 427 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 428 struct mbox_hdr *hdr; 429 u64 msg_size; 430 431 if (mdev->mbase == hw_mbase) 432 return; 433 434 hdr = hw_mbase + mbox->rx_start; 435 msg_size = hdr->msg_size; 436 437 if (msg_size > mbox->rx_size - msgs_offset) 438 msg_size = mbox->rx_size - msgs_offset; 439 440 /* Copy mbox messages from mbox memory to bounce buffer */ 441 memcpy(mdev->mbase + mbox->rx_start, 442 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 443 } 444 445 /* With the absence of API for 128-bit IO memory access for arm64, 446 * implement required operations at place. 447 */ 448 #if defined(CONFIG_ARM64) 449 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 450 { 451 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 452 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 453 } 454 455 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 456 { 457 u64 result; 458 459 __asm__ volatile(".cpu generic+lse\n" 460 "ldadd %x[i], %x[r], [%[b]]" 461 : [r]"=r"(result), "+m"(*ptr) 462 : [i]"r"(incr), [b]"r"(ptr) 463 : "memory"); 464 return result; 465 } 466 467 #else 468 #define otx2_write128(lo, hi, addr) 469 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 470 #endif 471 472 /* Alloc pointer from pool/aura */ 473 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 474 { 475 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf, 476 NPA_LF_AURA_OP_ALLOCX(0)); 477 u64 incr = (u64)aura | BIT_ULL(63); 478 479 return otx2_atomic64_add(incr, ptr); 480 } 481 482 /* Free pointer to a pool/aura */ 483 static inline void otx2_aura_freeptr(struct otx2_nic *pfvf, 484 int aura, s64 buf) 485 { 486 otx2_write128((u64)buf, (u64)aura | BIT_ULL(63), 487 otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0)); 488 } 489 490 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 491 { 492 if (type == AURA_NIX_SQ) 493 return pfvf->hw.rqpool_cnt + idx; 494 495 /* AURA_NIX_RQ */ 496 return idx; 497 } 498 499 /* Mbox APIs */ 500 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 501 { 502 int err; 503 504 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 505 return 0; 506 otx2_mbox_msg_send(&mbox->mbox, 0); 507 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 508 if (err) 509 return err; 510 511 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 512 } 513 514 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 515 { 516 int err; 517 518 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 519 return 0; 520 otx2_mbox_msg_send(&mbox->mbox_up, devid); 521 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 522 if (err) 523 return err; 524 525 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 526 } 527 528 /* Use this API to send mbox msgs in atomic context 529 * where sleeping is not allowed 530 */ 531 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 532 { 533 int err; 534 535 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 536 return 0; 537 otx2_mbox_msg_send(&mbox->mbox, 0); 538 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 539 if (err) 540 return err; 541 542 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 543 } 544 545 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 546 static struct _req_type __maybe_unused \ 547 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 548 { \ 549 struct _req_type *req; \ 550 \ 551 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 552 &mbox->mbox, 0, sizeof(struct _req_type), \ 553 sizeof(struct _rsp_type)); \ 554 if (!req) \ 555 return NULL; \ 556 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 557 req->hdr.id = _id; \ 558 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 559 return req; \ 560 } 561 562 MBOX_MESSAGES 563 #undef M 564 565 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 566 int \ 567 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 568 struct _req_type *req, \ 569 struct _rsp_type *rsp); \ 570 571 MBOX_UP_CGX_MESSAGES 572 #undef M 573 574 /* Time to wait before watchdog kicks off */ 575 #define OTX2_TX_TIMEOUT (100 * HZ) 576 577 #define RVU_PFVF_PF_SHIFT 10 578 #define RVU_PFVF_PF_MASK 0x3F 579 #define RVU_PFVF_FUNC_SHIFT 0 580 #define RVU_PFVF_FUNC_MASK 0x3FF 581 582 static inline int rvu_get_pf(u16 pcifunc) 583 { 584 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 585 } 586 587 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 588 struct page *page, 589 size_t offset, size_t size, 590 enum dma_data_direction dir) 591 { 592 dma_addr_t iova; 593 594 iova = dma_map_page_attrs(pfvf->dev, page, 595 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 596 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 597 return (dma_addr_t)NULL; 598 return iova; 599 } 600 601 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 602 dma_addr_t addr, size_t size, 603 enum dma_data_direction dir) 604 { 605 dma_unmap_page_attrs(pfvf->dev, addr, size, 606 dir, DMA_ATTR_SKIP_CPU_SYNC); 607 } 608 609 /* MSI-X APIs */ 610 void otx2_free_cints(struct otx2_nic *pfvf, int n); 611 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 612 int otx2_set_mac_address(struct net_device *netdev, void *p); 613 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 614 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 615 void otx2_get_mac_from_af(struct net_device *netdev); 616 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 617 int otx2_config_pause_frm(struct otx2_nic *pfvf); 618 void otx2_setup_segmentation(struct otx2_nic *pfvf); 619 620 /* RVU block related APIs */ 621 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 622 int otx2_detach_resources(struct mbox *mbox); 623 int otx2_config_npa(struct otx2_nic *pfvf); 624 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 625 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 626 void otx2_aura_pool_free(struct otx2_nic *pfvf); 627 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 628 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 629 int otx2_config_nix(struct otx2_nic *pfvf); 630 int otx2_config_nix_queues(struct otx2_nic *pfvf); 631 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl); 632 int otx2_txsch_alloc(struct otx2_nic *pfvf); 633 int otx2_txschq_stop(struct otx2_nic *pfvf); 634 void otx2_sqb_flush(struct otx2_nic *pfvf); 635 dma_addr_t __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool); 636 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 637 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 638 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 639 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 640 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 641 642 /* RSS configuration APIs*/ 643 int otx2_rss_init(struct otx2_nic *pfvf); 644 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 645 void otx2_set_rss_key(struct otx2_nic *pfvf); 646 int otx2_set_rss_table(struct otx2_nic *pfvf); 647 648 /* Mbox handlers */ 649 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 650 struct msix_offset_rsp *rsp); 651 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 652 struct npa_lf_alloc_rsp *rsp); 653 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 654 struct nix_lf_alloc_rsp *rsp); 655 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 656 struct nix_txsch_alloc_rsp *rsp); 657 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 658 struct cgx_stats_rsp *rsp); 659 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 660 struct nix_bp_cfg_rsp *rsp); 661 662 /* Device stats APIs */ 663 void otx2_get_dev_stats(struct otx2_nic *pfvf); 664 void otx2_get_stats64(struct net_device *netdev, 665 struct rtnl_link_stats64 *stats); 666 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 667 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 668 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 669 void otx2_set_ethtool_ops(struct net_device *netdev); 670 void otx2vf_set_ethtool_ops(struct net_device *netdev); 671 672 int otx2_open(struct net_device *netdev); 673 int otx2_stop(struct net_device *netdev); 674 int otx2_set_real_num_queues(struct net_device *netdev, 675 int tx_queues, int rx_queues); 676 /* MCAM filter related APIs */ 677 int otx2_mcam_flow_init(struct otx2_nic *pf); 678 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf); 679 void otx2_mcam_flow_del(struct otx2_nic *pf); 680 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 681 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 682 int otx2_get_flow(struct otx2_nic *pfvf, 683 struct ethtool_rxnfc *nfc, u32 location); 684 int otx2_get_all_flows(struct otx2_nic *pfvf, 685 struct ethtool_rxnfc *nfc, u32 *rule_locs); 686 int otx2_add_flow(struct otx2_nic *pfvf, 687 struct ethtool_rx_flow_spec *fsp); 688 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 689 int otx2_prepare_flow_request(struct ethtool_rx_flow_spec *fsp, 690 struct npc_install_flow_req *req); 691 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 692 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 693 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 694 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 695 696 #endif /* OTX2_COMMON_H */ 697