1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef OTX2_COMMON_H 12 #define OTX2_COMMON_H 13 14 #include <linux/pci.h> 15 #include <linux/iommu.h> 16 17 #include <mbox.h> 18 #include "otx2_reg.h" 19 #include "otx2_txrx.h" 20 21 /* PCI device IDs */ 22 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 23 24 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 25 26 /* PCI BAR nos */ 27 #define PCI_CFG_REG_BAR_NUM 2 28 #define PCI_MBOX_BAR_NUM 4 29 30 #define NAME_SIZE 32 31 32 enum arua_mapped_qtypes { 33 AURA_NIX_RQ, 34 AURA_NIX_SQ, 35 }; 36 37 /* NIX LF interrupts range*/ 38 #define NIX_LF_QINT_VEC_START 0x00 39 #define NIX_LF_CINT_VEC_START 0x40 40 #define NIX_LF_GINT_VEC 0x80 41 #define NIX_LF_ERR_VEC 0x81 42 #define NIX_LF_POISON_VEC 0x82 43 44 /* RSS configuration */ 45 struct otx2_rss_info { 46 u8 enable; 47 u32 flowkey_cfg; 48 u16 rss_size; 49 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 50 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 51 u8 key[RSS_HASH_KEY_SIZE]; 52 }; 53 54 /* NIX (or NPC) RX errors */ 55 enum otx2_errlvl { 56 NPC_ERRLVL_RE, 57 NPC_ERRLVL_LID_LA, 58 NPC_ERRLVL_LID_LB, 59 NPC_ERRLVL_LID_LC, 60 NPC_ERRLVL_LID_LD, 61 NPC_ERRLVL_LID_LE, 62 NPC_ERRLVL_LID_LF, 63 NPC_ERRLVL_LID_LG, 64 NPC_ERRLVL_LID_LH, 65 NPC_ERRLVL_NIX = 0x0F, 66 }; 67 68 enum otx2_errcodes_re { 69 /* NPC_ERRLVL_RE errcodes */ 70 ERRCODE_FCS = 0x7, 71 ERRCODE_FCS_RCV = 0x8, 72 ERRCODE_UNDERSIZE = 0x10, 73 ERRCODE_OVERSIZE = 0x11, 74 ERRCODE_OL2_LEN_MISMATCH = 0x12, 75 /* NPC_ERRLVL_NIX errcodes */ 76 ERRCODE_OL3_LEN = 0x10, 77 ERRCODE_OL4_LEN = 0x11, 78 ERRCODE_OL4_CSUM = 0x12, 79 ERRCODE_IL3_LEN = 0x20, 80 ERRCODE_IL4_LEN = 0x21, 81 ERRCODE_IL4_CSUM = 0x22, 82 }; 83 84 /* NIX TX stats */ 85 enum nix_stat_lf_tx { 86 TX_UCAST = 0x0, 87 TX_BCAST = 0x1, 88 TX_MCAST = 0x2, 89 TX_DROP = 0x3, 90 TX_OCTS = 0x4, 91 TX_STATS_ENUM_LAST, 92 }; 93 94 /* NIX RX stats */ 95 enum nix_stat_lf_rx { 96 RX_OCTS = 0x0, 97 RX_UCAST = 0x1, 98 RX_BCAST = 0x2, 99 RX_MCAST = 0x3, 100 RX_DROP = 0x4, 101 RX_DROP_OCTS = 0x5, 102 RX_FCS = 0x6, 103 RX_ERR = 0x7, 104 RX_DRP_BCAST = 0x8, 105 RX_DRP_MCAST = 0x9, 106 RX_DRP_L3BCAST = 0xa, 107 RX_DRP_L3MCAST = 0xb, 108 RX_STATS_ENUM_LAST, 109 }; 110 111 struct otx2_dev_stats { 112 u64 rx_bytes; 113 u64 rx_frames; 114 u64 rx_ucast_frames; 115 u64 rx_bcast_frames; 116 u64 rx_mcast_frames; 117 u64 rx_drops; 118 119 u64 tx_bytes; 120 u64 tx_frames; 121 u64 tx_ucast_frames; 122 u64 tx_bcast_frames; 123 u64 tx_mcast_frames; 124 u64 tx_drops; 125 }; 126 127 /* Driver counted stats */ 128 struct otx2_drv_stats { 129 atomic_t rx_fcs_errs; 130 atomic_t rx_oversize_errs; 131 atomic_t rx_undersize_errs; 132 atomic_t rx_csum_errs; 133 atomic_t rx_len_errs; 134 atomic_t rx_other_errs; 135 }; 136 137 struct mbox { 138 struct otx2_mbox mbox; 139 struct work_struct mbox_wrk; 140 struct otx2_mbox mbox_up; 141 struct work_struct mbox_up_wrk; 142 struct otx2_nic *pfvf; 143 void *bbuf_base; /* Bounce buffer for mbox memory */ 144 struct mutex lock; /* serialize mailbox access */ 145 int num_msgs; /* mbox number of messages */ 146 int up_num_msgs; /* mbox_up number of messages */ 147 }; 148 149 struct otx2_hw { 150 struct pci_dev *pdev; 151 struct otx2_rss_info rss_info; 152 u16 rx_queues; 153 u16 tx_queues; 154 u16 max_queues; 155 u16 pool_cnt; 156 u16 rqpool_cnt; 157 u16 sqpool_cnt; 158 159 /* NPA */ 160 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 161 u32 stack_pg_bytes; /* Size of stack page */ 162 u16 sqb_size; 163 164 /* NIX */ 165 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 166 167 /* HW settings, coalescing etc */ 168 u16 rx_chan_base; 169 u16 tx_chan_base; 170 u16 cq_qcount_wait; 171 u16 cq_ecount_wait; 172 u16 rq_skid; 173 u8 cq_time_wait; 174 175 /* For TSO segmentation */ 176 u8 lso_tsov4_idx; 177 u8 lso_tsov6_idx; 178 u8 hw_tso; 179 180 /* MSI-X */ 181 u8 cint_cnt; /* CQ interrupt count */ 182 u16 npa_msixoff; /* Offset of NPA vectors */ 183 u16 nix_msixoff; /* Offset of NIX vectors */ 184 char *irq_name; 185 cpumask_var_t *affinity_mask; 186 187 /* Stats */ 188 struct otx2_dev_stats dev_stats; 189 struct otx2_drv_stats drv_stats; 190 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 191 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 192 }; 193 194 struct refill_work { 195 struct delayed_work pool_refill_work; 196 struct otx2_nic *pf; 197 }; 198 199 struct otx2_nic { 200 void __iomem *reg_base; 201 struct net_device *netdev; 202 void *iommu_domain; 203 u16 max_frs; 204 u16 rbsize; /* Receive buffer size */ 205 206 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 207 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 208 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 209 u64 flags; 210 211 struct otx2_qset qset; 212 struct otx2_hw hw; 213 struct pci_dev *pdev; 214 struct device *dev; 215 216 /* Mbox */ 217 struct mbox mbox; 218 struct workqueue_struct *mbox_wq; 219 220 u16 pcifunc; /* RVU PF_FUNC */ 221 u16 bpid[NIX_MAX_BPID_CHAN]; 222 struct cgx_link_user_info linfo; 223 224 u64 reset_count; 225 struct work_struct reset_task; 226 struct refill_work *refill_wrk; 227 228 /* Ethtool stuff */ 229 u32 msg_enable; 230 231 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 232 int nix_blkaddr; 233 }; 234 235 static inline bool is_96xx_A0(struct pci_dev *pdev) 236 { 237 return (pdev->revision == 0x00) && 238 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 239 } 240 241 static inline bool is_96xx_B0(struct pci_dev *pdev) 242 { 243 return (pdev->revision == 0x01) && 244 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 245 } 246 247 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 248 { 249 struct otx2_hw *hw = &pfvf->hw; 250 251 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 252 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 253 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 254 255 hw->hw_tso = true; 256 257 if (is_96xx_A0(pfvf->pdev)) { 258 hw->hw_tso = false; 259 260 /* Time based irq coalescing is not supported */ 261 pfvf->hw.cq_qcount_wait = 0x0; 262 263 /* Due to HW issue previous silicons required minimum 264 * 600 unused CQE to avoid CQ overflow. 265 */ 266 pfvf->hw.rq_skid = 600; 267 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 268 } 269 } 270 271 /* Register read/write APIs */ 272 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 273 { 274 u64 blkaddr; 275 276 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 277 case BLKTYPE_NIX: 278 blkaddr = nic->nix_blkaddr; 279 break; 280 case BLKTYPE_NPA: 281 blkaddr = BLKADDR_NPA; 282 break; 283 default: 284 blkaddr = BLKADDR_RVUM; 285 break; 286 }; 287 288 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 289 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 290 291 return nic->reg_base + offset; 292 } 293 294 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 295 { 296 void __iomem *addr = otx2_get_regaddr(nic, offset); 297 298 writeq(val, addr); 299 } 300 301 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 302 { 303 void __iomem *addr = otx2_get_regaddr(nic, offset); 304 305 return readq(addr); 306 } 307 308 /* Mbox bounce buffer APIs */ 309 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 310 { 311 struct otx2_mbox *otx2_mbox; 312 struct otx2_mbox_dev *mdev; 313 314 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 315 if (!mbox->bbuf_base) 316 return -ENOMEM; 317 318 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 319 * prepare all mbox messages in bounce buffer instead of directly 320 * in hw mbox memory. 321 */ 322 otx2_mbox = &mbox->mbox; 323 mdev = &otx2_mbox->dev[0]; 324 mdev->mbase = mbox->bbuf_base; 325 326 otx2_mbox = &mbox->mbox_up; 327 mdev = &otx2_mbox->dev[0]; 328 mdev->mbase = mbox->bbuf_base; 329 return 0; 330 } 331 332 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 333 { 334 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 335 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 336 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 337 struct mbox_hdr *hdr; 338 u64 msg_size; 339 340 if (mdev->mbase == hw_mbase) 341 return; 342 343 hdr = hw_mbase + mbox->rx_start; 344 msg_size = hdr->msg_size; 345 346 if (msg_size > mbox->rx_size - msgs_offset) 347 msg_size = mbox->rx_size - msgs_offset; 348 349 /* Copy mbox messages from mbox memory to bounce buffer */ 350 memcpy(mdev->mbase + mbox->rx_start, 351 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 352 } 353 354 static inline void otx2_mbox_lock_init(struct mbox *mbox) 355 { 356 mutex_init(&mbox->lock); 357 } 358 359 static inline void otx2_mbox_lock(struct mbox *mbox) 360 { 361 mutex_lock(&mbox->lock); 362 } 363 364 static inline void otx2_mbox_unlock(struct mbox *mbox) 365 { 366 mutex_unlock(&mbox->lock); 367 } 368 369 /* With the absence of API for 128-bit IO memory access for arm64, 370 * implement required operations at place. 371 */ 372 #if defined(CONFIG_ARM64) 373 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 374 { 375 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 376 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 377 } 378 379 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 380 { 381 u64 result; 382 383 __asm__ volatile(".cpu generic+lse\n" 384 "ldadd %x[i], %x[r], [%[b]]" 385 : [r]"=r"(result), "+m"(*ptr) 386 : [i]"r"(incr), [b]"r"(ptr) 387 : "memory"); 388 return result; 389 } 390 391 static inline u64 otx2_lmt_flush(uint64_t addr) 392 { 393 u64 result = 0; 394 395 __asm__ volatile(".cpu generic+lse\n" 396 "ldeor xzr,%x[rf],[%[rs]]" 397 : [rf]"=r"(result) 398 : [rs]"r"(addr)); 399 return result; 400 } 401 402 #else 403 #define otx2_write128(lo, hi, addr) 404 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 405 #define otx2_lmt_flush(addr) ({ 0; }) 406 #endif 407 408 /* Alloc pointer from pool/aura */ 409 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 410 { 411 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf, 412 NPA_LF_AURA_OP_ALLOCX(0)); 413 u64 incr = (u64)aura | BIT_ULL(63); 414 415 return otx2_atomic64_add(incr, ptr); 416 } 417 418 /* Free pointer to a pool/aura */ 419 static inline void otx2_aura_freeptr(struct otx2_nic *pfvf, 420 int aura, s64 buf) 421 { 422 otx2_write128((u64)buf, (u64)aura | BIT_ULL(63), 423 otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0)); 424 } 425 426 /* Update page ref count */ 427 static inline void otx2_get_page(struct otx2_pool *pool) 428 { 429 if (!pool->page) 430 return; 431 432 if (pool->pageref) 433 page_ref_add(pool->page, pool->pageref); 434 pool->pageref = 0; 435 pool->page = NULL; 436 } 437 438 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 439 { 440 if (type == AURA_NIX_SQ) 441 return pfvf->hw.rqpool_cnt + idx; 442 443 /* AURA_NIX_RQ */ 444 return idx; 445 } 446 447 /* Mbox APIs */ 448 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 449 { 450 int err; 451 452 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 453 return 0; 454 otx2_mbox_msg_send(&mbox->mbox, 0); 455 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 456 if (err) 457 return err; 458 459 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 460 } 461 462 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 463 { 464 int err; 465 466 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 467 return 0; 468 otx2_mbox_msg_send(&mbox->mbox_up, devid); 469 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 470 if (err) 471 return err; 472 473 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 474 } 475 476 /* Use this API to send mbox msgs in atomic context 477 * where sleeping is not allowed 478 */ 479 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 480 { 481 int err; 482 483 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 484 return 0; 485 otx2_mbox_msg_send(&mbox->mbox, 0); 486 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 487 if (err) 488 return err; 489 490 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 491 } 492 493 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 494 static struct _req_type __maybe_unused \ 495 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 496 { \ 497 struct _req_type *req; \ 498 \ 499 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 500 &mbox->mbox, 0, sizeof(struct _req_type), \ 501 sizeof(struct _rsp_type)); \ 502 if (!req) \ 503 return NULL; \ 504 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 505 req->hdr.id = _id; \ 506 return req; \ 507 } 508 509 MBOX_MESSAGES 510 #undef M 511 512 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 513 int \ 514 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 515 struct _req_type *req, \ 516 struct _rsp_type *rsp); \ 517 518 MBOX_UP_CGX_MESSAGES 519 #undef M 520 521 /* Time to wait before watchdog kicks off */ 522 #define OTX2_TX_TIMEOUT (100 * HZ) 523 524 #define RVU_PFVF_PF_SHIFT 10 525 #define RVU_PFVF_PF_MASK 0x3F 526 #define RVU_PFVF_FUNC_SHIFT 0 527 #define RVU_PFVF_FUNC_MASK 0x3FF 528 529 static inline int rvu_get_pf(u16 pcifunc) 530 { 531 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 532 } 533 534 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 535 struct page *page, 536 size_t offset, size_t size, 537 enum dma_data_direction dir) 538 { 539 dma_addr_t iova; 540 541 iova = dma_map_page_attrs(pfvf->dev, page, 542 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 543 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 544 return (dma_addr_t)NULL; 545 return iova; 546 } 547 548 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 549 dma_addr_t addr, size_t size, 550 enum dma_data_direction dir) 551 { 552 dma_unmap_page_attrs(pfvf->dev, addr, size, 553 dir, DMA_ATTR_SKIP_CPU_SYNC); 554 } 555 556 /* MSI-X APIs */ 557 void otx2_free_cints(struct otx2_nic *pfvf, int n); 558 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 559 int otx2_set_mac_address(struct net_device *netdev, void *p); 560 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 561 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 562 void otx2_get_mac_from_af(struct net_device *netdev); 563 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 564 int otx2_config_pause_frm(struct otx2_nic *pfvf); 565 566 /* RVU block related APIs */ 567 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 568 int otx2_detach_resources(struct mbox *mbox); 569 int otx2_config_npa(struct otx2_nic *pfvf); 570 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 571 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 572 void otx2_aura_pool_free(struct otx2_nic *pfvf); 573 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 574 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 575 int otx2_config_nix(struct otx2_nic *pfvf); 576 int otx2_config_nix_queues(struct otx2_nic *pfvf); 577 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl); 578 int otx2_txsch_alloc(struct otx2_nic *pfvf); 579 int otx2_txschq_stop(struct otx2_nic *pfvf); 580 void otx2_sqb_flush(struct otx2_nic *pfvf); 581 dma_addr_t otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 582 gfp_t gfp); 583 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 584 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 585 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 586 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 587 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 588 589 /* RSS configuration APIs*/ 590 int otx2_rss_init(struct otx2_nic *pfvf); 591 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 592 void otx2_set_rss_key(struct otx2_nic *pfvf); 593 int otx2_set_rss_table(struct otx2_nic *pfvf); 594 595 /* Mbox handlers */ 596 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 597 struct msix_offset_rsp *rsp); 598 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 599 struct npa_lf_alloc_rsp *rsp); 600 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 601 struct nix_lf_alloc_rsp *rsp); 602 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 603 struct nix_txsch_alloc_rsp *rsp); 604 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 605 struct cgx_stats_rsp *rsp); 606 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 607 struct nix_bp_cfg_rsp *rsp); 608 609 /* Device stats APIs */ 610 void otx2_get_dev_stats(struct otx2_nic *pfvf); 611 void otx2_get_stats64(struct net_device *netdev, 612 struct rtnl_link_stats64 *stats); 613 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 614 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 615 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 616 void otx2_set_ethtool_ops(struct net_device *netdev); 617 618 int otx2_open(struct net_device *netdev); 619 int otx2_stop(struct net_device *netdev); 620 int otx2_set_real_num_queues(struct net_device *netdev, 621 int tx_queues, int rx_queues); 622 #endif /* OTX2_COMMON_H */ 623