1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_COMMON_H 9 #define OTX2_COMMON_H 10 11 #include <linux/ethtool.h> 12 #include <linux/pci.h> 13 #include <linux/iommu.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/ptp_clock_kernel.h> 16 #include <linux/timecounter.h> 17 #include <linux/soc/marvell/octeontx2/asm.h> 18 #include <net/macsec.h> 19 #include <net/pkt_cls.h> 20 #include <net/devlink.h> 21 #include <linux/time64.h> 22 #include <linux/dim.h> 23 #include <uapi/linux/if_macsec.h> 24 25 #include <mbox.h> 26 #include <npc.h> 27 #include "otx2_reg.h" 28 #include "otx2_txrx.h" 29 #include "otx2_devlink.h" 30 #include <rvu_trace.h> 31 #include "qos.h" 32 33 /* IPv4 flag more fragment bit */ 34 #define IPV4_FLAG_MORE 0x20 35 36 /* PCI device IDs */ 37 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 38 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 39 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 40 41 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 42 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00 43 44 /* PCI BAR nos */ 45 #define PCI_CFG_REG_BAR_NUM 2 46 #define PCI_MBOX_BAR_NUM 4 47 48 #define NAME_SIZE 32 49 50 #ifdef CONFIG_DCB 51 /* Max priority supported for PFC */ 52 #define NIX_PF_PFC_PRIO_MAX 8 53 #endif 54 55 enum arua_mapped_qtypes { 56 AURA_NIX_RQ, 57 AURA_NIX_SQ, 58 }; 59 60 /* NIX LF interrupts range*/ 61 #define NIX_LF_QINT_VEC_START 0x00 62 #define NIX_LF_CINT_VEC_START 0x40 63 #define NIX_LF_GINT_VEC 0x80 64 #define NIX_LF_ERR_VEC 0x81 65 #define NIX_LF_POISON_VEC 0x82 66 67 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 68 #define SEND_CQ_SKID 2000 69 70 #define OTX2_GET_RX_STATS(reg) \ 71 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 72 #define OTX2_GET_TX_STATS(reg) \ 73 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 74 75 struct otx2_lmt_info { 76 u64 lmt_addr; 77 u16 lmt_id; 78 }; 79 /* RSS configuration */ 80 struct otx2_rss_ctx { 81 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 82 }; 83 84 struct otx2_rss_info { 85 u8 enable; 86 u32 flowkey_cfg; 87 u16 rss_size; 88 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 89 u8 key[RSS_HASH_KEY_SIZE]; 90 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 91 }; 92 93 /* NIX (or NPC) RX errors */ 94 enum otx2_errlvl { 95 NPC_ERRLVL_RE, 96 NPC_ERRLVL_LID_LA, 97 NPC_ERRLVL_LID_LB, 98 NPC_ERRLVL_LID_LC, 99 NPC_ERRLVL_LID_LD, 100 NPC_ERRLVL_LID_LE, 101 NPC_ERRLVL_LID_LF, 102 NPC_ERRLVL_LID_LG, 103 NPC_ERRLVL_LID_LH, 104 NPC_ERRLVL_NIX = 0x0F, 105 }; 106 107 enum otx2_errcodes_re { 108 /* NPC_ERRLVL_RE errcodes */ 109 ERRCODE_FCS = 0x7, 110 ERRCODE_FCS_RCV = 0x8, 111 ERRCODE_UNDERSIZE = 0x10, 112 ERRCODE_OVERSIZE = 0x11, 113 ERRCODE_OL2_LEN_MISMATCH = 0x12, 114 /* NPC_ERRLVL_NIX errcodes */ 115 ERRCODE_OL3_LEN = 0x10, 116 ERRCODE_OL4_LEN = 0x11, 117 ERRCODE_OL4_CSUM = 0x12, 118 ERRCODE_IL3_LEN = 0x20, 119 ERRCODE_IL4_LEN = 0x21, 120 ERRCODE_IL4_CSUM = 0x22, 121 }; 122 123 /* NIX TX stats */ 124 enum nix_stat_lf_tx { 125 TX_UCAST = 0x0, 126 TX_BCAST = 0x1, 127 TX_MCAST = 0x2, 128 TX_DROP = 0x3, 129 TX_OCTS = 0x4, 130 TX_STATS_ENUM_LAST, 131 }; 132 133 /* NIX RX stats */ 134 enum nix_stat_lf_rx { 135 RX_OCTS = 0x0, 136 RX_UCAST = 0x1, 137 RX_BCAST = 0x2, 138 RX_MCAST = 0x3, 139 RX_DROP = 0x4, 140 RX_DROP_OCTS = 0x5, 141 RX_FCS = 0x6, 142 RX_ERR = 0x7, 143 RX_DRP_BCAST = 0x8, 144 RX_DRP_MCAST = 0x9, 145 RX_DRP_L3BCAST = 0xa, 146 RX_DRP_L3MCAST = 0xb, 147 RX_STATS_ENUM_LAST, 148 }; 149 150 struct otx2_dev_stats { 151 u64 rx_bytes; 152 u64 rx_frames; 153 u64 rx_ucast_frames; 154 u64 rx_bcast_frames; 155 u64 rx_mcast_frames; 156 u64 rx_drops; 157 158 u64 tx_bytes; 159 u64 tx_frames; 160 u64 tx_ucast_frames; 161 u64 tx_bcast_frames; 162 u64 tx_mcast_frames; 163 u64 tx_drops; 164 }; 165 166 /* Driver counted stats */ 167 struct otx2_drv_stats { 168 atomic_t rx_fcs_errs; 169 atomic_t rx_oversize_errs; 170 atomic_t rx_undersize_errs; 171 atomic_t rx_csum_errs; 172 atomic_t rx_len_errs; 173 atomic_t rx_other_errs; 174 }; 175 176 struct mbox { 177 struct otx2_mbox mbox; 178 struct work_struct mbox_wrk; 179 struct otx2_mbox mbox_up; 180 struct work_struct mbox_up_wrk; 181 struct otx2_nic *pfvf; 182 void *bbuf_base; /* Bounce buffer for mbox memory */ 183 struct mutex lock; /* serialize mailbox access */ 184 int num_msgs; /* mbox number of messages */ 185 int up_num_msgs; /* mbox_up number of messages */ 186 }; 187 188 /* Egress rate limiting definitions */ 189 #define MAX_BURST_EXPONENT 0x0FULL 190 #define MAX_BURST_MANTISSA 0xFFULL 191 #define MAX_BURST_SIZE 130816ULL 192 #define MAX_RATE_DIVIDER_EXPONENT 12ULL 193 #define MAX_RATE_EXPONENT 0x0FULL 194 #define MAX_RATE_MANTISSA 0xFFULL 195 196 /* Bitfields in NIX_TLX_PIR register */ 197 #define TLX_RATE_MANTISSA GENMASK_ULL(8, 1) 198 #define TLX_RATE_EXPONENT GENMASK_ULL(12, 9) 199 #define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13) 200 #define TLX_BURST_MANTISSA GENMASK_ULL(36, 29) 201 #define TLX_BURST_EXPONENT GENMASK_ULL(40, 37) 202 203 struct otx2_hw { 204 struct pci_dev *pdev; 205 struct otx2_rss_info rss_info; 206 u16 rx_queues; 207 u16 tx_queues; 208 u16 xdp_queues; 209 u16 tc_tx_queues; 210 u16 non_qos_queues; /* tx queues plus xdp queues */ 211 u16 max_queues; 212 u16 pool_cnt; 213 u16 rqpool_cnt; 214 u16 sqpool_cnt; 215 216 #define OTX2_DEFAULT_RBUF_LEN 2048 217 u16 rbuf_len; 218 u32 xqe_size; 219 220 /* NPA */ 221 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 222 u32 stack_pg_bytes; /* Size of stack page */ 223 u16 sqb_size; 224 225 /* NIX */ 226 u8 txschq_link_cfg_lvl; 227 u8 txschq_aggr_lvl_rr_prio; 228 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 229 u16 matchall_ipolicer; 230 u32 dwrr_mtu; 231 u8 smq_link_type; 232 233 /* HW settings, coalescing etc */ 234 u16 rx_chan_base; 235 u16 tx_chan_base; 236 u16 cq_qcount_wait; 237 u16 cq_ecount_wait; 238 u16 rq_skid; 239 u8 cq_time_wait; 240 241 /* Segmentation */ 242 u8 lso_tsov4_idx; 243 u8 lso_tsov6_idx; 244 u8 lso_udpv4_idx; 245 u8 lso_udpv6_idx; 246 247 /* RSS */ 248 u8 flowkey_alg_idx; 249 250 /* MSI-X */ 251 u8 cint_cnt; /* CQ interrupt count */ 252 u16 npa_msixoff; /* Offset of NPA vectors */ 253 u16 nix_msixoff; /* Offset of NIX vectors */ 254 char *irq_name; 255 cpumask_var_t *affinity_mask; 256 257 /* Stats */ 258 struct otx2_dev_stats dev_stats; 259 struct otx2_drv_stats drv_stats; 260 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 261 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 262 u64 cgx_fec_corr_blks; 263 u64 cgx_fec_uncorr_blks; 264 u8 cgx_links; /* No. of CGX links present in HW */ 265 u8 lbk_links; /* No. of LBK links present in HW */ 266 u8 tx_link; /* Transmit channel link number */ 267 #define HW_TSO 0 268 #define CN10K_MBOX 1 269 #define CN10K_LMTST 2 270 #define CN10K_RPM 3 271 #define CN10K_PTP_ONESTEP 4 272 #define CN10K_HW_MACSEC 5 273 #define QOS_CIR_PIR_SUPPORT 6 274 unsigned long cap_flag; 275 276 #define LMT_LINE_SIZE 128 277 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 278 u64 *lmt_base; 279 struct otx2_lmt_info __percpu *lmt_info; 280 }; 281 282 enum vfperm { 283 OTX2_RESET_VF_PERM, 284 OTX2_TRUSTED_VF, 285 }; 286 287 struct otx2_vf_config { 288 struct otx2_nic *pf; 289 struct delayed_work link_event_work; 290 bool intf_down; /* interface was either configured or not */ 291 u8 mac[ETH_ALEN]; 292 u16 vlan; 293 int tx_vtag_idx; 294 bool trusted; 295 }; 296 297 struct flr_work { 298 struct work_struct work; 299 struct otx2_nic *pf; 300 }; 301 302 struct refill_work { 303 struct delayed_work pool_refill_work; 304 struct otx2_nic *pf; 305 }; 306 307 /* PTPv2 originTimestamp structure */ 308 struct ptpv2_tstamp { 309 __be16 seconds_msb; /* 16 bits + */ 310 __be32 seconds_lsb; /* 32 bits = 48 bits*/ 311 __be32 nanoseconds; 312 } __packed; 313 314 struct otx2_ptp { 315 struct ptp_clock_info ptp_info; 316 struct ptp_clock *ptp_clock; 317 struct otx2_nic *nic; 318 319 struct cyclecounter cycle_counter; 320 struct timecounter time_counter; 321 322 struct delayed_work extts_work; 323 u64 last_extts; 324 u64 thresh; 325 326 struct ptp_pin_desc extts_config; 327 u64 (*convert_rx_ptp_tstmp)(u64 timestamp); 328 u64 (*convert_tx_ptp_tstmp)(u64 timestamp); 329 struct delayed_work synctstamp_work; 330 u64 tstamp; 331 u32 base_ns; 332 }; 333 334 #define OTX2_HW_TIMESTAMP_LEN 8 335 336 struct otx2_mac_table { 337 u8 addr[ETH_ALEN]; 338 u16 mcam_entry; 339 bool inuse; 340 }; 341 342 struct otx2_flow_config { 343 u16 *flow_ent; 344 u16 *def_ent; 345 u16 nr_flows; 346 #define OTX2_DEFAULT_FLOWCOUNT 16 347 #define OTX2_MAX_UNICAST_FLOWS 8 348 #define OTX2_MAX_VLAN_FLOWS 1 349 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 350 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \ 351 OTX2_MAX_UNICAST_FLOWS + \ 352 OTX2_MAX_VLAN_FLOWS) 353 u16 unicast_offset; 354 u16 rx_vlan_offset; 355 u16 vf_vlan_offset; 356 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 357 #define OTX2_VF_VLAN_RX_INDEX 0 358 #define OTX2_VF_VLAN_TX_INDEX 1 359 u32 *bmap_to_dmacindex; 360 unsigned long *dmacflt_bmap; 361 struct list_head flow_list; 362 u32 dmacflt_max_flows; 363 u16 max_flows; 364 struct list_head flow_list_tc; 365 bool ntuple; 366 }; 367 368 struct dev_hw_ops { 369 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); 370 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 371 int size, int qidx); 372 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 373 void (*aura_freeptr)(void *dev, int aura, u64 buf); 374 }; 375 376 #define CN10K_MCS_SA_PER_SC 4 377 378 /* Stats which need to be accumulated in software because 379 * of shared counters in hardware. 380 */ 381 struct cn10k_txsc_stats { 382 u64 InPktsUntagged; 383 u64 InPktsNoTag; 384 u64 InPktsBadTag; 385 u64 InPktsUnknownSCI; 386 u64 InPktsNoSCI; 387 u64 InPktsOverrun; 388 }; 389 390 struct cn10k_rxsc_stats { 391 u64 InOctetsValidated; 392 u64 InOctetsDecrypted; 393 u64 InPktsUnchecked; 394 u64 InPktsDelayed; 395 u64 InPktsOK; 396 u64 InPktsInvalid; 397 u64 InPktsLate; 398 u64 InPktsNotValid; 399 u64 InPktsNotUsingSA; 400 u64 InPktsUnusedSA; 401 }; 402 403 struct cn10k_mcs_txsc { 404 struct macsec_secy *sw_secy; 405 struct cn10k_txsc_stats stats; 406 struct list_head entry; 407 enum macsec_validation_type last_validate_frames; 408 bool last_replay_protect; 409 u16 hw_secy_id_tx; 410 u16 hw_secy_id_rx; 411 u16 hw_flow_id; 412 u16 hw_sc_id; 413 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 414 u8 sa_bmap; 415 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 416 u8 encoding_sa; 417 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 418 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 419 bool vlan_dev; /* macsec running on VLAN ? */ 420 }; 421 422 struct cn10k_mcs_rxsc { 423 struct macsec_secy *sw_secy; 424 struct macsec_rx_sc *sw_rxsc; 425 struct cn10k_rxsc_stats stats; 426 struct list_head entry; 427 u16 hw_flow_id; 428 u16 hw_sc_id; 429 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 430 u8 sa_bmap; 431 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 432 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 433 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 434 }; 435 436 struct cn10k_mcs_cfg { 437 struct list_head txsc_list; 438 struct list_head rxsc_list; 439 }; 440 441 struct otx2_nic { 442 void __iomem *reg_base; 443 struct net_device *netdev; 444 struct dev_hw_ops *hw_ops; 445 void *iommu_domain; 446 u16 tx_max_pktlen; 447 u16 rbsize; /* Receive buffer size */ 448 449 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 450 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 451 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 452 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 453 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 454 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 455 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 456 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 457 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 458 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 459 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 460 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 461 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 462 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 463 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 464 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15) 465 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) 466 u64 flags; 467 u64 *cq_op_addr; 468 469 struct bpf_prog *xdp_prog; 470 struct otx2_qset qset; 471 struct otx2_hw hw; 472 struct pci_dev *pdev; 473 struct device *dev; 474 475 /* Mbox */ 476 struct mbox mbox; 477 struct mbox *mbox_pfvf; 478 struct workqueue_struct *mbox_wq; 479 struct workqueue_struct *mbox_pfvf_wq; 480 481 u8 total_vfs; 482 u16 pcifunc; /* RVU PF_FUNC */ 483 u16 bpid[NIX_MAX_BPID_CHAN]; 484 struct otx2_vf_config *vf_configs; 485 struct cgx_link_user_info linfo; 486 487 /* NPC MCAM */ 488 struct otx2_flow_config *flow_cfg; 489 struct otx2_mac_table *mac_table; 490 491 u64 reset_count; 492 struct work_struct reset_task; 493 struct workqueue_struct *flr_wq; 494 struct flr_work *flr_wrk; 495 struct refill_work *refill_wrk; 496 struct workqueue_struct *otx2_wq; 497 struct work_struct rx_mode_work; 498 499 /* Ethtool stuff */ 500 u32 msg_enable; 501 502 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 503 int nix_blkaddr; 504 /* LMTST Lines info */ 505 struct qmem *dync_lmt; 506 u16 tot_lmt_lines; 507 u16 npa_lmt_lines; 508 u32 nix_lmt_size; 509 510 struct otx2_ptp *ptp; 511 struct hwtstamp_config tstamp; 512 513 unsigned long rq_bmap; 514 515 /* Devlink */ 516 struct otx2_devlink *dl; 517 #ifdef CONFIG_DCB 518 /* PFC */ 519 u8 pfc_en; 520 u8 *queue_to_pfc_map; 521 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 522 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX]; 523 #endif 524 /* qos */ 525 struct otx2_qos qos; 526 527 /* napi event count. It is needed for adaptive irq coalescing. */ 528 u32 napi_events; 529 530 #if IS_ENABLED(CONFIG_MACSEC) 531 struct cn10k_mcs_cfg *macsec_cfg; 532 #endif 533 }; 534 535 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 536 { 537 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF; 538 } 539 540 static inline bool is_96xx_A0(struct pci_dev *pdev) 541 { 542 return (pdev->revision == 0x00) && 543 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 544 } 545 546 static inline bool is_96xx_B0(struct pci_dev *pdev) 547 { 548 return (pdev->revision == 0x01) && 549 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 550 } 551 552 /* REVID for PCIe devices. 553 * Bits 0..1: minor pass, bit 3..2: major pass 554 * bits 7..4: midr id 555 */ 556 #define PCI_REVISION_ID_96XX 0x00 557 #define PCI_REVISION_ID_95XX 0x10 558 #define PCI_REVISION_ID_95XXN 0x20 559 #define PCI_REVISION_ID_98XX 0x30 560 #define PCI_REVISION_ID_95XXMM 0x40 561 #define PCI_REVISION_ID_95XXO 0xE0 562 563 static inline bool is_dev_otx2(struct pci_dev *pdev) 564 { 565 u8 midr = pdev->revision & 0xF0; 566 567 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 568 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 569 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 570 } 571 572 static inline bool is_dev_cn10kb(struct pci_dev *pdev) 573 { 574 return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF; 575 } 576 577 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 578 { 579 struct otx2_hw *hw = &pfvf->hw; 580 581 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 582 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 583 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 584 585 __set_bit(HW_TSO, &hw->cap_flag); 586 587 if (is_96xx_A0(pfvf->pdev)) { 588 __clear_bit(HW_TSO, &hw->cap_flag); 589 590 /* Time based irq coalescing is not supported */ 591 pfvf->hw.cq_qcount_wait = 0x0; 592 593 /* Due to HW issue previous silicons required minimum 594 * 600 unused CQE to avoid CQ overflow. 595 */ 596 pfvf->hw.rq_skid = 600; 597 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 598 } 599 if (is_96xx_B0(pfvf->pdev)) 600 __clear_bit(HW_TSO, &hw->cap_flag); 601 602 if (!is_dev_otx2(pfvf->pdev)) { 603 __set_bit(CN10K_MBOX, &hw->cap_flag); 604 __set_bit(CN10K_LMTST, &hw->cap_flag); 605 __set_bit(CN10K_RPM, &hw->cap_flag); 606 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag); 607 __set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag); 608 } 609 610 if (is_dev_cn10kb(pfvf->pdev)) 611 __set_bit(CN10K_HW_MACSEC, &hw->cap_flag); 612 } 613 614 /* Register read/write APIs */ 615 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 616 { 617 u64 blkaddr; 618 619 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 620 case BLKTYPE_NIX: 621 blkaddr = nic->nix_blkaddr; 622 break; 623 case BLKTYPE_NPA: 624 blkaddr = BLKADDR_NPA; 625 break; 626 default: 627 blkaddr = BLKADDR_RVUM; 628 break; 629 } 630 631 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 632 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 633 634 return nic->reg_base + offset; 635 } 636 637 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 638 { 639 void __iomem *addr = otx2_get_regaddr(nic, offset); 640 641 writeq(val, addr); 642 } 643 644 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 645 { 646 void __iomem *addr = otx2_get_regaddr(nic, offset); 647 648 return readq(addr); 649 } 650 651 /* Mbox bounce buffer APIs */ 652 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 653 { 654 struct otx2_mbox *otx2_mbox; 655 struct otx2_mbox_dev *mdev; 656 657 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 658 if (!mbox->bbuf_base) 659 return -ENOMEM; 660 661 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 662 * prepare all mbox messages in bounce buffer instead of directly 663 * in hw mbox memory. 664 */ 665 otx2_mbox = &mbox->mbox; 666 mdev = &otx2_mbox->dev[0]; 667 mdev->mbase = mbox->bbuf_base; 668 669 otx2_mbox = &mbox->mbox_up; 670 mdev = &otx2_mbox->dev[0]; 671 mdev->mbase = mbox->bbuf_base; 672 return 0; 673 } 674 675 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 676 { 677 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 678 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 679 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 680 struct mbox_hdr *hdr; 681 u64 msg_size; 682 683 if (mdev->mbase == hw_mbase) 684 return; 685 686 hdr = hw_mbase + mbox->rx_start; 687 msg_size = hdr->msg_size; 688 689 if (msg_size > mbox->rx_size - msgs_offset) 690 msg_size = mbox->rx_size - msgs_offset; 691 692 /* Copy mbox messages from mbox memory to bounce buffer */ 693 memcpy(mdev->mbase + mbox->rx_start, 694 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 695 } 696 697 /* With the absence of API for 128-bit IO memory access for arm64, 698 * implement required operations at place. 699 */ 700 #if defined(CONFIG_ARM64) 701 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 702 { 703 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 704 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 705 } 706 707 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 708 { 709 u64 result; 710 711 __asm__ volatile(".cpu generic+lse\n" 712 "ldadd %x[i], %x[r], [%[b]]" 713 : [r]"=r"(result), "+m"(*ptr) 714 : [i]"r"(incr), [b]"r"(ptr) 715 : "memory"); 716 return result; 717 } 718 719 #else 720 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 721 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 722 #endif 723 724 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 725 u64 *ptrs, u64 num_ptrs) 726 { 727 struct otx2_lmt_info *lmt_info; 728 u64 size = 0, count_eot = 0; 729 u64 tar_addr, val = 0; 730 731 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); 732 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 733 /* LMTID is same as AURA Id */ 734 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); 735 /* Set if [127:64] of last 128bit word has a valid pointer */ 736 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 737 /* Set AURA ID to free pointer */ 738 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 739 /* Target address for LMTST flush tells HW how many 128bit 740 * words are valid from NPA_LF_AURA_BATCH_FREE0. 741 * 742 * tar_addr[6:4] is LMTST size-1 in units of 128b. 743 */ 744 if (num_ptrs > 2) { 745 size = (sizeof(u64) * num_ptrs) / 16; 746 if (!count_eot) 747 size++; 748 tar_addr |= ((size - 1) & 0x7) << 4; 749 } 750 dma_wmb(); 751 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); 752 /* Perform LMTST flush */ 753 cn10k_lmt_flush(val, tar_addr); 754 } 755 756 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 757 { 758 struct otx2_nic *pfvf = dev; 759 u64 ptrs[2]; 760 761 ptrs[1] = buf; 762 get_cpu(); 763 /* Free only one buffer at time during init and teardown */ 764 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); 765 put_cpu(); 766 } 767 768 /* Alloc pointer from pool/aura */ 769 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 770 { 771 u64 *ptr = (__force u64 *)otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_ALLOCX(0)); 772 u64 incr = (u64)aura | BIT_ULL(63); 773 774 return otx2_atomic64_add(incr, ptr); 775 } 776 777 /* Free pointer to a pool/aura */ 778 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 779 { 780 struct otx2_nic *pfvf = dev; 781 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 782 783 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 784 } 785 786 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 787 { 788 if (type == AURA_NIX_SQ) 789 return pfvf->hw.rqpool_cnt + idx; 790 791 /* AURA_NIX_RQ */ 792 return idx; 793 } 794 795 /* Mbox APIs */ 796 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 797 { 798 int err; 799 800 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 801 return 0; 802 otx2_mbox_msg_send(&mbox->mbox, 0); 803 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 804 if (err) 805 return err; 806 807 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 808 } 809 810 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 811 { 812 int err; 813 814 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 815 return 0; 816 otx2_mbox_msg_send(&mbox->mbox_up, devid); 817 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 818 if (err) 819 return err; 820 821 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 822 } 823 824 /* Use this API to send mbox msgs in atomic context 825 * where sleeping is not allowed 826 */ 827 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 828 { 829 int err; 830 831 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 832 return 0; 833 otx2_mbox_msg_send(&mbox->mbox, 0); 834 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 835 if (err) 836 return err; 837 838 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 839 } 840 841 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 842 static struct _req_type __maybe_unused \ 843 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 844 { \ 845 struct _req_type *req; \ 846 \ 847 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 848 &mbox->mbox, 0, sizeof(struct _req_type), \ 849 sizeof(struct _rsp_type)); \ 850 if (!req) \ 851 return NULL; \ 852 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 853 req->hdr.id = _id; \ 854 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 855 return req; \ 856 } 857 858 MBOX_MESSAGES 859 #undef M 860 861 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 862 int \ 863 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 864 struct _req_type *req, \ 865 struct _rsp_type *rsp); \ 866 867 MBOX_UP_CGX_MESSAGES 868 MBOX_UP_MCS_MESSAGES 869 #undef M 870 871 /* Time to wait before watchdog kicks off */ 872 #define OTX2_TX_TIMEOUT (100 * HZ) 873 874 #define RVU_PFVF_PF_SHIFT 10 875 #define RVU_PFVF_PF_MASK 0x3F 876 #define RVU_PFVF_FUNC_SHIFT 0 877 #define RVU_PFVF_FUNC_MASK 0x3FF 878 879 static inline bool is_otx2_vf(u16 pcifunc) 880 { 881 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 882 } 883 884 static inline int rvu_get_pf(u16 pcifunc) 885 { 886 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 887 } 888 889 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 890 struct page *page, 891 size_t offset, size_t size, 892 enum dma_data_direction dir) 893 { 894 dma_addr_t iova; 895 896 iova = dma_map_page_attrs(pfvf->dev, page, 897 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 898 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 899 return (dma_addr_t)NULL; 900 return iova; 901 } 902 903 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 904 dma_addr_t addr, size_t size, 905 enum dma_data_direction dir) 906 { 907 dma_unmap_page_attrs(pfvf->dev, addr, size, 908 dir, DMA_ATTR_SKIP_CPU_SYNC); 909 } 910 911 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx) 912 { 913 u16 smq; 914 #ifdef CONFIG_DCB 915 if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx]) 916 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx]; 917 #endif 918 /* check if qidx falls under QOS queues */ 919 if (qidx >= pfvf->hw.non_qos_queues) 920 smq = pfvf->qos.qid_to_sqmap[qidx - pfvf->hw.non_qos_queues]; 921 else 922 smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 923 924 return smq; 925 } 926 927 static inline u16 otx2_get_total_tx_queues(struct otx2_nic *pfvf) 928 { 929 return pfvf->hw.non_qos_queues + pfvf->hw.tc_tx_queues; 930 } 931 932 static inline u64 otx2_convert_rate(u64 rate) 933 { 934 u64 converted_rate; 935 936 /* Convert bytes per second to Mbps */ 937 converted_rate = rate * 8; 938 converted_rate = max_t(u64, converted_rate / 1000000, 1); 939 940 return converted_rate; 941 } 942 943 /* MSI-X APIs */ 944 void otx2_free_cints(struct otx2_nic *pfvf, int n); 945 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 946 int otx2_set_mac_address(struct net_device *netdev, void *p); 947 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 948 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 949 void otx2_get_mac_from_af(struct net_device *netdev); 950 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 951 int otx2_config_pause_frm(struct otx2_nic *pfvf); 952 void otx2_setup_segmentation(struct otx2_nic *pfvf); 953 954 /* RVU block related APIs */ 955 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 956 int otx2_detach_resources(struct mbox *mbox); 957 int otx2_config_npa(struct otx2_nic *pfvf); 958 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 959 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 960 void otx2_aura_pool_free(struct otx2_nic *pfvf); 961 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 962 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 963 int otx2_config_nix(struct otx2_nic *pfvf); 964 int otx2_config_nix_queues(struct otx2_nic *pfvf); 965 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en); 966 int otx2_txsch_alloc(struct otx2_nic *pfvf); 967 void otx2_txschq_stop(struct otx2_nic *pfvf); 968 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq); 969 void otx2_sqb_flush(struct otx2_nic *pfvf); 970 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 971 dma_addr_t *dma); 972 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 973 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 974 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 975 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx); 976 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 977 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura); 978 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 979 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 980 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 981 dma_addr_t *dma); 982 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 983 int stack_pages, int numptrs, int buf_size, int type); 984 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 985 int pool_id, int numptrs); 986 987 /* RSS configuration APIs*/ 988 int otx2_rss_init(struct otx2_nic *pfvf); 989 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 990 void otx2_set_rss_key(struct otx2_nic *pfvf); 991 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 992 993 /* Mbox handlers */ 994 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 995 struct msix_offset_rsp *rsp); 996 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 997 struct npa_lf_alloc_rsp *rsp); 998 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 999 struct nix_lf_alloc_rsp *rsp); 1000 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1001 struct nix_txsch_alloc_rsp *rsp); 1002 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1003 struct cgx_stats_rsp *rsp); 1004 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1005 struct cgx_fec_stats_rsp *rsp); 1006 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 1007 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1008 struct nix_bp_cfg_rsp *rsp); 1009 1010 /* Device stats APIs */ 1011 void otx2_get_dev_stats(struct otx2_nic *pfvf); 1012 void otx2_get_stats64(struct net_device *netdev, 1013 struct rtnl_link_stats64 *stats); 1014 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 1015 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 1016 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 1017 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 1018 void otx2_set_ethtool_ops(struct net_device *netdev); 1019 void otx2vf_set_ethtool_ops(struct net_device *netdev); 1020 1021 int otx2_open(struct net_device *netdev); 1022 int otx2_stop(struct net_device *netdev); 1023 int otx2_set_real_num_queues(struct net_device *netdev, 1024 int tx_queues, int rx_queues); 1025 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd); 1026 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr); 1027 1028 /* MCAM filter related APIs */ 1029 int otx2_mcam_flow_init(struct otx2_nic *pf); 1030 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 1031 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 1032 void otx2_mcam_flow_del(struct otx2_nic *pf); 1033 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 1034 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 1035 int otx2_get_flow(struct otx2_nic *pfvf, 1036 struct ethtool_rxnfc *nfc, u32 location); 1037 int otx2_get_all_flows(struct otx2_nic *pfvf, 1038 struct ethtool_rxnfc *nfc, u32 *rule_locs); 1039 int otx2_add_flow(struct otx2_nic *pfvf, 1040 struct ethtool_rxnfc *nfc); 1041 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 1042 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 1043 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 1044 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 1045 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 1046 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 1047 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 1048 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx); 1049 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 1050 int otx2_handle_ntuple_tc_features(struct net_device *netdev, 1051 netdev_features_t features); 1052 int otx2_smq_flush(struct otx2_nic *pfvf, int smq); 1053 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1054 u64 iova, int size); 1055 1056 /* tc support */ 1057 int otx2_init_tc(struct otx2_nic *nic); 1058 void otx2_shutdown_tc(struct otx2_nic *nic); 1059 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 1060 void *type_data); 1061 /* CGX/RPM DMAC filters support */ 1062 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 1063 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1064 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1065 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos); 1066 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 1067 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 1068 1069 #ifdef CONFIG_DCB 1070 /* DCB support*/ 1071 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable); 1072 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf); 1073 int otx2_dcbnl_set_ops(struct net_device *dev); 1074 /* PFC support */ 1075 int otx2_pfc_txschq_config(struct otx2_nic *pfvf); 1076 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf); 1077 int otx2_pfc_txschq_update(struct otx2_nic *pfvf); 1078 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf); 1079 #endif 1080 1081 #if IS_ENABLED(CONFIG_MACSEC) 1082 /* MACSEC offload support */ 1083 int cn10k_mcs_init(struct otx2_nic *pfvf); 1084 void cn10k_mcs_free(struct otx2_nic *pfvf); 1085 void cn10k_handle_mcs_event(struct otx2_nic *pfvf, struct mcs_intr_info *event); 1086 #else 1087 static inline int cn10k_mcs_init(struct otx2_nic *pfvf) { return 0; } 1088 static inline void cn10k_mcs_free(struct otx2_nic *pfvf) {} 1089 static inline void cn10k_handle_mcs_event(struct otx2_nic *pfvf, 1090 struct mcs_intr_info *event) 1091 {} 1092 #endif /* CONFIG_MACSEC */ 1093 1094 /* qos support */ 1095 static inline void otx2_qos_init(struct otx2_nic *pfvf, int qos_txqs) 1096 { 1097 struct otx2_hw *hw = &pfvf->hw; 1098 1099 hw->tc_tx_queues = qos_txqs; 1100 INIT_LIST_HEAD(&pfvf->qos.qos_tree); 1101 mutex_init(&pfvf->qos.qos_lock); 1102 } 1103 1104 static inline void otx2_shutdown_qos(struct otx2_nic *pfvf) 1105 { 1106 mutex_destroy(&pfvf->qos.qos_lock); 1107 } 1108 1109 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1110 struct net_device *sb_dev); 1111 int otx2_get_txq_by_classid(struct otx2_nic *pfvf, u16 classid); 1112 void otx2_qos_config_txschq(struct otx2_nic *pfvf); 1113 void otx2_clean_qos_queues(struct otx2_nic *pfvf); 1114 #endif /* OTX2_COMMON_H */ 1115