1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_COMMON_H 9 #define OTX2_COMMON_H 10 11 #include <linux/ethtool.h> 12 #include <linux/pci.h> 13 #include <linux/iommu.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/ptp_clock_kernel.h> 16 #include <linux/timecounter.h> 17 #include <linux/soc/marvell/octeontx2/asm.h> 18 #include <net/macsec.h> 19 #include <net/pkt_cls.h> 20 #include <net/devlink.h> 21 #include <linux/time64.h> 22 #include <linux/dim.h> 23 #include <uapi/linux/if_macsec.h> 24 25 #include <mbox.h> 26 #include <npc.h> 27 #include "otx2_reg.h" 28 #include "otx2_txrx.h" 29 #include "otx2_devlink.h" 30 #include <rvu_trace.h> 31 #include "qos.h" 32 33 /* IPv4 flag more fragment bit */ 34 #define IPV4_FLAG_MORE 0x20 35 36 /* PCI device IDs */ 37 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 38 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 39 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 40 41 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 42 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00 43 44 /* PCI BAR nos */ 45 #define PCI_CFG_REG_BAR_NUM 2 46 #define PCI_MBOX_BAR_NUM 4 47 48 #define NAME_SIZE 32 49 50 #ifdef CONFIG_DCB 51 /* Max priority supported for PFC */ 52 #define NIX_PF_PFC_PRIO_MAX 8 53 #endif 54 55 enum arua_mapped_qtypes { 56 AURA_NIX_RQ, 57 AURA_NIX_SQ, 58 }; 59 60 /* NIX LF interrupts range*/ 61 #define NIX_LF_QINT_VEC_START 0x00 62 #define NIX_LF_CINT_VEC_START 0x40 63 #define NIX_LF_GINT_VEC 0x80 64 #define NIX_LF_ERR_VEC 0x81 65 #define NIX_LF_POISON_VEC 0x82 66 67 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 68 #define SEND_CQ_SKID 2000 69 70 #define OTX2_GET_RX_STATS(reg) \ 71 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 72 #define OTX2_GET_TX_STATS(reg) \ 73 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 74 75 struct otx2_lmt_info { 76 u64 lmt_addr; 77 u16 lmt_id; 78 }; 79 /* RSS configuration */ 80 struct otx2_rss_ctx { 81 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 82 }; 83 84 struct otx2_rss_info { 85 u8 enable; 86 u32 flowkey_cfg; 87 u16 rss_size; 88 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 89 u8 key[RSS_HASH_KEY_SIZE]; 90 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 91 }; 92 93 /* NIX (or NPC) RX errors */ 94 enum otx2_errlvl { 95 NPC_ERRLVL_RE, 96 NPC_ERRLVL_LID_LA, 97 NPC_ERRLVL_LID_LB, 98 NPC_ERRLVL_LID_LC, 99 NPC_ERRLVL_LID_LD, 100 NPC_ERRLVL_LID_LE, 101 NPC_ERRLVL_LID_LF, 102 NPC_ERRLVL_LID_LG, 103 NPC_ERRLVL_LID_LH, 104 NPC_ERRLVL_NIX = 0x0F, 105 }; 106 107 enum otx2_errcodes_re { 108 /* NPC_ERRLVL_RE errcodes */ 109 ERRCODE_FCS = 0x7, 110 ERRCODE_FCS_RCV = 0x8, 111 ERRCODE_UNDERSIZE = 0x10, 112 ERRCODE_OVERSIZE = 0x11, 113 ERRCODE_OL2_LEN_MISMATCH = 0x12, 114 /* NPC_ERRLVL_NIX errcodes */ 115 ERRCODE_OL3_LEN = 0x10, 116 ERRCODE_OL4_LEN = 0x11, 117 ERRCODE_OL4_CSUM = 0x12, 118 ERRCODE_IL3_LEN = 0x20, 119 ERRCODE_IL4_LEN = 0x21, 120 ERRCODE_IL4_CSUM = 0x22, 121 }; 122 123 /* NIX TX stats */ 124 enum nix_stat_lf_tx { 125 TX_UCAST = 0x0, 126 TX_BCAST = 0x1, 127 TX_MCAST = 0x2, 128 TX_DROP = 0x3, 129 TX_OCTS = 0x4, 130 TX_STATS_ENUM_LAST, 131 }; 132 133 /* NIX RX stats */ 134 enum nix_stat_lf_rx { 135 RX_OCTS = 0x0, 136 RX_UCAST = 0x1, 137 RX_BCAST = 0x2, 138 RX_MCAST = 0x3, 139 RX_DROP = 0x4, 140 RX_DROP_OCTS = 0x5, 141 RX_FCS = 0x6, 142 RX_ERR = 0x7, 143 RX_DRP_BCAST = 0x8, 144 RX_DRP_MCAST = 0x9, 145 RX_DRP_L3BCAST = 0xa, 146 RX_DRP_L3MCAST = 0xb, 147 RX_STATS_ENUM_LAST, 148 }; 149 150 struct otx2_dev_stats { 151 u64 rx_bytes; 152 u64 rx_frames; 153 u64 rx_ucast_frames; 154 u64 rx_bcast_frames; 155 u64 rx_mcast_frames; 156 u64 rx_drops; 157 158 u64 tx_bytes; 159 u64 tx_frames; 160 u64 tx_ucast_frames; 161 u64 tx_bcast_frames; 162 u64 tx_mcast_frames; 163 u64 tx_drops; 164 }; 165 166 /* Driver counted stats */ 167 struct otx2_drv_stats { 168 atomic_t rx_fcs_errs; 169 atomic_t rx_oversize_errs; 170 atomic_t rx_undersize_errs; 171 atomic_t rx_csum_errs; 172 atomic_t rx_len_errs; 173 atomic_t rx_other_errs; 174 }; 175 176 struct mbox { 177 struct otx2_mbox mbox; 178 struct work_struct mbox_wrk; 179 struct otx2_mbox mbox_up; 180 struct work_struct mbox_up_wrk; 181 struct otx2_nic *pfvf; 182 void *bbuf_base; /* Bounce buffer for mbox memory */ 183 struct mutex lock; /* serialize mailbox access */ 184 int num_msgs; /* mbox number of messages */ 185 int up_num_msgs; /* mbox_up number of messages */ 186 }; 187 188 /* Egress rate limiting definitions */ 189 #define MAX_BURST_EXPONENT 0x0FULL 190 #define MAX_BURST_MANTISSA 0xFFULL 191 #define MAX_BURST_SIZE 130816ULL 192 #define MAX_RATE_DIVIDER_EXPONENT 12ULL 193 #define MAX_RATE_EXPONENT 0x0FULL 194 #define MAX_RATE_MANTISSA 0xFFULL 195 196 /* Bitfields in NIX_TLX_PIR register */ 197 #define TLX_RATE_MANTISSA GENMASK_ULL(8, 1) 198 #define TLX_RATE_EXPONENT GENMASK_ULL(12, 9) 199 #define TLX_RATE_DIVIDER_EXPONENT GENMASK_ULL(16, 13) 200 #define TLX_BURST_MANTISSA GENMASK_ULL(36, 29) 201 #define TLX_BURST_EXPONENT GENMASK_ULL(40, 37) 202 203 struct otx2_hw { 204 struct pci_dev *pdev; 205 struct otx2_rss_info rss_info; 206 u16 rx_queues; 207 u16 tx_queues; 208 u16 xdp_queues; 209 u16 tc_tx_queues; 210 u16 non_qos_queues; /* tx queues plus xdp queues */ 211 u16 max_queues; 212 u16 pool_cnt; 213 u16 rqpool_cnt; 214 u16 sqpool_cnt; 215 216 #define OTX2_DEFAULT_RBUF_LEN 2048 217 u16 rbuf_len; 218 u32 xqe_size; 219 220 /* NPA */ 221 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 222 u32 stack_pg_bytes; /* Size of stack page */ 223 u16 sqb_size; 224 225 /* NIX */ 226 u8 txschq_link_cfg_lvl; 227 u8 txschq_aggr_lvl_rr_prio; 228 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 229 u16 matchall_ipolicer; 230 u32 dwrr_mtu; 231 u8 smq_link_type; 232 233 /* HW settings, coalescing etc */ 234 u16 rx_chan_base; 235 u16 tx_chan_base; 236 u16 cq_qcount_wait; 237 u16 cq_ecount_wait; 238 u16 rq_skid; 239 u8 cq_time_wait; 240 241 /* Segmentation */ 242 u8 lso_tsov4_idx; 243 u8 lso_tsov6_idx; 244 u8 lso_udpv4_idx; 245 u8 lso_udpv6_idx; 246 247 /* RSS */ 248 u8 flowkey_alg_idx; 249 250 /* MSI-X */ 251 u8 cint_cnt; /* CQ interrupt count */ 252 u16 npa_msixoff; /* Offset of NPA vectors */ 253 u16 nix_msixoff; /* Offset of NIX vectors */ 254 char *irq_name; 255 cpumask_var_t *affinity_mask; 256 257 /* Stats */ 258 struct otx2_dev_stats dev_stats; 259 struct otx2_drv_stats drv_stats; 260 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 261 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 262 u64 cgx_fec_corr_blks; 263 u64 cgx_fec_uncorr_blks; 264 u8 cgx_links; /* No. of CGX links present in HW */ 265 u8 lbk_links; /* No. of LBK links present in HW */ 266 u8 tx_link; /* Transmit channel link number */ 267 #define HW_TSO 0 268 #define CN10K_MBOX 1 269 #define CN10K_LMTST 2 270 #define CN10K_RPM 3 271 #define CN10K_PTP_ONESTEP 4 272 #define CN10K_HW_MACSEC 5 273 #define QOS_CIR_PIR_SUPPORT 6 274 unsigned long cap_flag; 275 276 #define LMT_LINE_SIZE 128 277 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 278 u64 *lmt_base; 279 struct otx2_lmt_info __percpu *lmt_info; 280 }; 281 282 enum vfperm { 283 OTX2_RESET_VF_PERM, 284 OTX2_TRUSTED_VF, 285 }; 286 287 struct otx2_vf_config { 288 struct otx2_nic *pf; 289 struct delayed_work link_event_work; 290 bool intf_down; /* interface was either configured or not */ 291 u8 mac[ETH_ALEN]; 292 u16 vlan; 293 int tx_vtag_idx; 294 bool trusted; 295 }; 296 297 struct flr_work { 298 struct work_struct work; 299 struct otx2_nic *pf; 300 }; 301 302 struct refill_work { 303 struct delayed_work pool_refill_work; 304 struct otx2_nic *pf; 305 }; 306 307 /* PTPv2 originTimestamp structure */ 308 struct ptpv2_tstamp { 309 __be16 seconds_msb; /* 16 bits + */ 310 __be32 seconds_lsb; /* 32 bits = 48 bits*/ 311 __be32 nanoseconds; 312 } __packed; 313 314 struct otx2_ptp { 315 struct ptp_clock_info ptp_info; 316 struct ptp_clock *ptp_clock; 317 struct otx2_nic *nic; 318 319 struct cyclecounter cycle_counter; 320 struct timecounter time_counter; 321 322 struct delayed_work extts_work; 323 u64 last_extts; 324 u64 thresh; 325 326 struct ptp_pin_desc extts_config; 327 u64 (*convert_rx_ptp_tstmp)(u64 timestamp); 328 u64 (*convert_tx_ptp_tstmp)(u64 timestamp); 329 u64 (*ptp_tstamp2nsec)(const struct timecounter *time_counter, u64 timestamp); 330 struct delayed_work synctstamp_work; 331 u64 tstamp; 332 u32 base_ns; 333 }; 334 335 #define OTX2_HW_TIMESTAMP_LEN 8 336 337 struct otx2_mac_table { 338 u8 addr[ETH_ALEN]; 339 u16 mcam_entry; 340 bool inuse; 341 }; 342 343 struct otx2_flow_config { 344 u16 *flow_ent; 345 u16 *def_ent; 346 u16 nr_flows; 347 #define OTX2_DEFAULT_FLOWCOUNT 16 348 #define OTX2_MAX_UNICAST_FLOWS 8 349 #define OTX2_MAX_VLAN_FLOWS 1 350 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 351 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \ 352 OTX2_MAX_UNICAST_FLOWS + \ 353 OTX2_MAX_VLAN_FLOWS) 354 u16 unicast_offset; 355 u16 rx_vlan_offset; 356 u16 vf_vlan_offset; 357 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 358 #define OTX2_VF_VLAN_RX_INDEX 0 359 #define OTX2_VF_VLAN_TX_INDEX 1 360 u32 *bmap_to_dmacindex; 361 unsigned long *dmacflt_bmap; 362 struct list_head flow_list; 363 u32 dmacflt_max_flows; 364 u16 max_flows; 365 struct list_head flow_list_tc; 366 bool ntuple; 367 }; 368 369 struct dev_hw_ops { 370 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); 371 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 372 int size, int qidx); 373 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 374 void (*aura_freeptr)(void *dev, int aura, u64 buf); 375 }; 376 377 #define CN10K_MCS_SA_PER_SC 4 378 379 /* Stats which need to be accumulated in software because 380 * of shared counters in hardware. 381 */ 382 struct cn10k_txsc_stats { 383 u64 InPktsUntagged; 384 u64 InPktsNoTag; 385 u64 InPktsBadTag; 386 u64 InPktsUnknownSCI; 387 u64 InPktsNoSCI; 388 u64 InPktsOverrun; 389 }; 390 391 struct cn10k_rxsc_stats { 392 u64 InOctetsValidated; 393 u64 InOctetsDecrypted; 394 u64 InPktsUnchecked; 395 u64 InPktsDelayed; 396 u64 InPktsOK; 397 u64 InPktsInvalid; 398 u64 InPktsLate; 399 u64 InPktsNotValid; 400 u64 InPktsNotUsingSA; 401 u64 InPktsUnusedSA; 402 }; 403 404 struct cn10k_mcs_txsc { 405 struct macsec_secy *sw_secy; 406 struct cn10k_txsc_stats stats; 407 struct list_head entry; 408 enum macsec_validation_type last_validate_frames; 409 bool last_replay_protect; 410 u16 hw_secy_id_tx; 411 u16 hw_secy_id_rx; 412 u16 hw_flow_id; 413 u16 hw_sc_id; 414 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 415 u8 sa_bmap; 416 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 417 u8 encoding_sa; 418 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 419 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 420 bool vlan_dev; /* macsec running on VLAN ? */ 421 }; 422 423 struct cn10k_mcs_rxsc { 424 struct macsec_secy *sw_secy; 425 struct macsec_rx_sc *sw_rxsc; 426 struct cn10k_rxsc_stats stats; 427 struct list_head entry; 428 u16 hw_flow_id; 429 u16 hw_sc_id; 430 u16 hw_sa_id[CN10K_MCS_SA_PER_SC]; 431 u8 sa_bmap; 432 u8 sa_key[CN10K_MCS_SA_PER_SC][MACSEC_MAX_KEY_LEN]; 433 u8 salt[CN10K_MCS_SA_PER_SC][MACSEC_SALT_LEN]; 434 ssci_t ssci[CN10K_MCS_SA_PER_SC]; 435 }; 436 437 struct cn10k_mcs_cfg { 438 struct list_head txsc_list; 439 struct list_head rxsc_list; 440 }; 441 442 struct otx2_nic { 443 void __iomem *reg_base; 444 struct net_device *netdev; 445 struct dev_hw_ops *hw_ops; 446 void *iommu_domain; 447 u16 tx_max_pktlen; 448 u16 rbsize; /* Receive buffer size */ 449 450 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 451 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 452 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 453 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 454 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 455 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 456 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 457 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 458 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 459 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 460 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 461 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 462 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 463 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 464 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 465 #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15) 466 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) 467 u64 flags; 468 u64 *cq_op_addr; 469 470 struct bpf_prog *xdp_prog; 471 struct otx2_qset qset; 472 struct otx2_hw hw; 473 struct pci_dev *pdev; 474 struct device *dev; 475 476 /* Mbox */ 477 struct mbox mbox; 478 struct mbox *mbox_pfvf; 479 struct workqueue_struct *mbox_wq; 480 struct workqueue_struct *mbox_pfvf_wq; 481 482 u8 total_vfs; 483 u16 pcifunc; /* RVU PF_FUNC */ 484 u16 bpid[NIX_MAX_BPID_CHAN]; 485 struct otx2_vf_config *vf_configs; 486 struct cgx_link_user_info linfo; 487 488 /* NPC MCAM */ 489 struct otx2_flow_config *flow_cfg; 490 struct otx2_mac_table *mac_table; 491 492 u64 reset_count; 493 struct work_struct reset_task; 494 struct workqueue_struct *flr_wq; 495 struct flr_work *flr_wrk; 496 struct refill_work *refill_wrk; 497 struct workqueue_struct *otx2_wq; 498 struct work_struct rx_mode_work; 499 500 /* Ethtool stuff */ 501 u32 msg_enable; 502 503 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 504 int nix_blkaddr; 505 /* LMTST Lines info */ 506 struct qmem *dync_lmt; 507 u16 tot_lmt_lines; 508 u16 npa_lmt_lines; 509 u32 nix_lmt_size; 510 511 struct otx2_ptp *ptp; 512 struct hwtstamp_config tstamp; 513 514 unsigned long rq_bmap; 515 516 /* Devlink */ 517 struct otx2_devlink *dl; 518 #ifdef CONFIG_DCB 519 /* PFC */ 520 u8 pfc_en; 521 u8 *queue_to_pfc_map; 522 u16 pfc_schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 523 bool pfc_alloc_status[NIX_PF_PFC_PRIO_MAX]; 524 #endif 525 /* qos */ 526 struct otx2_qos qos; 527 528 /* napi event count. It is needed for adaptive irq coalescing. */ 529 u32 napi_events; 530 531 #if IS_ENABLED(CONFIG_MACSEC) 532 struct cn10k_mcs_cfg *macsec_cfg; 533 #endif 534 }; 535 536 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 537 { 538 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF; 539 } 540 541 static inline bool is_96xx_A0(struct pci_dev *pdev) 542 { 543 return (pdev->revision == 0x00) && 544 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 545 } 546 547 static inline bool is_96xx_B0(struct pci_dev *pdev) 548 { 549 return (pdev->revision == 0x01) && 550 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 551 } 552 553 /* REVID for PCIe devices. 554 * Bits 0..1: minor pass, bit 3..2: major pass 555 * bits 7..4: midr id 556 */ 557 #define PCI_REVISION_ID_96XX 0x00 558 #define PCI_REVISION_ID_95XX 0x10 559 #define PCI_REVISION_ID_95XXN 0x20 560 #define PCI_REVISION_ID_98XX 0x30 561 #define PCI_REVISION_ID_95XXMM 0x40 562 #define PCI_REVISION_ID_95XXO 0xE0 563 564 static inline bool is_dev_otx2(struct pci_dev *pdev) 565 { 566 u8 midr = pdev->revision & 0xF0; 567 568 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 569 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 570 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 571 } 572 573 static inline bool is_dev_cn10kb(struct pci_dev *pdev) 574 { 575 return pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF; 576 } 577 578 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 579 { 580 struct otx2_hw *hw = &pfvf->hw; 581 582 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 583 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 584 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 585 586 __set_bit(HW_TSO, &hw->cap_flag); 587 588 if (is_96xx_A0(pfvf->pdev)) { 589 __clear_bit(HW_TSO, &hw->cap_flag); 590 591 /* Time based irq coalescing is not supported */ 592 pfvf->hw.cq_qcount_wait = 0x0; 593 594 /* Due to HW issue previous silicons required minimum 595 * 600 unused CQE to avoid CQ overflow. 596 */ 597 pfvf->hw.rq_skid = 600; 598 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 599 } 600 if (is_96xx_B0(pfvf->pdev)) 601 __clear_bit(HW_TSO, &hw->cap_flag); 602 603 if (!is_dev_otx2(pfvf->pdev)) { 604 __set_bit(CN10K_MBOX, &hw->cap_flag); 605 __set_bit(CN10K_LMTST, &hw->cap_flag); 606 __set_bit(CN10K_RPM, &hw->cap_flag); 607 __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag); 608 __set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag); 609 } 610 611 if (is_dev_cn10kb(pfvf->pdev)) 612 __set_bit(CN10K_HW_MACSEC, &hw->cap_flag); 613 } 614 615 /* Register read/write APIs */ 616 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 617 { 618 u64 blkaddr; 619 620 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 621 case BLKTYPE_NIX: 622 blkaddr = nic->nix_blkaddr; 623 break; 624 case BLKTYPE_NPA: 625 blkaddr = BLKADDR_NPA; 626 break; 627 default: 628 blkaddr = BLKADDR_RVUM; 629 break; 630 } 631 632 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 633 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 634 635 return nic->reg_base + offset; 636 } 637 638 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 639 { 640 void __iomem *addr = otx2_get_regaddr(nic, offset); 641 642 writeq(val, addr); 643 } 644 645 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 646 { 647 void __iomem *addr = otx2_get_regaddr(nic, offset); 648 649 return readq(addr); 650 } 651 652 /* Mbox bounce buffer APIs */ 653 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 654 { 655 struct otx2_mbox *otx2_mbox; 656 struct otx2_mbox_dev *mdev; 657 658 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 659 if (!mbox->bbuf_base) 660 return -ENOMEM; 661 662 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 663 * prepare all mbox messages in bounce buffer instead of directly 664 * in hw mbox memory. 665 */ 666 otx2_mbox = &mbox->mbox; 667 mdev = &otx2_mbox->dev[0]; 668 mdev->mbase = mbox->bbuf_base; 669 670 otx2_mbox = &mbox->mbox_up; 671 mdev = &otx2_mbox->dev[0]; 672 mdev->mbase = mbox->bbuf_base; 673 return 0; 674 } 675 676 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 677 { 678 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 679 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 680 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 681 struct mbox_hdr *hdr; 682 u64 msg_size; 683 684 if (mdev->mbase == hw_mbase) 685 return; 686 687 hdr = hw_mbase + mbox->rx_start; 688 msg_size = hdr->msg_size; 689 690 if (msg_size > mbox->rx_size - msgs_offset) 691 msg_size = mbox->rx_size - msgs_offset; 692 693 /* Copy mbox messages from mbox memory to bounce buffer */ 694 memcpy(mdev->mbase + mbox->rx_start, 695 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 696 } 697 698 /* With the absence of API for 128-bit IO memory access for arm64, 699 * implement required operations at place. 700 */ 701 #if defined(CONFIG_ARM64) 702 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 703 { 704 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 705 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 706 } 707 708 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 709 { 710 u64 result; 711 712 __asm__ volatile(".cpu generic+lse\n" 713 "ldadd %x[i], %x[r], [%[b]]" 714 : [r]"=r"(result), "+m"(*ptr) 715 : [i]"r"(incr), [b]"r"(ptr) 716 : "memory"); 717 return result; 718 } 719 720 #else 721 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 722 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 723 #endif 724 725 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 726 u64 *ptrs, u64 num_ptrs) 727 { 728 struct otx2_lmt_info *lmt_info; 729 u64 size = 0, count_eot = 0; 730 u64 tar_addr, val = 0; 731 732 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); 733 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 734 /* LMTID is same as AURA Id */ 735 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); 736 /* Set if [127:64] of last 128bit word has a valid pointer */ 737 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 738 /* Set AURA ID to free pointer */ 739 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 740 /* Target address for LMTST flush tells HW how many 128bit 741 * words are valid from NPA_LF_AURA_BATCH_FREE0. 742 * 743 * tar_addr[6:4] is LMTST size-1 in units of 128b. 744 */ 745 if (num_ptrs > 2) { 746 size = (sizeof(u64) * num_ptrs) / 16; 747 if (!count_eot) 748 size++; 749 tar_addr |= ((size - 1) & 0x7) << 4; 750 } 751 dma_wmb(); 752 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); 753 /* Perform LMTST flush */ 754 cn10k_lmt_flush(val, tar_addr); 755 } 756 757 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 758 { 759 struct otx2_nic *pfvf = dev; 760 u64 ptrs[2]; 761 762 ptrs[1] = buf; 763 get_cpu(); 764 /* Free only one buffer at time during init and teardown */ 765 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); 766 put_cpu(); 767 } 768 769 /* Alloc pointer from pool/aura */ 770 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 771 { 772 u64 *ptr = (__force u64 *)otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_ALLOCX(0)); 773 u64 incr = (u64)aura | BIT_ULL(63); 774 775 return otx2_atomic64_add(incr, ptr); 776 } 777 778 /* Free pointer to a pool/aura */ 779 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 780 { 781 struct otx2_nic *pfvf = dev; 782 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 783 784 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 785 } 786 787 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 788 { 789 if (type == AURA_NIX_SQ) 790 return pfvf->hw.rqpool_cnt + idx; 791 792 /* AURA_NIX_RQ */ 793 return idx; 794 } 795 796 /* Mbox APIs */ 797 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 798 { 799 int err; 800 801 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 802 return 0; 803 otx2_mbox_msg_send(&mbox->mbox, 0); 804 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 805 if (err) 806 return err; 807 808 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 809 } 810 811 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 812 { 813 int err; 814 815 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 816 return 0; 817 otx2_mbox_msg_send(&mbox->mbox_up, devid); 818 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 819 if (err) 820 return err; 821 822 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 823 } 824 825 /* Use this API to send mbox msgs in atomic context 826 * where sleeping is not allowed 827 */ 828 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 829 { 830 int err; 831 832 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 833 return 0; 834 otx2_mbox_msg_send(&mbox->mbox, 0); 835 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 836 if (err) 837 return err; 838 839 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 840 } 841 842 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 843 static struct _req_type __maybe_unused \ 844 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 845 { \ 846 struct _req_type *req; \ 847 \ 848 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 849 &mbox->mbox, 0, sizeof(struct _req_type), \ 850 sizeof(struct _rsp_type)); \ 851 if (!req) \ 852 return NULL; \ 853 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 854 req->hdr.id = _id; \ 855 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 856 return req; \ 857 } 858 859 MBOX_MESSAGES 860 #undef M 861 862 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 863 int \ 864 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 865 struct _req_type *req, \ 866 struct _rsp_type *rsp); \ 867 868 MBOX_UP_CGX_MESSAGES 869 MBOX_UP_MCS_MESSAGES 870 #undef M 871 872 /* Time to wait before watchdog kicks off */ 873 #define OTX2_TX_TIMEOUT (100 * HZ) 874 875 #define RVU_PFVF_PF_SHIFT 10 876 #define RVU_PFVF_PF_MASK 0x3F 877 #define RVU_PFVF_FUNC_SHIFT 0 878 #define RVU_PFVF_FUNC_MASK 0x3FF 879 880 static inline bool is_otx2_vf(u16 pcifunc) 881 { 882 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 883 } 884 885 static inline int rvu_get_pf(u16 pcifunc) 886 { 887 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 888 } 889 890 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 891 struct page *page, 892 size_t offset, size_t size, 893 enum dma_data_direction dir) 894 { 895 dma_addr_t iova; 896 897 iova = dma_map_page_attrs(pfvf->dev, page, 898 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 899 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 900 return (dma_addr_t)NULL; 901 return iova; 902 } 903 904 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 905 dma_addr_t addr, size_t size, 906 enum dma_data_direction dir) 907 { 908 dma_unmap_page_attrs(pfvf->dev, addr, size, 909 dir, DMA_ATTR_SKIP_CPU_SYNC); 910 } 911 912 static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx) 913 { 914 u16 smq; 915 #ifdef CONFIG_DCB 916 if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx]) 917 return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx]; 918 #endif 919 /* check if qidx falls under QOS queues */ 920 if (qidx >= pfvf->hw.non_qos_queues) 921 smq = pfvf->qos.qid_to_sqmap[qidx - pfvf->hw.non_qos_queues]; 922 else 923 smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 924 925 return smq; 926 } 927 928 static inline u16 otx2_get_total_tx_queues(struct otx2_nic *pfvf) 929 { 930 return pfvf->hw.non_qos_queues + pfvf->hw.tc_tx_queues; 931 } 932 933 static inline u64 otx2_convert_rate(u64 rate) 934 { 935 u64 converted_rate; 936 937 /* Convert bytes per second to Mbps */ 938 converted_rate = rate * 8; 939 converted_rate = max_t(u64, converted_rate / 1000000, 1); 940 941 return converted_rate; 942 } 943 944 static inline int otx2_tc_flower_rule_cnt(struct otx2_nic *pfvf) 945 { 946 /* return here if MCAM entries not allocated */ 947 if (!pfvf->flow_cfg) 948 return 0; 949 950 return pfvf->flow_cfg->nr_flows; 951 } 952 953 /* MSI-X APIs */ 954 void otx2_free_cints(struct otx2_nic *pfvf, int n); 955 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 956 int otx2_set_mac_address(struct net_device *netdev, void *p); 957 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 958 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 959 void otx2_get_mac_from_af(struct net_device *netdev); 960 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 961 int otx2_config_pause_frm(struct otx2_nic *pfvf); 962 void otx2_setup_segmentation(struct otx2_nic *pfvf); 963 964 /* RVU block related APIs */ 965 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 966 int otx2_detach_resources(struct mbox *mbox); 967 int otx2_config_npa(struct otx2_nic *pfvf); 968 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 969 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 970 void otx2_aura_pool_free(struct otx2_nic *pfvf); 971 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 972 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 973 int otx2_config_nix(struct otx2_nic *pfvf); 974 int otx2_config_nix_queues(struct otx2_nic *pfvf); 975 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool pfc_en); 976 int otx2_txsch_alloc(struct otx2_nic *pfvf); 977 void otx2_txschq_stop(struct otx2_nic *pfvf); 978 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq); 979 void otx2_sqb_flush(struct otx2_nic *pfvf); 980 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 981 dma_addr_t *dma); 982 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 983 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 984 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 985 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx); 986 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 987 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura); 988 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 989 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 990 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 991 dma_addr_t *dma); 992 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 993 int stack_pages, int numptrs, int buf_size, int type); 994 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 995 int pool_id, int numptrs); 996 997 /* RSS configuration APIs*/ 998 int otx2_rss_init(struct otx2_nic *pfvf); 999 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 1000 void otx2_set_rss_key(struct otx2_nic *pfvf); 1001 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 1002 1003 /* Mbox handlers */ 1004 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1005 struct msix_offset_rsp *rsp); 1006 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1007 struct npa_lf_alloc_rsp *rsp); 1008 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1009 struct nix_lf_alloc_rsp *rsp); 1010 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1011 struct nix_txsch_alloc_rsp *rsp); 1012 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1013 struct cgx_stats_rsp *rsp); 1014 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1015 struct cgx_fec_stats_rsp *rsp); 1016 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 1017 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1018 struct nix_bp_cfg_rsp *rsp); 1019 1020 /* Device stats APIs */ 1021 void otx2_get_dev_stats(struct otx2_nic *pfvf); 1022 void otx2_get_stats64(struct net_device *netdev, 1023 struct rtnl_link_stats64 *stats); 1024 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 1025 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 1026 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 1027 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 1028 void otx2_set_ethtool_ops(struct net_device *netdev); 1029 void otx2vf_set_ethtool_ops(struct net_device *netdev); 1030 1031 int otx2_open(struct net_device *netdev); 1032 int otx2_stop(struct net_device *netdev); 1033 int otx2_set_real_num_queues(struct net_device *netdev, 1034 int tx_queues, int rx_queues); 1035 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd); 1036 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr); 1037 1038 /* MCAM filter related APIs */ 1039 int otx2_mcam_flow_init(struct otx2_nic *pf); 1040 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 1041 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 1042 void otx2_mcam_flow_del(struct otx2_nic *pf); 1043 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 1044 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 1045 int otx2_get_flow(struct otx2_nic *pfvf, 1046 struct ethtool_rxnfc *nfc, u32 location); 1047 int otx2_get_all_flows(struct otx2_nic *pfvf, 1048 struct ethtool_rxnfc *nfc, u32 *rule_locs); 1049 int otx2_add_flow(struct otx2_nic *pfvf, 1050 struct ethtool_rxnfc *nfc); 1051 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 1052 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 1053 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 1054 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 1055 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 1056 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 1057 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 1058 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx); 1059 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 1060 int otx2_handle_ntuple_tc_features(struct net_device *netdev, 1061 netdev_features_t features); 1062 int otx2_smq_flush(struct otx2_nic *pfvf, int smq); 1063 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1064 u64 iova, int size); 1065 1066 /* tc support */ 1067 int otx2_init_tc(struct otx2_nic *nic); 1068 void otx2_shutdown_tc(struct otx2_nic *nic); 1069 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 1070 void *type_data); 1071 /* CGX/RPM DMAC filters support */ 1072 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 1073 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1074 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 1075 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos); 1076 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 1077 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 1078 1079 #ifdef CONFIG_DCB 1080 /* DCB support*/ 1081 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable); 1082 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf); 1083 int otx2_dcbnl_set_ops(struct net_device *dev); 1084 /* PFC support */ 1085 int otx2_pfc_txschq_config(struct otx2_nic *pfvf); 1086 int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf); 1087 int otx2_pfc_txschq_update(struct otx2_nic *pfvf); 1088 int otx2_pfc_txschq_stop(struct otx2_nic *pfvf); 1089 #endif 1090 1091 #if IS_ENABLED(CONFIG_MACSEC) 1092 /* MACSEC offload support */ 1093 int cn10k_mcs_init(struct otx2_nic *pfvf); 1094 void cn10k_mcs_free(struct otx2_nic *pfvf); 1095 void cn10k_handle_mcs_event(struct otx2_nic *pfvf, struct mcs_intr_info *event); 1096 #else 1097 static inline int cn10k_mcs_init(struct otx2_nic *pfvf) { return 0; } 1098 static inline void cn10k_mcs_free(struct otx2_nic *pfvf) {} 1099 static inline void cn10k_handle_mcs_event(struct otx2_nic *pfvf, 1100 struct mcs_intr_info *event) 1101 {} 1102 #endif /* CONFIG_MACSEC */ 1103 1104 /* qos support */ 1105 static inline void otx2_qos_init(struct otx2_nic *pfvf, int qos_txqs) 1106 { 1107 struct otx2_hw *hw = &pfvf->hw; 1108 1109 hw->tc_tx_queues = qos_txqs; 1110 INIT_LIST_HEAD(&pfvf->qos.qos_tree); 1111 mutex_init(&pfvf->qos.qos_lock); 1112 } 1113 1114 static inline void otx2_shutdown_qos(struct otx2_nic *pfvf) 1115 { 1116 mutex_destroy(&pfvf->qos.qos_lock); 1117 } 1118 1119 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1120 struct net_device *sb_dev); 1121 int otx2_get_txq_by_classid(struct otx2_nic *pfvf, u16 classid); 1122 void otx2_qos_config_txschq(struct otx2_nic *pfvf); 1123 void otx2_clean_qos_queues(struct otx2_nic *pfvf); 1124 #endif /* OTX2_COMMON_H */ 1125