1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_COMMON_H 9 #define OTX2_COMMON_H 10 11 #include <linux/ethtool.h> 12 #include <linux/pci.h> 13 #include <linux/iommu.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/ptp_clock_kernel.h> 16 #include <linux/timecounter.h> 17 #include <linux/soc/marvell/octeontx2/asm.h> 18 #include <net/pkt_cls.h> 19 #include <net/devlink.h> 20 #include <linux/time64.h> 21 #include <linux/dim.h> 22 23 #include <mbox.h> 24 #include <npc.h> 25 #include "otx2_reg.h" 26 #include "otx2_txrx.h" 27 #include "otx2_devlink.h" 28 #include <rvu_trace.h> 29 30 /* PCI device IDs */ 31 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 32 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 33 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 34 35 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 36 37 /* PCI BAR nos */ 38 #define PCI_CFG_REG_BAR_NUM 2 39 #define PCI_MBOX_BAR_NUM 4 40 41 #define NAME_SIZE 32 42 43 enum arua_mapped_qtypes { 44 AURA_NIX_RQ, 45 AURA_NIX_SQ, 46 }; 47 48 /* NIX LF interrupts range*/ 49 #define NIX_LF_QINT_VEC_START 0x00 50 #define NIX_LF_CINT_VEC_START 0x40 51 #define NIX_LF_GINT_VEC 0x80 52 #define NIX_LF_ERR_VEC 0x81 53 #define NIX_LF_POISON_VEC 0x82 54 55 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 56 #define SEND_CQ_SKID 2000 57 58 #define OTX2_GET_RX_STATS(reg) \ 59 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 60 #define OTX2_GET_TX_STATS(reg) \ 61 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 62 63 struct otx2_lmt_info { 64 u64 lmt_addr; 65 u16 lmt_id; 66 }; 67 /* RSS configuration */ 68 struct otx2_rss_ctx { 69 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 70 }; 71 72 struct otx2_rss_info { 73 u8 enable; 74 u32 flowkey_cfg; 75 u16 rss_size; 76 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 77 u8 key[RSS_HASH_KEY_SIZE]; 78 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 79 }; 80 81 /* NIX (or NPC) RX errors */ 82 enum otx2_errlvl { 83 NPC_ERRLVL_RE, 84 NPC_ERRLVL_LID_LA, 85 NPC_ERRLVL_LID_LB, 86 NPC_ERRLVL_LID_LC, 87 NPC_ERRLVL_LID_LD, 88 NPC_ERRLVL_LID_LE, 89 NPC_ERRLVL_LID_LF, 90 NPC_ERRLVL_LID_LG, 91 NPC_ERRLVL_LID_LH, 92 NPC_ERRLVL_NIX = 0x0F, 93 }; 94 95 enum otx2_errcodes_re { 96 /* NPC_ERRLVL_RE errcodes */ 97 ERRCODE_FCS = 0x7, 98 ERRCODE_FCS_RCV = 0x8, 99 ERRCODE_UNDERSIZE = 0x10, 100 ERRCODE_OVERSIZE = 0x11, 101 ERRCODE_OL2_LEN_MISMATCH = 0x12, 102 /* NPC_ERRLVL_NIX errcodes */ 103 ERRCODE_OL3_LEN = 0x10, 104 ERRCODE_OL4_LEN = 0x11, 105 ERRCODE_OL4_CSUM = 0x12, 106 ERRCODE_IL3_LEN = 0x20, 107 ERRCODE_IL4_LEN = 0x21, 108 ERRCODE_IL4_CSUM = 0x22, 109 }; 110 111 /* NIX TX stats */ 112 enum nix_stat_lf_tx { 113 TX_UCAST = 0x0, 114 TX_BCAST = 0x1, 115 TX_MCAST = 0x2, 116 TX_DROP = 0x3, 117 TX_OCTS = 0x4, 118 TX_STATS_ENUM_LAST, 119 }; 120 121 /* NIX RX stats */ 122 enum nix_stat_lf_rx { 123 RX_OCTS = 0x0, 124 RX_UCAST = 0x1, 125 RX_BCAST = 0x2, 126 RX_MCAST = 0x3, 127 RX_DROP = 0x4, 128 RX_DROP_OCTS = 0x5, 129 RX_FCS = 0x6, 130 RX_ERR = 0x7, 131 RX_DRP_BCAST = 0x8, 132 RX_DRP_MCAST = 0x9, 133 RX_DRP_L3BCAST = 0xa, 134 RX_DRP_L3MCAST = 0xb, 135 RX_STATS_ENUM_LAST, 136 }; 137 138 struct otx2_dev_stats { 139 u64 rx_bytes; 140 u64 rx_frames; 141 u64 rx_ucast_frames; 142 u64 rx_bcast_frames; 143 u64 rx_mcast_frames; 144 u64 rx_drops; 145 146 u64 tx_bytes; 147 u64 tx_frames; 148 u64 tx_ucast_frames; 149 u64 tx_bcast_frames; 150 u64 tx_mcast_frames; 151 u64 tx_drops; 152 }; 153 154 /* Driver counted stats */ 155 struct otx2_drv_stats { 156 atomic_t rx_fcs_errs; 157 atomic_t rx_oversize_errs; 158 atomic_t rx_undersize_errs; 159 atomic_t rx_csum_errs; 160 atomic_t rx_len_errs; 161 atomic_t rx_other_errs; 162 }; 163 164 struct mbox { 165 struct otx2_mbox mbox; 166 struct work_struct mbox_wrk; 167 struct otx2_mbox mbox_up; 168 struct work_struct mbox_up_wrk; 169 struct otx2_nic *pfvf; 170 void *bbuf_base; /* Bounce buffer for mbox memory */ 171 struct mutex lock; /* serialize mailbox access */ 172 int num_msgs; /* mbox number of messages */ 173 int up_num_msgs; /* mbox_up number of messages */ 174 }; 175 176 struct otx2_hw { 177 struct pci_dev *pdev; 178 struct otx2_rss_info rss_info; 179 u16 rx_queues; 180 u16 tx_queues; 181 u16 xdp_queues; 182 u16 tot_tx_queues; 183 u16 max_queues; 184 u16 pool_cnt; 185 u16 rqpool_cnt; 186 u16 sqpool_cnt; 187 188 #define OTX2_DEFAULT_RBUF_LEN 2048 189 u16 rbuf_len; 190 u32 xqe_size; 191 192 /* NPA */ 193 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 194 u32 stack_pg_bytes; /* Size of stack page */ 195 u16 sqb_size; 196 197 /* NIX */ 198 u8 txschq_link_cfg_lvl; 199 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 200 u16 matchall_ipolicer; 201 u32 dwrr_mtu; 202 203 /* HW settings, coalescing etc */ 204 u16 rx_chan_base; 205 u16 tx_chan_base; 206 u16 cq_qcount_wait; 207 u16 cq_ecount_wait; 208 u16 rq_skid; 209 u8 cq_time_wait; 210 211 /* Segmentation */ 212 u8 lso_tsov4_idx; 213 u8 lso_tsov6_idx; 214 u8 lso_udpv4_idx; 215 u8 lso_udpv6_idx; 216 217 /* RSS */ 218 u8 flowkey_alg_idx; 219 220 /* MSI-X */ 221 u8 cint_cnt; /* CQ interrupt count */ 222 u16 npa_msixoff; /* Offset of NPA vectors */ 223 u16 nix_msixoff; /* Offset of NIX vectors */ 224 char *irq_name; 225 cpumask_var_t *affinity_mask; 226 227 /* Stats */ 228 struct otx2_dev_stats dev_stats; 229 struct otx2_drv_stats drv_stats; 230 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 231 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 232 u64 cgx_fec_corr_blks; 233 u64 cgx_fec_uncorr_blks; 234 u8 cgx_links; /* No. of CGX links present in HW */ 235 u8 lbk_links; /* No. of LBK links present in HW */ 236 u8 tx_link; /* Transmit channel link number */ 237 #define HW_TSO 0 238 #define CN10K_MBOX 1 239 #define CN10K_LMTST 2 240 #define CN10K_RPM 3 241 unsigned long cap_flag; 242 243 #define LMT_LINE_SIZE 128 244 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 245 u64 *lmt_base; 246 struct otx2_lmt_info __percpu *lmt_info; 247 }; 248 249 enum vfperm { 250 OTX2_RESET_VF_PERM, 251 OTX2_TRUSTED_VF, 252 }; 253 254 struct otx2_vf_config { 255 struct otx2_nic *pf; 256 struct delayed_work link_event_work; 257 bool intf_down; /* interface was either configured or not */ 258 u8 mac[ETH_ALEN]; 259 u16 vlan; 260 int tx_vtag_idx; 261 bool trusted; 262 }; 263 264 struct flr_work { 265 struct work_struct work; 266 struct otx2_nic *pf; 267 }; 268 269 struct refill_work { 270 struct delayed_work pool_refill_work; 271 struct otx2_nic *pf; 272 }; 273 274 struct otx2_ptp { 275 struct ptp_clock_info ptp_info; 276 struct ptp_clock *ptp_clock; 277 struct otx2_nic *nic; 278 279 struct cyclecounter cycle_counter; 280 struct timecounter time_counter; 281 282 struct delayed_work extts_work; 283 u64 last_extts; 284 u64 thresh; 285 286 struct ptp_pin_desc extts_config; 287 u64 (*convert_rx_ptp_tstmp)(u64 timestamp); 288 u64 (*convert_tx_ptp_tstmp)(u64 timestamp); 289 }; 290 291 #define OTX2_HW_TIMESTAMP_LEN 8 292 293 struct otx2_mac_table { 294 u8 addr[ETH_ALEN]; 295 u16 mcam_entry; 296 bool inuse; 297 }; 298 299 struct otx2_flow_config { 300 u16 *flow_ent; 301 u16 *def_ent; 302 u16 nr_flows; 303 #define OTX2_DEFAULT_FLOWCOUNT 16 304 #define OTX2_MAX_UNICAST_FLOWS 8 305 #define OTX2_MAX_VLAN_FLOWS 1 306 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 307 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \ 308 OTX2_MAX_UNICAST_FLOWS + \ 309 OTX2_MAX_VLAN_FLOWS) 310 u16 unicast_offset; 311 u16 rx_vlan_offset; 312 u16 vf_vlan_offset; 313 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 314 #define OTX2_VF_VLAN_RX_INDEX 0 315 #define OTX2_VF_VLAN_TX_INDEX 1 316 u16 max_flows; 317 u8 dmacflt_max_flows; 318 u32 *bmap_to_dmacindex; 319 unsigned long *dmacflt_bmap; 320 struct list_head flow_list; 321 }; 322 323 struct otx2_tc_info { 324 /* hash table to store TC offloaded flows */ 325 struct rhashtable flow_table; 326 struct rhashtable_params flow_ht_params; 327 unsigned long *tc_entries_bitmap; 328 }; 329 330 struct dev_hw_ops { 331 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); 332 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 333 int size, int qidx); 334 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 335 void (*aura_freeptr)(void *dev, int aura, u64 buf); 336 }; 337 338 struct otx2_nic { 339 void __iomem *reg_base; 340 struct net_device *netdev; 341 struct dev_hw_ops *hw_ops; 342 void *iommu_domain; 343 u16 tx_max_pktlen; 344 u16 rbsize; /* Receive buffer size */ 345 346 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 347 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 348 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 349 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 350 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 351 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 352 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 353 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 354 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 355 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 356 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 357 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 358 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 359 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 360 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 361 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) 362 u64 flags; 363 u64 *cq_op_addr; 364 365 struct bpf_prog *xdp_prog; 366 struct otx2_qset qset; 367 struct otx2_hw hw; 368 struct pci_dev *pdev; 369 struct device *dev; 370 371 /* Mbox */ 372 struct mbox mbox; 373 struct mbox *mbox_pfvf; 374 struct workqueue_struct *mbox_wq; 375 struct workqueue_struct *mbox_pfvf_wq; 376 377 u8 total_vfs; 378 u16 pcifunc; /* RVU PF_FUNC */ 379 u16 bpid[NIX_MAX_BPID_CHAN]; 380 struct otx2_vf_config *vf_configs; 381 struct cgx_link_user_info linfo; 382 383 /* NPC MCAM */ 384 struct otx2_flow_config *flow_cfg; 385 struct otx2_mac_table *mac_table; 386 struct otx2_tc_info tc_info; 387 388 u64 reset_count; 389 struct work_struct reset_task; 390 struct workqueue_struct *flr_wq; 391 struct flr_work *flr_wrk; 392 struct refill_work *refill_wrk; 393 struct workqueue_struct *otx2_wq; 394 struct work_struct rx_mode_work; 395 396 /* Ethtool stuff */ 397 u32 msg_enable; 398 399 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 400 int nix_blkaddr; 401 /* LMTST Lines info */ 402 struct qmem *dync_lmt; 403 u16 tot_lmt_lines; 404 u16 npa_lmt_lines; 405 u32 nix_lmt_size; 406 407 struct otx2_ptp *ptp; 408 struct hwtstamp_config tstamp; 409 410 unsigned long rq_bmap; 411 412 /* Devlink */ 413 struct otx2_devlink *dl; 414 #ifdef CONFIG_DCB 415 /* PFC */ 416 u8 pfc_en; 417 u8 *queue_to_pfc_map; 418 #endif 419 420 /* napi event count. It is needed for adaptive irq coalescing. */ 421 u32 napi_events; 422 }; 423 424 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 425 { 426 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF; 427 } 428 429 static inline bool is_96xx_A0(struct pci_dev *pdev) 430 { 431 return (pdev->revision == 0x00) && 432 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 433 } 434 435 static inline bool is_96xx_B0(struct pci_dev *pdev) 436 { 437 return (pdev->revision == 0x01) && 438 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 439 } 440 441 /* REVID for PCIe devices. 442 * Bits 0..1: minor pass, bit 3..2: major pass 443 * bits 7..4: midr id 444 */ 445 #define PCI_REVISION_ID_96XX 0x00 446 #define PCI_REVISION_ID_95XX 0x10 447 #define PCI_REVISION_ID_95XXN 0x20 448 #define PCI_REVISION_ID_98XX 0x30 449 #define PCI_REVISION_ID_95XXMM 0x40 450 #define PCI_REVISION_ID_95XXO 0xE0 451 452 static inline bool is_dev_otx2(struct pci_dev *pdev) 453 { 454 u8 midr = pdev->revision & 0xF0; 455 456 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 457 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 458 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 459 } 460 461 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 462 { 463 struct otx2_hw *hw = &pfvf->hw; 464 465 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 466 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 467 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 468 469 __set_bit(HW_TSO, &hw->cap_flag); 470 471 if (is_96xx_A0(pfvf->pdev)) { 472 __clear_bit(HW_TSO, &hw->cap_flag); 473 474 /* Time based irq coalescing is not supported */ 475 pfvf->hw.cq_qcount_wait = 0x0; 476 477 /* Due to HW issue previous silicons required minimum 478 * 600 unused CQE to avoid CQ overflow. 479 */ 480 pfvf->hw.rq_skid = 600; 481 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 482 } 483 if (is_96xx_B0(pfvf->pdev)) 484 __clear_bit(HW_TSO, &hw->cap_flag); 485 486 if (!is_dev_otx2(pfvf->pdev)) { 487 __set_bit(CN10K_MBOX, &hw->cap_flag); 488 __set_bit(CN10K_LMTST, &hw->cap_flag); 489 __set_bit(CN10K_RPM, &hw->cap_flag); 490 } 491 } 492 493 /* Register read/write APIs */ 494 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 495 { 496 u64 blkaddr; 497 498 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 499 case BLKTYPE_NIX: 500 blkaddr = nic->nix_blkaddr; 501 break; 502 case BLKTYPE_NPA: 503 blkaddr = BLKADDR_NPA; 504 break; 505 default: 506 blkaddr = BLKADDR_RVUM; 507 break; 508 } 509 510 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 511 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 512 513 return nic->reg_base + offset; 514 } 515 516 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 517 { 518 void __iomem *addr = otx2_get_regaddr(nic, offset); 519 520 writeq(val, addr); 521 } 522 523 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 524 { 525 void __iomem *addr = otx2_get_regaddr(nic, offset); 526 527 return readq(addr); 528 } 529 530 /* Mbox bounce buffer APIs */ 531 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 532 { 533 struct otx2_mbox *otx2_mbox; 534 struct otx2_mbox_dev *mdev; 535 536 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 537 if (!mbox->bbuf_base) 538 return -ENOMEM; 539 540 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 541 * prepare all mbox messages in bounce buffer instead of directly 542 * in hw mbox memory. 543 */ 544 otx2_mbox = &mbox->mbox; 545 mdev = &otx2_mbox->dev[0]; 546 mdev->mbase = mbox->bbuf_base; 547 548 otx2_mbox = &mbox->mbox_up; 549 mdev = &otx2_mbox->dev[0]; 550 mdev->mbase = mbox->bbuf_base; 551 return 0; 552 } 553 554 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 555 { 556 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 557 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 558 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 559 struct mbox_hdr *hdr; 560 u64 msg_size; 561 562 if (mdev->mbase == hw_mbase) 563 return; 564 565 hdr = hw_mbase + mbox->rx_start; 566 msg_size = hdr->msg_size; 567 568 if (msg_size > mbox->rx_size - msgs_offset) 569 msg_size = mbox->rx_size - msgs_offset; 570 571 /* Copy mbox messages from mbox memory to bounce buffer */ 572 memcpy(mdev->mbase + mbox->rx_start, 573 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 574 } 575 576 /* With the absence of API for 128-bit IO memory access for arm64, 577 * implement required operations at place. 578 */ 579 #if defined(CONFIG_ARM64) 580 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 581 { 582 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 583 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 584 } 585 586 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 587 { 588 u64 result; 589 590 __asm__ volatile(".cpu generic+lse\n" 591 "ldadd %x[i], %x[r], [%[b]]" 592 : [r]"=r"(result), "+m"(*ptr) 593 : [i]"r"(incr), [b]"r"(ptr) 594 : "memory"); 595 return result; 596 } 597 598 #else 599 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 600 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 601 #endif 602 603 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 604 u64 *ptrs, u64 num_ptrs) 605 { 606 struct otx2_lmt_info *lmt_info; 607 u64 size = 0, count_eot = 0; 608 u64 tar_addr, val = 0; 609 610 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); 611 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 612 /* LMTID is same as AURA Id */ 613 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); 614 /* Set if [127:64] of last 128bit word has a valid pointer */ 615 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 616 /* Set AURA ID to free pointer */ 617 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 618 /* Target address for LMTST flush tells HW how many 128bit 619 * words are valid from NPA_LF_AURA_BATCH_FREE0. 620 * 621 * tar_addr[6:4] is LMTST size-1 in units of 128b. 622 */ 623 if (num_ptrs > 2) { 624 size = (sizeof(u64) * num_ptrs) / 16; 625 if (!count_eot) 626 size++; 627 tar_addr |= ((size - 1) & 0x7) << 4; 628 } 629 dma_wmb(); 630 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); 631 /* Perform LMTST flush */ 632 cn10k_lmt_flush(val, tar_addr); 633 } 634 635 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 636 { 637 struct otx2_nic *pfvf = dev; 638 u64 ptrs[2]; 639 640 ptrs[1] = buf; 641 /* Free only one buffer at time during init and teardown */ 642 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); 643 } 644 645 /* Alloc pointer from pool/aura */ 646 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 647 { 648 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf, 649 NPA_LF_AURA_OP_ALLOCX(0)); 650 u64 incr = (u64)aura | BIT_ULL(63); 651 652 return otx2_atomic64_add(incr, ptr); 653 } 654 655 /* Free pointer to a pool/aura */ 656 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 657 { 658 struct otx2_nic *pfvf = dev; 659 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 660 661 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 662 } 663 664 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 665 { 666 if (type == AURA_NIX_SQ) 667 return pfvf->hw.rqpool_cnt + idx; 668 669 /* AURA_NIX_RQ */ 670 return idx; 671 } 672 673 /* Mbox APIs */ 674 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 675 { 676 int err; 677 678 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 679 return 0; 680 otx2_mbox_msg_send(&mbox->mbox, 0); 681 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 682 if (err) 683 return err; 684 685 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 686 } 687 688 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 689 { 690 int err; 691 692 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 693 return 0; 694 otx2_mbox_msg_send(&mbox->mbox_up, devid); 695 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 696 if (err) 697 return err; 698 699 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 700 } 701 702 /* Use this API to send mbox msgs in atomic context 703 * where sleeping is not allowed 704 */ 705 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 706 { 707 int err; 708 709 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 710 return 0; 711 otx2_mbox_msg_send(&mbox->mbox, 0); 712 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 713 if (err) 714 return err; 715 716 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 717 } 718 719 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 720 static struct _req_type __maybe_unused \ 721 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 722 { \ 723 struct _req_type *req; \ 724 \ 725 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 726 &mbox->mbox, 0, sizeof(struct _req_type), \ 727 sizeof(struct _rsp_type)); \ 728 if (!req) \ 729 return NULL; \ 730 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 731 req->hdr.id = _id; \ 732 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 733 return req; \ 734 } 735 736 MBOX_MESSAGES 737 #undef M 738 739 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 740 int \ 741 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 742 struct _req_type *req, \ 743 struct _rsp_type *rsp); \ 744 745 MBOX_UP_CGX_MESSAGES 746 #undef M 747 748 /* Time to wait before watchdog kicks off */ 749 #define OTX2_TX_TIMEOUT (100 * HZ) 750 751 #define RVU_PFVF_PF_SHIFT 10 752 #define RVU_PFVF_PF_MASK 0x3F 753 #define RVU_PFVF_FUNC_SHIFT 0 754 #define RVU_PFVF_FUNC_MASK 0x3FF 755 756 static inline bool is_otx2_vf(u16 pcifunc) 757 { 758 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 759 } 760 761 static inline int rvu_get_pf(u16 pcifunc) 762 { 763 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 764 } 765 766 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 767 struct page *page, 768 size_t offset, size_t size, 769 enum dma_data_direction dir) 770 { 771 dma_addr_t iova; 772 773 iova = dma_map_page_attrs(pfvf->dev, page, 774 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 775 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 776 return (dma_addr_t)NULL; 777 return iova; 778 } 779 780 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 781 dma_addr_t addr, size_t size, 782 enum dma_data_direction dir) 783 { 784 dma_unmap_page_attrs(pfvf->dev, addr, size, 785 dir, DMA_ATTR_SKIP_CPU_SYNC); 786 } 787 788 /* MSI-X APIs */ 789 void otx2_free_cints(struct otx2_nic *pfvf, int n); 790 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 791 int otx2_set_mac_address(struct net_device *netdev, void *p); 792 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 793 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 794 void otx2_get_mac_from_af(struct net_device *netdev); 795 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 796 int otx2_config_pause_frm(struct otx2_nic *pfvf); 797 void otx2_setup_segmentation(struct otx2_nic *pfvf); 798 799 /* RVU block related APIs */ 800 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 801 int otx2_detach_resources(struct mbox *mbox); 802 int otx2_config_npa(struct otx2_nic *pfvf); 803 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 804 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 805 void otx2_aura_pool_free(struct otx2_nic *pfvf); 806 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 807 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 808 int otx2_config_nix(struct otx2_nic *pfvf); 809 int otx2_config_nix_queues(struct otx2_nic *pfvf); 810 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl); 811 int otx2_txsch_alloc(struct otx2_nic *pfvf); 812 int otx2_txschq_stop(struct otx2_nic *pfvf); 813 void otx2_sqb_flush(struct otx2_nic *pfvf); 814 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 815 dma_addr_t *dma); 816 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 817 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 818 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 819 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 820 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 821 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 822 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 823 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 824 dma_addr_t *dma); 825 826 /* RSS configuration APIs*/ 827 int otx2_rss_init(struct otx2_nic *pfvf); 828 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 829 void otx2_set_rss_key(struct otx2_nic *pfvf); 830 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 831 832 /* Mbox handlers */ 833 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 834 struct msix_offset_rsp *rsp); 835 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 836 struct npa_lf_alloc_rsp *rsp); 837 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 838 struct nix_lf_alloc_rsp *rsp); 839 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 840 struct nix_txsch_alloc_rsp *rsp); 841 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 842 struct cgx_stats_rsp *rsp); 843 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 844 struct cgx_fec_stats_rsp *rsp); 845 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 846 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 847 struct nix_bp_cfg_rsp *rsp); 848 849 /* Device stats APIs */ 850 void otx2_get_dev_stats(struct otx2_nic *pfvf); 851 void otx2_get_stats64(struct net_device *netdev, 852 struct rtnl_link_stats64 *stats); 853 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 854 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 855 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 856 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 857 void otx2_set_ethtool_ops(struct net_device *netdev); 858 void otx2vf_set_ethtool_ops(struct net_device *netdev); 859 860 int otx2_open(struct net_device *netdev); 861 int otx2_stop(struct net_device *netdev); 862 int otx2_set_real_num_queues(struct net_device *netdev, 863 int tx_queues, int rx_queues); 864 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd); 865 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr); 866 867 /* MCAM filter related APIs */ 868 int otx2_mcam_flow_init(struct otx2_nic *pf); 869 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 870 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 871 void otx2_mcam_flow_del(struct otx2_nic *pf); 872 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 873 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 874 int otx2_get_flow(struct otx2_nic *pfvf, 875 struct ethtool_rxnfc *nfc, u32 location); 876 int otx2_get_all_flows(struct otx2_nic *pfvf, 877 struct ethtool_rxnfc *nfc, u32 *rule_locs); 878 int otx2_add_flow(struct otx2_nic *pfvf, 879 struct ethtool_rxnfc *nfc); 880 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 881 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 882 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 883 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 884 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 885 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 886 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 887 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx); 888 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 889 int otx2_handle_ntuple_tc_features(struct net_device *netdev, 890 netdev_features_t features); 891 /* tc support */ 892 int otx2_init_tc(struct otx2_nic *nic); 893 void otx2_shutdown_tc(struct otx2_nic *nic); 894 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 895 void *type_data); 896 int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic); 897 /* CGX/RPM DMAC filters support */ 898 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 899 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 900 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u32 bit_pos); 901 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u32 bit_pos); 902 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 903 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 904 905 #ifdef CONFIG_DCB 906 /* DCB support*/ 907 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable); 908 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf); 909 int otx2_dcbnl_set_ops(struct net_device *dev); 910 #endif 911 #endif /* OTX2_COMMON_H */ 912