1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <net/tso.h> 14 15 #include "otx2_reg.h" 16 #include "otx2_common.h" 17 #include "otx2_struct.h" 18 #include "cn10k.h" 19 20 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 21 struct otx2_nic *pfvf, int qidx) 22 { 23 u64 incr = (u64)qidx << 32; 24 u64 *ptr; 25 26 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 27 stats->bytes = otx2_atomic64_add(incr, ptr); 28 29 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 30 stats->pkts = otx2_atomic64_add(incr, ptr); 31 } 32 33 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 34 struct otx2_nic *pfvf, int qidx) 35 { 36 u64 incr = (u64)qidx << 32; 37 u64 *ptr; 38 39 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 40 stats->bytes = otx2_atomic64_add(incr, ptr); 41 42 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 43 stats->pkts = otx2_atomic64_add(incr, ptr); 44 } 45 46 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 47 { 48 struct msg_req *req; 49 50 if (!netif_running(pfvf->netdev)) 51 return; 52 53 mutex_lock(&pfvf->mbox.lock); 54 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 55 if (!req) { 56 mutex_unlock(&pfvf->mbox.lock); 57 return; 58 } 59 60 otx2_sync_mbox_msg(&pfvf->mbox); 61 mutex_unlock(&pfvf->mbox.lock); 62 } 63 64 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 65 { 66 struct msg_req *req; 67 68 if (!netif_running(pfvf->netdev)) 69 return; 70 mutex_lock(&pfvf->mbox.lock); 71 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 72 if (req) 73 otx2_sync_mbox_msg(&pfvf->mbox); 74 mutex_unlock(&pfvf->mbox.lock); 75 } 76 77 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 78 { 79 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 80 81 if (!pfvf->qset.rq) 82 return 0; 83 84 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 85 return 1; 86 } 87 88 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 89 { 90 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 91 92 if (!pfvf->qset.sq) 93 return 0; 94 95 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 96 return 1; 97 } 98 99 void otx2_get_dev_stats(struct otx2_nic *pfvf) 100 { 101 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 102 103 #define OTX2_GET_RX_STATS(reg) \ 104 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 105 #define OTX2_GET_TX_STATS(reg) \ 106 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 107 108 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 109 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 110 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 111 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 112 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 113 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 114 dev_stats->rx_mcast_frames + 115 dev_stats->rx_ucast_frames; 116 117 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 118 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 119 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 120 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 121 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 122 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 123 dev_stats->tx_mcast_frames + 124 dev_stats->tx_ucast_frames; 125 } 126 127 void otx2_get_stats64(struct net_device *netdev, 128 struct rtnl_link_stats64 *stats) 129 { 130 struct otx2_nic *pfvf = netdev_priv(netdev); 131 struct otx2_dev_stats *dev_stats; 132 133 otx2_get_dev_stats(pfvf); 134 135 dev_stats = &pfvf->hw.dev_stats; 136 stats->rx_bytes = dev_stats->rx_bytes; 137 stats->rx_packets = dev_stats->rx_frames; 138 stats->rx_dropped = dev_stats->rx_drops; 139 stats->multicast = dev_stats->rx_mcast_frames; 140 141 stats->tx_bytes = dev_stats->tx_bytes; 142 stats->tx_packets = dev_stats->tx_frames; 143 stats->tx_dropped = dev_stats->tx_drops; 144 } 145 EXPORT_SYMBOL(otx2_get_stats64); 146 147 /* Sync MAC address with RVU AF */ 148 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 149 { 150 struct nix_set_mac_addr *req; 151 int err; 152 153 mutex_lock(&pfvf->mbox.lock); 154 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 155 if (!req) { 156 mutex_unlock(&pfvf->mbox.lock); 157 return -ENOMEM; 158 } 159 160 ether_addr_copy(req->mac_addr, mac); 161 162 err = otx2_sync_mbox_msg(&pfvf->mbox); 163 mutex_unlock(&pfvf->mbox.lock); 164 return err; 165 } 166 167 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 168 struct net_device *netdev) 169 { 170 struct nix_get_mac_addr_rsp *rsp; 171 struct mbox_msghdr *msghdr; 172 struct msg_req *req; 173 int err; 174 175 mutex_lock(&pfvf->mbox.lock); 176 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 177 if (!req) { 178 mutex_unlock(&pfvf->mbox.lock); 179 return -ENOMEM; 180 } 181 182 err = otx2_sync_mbox_msg(&pfvf->mbox); 183 if (err) { 184 mutex_unlock(&pfvf->mbox.lock); 185 return err; 186 } 187 188 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 189 if (IS_ERR(msghdr)) { 190 mutex_unlock(&pfvf->mbox.lock); 191 return PTR_ERR(msghdr); 192 } 193 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 194 ether_addr_copy(netdev->dev_addr, rsp->mac_addr); 195 mutex_unlock(&pfvf->mbox.lock); 196 197 return 0; 198 } 199 200 int otx2_set_mac_address(struct net_device *netdev, void *p) 201 { 202 struct otx2_nic *pfvf = netdev_priv(netdev); 203 struct sockaddr *addr = p; 204 205 if (!is_valid_ether_addr(addr->sa_data)) 206 return -EADDRNOTAVAIL; 207 208 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 209 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 210 /* update dmac field in vlan offload rule */ 211 if (netif_running(netdev) && 212 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 213 otx2_install_rxvlan_offload_flow(pfvf); 214 /* update dmac address in ntuple and DMAC filter list */ 215 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 216 otx2_dmacflt_update_pfmac_flow(pfvf); 217 } else { 218 return -EPERM; 219 } 220 221 return 0; 222 } 223 EXPORT_SYMBOL(otx2_set_mac_address); 224 225 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 226 { 227 struct nix_frs_cfg *req; 228 int err; 229 230 mutex_lock(&pfvf->mbox.lock); 231 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 232 if (!req) { 233 mutex_unlock(&pfvf->mbox.lock); 234 return -ENOMEM; 235 } 236 237 req->maxlen = pfvf->max_frs; 238 239 err = otx2_sync_mbox_msg(&pfvf->mbox); 240 mutex_unlock(&pfvf->mbox.lock); 241 return err; 242 } 243 244 int otx2_config_pause_frm(struct otx2_nic *pfvf) 245 { 246 struct cgx_pause_frm_cfg *req; 247 int err; 248 249 if (is_otx2_lbkvf(pfvf->pdev)) 250 return 0; 251 252 mutex_lock(&pfvf->mbox.lock); 253 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 254 if (!req) { 255 err = -ENOMEM; 256 goto unlock; 257 } 258 259 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 260 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 261 req->set = 1; 262 263 err = otx2_sync_mbox_msg(&pfvf->mbox); 264 unlock: 265 mutex_unlock(&pfvf->mbox.lock); 266 return err; 267 } 268 269 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 270 { 271 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 272 struct nix_rss_flowkey_cfg_rsp *rsp; 273 struct nix_rss_flowkey_cfg *req; 274 int err; 275 276 mutex_lock(&pfvf->mbox.lock); 277 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 278 if (!req) { 279 mutex_unlock(&pfvf->mbox.lock); 280 return -ENOMEM; 281 } 282 req->mcam_index = -1; /* Default or reserved index */ 283 req->flowkey_cfg = rss->flowkey_cfg; 284 req->group = DEFAULT_RSS_CONTEXT_GROUP; 285 286 err = otx2_sync_mbox_msg(&pfvf->mbox); 287 if (err) 288 goto fail; 289 290 rsp = (struct nix_rss_flowkey_cfg_rsp *) 291 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 292 if (IS_ERR(rsp)) { 293 err = PTR_ERR(rsp); 294 goto fail; 295 } 296 297 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 298 fail: 299 mutex_unlock(&pfvf->mbox.lock); 300 return err; 301 } 302 303 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 304 { 305 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 306 const int index = rss->rss_size * ctx_id; 307 struct mbox *mbox = &pfvf->mbox; 308 struct otx2_rss_ctx *rss_ctx; 309 struct nix_aq_enq_req *aq; 310 int idx, err; 311 312 mutex_lock(&mbox->lock); 313 rss_ctx = rss->rss_ctx[ctx_id]; 314 /* Get memory to put this msg */ 315 for (idx = 0; idx < rss->rss_size; idx++) { 316 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 317 if (!aq) { 318 /* The shared memory buffer can be full. 319 * Flush it and retry 320 */ 321 err = otx2_sync_mbox_msg(mbox); 322 if (err) { 323 mutex_unlock(&mbox->lock); 324 return err; 325 } 326 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 327 if (!aq) { 328 mutex_unlock(&mbox->lock); 329 return -ENOMEM; 330 } 331 } 332 333 aq->rss.rq = rss_ctx->ind_tbl[idx]; 334 335 /* Fill AQ info */ 336 aq->qidx = index + idx; 337 aq->ctype = NIX_AQ_CTYPE_RSS; 338 aq->op = NIX_AQ_INSTOP_INIT; 339 } 340 err = otx2_sync_mbox_msg(mbox); 341 mutex_unlock(&mbox->lock); 342 return err; 343 } 344 345 void otx2_set_rss_key(struct otx2_nic *pfvf) 346 { 347 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 348 u64 *key = (u64 *)&rss->key[4]; 349 int idx; 350 351 /* 352bit or 44byte key needs to be configured as below 352 * NIX_LF_RX_SECRETX0 = key<351:288> 353 * NIX_LF_RX_SECRETX1 = key<287:224> 354 * NIX_LF_RX_SECRETX2 = key<223:160> 355 * NIX_LF_RX_SECRETX3 = key<159:96> 356 * NIX_LF_RX_SECRETX4 = key<95:32> 357 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 358 */ 359 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 360 (u64)(*((u32 *)&rss->key)) << 32); 361 idx = sizeof(rss->key) / sizeof(u64); 362 while (idx > 0) { 363 idx--; 364 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 365 } 366 } 367 368 int otx2_rss_init(struct otx2_nic *pfvf) 369 { 370 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 371 struct otx2_rss_ctx *rss_ctx; 372 int idx, ret = 0; 373 374 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 375 376 /* Init RSS key if it is not setup already */ 377 if (!rss->enable) 378 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 379 otx2_set_rss_key(pfvf); 380 381 if (!netif_is_rxfh_configured(pfvf->netdev)) { 382 /* Set RSS group 0 as default indirection table */ 383 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 384 GFP_KERNEL); 385 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 386 return -ENOMEM; 387 388 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 389 for (idx = 0; idx < rss->rss_size; idx++) 390 rss_ctx->ind_tbl[idx] = 391 ethtool_rxfh_indir_default(idx, 392 pfvf->hw.rx_queues); 393 } 394 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 395 if (ret) 396 return ret; 397 398 /* Flowkey or hash config to be used for generating flow tag */ 399 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 400 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 401 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 402 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 403 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 404 405 ret = otx2_set_flowkey_cfg(pfvf); 406 if (ret) 407 return ret; 408 409 rss->enable = true; 410 return 0; 411 } 412 413 /* Setup UDP segmentation algorithm in HW */ 414 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 415 { 416 struct nix_lso_format *field; 417 418 field = (struct nix_lso_format *)&lso->fields[0]; 419 lso->field_mask = GENMASK(18, 0); 420 421 /* IP's Length field */ 422 field->layer = NIX_TXLAYER_OL3; 423 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 424 field->offset = v4 ? 2 : 4; 425 field->sizem1 = 1; /* i.e 2 bytes */ 426 field->alg = NIX_LSOALG_ADD_PAYLEN; 427 field++; 428 429 /* No ID field in IPv6 header */ 430 if (v4) { 431 /* Increment IPID */ 432 field->layer = NIX_TXLAYER_OL3; 433 field->offset = 4; 434 field->sizem1 = 1; /* i.e 2 bytes */ 435 field->alg = NIX_LSOALG_ADD_SEGNUM; 436 field++; 437 } 438 439 /* Update length in UDP header */ 440 field->layer = NIX_TXLAYER_OL4; 441 field->offset = 4; 442 field->sizem1 = 1; 443 field->alg = NIX_LSOALG_ADD_PAYLEN; 444 } 445 446 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 447 void otx2_setup_segmentation(struct otx2_nic *pfvf) 448 { 449 struct nix_lso_format_cfg_rsp *rsp; 450 struct nix_lso_format_cfg *lso; 451 struct otx2_hw *hw = &pfvf->hw; 452 int err; 453 454 mutex_lock(&pfvf->mbox.lock); 455 456 /* UDPv4 segmentation */ 457 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 458 if (!lso) 459 goto fail; 460 461 /* Setup UDP/IP header fields that HW should update per segment */ 462 otx2_setup_udp_segmentation(lso, true); 463 464 err = otx2_sync_mbox_msg(&pfvf->mbox); 465 if (err) 466 goto fail; 467 468 rsp = (struct nix_lso_format_cfg_rsp *) 469 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 470 if (IS_ERR(rsp)) 471 goto fail; 472 473 hw->lso_udpv4_idx = rsp->lso_format_idx; 474 475 /* UDPv6 segmentation */ 476 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 477 if (!lso) 478 goto fail; 479 480 /* Setup UDP/IP header fields that HW should update per segment */ 481 otx2_setup_udp_segmentation(lso, false); 482 483 err = otx2_sync_mbox_msg(&pfvf->mbox); 484 if (err) 485 goto fail; 486 487 rsp = (struct nix_lso_format_cfg_rsp *) 488 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 489 if (IS_ERR(rsp)) 490 goto fail; 491 492 hw->lso_udpv6_idx = rsp->lso_format_idx; 493 mutex_unlock(&pfvf->mbox.lock); 494 return; 495 fail: 496 mutex_unlock(&pfvf->mbox.lock); 497 netdev_info(pfvf->netdev, 498 "Failed to get LSO index for UDP GSO offload, disabling\n"); 499 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 500 } 501 502 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 503 { 504 /* Configure CQE interrupt coalescing parameters 505 * 506 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 507 * set 1 less than cq_ecount_wait. And cq_time_wait is in 508 * usecs, convert that to 100ns count. 509 */ 510 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 511 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 512 ((u64)pfvf->hw.cq_qcount_wait << 32) | 513 (pfvf->hw.cq_ecount_wait - 1)); 514 } 515 516 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 517 dma_addr_t *dma) 518 { 519 u8 *buf; 520 521 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 522 if (unlikely(!buf)) 523 return -ENOMEM; 524 525 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 526 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 527 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 528 page_frag_free(buf); 529 return -ENOMEM; 530 } 531 532 return 0; 533 } 534 535 static int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 536 dma_addr_t *dma) 537 { 538 int ret; 539 540 local_bh_disable(); 541 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 542 local_bh_enable(); 543 return ret; 544 } 545 546 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 547 dma_addr_t *dma) 548 { 549 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) { 550 struct refill_work *work; 551 struct delayed_work *dwork; 552 553 work = &pfvf->refill_wrk[cq->cq_idx]; 554 dwork = &work->pool_refill_work; 555 /* Schedule a task if no other task is running */ 556 if (!cq->refill_task_sched) { 557 cq->refill_task_sched = true; 558 schedule_delayed_work(dwork, 559 msecs_to_jiffies(100)); 560 } 561 return -ENOMEM; 562 } 563 return 0; 564 } 565 566 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 567 { 568 struct otx2_nic *pfvf = netdev_priv(netdev); 569 570 schedule_work(&pfvf->reset_task); 571 } 572 EXPORT_SYMBOL(otx2_tx_timeout); 573 574 void otx2_get_mac_from_af(struct net_device *netdev) 575 { 576 struct otx2_nic *pfvf = netdev_priv(netdev); 577 int err; 578 579 err = otx2_hw_get_mac_addr(pfvf, netdev); 580 if (err) 581 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 582 583 /* If AF doesn't provide a valid MAC, generate a random one */ 584 if (!is_valid_ether_addr(netdev->dev_addr)) 585 eth_hw_addr_random(netdev); 586 } 587 EXPORT_SYMBOL(otx2_get_mac_from_af); 588 589 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl) 590 { 591 struct otx2_hw *hw = &pfvf->hw; 592 struct nix_txschq_config *req; 593 u64 schq, parent; 594 u64 dwrr_val; 595 596 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->max_frs); 597 598 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 599 if (!req) 600 return -ENOMEM; 601 602 req->lvl = lvl; 603 req->num_regs = 1; 604 605 schq = hw->txschq_list[lvl][0]; 606 /* Set topology e.t.c configuration */ 607 if (lvl == NIX_TXSCH_LVL_SMQ) { 608 req->reg[0] = NIX_AF_SMQX_CFG(schq); 609 req->regval[0] = ((pfvf->netdev->max_mtu + OTX2_ETH_HLEN) << 8) 610 | OTX2_MIN_MTU; 611 612 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 613 (0x2ULL << 36); 614 req->num_regs++; 615 /* MDQ config */ 616 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0]; 617 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 618 req->regval[1] = parent << 16; 619 req->num_regs++; 620 /* Set DWRR quantum */ 621 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 622 req->regval[2] = dwrr_val; 623 } else if (lvl == NIX_TXSCH_LVL_TL4) { 624 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0]; 625 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 626 req->regval[0] = parent << 16; 627 req->num_regs++; 628 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 629 req->regval[1] = dwrr_val; 630 } else if (lvl == NIX_TXSCH_LVL_TL3) { 631 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0]; 632 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 633 req->regval[0] = parent << 16; 634 req->num_regs++; 635 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 636 req->regval[1] = dwrr_val; 637 } else if (lvl == NIX_TXSCH_LVL_TL2) { 638 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0]; 639 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 640 req->regval[0] = parent << 16; 641 642 req->num_regs++; 643 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 644 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val; 645 646 req->num_regs++; 647 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 648 /* Enable this queue and backpressure */ 649 req->regval[2] = BIT_ULL(13) | BIT_ULL(12); 650 651 } else if (lvl == NIX_TXSCH_LVL_TL1) { 652 /* Default config for TL1. 653 * For VF this is always ignored. 654 */ 655 656 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 657 * clip it to 16384, so configuring a 24bit max value 658 * will work on both OTx2 and CN10K. 659 */ 660 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 661 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 662 663 req->num_regs++; 664 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 665 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 666 667 req->num_regs++; 668 req->reg[2] = NIX_AF_TL1X_CIR(schq); 669 req->regval[2] = 0; 670 } 671 672 return otx2_sync_mbox_msg(&pfvf->mbox); 673 } 674 675 int otx2_txsch_alloc(struct otx2_nic *pfvf) 676 { 677 struct nix_txsch_alloc_req *req; 678 int lvl; 679 680 /* Get memory to put this msg */ 681 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 682 if (!req) 683 return -ENOMEM; 684 685 /* Request one schq per level */ 686 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 687 req->schq[lvl] = 1; 688 689 return otx2_sync_mbox_msg(&pfvf->mbox); 690 } 691 692 int otx2_txschq_stop(struct otx2_nic *pfvf) 693 { 694 struct nix_txsch_free_req *free_req; 695 int lvl, schq, err; 696 697 mutex_lock(&pfvf->mbox.lock); 698 /* Free the transmit schedulers */ 699 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 700 if (!free_req) { 701 mutex_unlock(&pfvf->mbox.lock); 702 return -ENOMEM; 703 } 704 705 free_req->flags = TXSCHQ_FREE_ALL; 706 err = otx2_sync_mbox_msg(&pfvf->mbox); 707 mutex_unlock(&pfvf->mbox.lock); 708 709 /* Clear the txschq list */ 710 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 711 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 712 pfvf->hw.txschq_list[lvl][schq] = 0; 713 } 714 return err; 715 } 716 717 void otx2_sqb_flush(struct otx2_nic *pfvf) 718 { 719 int qidx, sqe_tail, sqe_head; 720 u64 incr, *ptr, val; 721 int timeout = 1000; 722 723 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 724 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 725 incr = (u64)qidx << 32; 726 while (timeout) { 727 val = otx2_atomic64_add(incr, ptr); 728 sqe_head = (val >> 20) & 0x3F; 729 sqe_tail = (val >> 28) & 0x3F; 730 if (sqe_head == sqe_tail) 731 break; 732 usleep_range(1, 3); 733 timeout--; 734 } 735 } 736 } 737 738 /* RED and drop levels of CQ on packet reception. 739 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 740 */ 741 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 742 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 743 744 /* RED and drop levels of AURA for packet reception. 745 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 746 * Eg: For RQ length 1K, for pass/drop level 204/230. 747 * RED accepts pkts if free pointers > 102 & <= 205. 748 * Drops pkts if free pointers < 102. 749 */ 750 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 751 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 752 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 753 754 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 755 { 756 struct otx2_qset *qset = &pfvf->qset; 757 struct nix_aq_enq_req *aq; 758 759 /* Get memory to put this msg */ 760 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 761 if (!aq) 762 return -ENOMEM; 763 764 aq->rq.cq = qidx; 765 aq->rq.ena = 1; 766 aq->rq.pb_caching = 1; 767 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 768 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 769 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 770 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 771 aq->rq.qint_idx = 0; 772 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 773 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 774 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 775 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 776 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 777 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 778 779 /* Fill AQ info */ 780 aq->qidx = qidx; 781 aq->ctype = NIX_AQ_CTYPE_RQ; 782 aq->op = NIX_AQ_INSTOP_INIT; 783 784 return otx2_sync_mbox_msg(&pfvf->mbox); 785 } 786 787 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 788 { 789 struct otx2_nic *pfvf = dev; 790 struct otx2_snd_queue *sq; 791 struct nix_aq_enq_req *aq; 792 793 sq = &pfvf->qset.sq[qidx]; 794 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 795 /* Get memory to put this msg */ 796 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 797 if (!aq) 798 return -ENOMEM; 799 800 aq->sq.cq = pfvf->hw.rx_queues + qidx; 801 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 802 aq->sq.cq_ena = 1; 803 aq->sq.ena = 1; 804 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 805 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 806 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->max_frs); 807 aq->sq.default_chan = pfvf->hw.tx_chan_base; 808 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 809 aq->sq.sqb_aura = sqb_aura; 810 aq->sq.sq_int_ena = NIX_SQINT_BITS; 811 aq->sq.qint_idx = 0; 812 /* Due pipelining impact minimum 2000 unused SQ CQE's 813 * need to maintain to avoid CQ overflow. 814 */ 815 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 816 817 /* Fill AQ info */ 818 aq->qidx = qidx; 819 aq->ctype = NIX_AQ_CTYPE_SQ; 820 aq->op = NIX_AQ_INSTOP_INIT; 821 822 return otx2_sync_mbox_msg(&pfvf->mbox); 823 } 824 825 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 826 { 827 struct otx2_qset *qset = &pfvf->qset; 828 struct otx2_snd_queue *sq; 829 struct otx2_pool *pool; 830 int err; 831 832 pool = &pfvf->qset.pool[sqb_aura]; 833 sq = &qset->sq[qidx]; 834 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 835 sq->sqe_cnt = qset->sqe_cnt; 836 837 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 838 if (err) 839 return err; 840 841 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 842 TSO_HEADER_SIZE); 843 if (err) 844 return err; 845 846 sq->sqe_base = sq->sqe->base; 847 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 848 if (!sq->sg) 849 return -ENOMEM; 850 851 if (pfvf->ptp) { 852 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 853 sizeof(*sq->timestamps)); 854 if (err) 855 return err; 856 } 857 858 sq->head = 0; 859 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 860 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 861 /* Set SQE threshold to 10% of total SQEs */ 862 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 863 sq->aura_id = sqb_aura; 864 sq->aura_fc_addr = pool->fc_addr->base; 865 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 866 867 sq->stats.bytes = 0; 868 sq->stats.pkts = 0; 869 870 return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); 871 872 } 873 874 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 875 { 876 struct otx2_qset *qset = &pfvf->qset; 877 struct nix_aq_enq_req *aq; 878 struct otx2_cq_queue *cq; 879 int err, pool_id; 880 881 cq = &qset->cq[qidx]; 882 cq->cq_idx = qidx; 883 if (qidx < pfvf->hw.rx_queues) { 884 cq->cq_type = CQ_RX; 885 cq->cint_idx = qidx; 886 cq->cqe_cnt = qset->rqe_cnt; 887 } else { 888 cq->cq_type = CQ_TX; 889 cq->cint_idx = qidx - pfvf->hw.rx_queues; 890 cq->cqe_cnt = qset->sqe_cnt; 891 } 892 cq->cqe_size = pfvf->qset.xqe_size; 893 894 /* Allocate memory for CQEs */ 895 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 896 if (err) 897 return err; 898 899 /* Save CQE CPU base for faster reference */ 900 cq->cqe_base = cq->cqe->base; 901 /* In case where all RQs auras point to single pool, 902 * all CQs receive buffer pool also point to same pool. 903 */ 904 pool_id = ((cq->cq_type == CQ_RX) && 905 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 906 cq->rbpool = &qset->pool[pool_id]; 907 cq->refill_task_sched = false; 908 909 /* Get memory to put this msg */ 910 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 911 if (!aq) 912 return -ENOMEM; 913 914 aq->cq.ena = 1; 915 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 916 aq->cq.caching = 1; 917 aq->cq.base = cq->cqe->iova; 918 aq->cq.cint_idx = cq->cint_idx; 919 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 920 aq->cq.qint_idx = 0; 921 aq->cq.avg_level = 255; 922 923 if (qidx < pfvf->hw.rx_queues) { 924 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 925 aq->cq.drop_ena = 1; 926 927 if (!is_otx2_lbkvf(pfvf->pdev)) { 928 /* Enable receive CQ backpressure */ 929 aq->cq.bp_ena = 1; 930 aq->cq.bpid = pfvf->bpid[0]; 931 932 /* Set backpressure level is same as cq pass level */ 933 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 934 } 935 } 936 937 /* Fill AQ info */ 938 aq->qidx = qidx; 939 aq->ctype = NIX_AQ_CTYPE_CQ; 940 aq->op = NIX_AQ_INSTOP_INIT; 941 942 return otx2_sync_mbox_msg(&pfvf->mbox); 943 } 944 945 static void otx2_pool_refill_task(struct work_struct *work) 946 { 947 struct otx2_cq_queue *cq; 948 struct otx2_pool *rbpool; 949 struct refill_work *wrk; 950 int qidx, free_ptrs = 0; 951 struct otx2_nic *pfvf; 952 dma_addr_t bufptr; 953 954 wrk = container_of(work, struct refill_work, pool_refill_work.work); 955 pfvf = wrk->pf; 956 qidx = wrk - pfvf->refill_wrk; 957 cq = &pfvf->qset.cq[qidx]; 958 rbpool = cq->rbpool; 959 free_ptrs = cq->pool_ptrs; 960 961 while (cq->pool_ptrs) { 962 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) { 963 /* Schedule a WQ if we fails to free atleast half of the 964 * pointers else enable napi for this RQ. 965 */ 966 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 967 struct delayed_work *dwork; 968 969 dwork = &wrk->pool_refill_work; 970 schedule_delayed_work(dwork, 971 msecs_to_jiffies(100)); 972 } else { 973 cq->refill_task_sched = false; 974 } 975 return; 976 } 977 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 978 cq->pool_ptrs--; 979 } 980 cq->refill_task_sched = false; 981 } 982 983 int otx2_config_nix_queues(struct otx2_nic *pfvf) 984 { 985 int qidx, err; 986 987 /* Initialize RX queues */ 988 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 989 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 990 991 err = otx2_rq_init(pfvf, qidx, lpb_aura); 992 if (err) 993 return err; 994 } 995 996 /* Initialize TX queues */ 997 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 998 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 999 1000 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1001 if (err) 1002 return err; 1003 } 1004 1005 /* Initialize completion queues */ 1006 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1007 err = otx2_cq_init(pfvf, qidx); 1008 if (err) 1009 return err; 1010 } 1011 1012 /* Initialize work queue for receive buffer refill */ 1013 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1014 sizeof(struct refill_work), GFP_KERNEL); 1015 if (!pfvf->refill_wrk) 1016 return -ENOMEM; 1017 1018 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1019 pfvf->refill_wrk[qidx].pf = pfvf; 1020 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1021 otx2_pool_refill_task); 1022 } 1023 return 0; 1024 } 1025 1026 int otx2_config_nix(struct otx2_nic *pfvf) 1027 { 1028 struct nix_lf_alloc_req *nixlf; 1029 struct nix_lf_alloc_rsp *rsp; 1030 int err; 1031 1032 pfvf->qset.xqe_size = NIX_XQESZ_W16 ? 128 : 512; 1033 1034 /* Get memory to put this msg */ 1035 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1036 if (!nixlf) 1037 return -ENOMEM; 1038 1039 /* Set RQ/SQ/CQ counts */ 1040 nixlf->rq_cnt = pfvf->hw.rx_queues; 1041 nixlf->sq_cnt = pfvf->hw.tx_queues; 1042 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1043 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1044 nixlf->rss_grps = MAX_RSS_GROUPS; 1045 nixlf->xqe_sz = NIX_XQESZ_W16; 1046 /* We don't know absolute NPA LF idx attached. 1047 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1048 * NPA LF attached to this RVU PF/VF. 1049 */ 1050 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1051 /* Disable alignment pad, enable L2 length check, 1052 * enable L4 TCP/UDP checksum verification. 1053 */ 1054 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1055 1056 err = otx2_sync_mbox_msg(&pfvf->mbox); 1057 if (err) 1058 return err; 1059 1060 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1061 &nixlf->hdr); 1062 if (IS_ERR(rsp)) 1063 return PTR_ERR(rsp); 1064 1065 if (rsp->qints < 1) 1066 return -ENXIO; 1067 1068 return rsp->hdr.rc; 1069 } 1070 1071 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1072 { 1073 struct otx2_qset *qset = &pfvf->qset; 1074 struct otx2_hw *hw = &pfvf->hw; 1075 struct otx2_snd_queue *sq; 1076 int sqb, qidx; 1077 u64 iova, pa; 1078 1079 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1080 sq = &qset->sq[qidx]; 1081 if (!sq->sqb_ptrs) 1082 continue; 1083 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1084 if (!sq->sqb_ptrs[sqb]) 1085 continue; 1086 iova = sq->sqb_ptrs[sqb]; 1087 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1088 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1089 DMA_FROM_DEVICE, 1090 DMA_ATTR_SKIP_CPU_SYNC); 1091 put_page(virt_to_page(phys_to_virt(pa))); 1092 } 1093 sq->sqb_count = 0; 1094 } 1095 } 1096 1097 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1098 { 1099 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1100 u64 iova, pa; 1101 1102 if (type == AURA_NIX_SQ) { 1103 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1104 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1105 size = pfvf->hw.sqb_size; 1106 } 1107 if (type == AURA_NIX_RQ) { 1108 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1109 pool_end = pfvf->hw.rqpool_cnt; 1110 size = pfvf->rbsize; 1111 } 1112 1113 /* Free SQB and RQB pointers from the aura pool */ 1114 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1115 iova = otx2_aura_allocptr(pfvf, pool_id); 1116 while (iova) { 1117 if (type == AURA_NIX_RQ) 1118 iova -= OTX2_HEAD_ROOM; 1119 1120 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1121 dma_unmap_page_attrs(pfvf->dev, iova, size, 1122 DMA_FROM_DEVICE, 1123 DMA_ATTR_SKIP_CPU_SYNC); 1124 put_page(virt_to_page(phys_to_virt(pa))); 1125 iova = otx2_aura_allocptr(pfvf, pool_id); 1126 } 1127 } 1128 } 1129 1130 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1131 { 1132 struct otx2_pool *pool; 1133 int pool_id; 1134 1135 if (!pfvf->qset.pool) 1136 return; 1137 1138 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1139 pool = &pfvf->qset.pool[pool_id]; 1140 qmem_free(pfvf->dev, pool->stack); 1141 qmem_free(pfvf->dev, pool->fc_addr); 1142 } 1143 devm_kfree(pfvf->dev, pfvf->qset.pool); 1144 pfvf->qset.pool = NULL; 1145 } 1146 1147 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1148 int pool_id, int numptrs) 1149 { 1150 struct npa_aq_enq_req *aq; 1151 struct otx2_pool *pool; 1152 int err; 1153 1154 pool = &pfvf->qset.pool[pool_id]; 1155 1156 /* Allocate memory for HW to update Aura count. 1157 * Alloc one cache line, so that it fits all FC_STYPE modes. 1158 */ 1159 if (!pool->fc_addr) { 1160 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1161 if (err) 1162 return err; 1163 } 1164 1165 /* Initialize this aura's context via AF */ 1166 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1167 if (!aq) { 1168 /* Shared mbox memory buffer is full, flush it and retry */ 1169 err = otx2_sync_mbox_msg(&pfvf->mbox); 1170 if (err) 1171 return err; 1172 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1173 if (!aq) 1174 return -ENOMEM; 1175 } 1176 1177 aq->aura_id = aura_id; 1178 /* Will be filled by AF with correct pool context address */ 1179 aq->aura.pool_addr = pool_id; 1180 aq->aura.pool_caching = 1; 1181 aq->aura.shift = ilog2(numptrs) - 8; 1182 aq->aura.count = numptrs; 1183 aq->aura.limit = numptrs; 1184 aq->aura.avg_level = 255; 1185 aq->aura.ena = 1; 1186 aq->aura.fc_ena = 1; 1187 aq->aura.fc_addr = pool->fc_addr->iova; 1188 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1189 1190 /* Enable backpressure for RQ aura */ 1191 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1192 aq->aura.bp_ena = 0; 1193 /* If NIX1 LF is attached then specify NIX1_RX. 1194 * 1195 * Below NPA_AURA_S[BP_ENA] is set according to the 1196 * NPA_BPINTF_E enumeration given as: 1197 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1198 * NIX0_RX is 0x0 + 0*0x1 = 0 1199 * NIX1_RX is 0x0 + 1*0x1 = 1 1200 * But in HRM it is given that 1201 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1202 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1203 * enumerated by NPA_BPINTF_E." 1204 */ 1205 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1206 aq->aura.bp_ena = 1; 1207 aq->aura.nix0_bpid = pfvf->bpid[0]; 1208 1209 /* Set backpressure level for RQ's Aura */ 1210 aq->aura.bp = RQ_BP_LVL_AURA; 1211 } 1212 1213 /* Fill AQ info */ 1214 aq->ctype = NPA_AQ_CTYPE_AURA; 1215 aq->op = NPA_AQ_INSTOP_INIT; 1216 1217 return 0; 1218 } 1219 1220 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1221 int stack_pages, int numptrs, int buf_size) 1222 { 1223 struct npa_aq_enq_req *aq; 1224 struct otx2_pool *pool; 1225 int err; 1226 1227 pool = &pfvf->qset.pool[pool_id]; 1228 /* Alloc memory for stack which is used to store buffer pointers */ 1229 err = qmem_alloc(pfvf->dev, &pool->stack, 1230 stack_pages, pfvf->hw.stack_pg_bytes); 1231 if (err) 1232 return err; 1233 1234 pool->rbsize = buf_size; 1235 1236 /* Set LMTST addr for NPA batch free */ 1237 if (test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) 1238 pool->lmt_addr = (__force u64 *)((u64)pfvf->hw.npa_lmt_base + 1239 (pool_id * LMT_LINE_SIZE)); 1240 1241 /* Initialize this pool's context via AF */ 1242 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1243 if (!aq) { 1244 /* Shared mbox memory buffer is full, flush it and retry */ 1245 err = otx2_sync_mbox_msg(&pfvf->mbox); 1246 if (err) { 1247 qmem_free(pfvf->dev, pool->stack); 1248 return err; 1249 } 1250 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1251 if (!aq) { 1252 qmem_free(pfvf->dev, pool->stack); 1253 return -ENOMEM; 1254 } 1255 } 1256 1257 aq->aura_id = pool_id; 1258 aq->pool.stack_base = pool->stack->iova; 1259 aq->pool.stack_caching = 1; 1260 aq->pool.ena = 1; 1261 aq->pool.buf_size = buf_size / 128; 1262 aq->pool.stack_max_pages = stack_pages; 1263 aq->pool.shift = ilog2(numptrs) - 8; 1264 aq->pool.ptr_start = 0; 1265 aq->pool.ptr_end = ~0ULL; 1266 1267 /* Fill AQ info */ 1268 aq->ctype = NPA_AQ_CTYPE_POOL; 1269 aq->op = NPA_AQ_INSTOP_INIT; 1270 1271 return 0; 1272 } 1273 1274 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1275 { 1276 int qidx, pool_id, stack_pages, num_sqbs; 1277 struct otx2_qset *qset = &pfvf->qset; 1278 struct otx2_hw *hw = &pfvf->hw; 1279 struct otx2_snd_queue *sq; 1280 struct otx2_pool *pool; 1281 dma_addr_t bufptr; 1282 int err, ptr; 1283 1284 /* Calculate number of SQBs needed. 1285 * 1286 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1287 * Last SQE is used for pointing to next SQB. 1288 */ 1289 num_sqbs = (hw->sqb_size / 128) - 1; 1290 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1291 1292 /* Get no of stack pages needed */ 1293 stack_pages = 1294 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1295 1296 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1297 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1298 /* Initialize aura context */ 1299 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1300 if (err) 1301 goto fail; 1302 1303 /* Initialize pool context */ 1304 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1305 num_sqbs, hw->sqb_size); 1306 if (err) 1307 goto fail; 1308 } 1309 1310 /* Flush accumulated messages */ 1311 err = otx2_sync_mbox_msg(&pfvf->mbox); 1312 if (err) 1313 goto fail; 1314 1315 /* Allocate pointers and free them to aura/pool */ 1316 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1317 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1318 pool = &pfvf->qset.pool[pool_id]; 1319 1320 sq = &qset->sq[qidx]; 1321 sq->sqb_count = 0; 1322 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1323 if (!sq->sqb_ptrs) 1324 return -ENOMEM; 1325 1326 for (ptr = 0; ptr < num_sqbs; ptr++) { 1327 if (otx2_alloc_rbuf(pfvf, pool, &bufptr)) 1328 return -ENOMEM; 1329 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1330 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1331 } 1332 } 1333 1334 return 0; 1335 fail: 1336 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1337 otx2_aura_pool_free(pfvf); 1338 return err; 1339 } 1340 1341 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1342 { 1343 struct otx2_hw *hw = &pfvf->hw; 1344 int stack_pages, pool_id, rq; 1345 struct otx2_pool *pool; 1346 int err, ptr, num_ptrs; 1347 dma_addr_t bufptr; 1348 1349 num_ptrs = pfvf->qset.rqe_cnt; 1350 1351 stack_pages = 1352 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1353 1354 for (rq = 0; rq < hw->rx_queues; rq++) { 1355 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1356 /* Initialize aura context */ 1357 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1358 if (err) 1359 goto fail; 1360 } 1361 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1362 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1363 num_ptrs, pfvf->rbsize); 1364 if (err) 1365 goto fail; 1366 } 1367 1368 /* Flush accumulated messages */ 1369 err = otx2_sync_mbox_msg(&pfvf->mbox); 1370 if (err) 1371 goto fail; 1372 1373 /* Allocate pointers and free them to aura/pool */ 1374 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1375 pool = &pfvf->qset.pool[pool_id]; 1376 for (ptr = 0; ptr < num_ptrs; ptr++) { 1377 if (otx2_alloc_rbuf(pfvf, pool, &bufptr)) 1378 return -ENOMEM; 1379 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1380 bufptr + OTX2_HEAD_ROOM); 1381 } 1382 } 1383 1384 return 0; 1385 fail: 1386 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1387 otx2_aura_pool_free(pfvf); 1388 return err; 1389 } 1390 1391 int otx2_config_npa(struct otx2_nic *pfvf) 1392 { 1393 struct otx2_qset *qset = &pfvf->qset; 1394 struct npa_lf_alloc_req *npalf; 1395 struct otx2_hw *hw = &pfvf->hw; 1396 int aura_cnt; 1397 1398 /* Pool - Stack of free buffer pointers 1399 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1400 */ 1401 1402 if (!hw->pool_cnt) 1403 return -EINVAL; 1404 1405 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1406 sizeof(struct otx2_pool), GFP_KERNEL); 1407 if (!qset->pool) 1408 return -ENOMEM; 1409 1410 /* Get memory to put this msg */ 1411 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1412 if (!npalf) 1413 return -ENOMEM; 1414 1415 /* Set aura and pool counts */ 1416 npalf->nr_pools = hw->pool_cnt; 1417 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1418 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1419 1420 return otx2_sync_mbox_msg(&pfvf->mbox); 1421 } 1422 1423 int otx2_detach_resources(struct mbox *mbox) 1424 { 1425 struct rsrc_detach *detach; 1426 1427 mutex_lock(&mbox->lock); 1428 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1429 if (!detach) { 1430 mutex_unlock(&mbox->lock); 1431 return -ENOMEM; 1432 } 1433 1434 /* detach all */ 1435 detach->partial = false; 1436 1437 /* Send detach request to AF */ 1438 otx2_mbox_msg_send(&mbox->mbox, 0); 1439 mutex_unlock(&mbox->lock); 1440 return 0; 1441 } 1442 EXPORT_SYMBOL(otx2_detach_resources); 1443 1444 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1445 { 1446 struct rsrc_attach *attach; 1447 struct msg_req *msix; 1448 int err; 1449 1450 mutex_lock(&pfvf->mbox.lock); 1451 /* Get memory to put this msg */ 1452 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1453 if (!attach) { 1454 mutex_unlock(&pfvf->mbox.lock); 1455 return -ENOMEM; 1456 } 1457 1458 attach->npalf = true; 1459 attach->nixlf = true; 1460 1461 /* Send attach request to AF */ 1462 err = otx2_sync_mbox_msg(&pfvf->mbox); 1463 if (err) { 1464 mutex_unlock(&pfvf->mbox.lock); 1465 return err; 1466 } 1467 1468 pfvf->nix_blkaddr = BLKADDR_NIX0; 1469 1470 /* If the platform has two NIX blocks then LF may be 1471 * allocated from NIX1. 1472 */ 1473 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1474 pfvf->nix_blkaddr = BLKADDR_NIX1; 1475 1476 /* Get NPA and NIX MSIX vector offsets */ 1477 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1478 if (!msix) { 1479 mutex_unlock(&pfvf->mbox.lock); 1480 return -ENOMEM; 1481 } 1482 1483 err = otx2_sync_mbox_msg(&pfvf->mbox); 1484 if (err) { 1485 mutex_unlock(&pfvf->mbox.lock); 1486 return err; 1487 } 1488 mutex_unlock(&pfvf->mbox.lock); 1489 1490 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1491 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1492 dev_err(pfvf->dev, 1493 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1494 return -EINVAL; 1495 } 1496 1497 return 0; 1498 } 1499 EXPORT_SYMBOL(otx2_attach_npa_nix); 1500 1501 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1502 { 1503 struct hwctx_disable_req *req; 1504 1505 mutex_lock(&mbox->lock); 1506 /* Request AQ to disable this context */ 1507 if (npa) 1508 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1509 else 1510 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1511 1512 if (!req) { 1513 mutex_unlock(&mbox->lock); 1514 return; 1515 } 1516 1517 req->ctype = type; 1518 1519 if (otx2_sync_mbox_msg(mbox)) 1520 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1521 __func__); 1522 1523 mutex_unlock(&mbox->lock); 1524 } 1525 1526 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1527 { 1528 struct nix_bp_cfg_req *req; 1529 1530 if (enable) 1531 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1532 else 1533 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1534 1535 if (!req) 1536 return -ENOMEM; 1537 1538 req->chan_base = 0; 1539 req->chan_cnt = 1; 1540 req->bpid_per_chan = 0; 1541 1542 return otx2_sync_mbox_msg(&pfvf->mbox); 1543 } 1544 1545 /* Mbox message handlers */ 1546 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1547 struct cgx_stats_rsp *rsp) 1548 { 1549 int id; 1550 1551 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1552 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1553 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1554 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1555 } 1556 1557 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1558 struct cgx_fec_stats_rsp *rsp) 1559 { 1560 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1561 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1562 } 1563 1564 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1565 struct nix_txsch_alloc_rsp *rsp) 1566 { 1567 int lvl, schq; 1568 1569 /* Setup transmit scheduler list */ 1570 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 1571 for (schq = 0; schq < rsp->schq[lvl]; schq++) 1572 pf->hw.txschq_list[lvl][schq] = 1573 rsp->schq_list[lvl][schq]; 1574 } 1575 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc); 1576 1577 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1578 struct npa_lf_alloc_rsp *rsp) 1579 { 1580 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1581 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1582 } 1583 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1584 1585 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1586 struct nix_lf_alloc_rsp *rsp) 1587 { 1588 pfvf->hw.sqb_size = rsp->sqb_size; 1589 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1590 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1591 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1592 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1593 pfvf->hw.cgx_links = rsp->cgx_links; 1594 pfvf->hw.lbk_links = rsp->lbk_links; 1595 pfvf->hw.tx_link = rsp->tx_link; 1596 } 1597 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1598 1599 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1600 struct msix_offset_rsp *rsp) 1601 { 1602 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1603 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1604 } 1605 EXPORT_SYMBOL(mbox_handler_msix_offset); 1606 1607 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1608 struct nix_bp_cfg_rsp *rsp) 1609 { 1610 int chan, chan_id; 1611 1612 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1613 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1614 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1615 } 1616 } 1617 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1618 1619 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1620 { 1621 struct otx2_qset *qset = &pfvf->qset; 1622 struct otx2_hw *hw = &pfvf->hw; 1623 int irq, qidx; 1624 1625 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1626 qidx < n; 1627 qidx++, irq++) { 1628 int vector = pci_irq_vector(pfvf->pdev, irq); 1629 1630 irq_set_affinity_hint(vector, NULL); 1631 free_cpumask_var(hw->affinity_mask[irq]); 1632 free_irq(vector, &qset->napi[qidx]); 1633 } 1634 } 1635 1636 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1637 { 1638 struct otx2_hw *hw = &pfvf->hw; 1639 int vec, cpu, irq, cint; 1640 1641 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1642 cpu = cpumask_first(cpu_online_mask); 1643 1644 /* CQ interrupts */ 1645 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1646 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1647 return; 1648 1649 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1650 1651 irq = pci_irq_vector(pfvf->pdev, vec); 1652 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1653 1654 cpu = cpumask_next(cpu, cpu_online_mask); 1655 if (unlikely(cpu >= nr_cpu_ids)) 1656 cpu = 0; 1657 } 1658 } 1659 1660 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1661 { 1662 struct nix_hw_info *rsp; 1663 struct msg_req *req; 1664 u16 max_mtu; 1665 int rc; 1666 1667 mutex_lock(&pfvf->mbox.lock); 1668 1669 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1670 if (!req) { 1671 rc = -ENOMEM; 1672 goto out; 1673 } 1674 1675 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1676 if (!rc) { 1677 rsp = (struct nix_hw_info *) 1678 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1679 1680 /* HW counts VLAN insertion bytes (8 for double tag) 1681 * irrespective of whether SQE is requesting to insert VLAN 1682 * in the packet or not. Hence these 8 bytes have to be 1683 * discounted from max packet size otherwise HW will throw 1684 * SMQ errors 1685 */ 1686 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1687 1688 /* Also save DWRR MTU, needed for DWRR weight calculation */ 1689 pfvf->hw.dwrr_mtu = rsp->rpm_dwrr_mtu; 1690 if (!pfvf->hw.dwrr_mtu) 1691 pfvf->hw.dwrr_mtu = 1; 1692 } 1693 1694 out: 1695 mutex_unlock(&pfvf->mbox.lock); 1696 if (rc) { 1697 dev_warn(pfvf->dev, 1698 "Failed to get MTU from hardware setting default value(1500)\n"); 1699 max_mtu = 1500; 1700 } 1701 return max_mtu; 1702 } 1703 EXPORT_SYMBOL(otx2_get_max_mtu); 1704 1705 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1706 int __weak \ 1707 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1708 struct _req_type *req, \ 1709 struct _rsp_type *rsp) \ 1710 { \ 1711 /* Nothing to do here */ \ 1712 return 0; \ 1713 } \ 1714 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1715 MBOX_UP_CGX_MESSAGES 1716 #undef M 1717