1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 #include <net/tso.h> 11 12 #include "otx2_reg.h" 13 #include "otx2_common.h" 14 #include "otx2_struct.h" 15 #include "cn10k.h" 16 17 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 18 struct otx2_nic *pfvf, int qidx) 19 { 20 u64 incr = (u64)qidx << 32; 21 u64 *ptr; 22 23 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 24 stats->bytes = otx2_atomic64_add(incr, ptr); 25 26 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 27 stats->pkts = otx2_atomic64_add(incr, ptr); 28 } 29 30 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 31 struct otx2_nic *pfvf, int qidx) 32 { 33 u64 incr = (u64)qidx << 32; 34 u64 *ptr; 35 36 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 37 stats->bytes = otx2_atomic64_add(incr, ptr); 38 39 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 40 stats->pkts = otx2_atomic64_add(incr, ptr); 41 } 42 43 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 44 { 45 struct msg_req *req; 46 47 if (!netif_running(pfvf->netdev)) 48 return; 49 50 mutex_lock(&pfvf->mbox.lock); 51 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 52 if (!req) { 53 mutex_unlock(&pfvf->mbox.lock); 54 return; 55 } 56 57 otx2_sync_mbox_msg(&pfvf->mbox); 58 mutex_unlock(&pfvf->mbox.lock); 59 } 60 61 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 62 { 63 struct msg_req *req; 64 65 if (!netif_running(pfvf->netdev)) 66 return; 67 mutex_lock(&pfvf->mbox.lock); 68 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 69 if (req) 70 otx2_sync_mbox_msg(&pfvf->mbox); 71 mutex_unlock(&pfvf->mbox.lock); 72 } 73 74 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 75 { 76 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 77 78 if (!pfvf->qset.rq) 79 return 0; 80 81 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 82 return 1; 83 } 84 85 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 86 { 87 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 88 89 if (!pfvf->qset.sq) 90 return 0; 91 92 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 93 return 1; 94 } 95 96 void otx2_get_dev_stats(struct otx2_nic *pfvf) 97 { 98 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 99 100 #define OTX2_GET_RX_STATS(reg) \ 101 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 102 #define OTX2_GET_TX_STATS(reg) \ 103 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 104 105 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 106 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 107 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 108 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 109 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 110 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 111 dev_stats->rx_mcast_frames + 112 dev_stats->rx_ucast_frames; 113 114 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 115 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 116 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 117 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 118 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 119 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 120 dev_stats->tx_mcast_frames + 121 dev_stats->tx_ucast_frames; 122 } 123 124 void otx2_get_stats64(struct net_device *netdev, 125 struct rtnl_link_stats64 *stats) 126 { 127 struct otx2_nic *pfvf = netdev_priv(netdev); 128 struct otx2_dev_stats *dev_stats; 129 130 otx2_get_dev_stats(pfvf); 131 132 dev_stats = &pfvf->hw.dev_stats; 133 stats->rx_bytes = dev_stats->rx_bytes; 134 stats->rx_packets = dev_stats->rx_frames; 135 stats->rx_dropped = dev_stats->rx_drops; 136 stats->multicast = dev_stats->rx_mcast_frames; 137 138 stats->tx_bytes = dev_stats->tx_bytes; 139 stats->tx_packets = dev_stats->tx_frames; 140 stats->tx_dropped = dev_stats->tx_drops; 141 } 142 EXPORT_SYMBOL(otx2_get_stats64); 143 144 /* Sync MAC address with RVU AF */ 145 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 146 { 147 struct nix_set_mac_addr *req; 148 int err; 149 150 mutex_lock(&pfvf->mbox.lock); 151 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 152 if (!req) { 153 mutex_unlock(&pfvf->mbox.lock); 154 return -ENOMEM; 155 } 156 157 ether_addr_copy(req->mac_addr, mac); 158 159 err = otx2_sync_mbox_msg(&pfvf->mbox); 160 mutex_unlock(&pfvf->mbox.lock); 161 return err; 162 } 163 164 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 165 struct net_device *netdev) 166 { 167 struct nix_get_mac_addr_rsp *rsp; 168 struct mbox_msghdr *msghdr; 169 struct msg_req *req; 170 int err; 171 172 mutex_lock(&pfvf->mbox.lock); 173 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 174 if (!req) { 175 mutex_unlock(&pfvf->mbox.lock); 176 return -ENOMEM; 177 } 178 179 err = otx2_sync_mbox_msg(&pfvf->mbox); 180 if (err) { 181 mutex_unlock(&pfvf->mbox.lock); 182 return err; 183 } 184 185 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 186 if (IS_ERR(msghdr)) { 187 mutex_unlock(&pfvf->mbox.lock); 188 return PTR_ERR(msghdr); 189 } 190 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 191 eth_hw_addr_set(netdev, rsp->mac_addr); 192 mutex_unlock(&pfvf->mbox.lock); 193 194 return 0; 195 } 196 197 int otx2_set_mac_address(struct net_device *netdev, void *p) 198 { 199 struct otx2_nic *pfvf = netdev_priv(netdev); 200 struct sockaddr *addr = p; 201 202 if (!is_valid_ether_addr(addr->sa_data)) 203 return -EADDRNOTAVAIL; 204 205 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 206 eth_hw_addr_set(netdev, addr->sa_data); 207 /* update dmac field in vlan offload rule */ 208 if (netif_running(netdev) && 209 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 210 otx2_install_rxvlan_offload_flow(pfvf); 211 /* update dmac address in ntuple and DMAC filter list */ 212 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 213 otx2_dmacflt_update_pfmac_flow(pfvf); 214 } else { 215 return -EPERM; 216 } 217 218 return 0; 219 } 220 EXPORT_SYMBOL(otx2_set_mac_address); 221 222 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 223 { 224 struct nix_frs_cfg *req; 225 int err; 226 227 mutex_lock(&pfvf->mbox.lock); 228 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 229 if (!req) { 230 mutex_unlock(&pfvf->mbox.lock); 231 return -ENOMEM; 232 } 233 234 req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 235 236 err = otx2_sync_mbox_msg(&pfvf->mbox); 237 mutex_unlock(&pfvf->mbox.lock); 238 return err; 239 } 240 241 int otx2_config_pause_frm(struct otx2_nic *pfvf) 242 { 243 struct cgx_pause_frm_cfg *req; 244 int err; 245 246 if (is_otx2_lbkvf(pfvf->pdev)) 247 return 0; 248 249 mutex_lock(&pfvf->mbox.lock); 250 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 251 if (!req) { 252 err = -ENOMEM; 253 goto unlock; 254 } 255 256 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 257 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 258 req->set = 1; 259 260 err = otx2_sync_mbox_msg(&pfvf->mbox); 261 unlock: 262 mutex_unlock(&pfvf->mbox.lock); 263 return err; 264 } 265 266 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 267 { 268 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 269 struct nix_rss_flowkey_cfg_rsp *rsp; 270 struct nix_rss_flowkey_cfg *req; 271 int err; 272 273 mutex_lock(&pfvf->mbox.lock); 274 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 275 if (!req) { 276 mutex_unlock(&pfvf->mbox.lock); 277 return -ENOMEM; 278 } 279 req->mcam_index = -1; /* Default or reserved index */ 280 req->flowkey_cfg = rss->flowkey_cfg; 281 req->group = DEFAULT_RSS_CONTEXT_GROUP; 282 283 err = otx2_sync_mbox_msg(&pfvf->mbox); 284 if (err) 285 goto fail; 286 287 rsp = (struct nix_rss_flowkey_cfg_rsp *) 288 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 289 if (IS_ERR(rsp)) { 290 err = PTR_ERR(rsp); 291 goto fail; 292 } 293 294 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 295 fail: 296 mutex_unlock(&pfvf->mbox.lock); 297 return err; 298 } 299 300 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 301 { 302 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 303 const int index = rss->rss_size * ctx_id; 304 struct mbox *mbox = &pfvf->mbox; 305 struct otx2_rss_ctx *rss_ctx; 306 struct nix_aq_enq_req *aq; 307 int idx, err; 308 309 mutex_lock(&mbox->lock); 310 rss_ctx = rss->rss_ctx[ctx_id]; 311 /* Get memory to put this msg */ 312 for (idx = 0; idx < rss->rss_size; idx++) { 313 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 314 if (!aq) { 315 /* The shared memory buffer can be full. 316 * Flush it and retry 317 */ 318 err = otx2_sync_mbox_msg(mbox); 319 if (err) { 320 mutex_unlock(&mbox->lock); 321 return err; 322 } 323 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 324 if (!aq) { 325 mutex_unlock(&mbox->lock); 326 return -ENOMEM; 327 } 328 } 329 330 aq->rss.rq = rss_ctx->ind_tbl[idx]; 331 332 /* Fill AQ info */ 333 aq->qidx = index + idx; 334 aq->ctype = NIX_AQ_CTYPE_RSS; 335 aq->op = NIX_AQ_INSTOP_INIT; 336 } 337 err = otx2_sync_mbox_msg(mbox); 338 mutex_unlock(&mbox->lock); 339 return err; 340 } 341 342 void otx2_set_rss_key(struct otx2_nic *pfvf) 343 { 344 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 345 u64 *key = (u64 *)&rss->key[4]; 346 int idx; 347 348 /* 352bit or 44byte key needs to be configured as below 349 * NIX_LF_RX_SECRETX0 = key<351:288> 350 * NIX_LF_RX_SECRETX1 = key<287:224> 351 * NIX_LF_RX_SECRETX2 = key<223:160> 352 * NIX_LF_RX_SECRETX3 = key<159:96> 353 * NIX_LF_RX_SECRETX4 = key<95:32> 354 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 355 */ 356 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 357 (u64)(*((u32 *)&rss->key)) << 32); 358 idx = sizeof(rss->key) / sizeof(u64); 359 while (idx > 0) { 360 idx--; 361 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 362 } 363 } 364 365 int otx2_rss_init(struct otx2_nic *pfvf) 366 { 367 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 368 struct otx2_rss_ctx *rss_ctx; 369 int idx, ret = 0; 370 371 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 372 373 /* Init RSS key if it is not setup already */ 374 if (!rss->enable) 375 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 376 otx2_set_rss_key(pfvf); 377 378 if (!netif_is_rxfh_configured(pfvf->netdev)) { 379 /* Set RSS group 0 as default indirection table */ 380 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 381 GFP_KERNEL); 382 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 383 return -ENOMEM; 384 385 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 386 for (idx = 0; idx < rss->rss_size; idx++) 387 rss_ctx->ind_tbl[idx] = 388 ethtool_rxfh_indir_default(idx, 389 pfvf->hw.rx_queues); 390 } 391 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 392 if (ret) 393 return ret; 394 395 /* Flowkey or hash config to be used for generating flow tag */ 396 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 397 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 398 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 399 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 400 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 401 402 ret = otx2_set_flowkey_cfg(pfvf); 403 if (ret) 404 return ret; 405 406 rss->enable = true; 407 return 0; 408 } 409 410 /* Setup UDP segmentation algorithm in HW */ 411 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 412 { 413 struct nix_lso_format *field; 414 415 field = (struct nix_lso_format *)&lso->fields[0]; 416 lso->field_mask = GENMASK(18, 0); 417 418 /* IP's Length field */ 419 field->layer = NIX_TXLAYER_OL3; 420 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 421 field->offset = v4 ? 2 : 4; 422 field->sizem1 = 1; /* i.e 2 bytes */ 423 field->alg = NIX_LSOALG_ADD_PAYLEN; 424 field++; 425 426 /* No ID field in IPv6 header */ 427 if (v4) { 428 /* Increment IPID */ 429 field->layer = NIX_TXLAYER_OL3; 430 field->offset = 4; 431 field->sizem1 = 1; /* i.e 2 bytes */ 432 field->alg = NIX_LSOALG_ADD_SEGNUM; 433 field++; 434 } 435 436 /* Update length in UDP header */ 437 field->layer = NIX_TXLAYER_OL4; 438 field->offset = 4; 439 field->sizem1 = 1; 440 field->alg = NIX_LSOALG_ADD_PAYLEN; 441 } 442 443 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 444 void otx2_setup_segmentation(struct otx2_nic *pfvf) 445 { 446 struct nix_lso_format_cfg_rsp *rsp; 447 struct nix_lso_format_cfg *lso; 448 struct otx2_hw *hw = &pfvf->hw; 449 int err; 450 451 mutex_lock(&pfvf->mbox.lock); 452 453 /* UDPv4 segmentation */ 454 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 455 if (!lso) 456 goto fail; 457 458 /* Setup UDP/IP header fields that HW should update per segment */ 459 otx2_setup_udp_segmentation(lso, true); 460 461 err = otx2_sync_mbox_msg(&pfvf->mbox); 462 if (err) 463 goto fail; 464 465 rsp = (struct nix_lso_format_cfg_rsp *) 466 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 467 if (IS_ERR(rsp)) 468 goto fail; 469 470 hw->lso_udpv4_idx = rsp->lso_format_idx; 471 472 /* UDPv6 segmentation */ 473 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 474 if (!lso) 475 goto fail; 476 477 /* Setup UDP/IP header fields that HW should update per segment */ 478 otx2_setup_udp_segmentation(lso, false); 479 480 err = otx2_sync_mbox_msg(&pfvf->mbox); 481 if (err) 482 goto fail; 483 484 rsp = (struct nix_lso_format_cfg_rsp *) 485 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 486 if (IS_ERR(rsp)) 487 goto fail; 488 489 hw->lso_udpv6_idx = rsp->lso_format_idx; 490 mutex_unlock(&pfvf->mbox.lock); 491 return; 492 fail: 493 mutex_unlock(&pfvf->mbox.lock); 494 netdev_info(pfvf->netdev, 495 "Failed to get LSO index for UDP GSO offload, disabling\n"); 496 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 497 } 498 499 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 500 { 501 /* Configure CQE interrupt coalescing parameters 502 * 503 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 504 * set 1 less than cq_ecount_wait. And cq_time_wait is in 505 * usecs, convert that to 100ns count. 506 */ 507 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 508 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 509 ((u64)pfvf->hw.cq_qcount_wait << 32) | 510 (pfvf->hw.cq_ecount_wait - 1)); 511 } 512 513 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 514 dma_addr_t *dma) 515 { 516 u8 *buf; 517 518 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 519 if (unlikely(!buf)) 520 return -ENOMEM; 521 522 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 523 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 524 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 525 page_frag_free(buf); 526 return -ENOMEM; 527 } 528 529 return 0; 530 } 531 532 static int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 533 dma_addr_t *dma) 534 { 535 int ret; 536 537 local_bh_disable(); 538 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 539 local_bh_enable(); 540 return ret; 541 } 542 543 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 544 dma_addr_t *dma) 545 { 546 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) { 547 struct refill_work *work; 548 struct delayed_work *dwork; 549 550 work = &pfvf->refill_wrk[cq->cq_idx]; 551 dwork = &work->pool_refill_work; 552 /* Schedule a task if no other task is running */ 553 if (!cq->refill_task_sched) { 554 cq->refill_task_sched = true; 555 schedule_delayed_work(dwork, 556 msecs_to_jiffies(100)); 557 } 558 return -ENOMEM; 559 } 560 return 0; 561 } 562 563 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 564 { 565 struct otx2_nic *pfvf = netdev_priv(netdev); 566 567 schedule_work(&pfvf->reset_task); 568 } 569 EXPORT_SYMBOL(otx2_tx_timeout); 570 571 void otx2_get_mac_from_af(struct net_device *netdev) 572 { 573 struct otx2_nic *pfvf = netdev_priv(netdev); 574 int err; 575 576 err = otx2_hw_get_mac_addr(pfvf, netdev); 577 if (err) 578 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 579 580 /* If AF doesn't provide a valid MAC, generate a random one */ 581 if (!is_valid_ether_addr(netdev->dev_addr)) 582 eth_hw_addr_random(netdev); 583 } 584 EXPORT_SYMBOL(otx2_get_mac_from_af); 585 586 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl) 587 { 588 struct otx2_hw *hw = &pfvf->hw; 589 struct nix_txschq_config *req; 590 u64 schq, parent; 591 u64 dwrr_val; 592 593 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 594 595 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 596 if (!req) 597 return -ENOMEM; 598 599 req->lvl = lvl; 600 req->num_regs = 1; 601 602 schq = hw->txschq_list[lvl][0]; 603 /* Set topology e.t.c configuration */ 604 if (lvl == NIX_TXSCH_LVL_SMQ) { 605 req->reg[0] = NIX_AF_SMQX_CFG(schq); 606 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU; 607 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 608 (0x2ULL << 36); 609 req->num_regs++; 610 /* MDQ config */ 611 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0]; 612 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 613 req->regval[1] = parent << 16; 614 req->num_regs++; 615 /* Set DWRR quantum */ 616 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 617 req->regval[2] = dwrr_val; 618 } else if (lvl == NIX_TXSCH_LVL_TL4) { 619 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0]; 620 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 621 req->regval[0] = parent << 16; 622 req->num_regs++; 623 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 624 req->regval[1] = dwrr_val; 625 } else if (lvl == NIX_TXSCH_LVL_TL3) { 626 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0]; 627 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 628 req->regval[0] = parent << 16; 629 req->num_regs++; 630 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 631 req->regval[1] = dwrr_val; 632 } else if (lvl == NIX_TXSCH_LVL_TL2) { 633 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0]; 634 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 635 req->regval[0] = parent << 16; 636 637 req->num_regs++; 638 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 639 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val; 640 641 req->num_regs++; 642 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 643 /* Enable this queue and backpressure */ 644 req->regval[2] = BIT_ULL(13) | BIT_ULL(12); 645 646 } else if (lvl == NIX_TXSCH_LVL_TL1) { 647 /* Default config for TL1. 648 * For VF this is always ignored. 649 */ 650 651 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 652 * clip it to 16384, so configuring a 24bit max value 653 * will work on both OTx2 and CN10K. 654 */ 655 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 656 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 657 658 req->num_regs++; 659 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 660 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 661 662 req->num_regs++; 663 req->reg[2] = NIX_AF_TL1X_CIR(schq); 664 req->regval[2] = 0; 665 } 666 667 return otx2_sync_mbox_msg(&pfvf->mbox); 668 } 669 670 int otx2_txsch_alloc(struct otx2_nic *pfvf) 671 { 672 struct nix_txsch_alloc_req *req; 673 int lvl; 674 675 /* Get memory to put this msg */ 676 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 677 if (!req) 678 return -ENOMEM; 679 680 /* Request one schq per level */ 681 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 682 req->schq[lvl] = 1; 683 684 return otx2_sync_mbox_msg(&pfvf->mbox); 685 } 686 687 int otx2_txschq_stop(struct otx2_nic *pfvf) 688 { 689 struct nix_txsch_free_req *free_req; 690 int lvl, schq, err; 691 692 mutex_lock(&pfvf->mbox.lock); 693 /* Free the transmit schedulers */ 694 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 695 if (!free_req) { 696 mutex_unlock(&pfvf->mbox.lock); 697 return -ENOMEM; 698 } 699 700 free_req->flags = TXSCHQ_FREE_ALL; 701 err = otx2_sync_mbox_msg(&pfvf->mbox); 702 mutex_unlock(&pfvf->mbox.lock); 703 704 /* Clear the txschq list */ 705 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 706 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 707 pfvf->hw.txschq_list[lvl][schq] = 0; 708 } 709 return err; 710 } 711 712 void otx2_sqb_flush(struct otx2_nic *pfvf) 713 { 714 int qidx, sqe_tail, sqe_head; 715 u64 incr, *ptr, val; 716 int timeout = 1000; 717 718 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 719 for (qidx = 0; qidx < pfvf->hw.tot_tx_queues; qidx++) { 720 incr = (u64)qidx << 32; 721 while (timeout) { 722 val = otx2_atomic64_add(incr, ptr); 723 sqe_head = (val >> 20) & 0x3F; 724 sqe_tail = (val >> 28) & 0x3F; 725 if (sqe_head == sqe_tail) 726 break; 727 usleep_range(1, 3); 728 timeout--; 729 } 730 } 731 } 732 733 /* RED and drop levels of CQ on packet reception. 734 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 735 */ 736 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 737 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 738 739 /* RED and drop levels of AURA for packet reception. 740 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 741 * Eg: For RQ length 1K, for pass/drop level 204/230. 742 * RED accepts pkts if free pointers > 102 & <= 205. 743 * Drops pkts if free pointers < 102. 744 */ 745 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 746 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 747 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 748 749 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 750 { 751 struct otx2_qset *qset = &pfvf->qset; 752 struct nix_aq_enq_req *aq; 753 754 /* Get memory to put this msg */ 755 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 756 if (!aq) 757 return -ENOMEM; 758 759 aq->rq.cq = qidx; 760 aq->rq.ena = 1; 761 aq->rq.pb_caching = 1; 762 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 763 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 764 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 765 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 766 aq->rq.qint_idx = 0; 767 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 768 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 769 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 770 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 771 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 772 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 773 774 /* Fill AQ info */ 775 aq->qidx = qidx; 776 aq->ctype = NIX_AQ_CTYPE_RQ; 777 aq->op = NIX_AQ_INSTOP_INIT; 778 779 return otx2_sync_mbox_msg(&pfvf->mbox); 780 } 781 782 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 783 { 784 struct otx2_nic *pfvf = dev; 785 struct otx2_snd_queue *sq; 786 struct nix_aq_enq_req *aq; 787 788 sq = &pfvf->qset.sq[qidx]; 789 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 790 /* Get memory to put this msg */ 791 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 792 if (!aq) 793 return -ENOMEM; 794 795 aq->sq.cq = pfvf->hw.rx_queues + qidx; 796 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 797 aq->sq.cq_ena = 1; 798 aq->sq.ena = 1; 799 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 800 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 801 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 802 aq->sq.default_chan = pfvf->hw.tx_chan_base; 803 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 804 aq->sq.sqb_aura = sqb_aura; 805 aq->sq.sq_int_ena = NIX_SQINT_BITS; 806 aq->sq.qint_idx = 0; 807 /* Due pipelining impact minimum 2000 unused SQ CQE's 808 * need to maintain to avoid CQ overflow. 809 */ 810 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 811 812 /* Fill AQ info */ 813 aq->qidx = qidx; 814 aq->ctype = NIX_AQ_CTYPE_SQ; 815 aq->op = NIX_AQ_INSTOP_INIT; 816 817 return otx2_sync_mbox_msg(&pfvf->mbox); 818 } 819 820 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 821 { 822 struct otx2_qset *qset = &pfvf->qset; 823 struct otx2_snd_queue *sq; 824 struct otx2_pool *pool; 825 int err; 826 827 pool = &pfvf->qset.pool[sqb_aura]; 828 sq = &qset->sq[qidx]; 829 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 830 sq->sqe_cnt = qset->sqe_cnt; 831 832 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 833 if (err) 834 return err; 835 836 if (qidx < pfvf->hw.tx_queues) { 837 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 838 TSO_HEADER_SIZE); 839 if (err) 840 return err; 841 } 842 843 sq->sqe_base = sq->sqe->base; 844 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 845 if (!sq->sg) 846 return -ENOMEM; 847 848 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) { 849 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 850 sizeof(*sq->timestamps)); 851 if (err) 852 return err; 853 } 854 855 sq->head = 0; 856 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 857 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 858 /* Set SQE threshold to 10% of total SQEs */ 859 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 860 sq->aura_id = sqb_aura; 861 sq->aura_fc_addr = pool->fc_addr->base; 862 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 863 864 sq->stats.bytes = 0; 865 sq->stats.pkts = 0; 866 867 return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); 868 869 } 870 871 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 872 { 873 struct otx2_qset *qset = &pfvf->qset; 874 int err, pool_id, non_xdp_queues; 875 struct nix_aq_enq_req *aq; 876 struct otx2_cq_queue *cq; 877 878 cq = &qset->cq[qidx]; 879 cq->cq_idx = qidx; 880 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues; 881 if (qidx < pfvf->hw.rx_queues) { 882 cq->cq_type = CQ_RX; 883 cq->cint_idx = qidx; 884 cq->cqe_cnt = qset->rqe_cnt; 885 if (pfvf->xdp_prog) 886 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0); 887 } else if (qidx < non_xdp_queues) { 888 cq->cq_type = CQ_TX; 889 cq->cint_idx = qidx - pfvf->hw.rx_queues; 890 cq->cqe_cnt = qset->sqe_cnt; 891 } else { 892 cq->cq_type = CQ_XDP; 893 cq->cint_idx = qidx - non_xdp_queues; 894 cq->cqe_cnt = qset->sqe_cnt; 895 } 896 cq->cqe_size = pfvf->qset.xqe_size; 897 898 /* Allocate memory for CQEs */ 899 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 900 if (err) 901 return err; 902 903 /* Save CQE CPU base for faster reference */ 904 cq->cqe_base = cq->cqe->base; 905 /* In case where all RQs auras point to single pool, 906 * all CQs receive buffer pool also point to same pool. 907 */ 908 pool_id = ((cq->cq_type == CQ_RX) && 909 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 910 cq->rbpool = &qset->pool[pool_id]; 911 cq->refill_task_sched = false; 912 913 /* Get memory to put this msg */ 914 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 915 if (!aq) 916 return -ENOMEM; 917 918 aq->cq.ena = 1; 919 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 920 aq->cq.caching = 1; 921 aq->cq.base = cq->cqe->iova; 922 aq->cq.cint_idx = cq->cint_idx; 923 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 924 aq->cq.qint_idx = 0; 925 aq->cq.avg_level = 255; 926 927 if (qidx < pfvf->hw.rx_queues) { 928 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 929 aq->cq.drop_ena = 1; 930 931 if (!is_otx2_lbkvf(pfvf->pdev)) { 932 /* Enable receive CQ backpressure */ 933 aq->cq.bp_ena = 1; 934 aq->cq.bpid = pfvf->bpid[0]; 935 936 /* Set backpressure level is same as cq pass level */ 937 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 938 } 939 } 940 941 /* Fill AQ info */ 942 aq->qidx = qidx; 943 aq->ctype = NIX_AQ_CTYPE_CQ; 944 aq->op = NIX_AQ_INSTOP_INIT; 945 946 return otx2_sync_mbox_msg(&pfvf->mbox); 947 } 948 949 static void otx2_pool_refill_task(struct work_struct *work) 950 { 951 struct otx2_cq_queue *cq; 952 struct otx2_pool *rbpool; 953 struct refill_work *wrk; 954 int qidx, free_ptrs = 0; 955 struct otx2_nic *pfvf; 956 dma_addr_t bufptr; 957 958 wrk = container_of(work, struct refill_work, pool_refill_work.work); 959 pfvf = wrk->pf; 960 qidx = wrk - pfvf->refill_wrk; 961 cq = &pfvf->qset.cq[qidx]; 962 rbpool = cq->rbpool; 963 free_ptrs = cq->pool_ptrs; 964 965 while (cq->pool_ptrs) { 966 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) { 967 /* Schedule a WQ if we fails to free atleast half of the 968 * pointers else enable napi for this RQ. 969 */ 970 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 971 struct delayed_work *dwork; 972 973 dwork = &wrk->pool_refill_work; 974 schedule_delayed_work(dwork, 975 msecs_to_jiffies(100)); 976 } else { 977 cq->refill_task_sched = false; 978 } 979 return; 980 } 981 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 982 cq->pool_ptrs--; 983 } 984 cq->refill_task_sched = false; 985 } 986 987 int otx2_config_nix_queues(struct otx2_nic *pfvf) 988 { 989 int qidx, err; 990 991 /* Initialize RX queues */ 992 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 993 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 994 995 err = otx2_rq_init(pfvf, qidx, lpb_aura); 996 if (err) 997 return err; 998 } 999 1000 /* Initialize TX queues */ 1001 for (qidx = 0; qidx < pfvf->hw.tot_tx_queues; qidx++) { 1002 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1003 1004 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1005 if (err) 1006 return err; 1007 } 1008 1009 /* Initialize completion queues */ 1010 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1011 err = otx2_cq_init(pfvf, qidx); 1012 if (err) 1013 return err; 1014 } 1015 1016 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, 1017 NIX_LF_CQ_OP_STATUS); 1018 1019 /* Initialize work queue for receive buffer refill */ 1020 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1021 sizeof(struct refill_work), GFP_KERNEL); 1022 if (!pfvf->refill_wrk) 1023 return -ENOMEM; 1024 1025 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1026 pfvf->refill_wrk[qidx].pf = pfvf; 1027 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1028 otx2_pool_refill_task); 1029 } 1030 return 0; 1031 } 1032 1033 int otx2_config_nix(struct otx2_nic *pfvf) 1034 { 1035 struct nix_lf_alloc_req *nixlf; 1036 struct nix_lf_alloc_rsp *rsp; 1037 int err; 1038 1039 pfvf->qset.xqe_size = NIX_XQESZ_W16 ? 128 : 512; 1040 1041 /* Get memory to put this msg */ 1042 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1043 if (!nixlf) 1044 return -ENOMEM; 1045 1046 /* Set RQ/SQ/CQ counts */ 1047 nixlf->rq_cnt = pfvf->hw.rx_queues; 1048 nixlf->sq_cnt = pfvf->hw.tot_tx_queues; 1049 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1050 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1051 nixlf->rss_grps = MAX_RSS_GROUPS; 1052 nixlf->xqe_sz = NIX_XQESZ_W16; 1053 /* We don't know absolute NPA LF idx attached. 1054 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1055 * NPA LF attached to this RVU PF/VF. 1056 */ 1057 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1058 /* Disable alignment pad, enable L2 length check, 1059 * enable L4 TCP/UDP checksum verification. 1060 */ 1061 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1062 1063 err = otx2_sync_mbox_msg(&pfvf->mbox); 1064 if (err) 1065 return err; 1066 1067 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1068 &nixlf->hdr); 1069 if (IS_ERR(rsp)) 1070 return PTR_ERR(rsp); 1071 1072 if (rsp->qints < 1) 1073 return -ENXIO; 1074 1075 return rsp->hdr.rc; 1076 } 1077 1078 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1079 { 1080 struct otx2_qset *qset = &pfvf->qset; 1081 struct otx2_hw *hw = &pfvf->hw; 1082 struct otx2_snd_queue *sq; 1083 int sqb, qidx; 1084 u64 iova, pa; 1085 1086 for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) { 1087 sq = &qset->sq[qidx]; 1088 if (!sq->sqb_ptrs) 1089 continue; 1090 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1091 if (!sq->sqb_ptrs[sqb]) 1092 continue; 1093 iova = sq->sqb_ptrs[sqb]; 1094 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1095 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1096 DMA_FROM_DEVICE, 1097 DMA_ATTR_SKIP_CPU_SYNC); 1098 put_page(virt_to_page(phys_to_virt(pa))); 1099 } 1100 sq->sqb_count = 0; 1101 } 1102 } 1103 1104 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1105 { 1106 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1107 u64 iova, pa; 1108 1109 if (type == AURA_NIX_SQ) { 1110 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1111 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1112 size = pfvf->hw.sqb_size; 1113 } 1114 if (type == AURA_NIX_RQ) { 1115 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1116 pool_end = pfvf->hw.rqpool_cnt; 1117 size = pfvf->rbsize; 1118 } 1119 1120 /* Free SQB and RQB pointers from the aura pool */ 1121 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1122 iova = otx2_aura_allocptr(pfvf, pool_id); 1123 while (iova) { 1124 if (type == AURA_NIX_RQ) 1125 iova -= OTX2_HEAD_ROOM; 1126 1127 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1128 dma_unmap_page_attrs(pfvf->dev, iova, size, 1129 DMA_FROM_DEVICE, 1130 DMA_ATTR_SKIP_CPU_SYNC); 1131 put_page(virt_to_page(phys_to_virt(pa))); 1132 iova = otx2_aura_allocptr(pfvf, pool_id); 1133 } 1134 } 1135 } 1136 1137 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1138 { 1139 struct otx2_pool *pool; 1140 int pool_id; 1141 1142 if (!pfvf->qset.pool) 1143 return; 1144 1145 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1146 pool = &pfvf->qset.pool[pool_id]; 1147 qmem_free(pfvf->dev, pool->stack); 1148 qmem_free(pfvf->dev, pool->fc_addr); 1149 } 1150 devm_kfree(pfvf->dev, pfvf->qset.pool); 1151 pfvf->qset.pool = NULL; 1152 } 1153 1154 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1155 int pool_id, int numptrs) 1156 { 1157 struct npa_aq_enq_req *aq; 1158 struct otx2_pool *pool; 1159 int err; 1160 1161 pool = &pfvf->qset.pool[pool_id]; 1162 1163 /* Allocate memory for HW to update Aura count. 1164 * Alloc one cache line, so that it fits all FC_STYPE modes. 1165 */ 1166 if (!pool->fc_addr) { 1167 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1168 if (err) 1169 return err; 1170 } 1171 1172 /* Initialize this aura's context via AF */ 1173 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1174 if (!aq) { 1175 /* Shared mbox memory buffer is full, flush it and retry */ 1176 err = otx2_sync_mbox_msg(&pfvf->mbox); 1177 if (err) 1178 return err; 1179 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1180 if (!aq) 1181 return -ENOMEM; 1182 } 1183 1184 aq->aura_id = aura_id; 1185 /* Will be filled by AF with correct pool context address */ 1186 aq->aura.pool_addr = pool_id; 1187 aq->aura.pool_caching = 1; 1188 aq->aura.shift = ilog2(numptrs) - 8; 1189 aq->aura.count = numptrs; 1190 aq->aura.limit = numptrs; 1191 aq->aura.avg_level = 255; 1192 aq->aura.ena = 1; 1193 aq->aura.fc_ena = 1; 1194 aq->aura.fc_addr = pool->fc_addr->iova; 1195 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1196 1197 /* Enable backpressure for RQ aura */ 1198 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1199 aq->aura.bp_ena = 0; 1200 /* If NIX1 LF is attached then specify NIX1_RX. 1201 * 1202 * Below NPA_AURA_S[BP_ENA] is set according to the 1203 * NPA_BPINTF_E enumeration given as: 1204 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1205 * NIX0_RX is 0x0 + 0*0x1 = 0 1206 * NIX1_RX is 0x0 + 1*0x1 = 1 1207 * But in HRM it is given that 1208 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1209 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1210 * enumerated by NPA_BPINTF_E." 1211 */ 1212 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1213 aq->aura.bp_ena = 1; 1214 aq->aura.nix0_bpid = pfvf->bpid[0]; 1215 1216 /* Set backpressure level for RQ's Aura */ 1217 aq->aura.bp = RQ_BP_LVL_AURA; 1218 } 1219 1220 /* Fill AQ info */ 1221 aq->ctype = NPA_AQ_CTYPE_AURA; 1222 aq->op = NPA_AQ_INSTOP_INIT; 1223 1224 return 0; 1225 } 1226 1227 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1228 int stack_pages, int numptrs, int buf_size) 1229 { 1230 struct npa_aq_enq_req *aq; 1231 struct otx2_pool *pool; 1232 int err; 1233 1234 pool = &pfvf->qset.pool[pool_id]; 1235 /* Alloc memory for stack which is used to store buffer pointers */ 1236 err = qmem_alloc(pfvf->dev, &pool->stack, 1237 stack_pages, pfvf->hw.stack_pg_bytes); 1238 if (err) 1239 return err; 1240 1241 pool->rbsize = buf_size; 1242 1243 /* Initialize this pool's context via AF */ 1244 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1245 if (!aq) { 1246 /* Shared mbox memory buffer is full, flush it and retry */ 1247 err = otx2_sync_mbox_msg(&pfvf->mbox); 1248 if (err) { 1249 qmem_free(pfvf->dev, pool->stack); 1250 return err; 1251 } 1252 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1253 if (!aq) { 1254 qmem_free(pfvf->dev, pool->stack); 1255 return -ENOMEM; 1256 } 1257 } 1258 1259 aq->aura_id = pool_id; 1260 aq->pool.stack_base = pool->stack->iova; 1261 aq->pool.stack_caching = 1; 1262 aq->pool.ena = 1; 1263 aq->pool.buf_size = buf_size / 128; 1264 aq->pool.stack_max_pages = stack_pages; 1265 aq->pool.shift = ilog2(numptrs) - 8; 1266 aq->pool.ptr_start = 0; 1267 aq->pool.ptr_end = ~0ULL; 1268 1269 /* Fill AQ info */ 1270 aq->ctype = NPA_AQ_CTYPE_POOL; 1271 aq->op = NPA_AQ_INSTOP_INIT; 1272 1273 return 0; 1274 } 1275 1276 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1277 { 1278 int qidx, pool_id, stack_pages, num_sqbs; 1279 struct otx2_qset *qset = &pfvf->qset; 1280 struct otx2_hw *hw = &pfvf->hw; 1281 struct otx2_snd_queue *sq; 1282 struct otx2_pool *pool; 1283 dma_addr_t bufptr; 1284 int err, ptr; 1285 1286 /* Calculate number of SQBs needed. 1287 * 1288 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1289 * Last SQE is used for pointing to next SQB. 1290 */ 1291 num_sqbs = (hw->sqb_size / 128) - 1; 1292 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1293 1294 /* Get no of stack pages needed */ 1295 stack_pages = 1296 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1297 1298 for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) { 1299 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1300 /* Initialize aura context */ 1301 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1302 if (err) 1303 goto fail; 1304 1305 /* Initialize pool context */ 1306 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1307 num_sqbs, hw->sqb_size); 1308 if (err) 1309 goto fail; 1310 } 1311 1312 /* Flush accumulated messages */ 1313 err = otx2_sync_mbox_msg(&pfvf->mbox); 1314 if (err) 1315 goto fail; 1316 1317 /* Allocate pointers and free them to aura/pool */ 1318 for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) { 1319 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1320 pool = &pfvf->qset.pool[pool_id]; 1321 1322 sq = &qset->sq[qidx]; 1323 sq->sqb_count = 0; 1324 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1325 if (!sq->sqb_ptrs) 1326 return -ENOMEM; 1327 1328 for (ptr = 0; ptr < num_sqbs; ptr++) { 1329 if (otx2_alloc_rbuf(pfvf, pool, &bufptr)) 1330 return -ENOMEM; 1331 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1332 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1333 } 1334 } 1335 1336 return 0; 1337 fail: 1338 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1339 otx2_aura_pool_free(pfvf); 1340 return err; 1341 } 1342 1343 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1344 { 1345 struct otx2_hw *hw = &pfvf->hw; 1346 int stack_pages, pool_id, rq; 1347 struct otx2_pool *pool; 1348 int err, ptr, num_ptrs; 1349 dma_addr_t bufptr; 1350 1351 num_ptrs = pfvf->qset.rqe_cnt; 1352 1353 stack_pages = 1354 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1355 1356 for (rq = 0; rq < hw->rx_queues; rq++) { 1357 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1358 /* Initialize aura context */ 1359 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1360 if (err) 1361 goto fail; 1362 } 1363 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1364 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1365 num_ptrs, pfvf->rbsize); 1366 if (err) 1367 goto fail; 1368 } 1369 1370 /* Flush accumulated messages */ 1371 err = otx2_sync_mbox_msg(&pfvf->mbox); 1372 if (err) 1373 goto fail; 1374 1375 /* Allocate pointers and free them to aura/pool */ 1376 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1377 pool = &pfvf->qset.pool[pool_id]; 1378 for (ptr = 0; ptr < num_ptrs; ptr++) { 1379 if (otx2_alloc_rbuf(pfvf, pool, &bufptr)) 1380 return -ENOMEM; 1381 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1382 bufptr + OTX2_HEAD_ROOM); 1383 } 1384 } 1385 1386 return 0; 1387 fail: 1388 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1389 otx2_aura_pool_free(pfvf); 1390 return err; 1391 } 1392 1393 int otx2_config_npa(struct otx2_nic *pfvf) 1394 { 1395 struct otx2_qset *qset = &pfvf->qset; 1396 struct npa_lf_alloc_req *npalf; 1397 struct otx2_hw *hw = &pfvf->hw; 1398 int aura_cnt; 1399 1400 /* Pool - Stack of free buffer pointers 1401 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1402 */ 1403 1404 if (!hw->pool_cnt) 1405 return -EINVAL; 1406 1407 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1408 sizeof(struct otx2_pool), GFP_KERNEL); 1409 if (!qset->pool) 1410 return -ENOMEM; 1411 1412 /* Get memory to put this msg */ 1413 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1414 if (!npalf) 1415 return -ENOMEM; 1416 1417 /* Set aura and pool counts */ 1418 npalf->nr_pools = hw->pool_cnt; 1419 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1420 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1421 1422 return otx2_sync_mbox_msg(&pfvf->mbox); 1423 } 1424 1425 int otx2_detach_resources(struct mbox *mbox) 1426 { 1427 struct rsrc_detach *detach; 1428 1429 mutex_lock(&mbox->lock); 1430 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1431 if (!detach) { 1432 mutex_unlock(&mbox->lock); 1433 return -ENOMEM; 1434 } 1435 1436 /* detach all */ 1437 detach->partial = false; 1438 1439 /* Send detach request to AF */ 1440 otx2_mbox_msg_send(&mbox->mbox, 0); 1441 mutex_unlock(&mbox->lock); 1442 return 0; 1443 } 1444 EXPORT_SYMBOL(otx2_detach_resources); 1445 1446 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1447 { 1448 struct rsrc_attach *attach; 1449 struct msg_req *msix; 1450 int err; 1451 1452 mutex_lock(&pfvf->mbox.lock); 1453 /* Get memory to put this msg */ 1454 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1455 if (!attach) { 1456 mutex_unlock(&pfvf->mbox.lock); 1457 return -ENOMEM; 1458 } 1459 1460 attach->npalf = true; 1461 attach->nixlf = true; 1462 1463 /* Send attach request to AF */ 1464 err = otx2_sync_mbox_msg(&pfvf->mbox); 1465 if (err) { 1466 mutex_unlock(&pfvf->mbox.lock); 1467 return err; 1468 } 1469 1470 pfvf->nix_blkaddr = BLKADDR_NIX0; 1471 1472 /* If the platform has two NIX blocks then LF may be 1473 * allocated from NIX1. 1474 */ 1475 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1476 pfvf->nix_blkaddr = BLKADDR_NIX1; 1477 1478 /* Get NPA and NIX MSIX vector offsets */ 1479 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1480 if (!msix) { 1481 mutex_unlock(&pfvf->mbox.lock); 1482 return -ENOMEM; 1483 } 1484 1485 err = otx2_sync_mbox_msg(&pfvf->mbox); 1486 if (err) { 1487 mutex_unlock(&pfvf->mbox.lock); 1488 return err; 1489 } 1490 mutex_unlock(&pfvf->mbox.lock); 1491 1492 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1493 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1494 dev_err(pfvf->dev, 1495 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1496 return -EINVAL; 1497 } 1498 1499 return 0; 1500 } 1501 EXPORT_SYMBOL(otx2_attach_npa_nix); 1502 1503 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1504 { 1505 struct hwctx_disable_req *req; 1506 1507 mutex_lock(&mbox->lock); 1508 /* Request AQ to disable this context */ 1509 if (npa) 1510 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1511 else 1512 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1513 1514 if (!req) { 1515 mutex_unlock(&mbox->lock); 1516 return; 1517 } 1518 1519 req->ctype = type; 1520 1521 if (otx2_sync_mbox_msg(mbox)) 1522 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1523 __func__); 1524 1525 mutex_unlock(&mbox->lock); 1526 } 1527 1528 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1529 { 1530 struct nix_bp_cfg_req *req; 1531 1532 if (enable) 1533 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1534 else 1535 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1536 1537 if (!req) 1538 return -ENOMEM; 1539 1540 req->chan_base = 0; 1541 req->chan_cnt = 1; 1542 req->bpid_per_chan = 0; 1543 1544 return otx2_sync_mbox_msg(&pfvf->mbox); 1545 } 1546 1547 /* Mbox message handlers */ 1548 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1549 struct cgx_stats_rsp *rsp) 1550 { 1551 int id; 1552 1553 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1554 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1555 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1556 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1557 } 1558 1559 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1560 struct cgx_fec_stats_rsp *rsp) 1561 { 1562 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1563 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1564 } 1565 1566 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1567 struct nix_txsch_alloc_rsp *rsp) 1568 { 1569 int lvl, schq; 1570 1571 /* Setup transmit scheduler list */ 1572 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 1573 for (schq = 0; schq < rsp->schq[lvl]; schq++) 1574 pf->hw.txschq_list[lvl][schq] = 1575 rsp->schq_list[lvl][schq]; 1576 } 1577 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc); 1578 1579 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1580 struct npa_lf_alloc_rsp *rsp) 1581 { 1582 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1583 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1584 } 1585 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1586 1587 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1588 struct nix_lf_alloc_rsp *rsp) 1589 { 1590 pfvf->hw.sqb_size = rsp->sqb_size; 1591 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1592 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1593 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1594 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1595 pfvf->hw.cgx_links = rsp->cgx_links; 1596 pfvf->hw.lbk_links = rsp->lbk_links; 1597 pfvf->hw.tx_link = rsp->tx_link; 1598 } 1599 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1600 1601 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1602 struct msix_offset_rsp *rsp) 1603 { 1604 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1605 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1606 } 1607 EXPORT_SYMBOL(mbox_handler_msix_offset); 1608 1609 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1610 struct nix_bp_cfg_rsp *rsp) 1611 { 1612 int chan, chan_id; 1613 1614 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1615 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1616 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1617 } 1618 } 1619 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1620 1621 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1622 { 1623 struct otx2_qset *qset = &pfvf->qset; 1624 struct otx2_hw *hw = &pfvf->hw; 1625 int irq, qidx; 1626 1627 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1628 qidx < n; 1629 qidx++, irq++) { 1630 int vector = pci_irq_vector(pfvf->pdev, irq); 1631 1632 irq_set_affinity_hint(vector, NULL); 1633 free_cpumask_var(hw->affinity_mask[irq]); 1634 free_irq(vector, &qset->napi[qidx]); 1635 } 1636 } 1637 1638 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1639 { 1640 struct otx2_hw *hw = &pfvf->hw; 1641 int vec, cpu, irq, cint; 1642 1643 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1644 cpu = cpumask_first(cpu_online_mask); 1645 1646 /* CQ interrupts */ 1647 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1648 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1649 return; 1650 1651 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1652 1653 irq = pci_irq_vector(pfvf->pdev, vec); 1654 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1655 1656 cpu = cpumask_next(cpu, cpu_online_mask); 1657 if (unlikely(cpu >= nr_cpu_ids)) 1658 cpu = 0; 1659 } 1660 } 1661 1662 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1663 { 1664 struct nix_hw_info *rsp; 1665 struct msg_req *req; 1666 u16 max_mtu; 1667 int rc; 1668 1669 mutex_lock(&pfvf->mbox.lock); 1670 1671 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1672 if (!req) { 1673 rc = -ENOMEM; 1674 goto out; 1675 } 1676 1677 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1678 if (!rc) { 1679 rsp = (struct nix_hw_info *) 1680 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1681 1682 /* HW counts VLAN insertion bytes (8 for double tag) 1683 * irrespective of whether SQE is requesting to insert VLAN 1684 * in the packet or not. Hence these 8 bytes have to be 1685 * discounted from max packet size otherwise HW will throw 1686 * SMQ errors 1687 */ 1688 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1689 1690 /* Also save DWRR MTU, needed for DWRR weight calculation */ 1691 pfvf->hw.dwrr_mtu = rsp->rpm_dwrr_mtu; 1692 if (!pfvf->hw.dwrr_mtu) 1693 pfvf->hw.dwrr_mtu = 1; 1694 } 1695 1696 out: 1697 mutex_unlock(&pfvf->mbox.lock); 1698 if (rc) { 1699 dev_warn(pfvf->dev, 1700 "Failed to get MTU from hardware setting default value(1500)\n"); 1701 max_mtu = 1500; 1702 } 1703 return max_mtu; 1704 } 1705 EXPORT_SYMBOL(otx2_get_max_mtu); 1706 1707 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1708 int __weak \ 1709 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1710 struct _req_type *req, \ 1711 struct _rsp_type *rsp) \ 1712 { \ 1713 /* Nothing to do here */ \ 1714 return 0; \ 1715 } \ 1716 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1717 MBOX_UP_CGX_MESSAGES 1718 #undef M 1719