1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 #include <net/page_pool/helpers.h> 11 #include <net/tso.h> 12 #include <linux/bitfield.h> 13 14 #include "otx2_reg.h" 15 #include "otx2_common.h" 16 #include "otx2_struct.h" 17 #include "cn10k.h" 18 19 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 20 struct otx2_nic *pfvf, int qidx) 21 { 22 u64 incr = (u64)qidx << 32; 23 u64 *ptr; 24 25 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 26 stats->bytes = otx2_atomic64_add(incr, ptr); 27 28 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 29 stats->pkts = otx2_atomic64_add(incr, ptr); 30 } 31 32 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 33 struct otx2_nic *pfvf, int qidx) 34 { 35 u64 incr = (u64)qidx << 32; 36 u64 *ptr; 37 38 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 39 stats->bytes = otx2_atomic64_add(incr, ptr); 40 41 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 42 stats->pkts = otx2_atomic64_add(incr, ptr); 43 } 44 45 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 46 { 47 struct msg_req *req; 48 49 if (!netif_running(pfvf->netdev)) 50 return; 51 52 mutex_lock(&pfvf->mbox.lock); 53 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 54 if (!req) { 55 mutex_unlock(&pfvf->mbox.lock); 56 return; 57 } 58 59 otx2_sync_mbox_msg(&pfvf->mbox); 60 mutex_unlock(&pfvf->mbox.lock); 61 } 62 63 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 64 { 65 struct msg_req *req; 66 67 if (!netif_running(pfvf->netdev)) 68 return; 69 mutex_lock(&pfvf->mbox.lock); 70 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 71 if (req) 72 otx2_sync_mbox_msg(&pfvf->mbox); 73 mutex_unlock(&pfvf->mbox.lock); 74 } 75 76 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 77 { 78 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 79 80 if (!pfvf->qset.rq) 81 return 0; 82 83 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 84 return 1; 85 } 86 87 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 88 { 89 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 90 91 if (!pfvf->qset.sq) 92 return 0; 93 94 if (qidx >= pfvf->hw.non_qos_queues) { 95 if (!test_bit(qidx - pfvf->hw.non_qos_queues, pfvf->qos.qos_sq_bmap)) 96 return 0; 97 } 98 99 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 100 return 1; 101 } 102 103 void otx2_get_dev_stats(struct otx2_nic *pfvf) 104 { 105 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 106 107 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 108 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 109 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 110 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 111 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 112 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 113 dev_stats->rx_mcast_frames + 114 dev_stats->rx_ucast_frames; 115 116 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 117 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 118 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 119 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 120 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 121 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 122 dev_stats->tx_mcast_frames + 123 dev_stats->tx_ucast_frames; 124 } 125 126 void otx2_get_stats64(struct net_device *netdev, 127 struct rtnl_link_stats64 *stats) 128 { 129 struct otx2_nic *pfvf = netdev_priv(netdev); 130 struct otx2_dev_stats *dev_stats; 131 132 otx2_get_dev_stats(pfvf); 133 134 dev_stats = &pfvf->hw.dev_stats; 135 stats->rx_bytes = dev_stats->rx_bytes; 136 stats->rx_packets = dev_stats->rx_frames; 137 stats->rx_dropped = dev_stats->rx_drops; 138 stats->multicast = dev_stats->rx_mcast_frames; 139 140 stats->tx_bytes = dev_stats->tx_bytes; 141 stats->tx_packets = dev_stats->tx_frames; 142 stats->tx_dropped = dev_stats->tx_drops; 143 } 144 EXPORT_SYMBOL(otx2_get_stats64); 145 146 /* Sync MAC address with RVU AF */ 147 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 148 { 149 struct nix_set_mac_addr *req; 150 int err; 151 152 mutex_lock(&pfvf->mbox.lock); 153 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 154 if (!req) { 155 mutex_unlock(&pfvf->mbox.lock); 156 return -ENOMEM; 157 } 158 159 ether_addr_copy(req->mac_addr, mac); 160 161 err = otx2_sync_mbox_msg(&pfvf->mbox); 162 mutex_unlock(&pfvf->mbox.lock); 163 return err; 164 } 165 166 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 167 struct net_device *netdev) 168 { 169 struct nix_get_mac_addr_rsp *rsp; 170 struct mbox_msghdr *msghdr; 171 struct msg_req *req; 172 int err; 173 174 mutex_lock(&pfvf->mbox.lock); 175 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 176 if (!req) { 177 mutex_unlock(&pfvf->mbox.lock); 178 return -ENOMEM; 179 } 180 181 err = otx2_sync_mbox_msg(&pfvf->mbox); 182 if (err) { 183 mutex_unlock(&pfvf->mbox.lock); 184 return err; 185 } 186 187 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 188 if (IS_ERR(msghdr)) { 189 mutex_unlock(&pfvf->mbox.lock); 190 return PTR_ERR(msghdr); 191 } 192 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 193 eth_hw_addr_set(netdev, rsp->mac_addr); 194 mutex_unlock(&pfvf->mbox.lock); 195 196 return 0; 197 } 198 199 int otx2_set_mac_address(struct net_device *netdev, void *p) 200 { 201 struct otx2_nic *pfvf = netdev_priv(netdev); 202 struct sockaddr *addr = p; 203 204 if (!is_valid_ether_addr(addr->sa_data)) 205 return -EADDRNOTAVAIL; 206 207 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 208 eth_hw_addr_set(netdev, addr->sa_data); 209 /* update dmac field in vlan offload rule */ 210 if (netif_running(netdev) && 211 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 212 otx2_install_rxvlan_offload_flow(pfvf); 213 /* update dmac address in ntuple and DMAC filter list */ 214 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 215 otx2_dmacflt_update_pfmac_flow(pfvf); 216 } else { 217 return -EPERM; 218 } 219 220 return 0; 221 } 222 EXPORT_SYMBOL(otx2_set_mac_address); 223 224 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 225 { 226 struct nix_frs_cfg *req; 227 u16 maxlen; 228 int err; 229 230 maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 231 232 mutex_lock(&pfvf->mbox.lock); 233 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 234 if (!req) { 235 mutex_unlock(&pfvf->mbox.lock); 236 return -ENOMEM; 237 } 238 239 req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 240 241 /* Use max receive length supported by hardware for loopback devices */ 242 if (is_otx2_lbkvf(pfvf->pdev)) 243 req->maxlen = maxlen; 244 245 err = otx2_sync_mbox_msg(&pfvf->mbox); 246 mutex_unlock(&pfvf->mbox.lock); 247 return err; 248 } 249 250 int otx2_config_pause_frm(struct otx2_nic *pfvf) 251 { 252 struct cgx_pause_frm_cfg *req; 253 int err; 254 255 if (is_otx2_lbkvf(pfvf->pdev)) 256 return 0; 257 258 mutex_lock(&pfvf->mbox.lock); 259 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 260 if (!req) { 261 err = -ENOMEM; 262 goto unlock; 263 } 264 265 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 266 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 267 req->set = 1; 268 269 err = otx2_sync_mbox_msg(&pfvf->mbox); 270 unlock: 271 mutex_unlock(&pfvf->mbox.lock); 272 return err; 273 } 274 EXPORT_SYMBOL(otx2_config_pause_frm); 275 276 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 277 { 278 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 279 struct nix_rss_flowkey_cfg_rsp *rsp; 280 struct nix_rss_flowkey_cfg *req; 281 int err; 282 283 mutex_lock(&pfvf->mbox.lock); 284 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 285 if (!req) { 286 mutex_unlock(&pfvf->mbox.lock); 287 return -ENOMEM; 288 } 289 req->mcam_index = -1; /* Default or reserved index */ 290 req->flowkey_cfg = rss->flowkey_cfg; 291 req->group = DEFAULT_RSS_CONTEXT_GROUP; 292 293 err = otx2_sync_mbox_msg(&pfvf->mbox); 294 if (err) 295 goto fail; 296 297 rsp = (struct nix_rss_flowkey_cfg_rsp *) 298 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 299 if (IS_ERR(rsp)) { 300 err = PTR_ERR(rsp); 301 goto fail; 302 } 303 304 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 305 fail: 306 mutex_unlock(&pfvf->mbox.lock); 307 return err; 308 } 309 310 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 311 { 312 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 313 const int index = rss->rss_size * ctx_id; 314 struct mbox *mbox = &pfvf->mbox; 315 struct otx2_rss_ctx *rss_ctx; 316 struct nix_aq_enq_req *aq; 317 int idx, err; 318 319 mutex_lock(&mbox->lock); 320 rss_ctx = rss->rss_ctx[ctx_id]; 321 /* Get memory to put this msg */ 322 for (idx = 0; idx < rss->rss_size; idx++) { 323 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 324 if (!aq) { 325 /* The shared memory buffer can be full. 326 * Flush it and retry 327 */ 328 err = otx2_sync_mbox_msg(mbox); 329 if (err) { 330 mutex_unlock(&mbox->lock); 331 return err; 332 } 333 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 334 if (!aq) { 335 mutex_unlock(&mbox->lock); 336 return -ENOMEM; 337 } 338 } 339 340 aq->rss.rq = rss_ctx->ind_tbl[idx]; 341 342 /* Fill AQ info */ 343 aq->qidx = index + idx; 344 aq->ctype = NIX_AQ_CTYPE_RSS; 345 aq->op = NIX_AQ_INSTOP_INIT; 346 } 347 err = otx2_sync_mbox_msg(mbox); 348 mutex_unlock(&mbox->lock); 349 return err; 350 } 351 352 void otx2_set_rss_key(struct otx2_nic *pfvf) 353 { 354 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 355 u64 *key = (u64 *)&rss->key[4]; 356 int idx; 357 358 /* 352bit or 44byte key needs to be configured as below 359 * NIX_LF_RX_SECRETX0 = key<351:288> 360 * NIX_LF_RX_SECRETX1 = key<287:224> 361 * NIX_LF_RX_SECRETX2 = key<223:160> 362 * NIX_LF_RX_SECRETX3 = key<159:96> 363 * NIX_LF_RX_SECRETX4 = key<95:32> 364 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 365 */ 366 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 367 (u64)(*((u32 *)&rss->key)) << 32); 368 idx = sizeof(rss->key) / sizeof(u64); 369 while (idx > 0) { 370 idx--; 371 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 372 } 373 } 374 375 int otx2_rss_init(struct otx2_nic *pfvf) 376 { 377 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 378 struct otx2_rss_ctx *rss_ctx; 379 int idx, ret = 0; 380 381 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 382 383 /* Init RSS key if it is not setup already */ 384 if (!rss->enable) 385 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 386 otx2_set_rss_key(pfvf); 387 388 if (!netif_is_rxfh_configured(pfvf->netdev)) { 389 /* Set RSS group 0 as default indirection table */ 390 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 391 GFP_KERNEL); 392 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 393 return -ENOMEM; 394 395 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 396 for (idx = 0; idx < rss->rss_size; idx++) 397 rss_ctx->ind_tbl[idx] = 398 ethtool_rxfh_indir_default(idx, 399 pfvf->hw.rx_queues); 400 } 401 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 402 if (ret) 403 return ret; 404 405 /* Flowkey or hash config to be used for generating flow tag */ 406 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 407 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 408 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 409 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 410 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 411 412 ret = otx2_set_flowkey_cfg(pfvf); 413 if (ret) 414 return ret; 415 416 rss->enable = true; 417 return 0; 418 } 419 420 /* Setup UDP segmentation algorithm in HW */ 421 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 422 { 423 struct nix_lso_format *field; 424 425 field = (struct nix_lso_format *)&lso->fields[0]; 426 lso->field_mask = GENMASK(18, 0); 427 428 /* IP's Length field */ 429 field->layer = NIX_TXLAYER_OL3; 430 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 431 field->offset = v4 ? 2 : 4; 432 field->sizem1 = 1; /* i.e 2 bytes */ 433 field->alg = NIX_LSOALG_ADD_PAYLEN; 434 field++; 435 436 /* No ID field in IPv6 header */ 437 if (v4) { 438 /* Increment IPID */ 439 field->layer = NIX_TXLAYER_OL3; 440 field->offset = 4; 441 field->sizem1 = 1; /* i.e 2 bytes */ 442 field->alg = NIX_LSOALG_ADD_SEGNUM; 443 field++; 444 } 445 446 /* Update length in UDP header */ 447 field->layer = NIX_TXLAYER_OL4; 448 field->offset = 4; 449 field->sizem1 = 1; 450 field->alg = NIX_LSOALG_ADD_PAYLEN; 451 } 452 453 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 454 void otx2_setup_segmentation(struct otx2_nic *pfvf) 455 { 456 struct nix_lso_format_cfg_rsp *rsp; 457 struct nix_lso_format_cfg *lso; 458 struct otx2_hw *hw = &pfvf->hw; 459 int err; 460 461 mutex_lock(&pfvf->mbox.lock); 462 463 /* UDPv4 segmentation */ 464 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 465 if (!lso) 466 goto fail; 467 468 /* Setup UDP/IP header fields that HW should update per segment */ 469 otx2_setup_udp_segmentation(lso, true); 470 471 err = otx2_sync_mbox_msg(&pfvf->mbox); 472 if (err) 473 goto fail; 474 475 rsp = (struct nix_lso_format_cfg_rsp *) 476 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 477 if (IS_ERR(rsp)) 478 goto fail; 479 480 hw->lso_udpv4_idx = rsp->lso_format_idx; 481 482 /* UDPv6 segmentation */ 483 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 484 if (!lso) 485 goto fail; 486 487 /* Setup UDP/IP header fields that HW should update per segment */ 488 otx2_setup_udp_segmentation(lso, false); 489 490 err = otx2_sync_mbox_msg(&pfvf->mbox); 491 if (err) 492 goto fail; 493 494 rsp = (struct nix_lso_format_cfg_rsp *) 495 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 496 if (IS_ERR(rsp)) 497 goto fail; 498 499 hw->lso_udpv6_idx = rsp->lso_format_idx; 500 mutex_unlock(&pfvf->mbox.lock); 501 return; 502 fail: 503 mutex_unlock(&pfvf->mbox.lock); 504 netdev_info(pfvf->netdev, 505 "Failed to get LSO index for UDP GSO offload, disabling\n"); 506 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 507 } 508 509 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 510 { 511 /* Configure CQE interrupt coalescing parameters 512 * 513 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 514 * set 1 less than cq_ecount_wait. And cq_time_wait is in 515 * usecs, convert that to 100ns count. 516 */ 517 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 518 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 519 ((u64)pfvf->hw.cq_qcount_wait << 32) | 520 (pfvf->hw.cq_ecount_wait - 1)); 521 } 522 523 static int otx2_alloc_pool_buf(struct otx2_nic *pfvf, struct otx2_pool *pool, 524 dma_addr_t *dma) 525 { 526 unsigned int offset = 0; 527 struct page *page; 528 size_t sz; 529 530 sz = SKB_DATA_ALIGN(pool->rbsize); 531 sz = ALIGN(sz, OTX2_ALIGN); 532 533 page = page_pool_alloc_frag(pool->page_pool, &offset, sz, GFP_ATOMIC); 534 if (unlikely(!page)) 535 return -ENOMEM; 536 537 *dma = page_pool_get_dma_addr(page) + offset; 538 return 0; 539 } 540 541 static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 542 dma_addr_t *dma) 543 { 544 u8 *buf; 545 546 if (pool->page_pool) 547 return otx2_alloc_pool_buf(pfvf, pool, dma); 548 549 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 550 if (unlikely(!buf)) 551 return -ENOMEM; 552 553 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 554 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 555 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 556 page_frag_free(buf); 557 return -ENOMEM; 558 } 559 560 return 0; 561 } 562 563 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 564 dma_addr_t *dma) 565 { 566 int ret; 567 568 local_bh_disable(); 569 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 570 local_bh_enable(); 571 return ret; 572 } 573 574 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 575 dma_addr_t *dma) 576 { 577 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) { 578 struct refill_work *work; 579 struct delayed_work *dwork; 580 581 work = &pfvf->refill_wrk[cq->cq_idx]; 582 dwork = &work->pool_refill_work; 583 /* Schedule a task if no other task is running */ 584 if (!cq->refill_task_sched) { 585 cq->refill_task_sched = true; 586 schedule_delayed_work(dwork, 587 msecs_to_jiffies(100)); 588 } 589 return -ENOMEM; 590 } 591 return 0; 592 } 593 594 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 595 { 596 struct otx2_nic *pfvf = netdev_priv(netdev); 597 598 schedule_work(&pfvf->reset_task); 599 } 600 EXPORT_SYMBOL(otx2_tx_timeout); 601 602 void otx2_get_mac_from_af(struct net_device *netdev) 603 { 604 struct otx2_nic *pfvf = netdev_priv(netdev); 605 int err; 606 607 err = otx2_hw_get_mac_addr(pfvf, netdev); 608 if (err) 609 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 610 611 /* If AF doesn't provide a valid MAC, generate a random one */ 612 if (!is_valid_ether_addr(netdev->dev_addr)) 613 eth_hw_addr_random(netdev); 614 } 615 EXPORT_SYMBOL(otx2_get_mac_from_af); 616 617 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc) 618 { 619 u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC]; 620 struct otx2_hw *hw = &pfvf->hw; 621 struct nix_txschq_config *req; 622 u64 schq, parent; 623 u64 dwrr_val; 624 625 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 626 627 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 628 if (!req) 629 return -ENOMEM; 630 631 req->lvl = lvl; 632 req->num_regs = 1; 633 634 schq_list = hw->txschq_list; 635 #ifdef CONFIG_DCB 636 if (txschq_for_pfc) 637 schq_list = pfvf->pfc_schq_list; 638 #endif 639 640 schq = schq_list[lvl][prio]; 641 /* Set topology e.t.c configuration */ 642 if (lvl == NIX_TXSCH_LVL_SMQ) { 643 req->reg[0] = NIX_AF_SMQX_CFG(schq); 644 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU; 645 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 646 (0x2ULL << 36); 647 /* Set link type for DWRR MTU selection on CN10K silicons */ 648 if (!is_dev_otx2(pfvf->pdev)) 649 req->regval[0] |= FIELD_PREP(GENMASK_ULL(58, 57), 650 (u64)hw->smq_link_type); 651 req->num_regs++; 652 /* MDQ config */ 653 parent = schq_list[NIX_TXSCH_LVL_TL4][prio]; 654 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 655 req->regval[1] = parent << 16; 656 req->num_regs++; 657 /* Set DWRR quantum */ 658 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 659 req->regval[2] = dwrr_val; 660 } else if (lvl == NIX_TXSCH_LVL_TL4) { 661 parent = schq_list[NIX_TXSCH_LVL_TL3][prio]; 662 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 663 req->regval[0] = parent << 16; 664 req->num_regs++; 665 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 666 req->regval[1] = dwrr_val; 667 } else if (lvl == NIX_TXSCH_LVL_TL3) { 668 parent = schq_list[NIX_TXSCH_LVL_TL2][prio]; 669 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 670 req->regval[0] = parent << 16; 671 req->num_regs++; 672 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 673 req->regval[1] = dwrr_val; 674 if (lvl == hw->txschq_link_cfg_lvl) { 675 req->num_regs++; 676 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 677 /* Enable this queue and backpressure 678 * and set relative channel 679 */ 680 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 681 } 682 } else if (lvl == NIX_TXSCH_LVL_TL2) { 683 parent = schq_list[NIX_TXSCH_LVL_TL1][prio]; 684 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 685 req->regval[0] = parent << 16; 686 687 req->num_regs++; 688 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 689 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val; 690 691 if (lvl == hw->txschq_link_cfg_lvl) { 692 req->num_regs++; 693 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 694 /* Enable this queue and backpressure 695 * and set relative channel 696 */ 697 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 698 } 699 } else if (lvl == NIX_TXSCH_LVL_TL1) { 700 /* Default config for TL1. 701 * For VF this is always ignored. 702 */ 703 704 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 705 * clip it to 16384, so configuring a 24bit max value 706 * will work on both OTx2 and CN10K. 707 */ 708 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 709 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 710 711 req->num_regs++; 712 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 713 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 714 715 req->num_regs++; 716 req->reg[2] = NIX_AF_TL1X_CIR(schq); 717 req->regval[2] = 0; 718 } 719 720 return otx2_sync_mbox_msg(&pfvf->mbox); 721 } 722 EXPORT_SYMBOL(otx2_txschq_config); 723 724 int otx2_smq_flush(struct otx2_nic *pfvf, int smq) 725 { 726 struct nix_txschq_config *req; 727 int rc; 728 729 mutex_lock(&pfvf->mbox.lock); 730 731 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 732 if (!req) { 733 mutex_unlock(&pfvf->mbox.lock); 734 return -ENOMEM; 735 } 736 737 req->lvl = NIX_TXSCH_LVL_SMQ; 738 req->reg[0] = NIX_AF_SMQX_CFG(smq); 739 req->regval[0] |= BIT_ULL(49); 740 req->num_regs++; 741 742 rc = otx2_sync_mbox_msg(&pfvf->mbox); 743 mutex_unlock(&pfvf->mbox.lock); 744 return rc; 745 } 746 EXPORT_SYMBOL(otx2_smq_flush); 747 748 int otx2_txsch_alloc(struct otx2_nic *pfvf) 749 { 750 struct nix_txsch_alloc_req *req; 751 struct nix_txsch_alloc_rsp *rsp; 752 int lvl, schq, rc; 753 754 /* Get memory to put this msg */ 755 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 756 if (!req) 757 return -ENOMEM; 758 759 /* Request one schq per level */ 760 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 761 req->schq[lvl] = 1; 762 rc = otx2_sync_mbox_msg(&pfvf->mbox); 763 if (rc) 764 return rc; 765 766 rsp = (struct nix_txsch_alloc_rsp *) 767 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 768 if (IS_ERR(rsp)) 769 return PTR_ERR(rsp); 770 771 /* Setup transmit scheduler list */ 772 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 773 for (schq = 0; schq < rsp->schq[lvl]; schq++) 774 pfvf->hw.txschq_list[lvl][schq] = 775 rsp->schq_list[lvl][schq]; 776 777 pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl; 778 pfvf->hw.txschq_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio; 779 780 return 0; 781 } 782 783 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq) 784 { 785 struct nix_txsch_free_req *free_req; 786 int err; 787 788 mutex_lock(&pfvf->mbox.lock); 789 790 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 791 if (!free_req) { 792 mutex_unlock(&pfvf->mbox.lock); 793 netdev_err(pfvf->netdev, 794 "Failed alloc txschq free req\n"); 795 return; 796 } 797 798 free_req->schq_lvl = lvl; 799 free_req->schq = schq; 800 801 err = otx2_sync_mbox_msg(&pfvf->mbox); 802 if (err) { 803 netdev_err(pfvf->netdev, 804 "Failed stop txschq %d at level %d\n", schq, lvl); 805 } 806 807 mutex_unlock(&pfvf->mbox.lock); 808 } 809 810 void otx2_txschq_stop(struct otx2_nic *pfvf) 811 { 812 int lvl, schq; 813 814 /* free non QOS TLx nodes */ 815 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 816 otx2_txschq_free_one(pfvf, lvl, 817 pfvf->hw.txschq_list[lvl][0]); 818 819 /* Clear the txschq list */ 820 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 821 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 822 pfvf->hw.txschq_list[lvl][schq] = 0; 823 } 824 825 } 826 827 void otx2_sqb_flush(struct otx2_nic *pfvf) 828 { 829 int qidx, sqe_tail, sqe_head; 830 struct otx2_snd_queue *sq; 831 u64 incr, *ptr, val; 832 int timeout = 1000; 833 834 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 835 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 836 sq = &pfvf->qset.sq[qidx]; 837 if (!sq->sqb_ptrs) 838 continue; 839 840 incr = (u64)qidx << 32; 841 while (timeout) { 842 val = otx2_atomic64_add(incr, ptr); 843 sqe_head = (val >> 20) & 0x3F; 844 sqe_tail = (val >> 28) & 0x3F; 845 if (sqe_head == sqe_tail) 846 break; 847 usleep_range(1, 3); 848 timeout--; 849 } 850 } 851 } 852 853 /* RED and drop levels of CQ on packet reception. 854 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 855 */ 856 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 857 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 858 859 /* RED and drop levels of AURA for packet reception. 860 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 861 * Eg: For RQ length 1K, for pass/drop level 204/230. 862 * RED accepts pkts if free pointers > 102 & <= 205. 863 * Drops pkts if free pointers < 102. 864 */ 865 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 866 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 867 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 868 869 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 870 { 871 struct otx2_qset *qset = &pfvf->qset; 872 struct nix_aq_enq_req *aq; 873 874 /* Get memory to put this msg */ 875 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 876 if (!aq) 877 return -ENOMEM; 878 879 aq->rq.cq = qidx; 880 aq->rq.ena = 1; 881 aq->rq.pb_caching = 1; 882 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 883 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 884 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 885 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 886 aq->rq.qint_idx = 0; 887 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 888 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 889 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 890 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 891 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 892 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 893 894 /* Fill AQ info */ 895 aq->qidx = qidx; 896 aq->ctype = NIX_AQ_CTYPE_RQ; 897 aq->op = NIX_AQ_INSTOP_INIT; 898 899 return otx2_sync_mbox_msg(&pfvf->mbox); 900 } 901 902 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 903 { 904 struct otx2_nic *pfvf = dev; 905 struct otx2_snd_queue *sq; 906 struct nix_aq_enq_req *aq; 907 908 sq = &pfvf->qset.sq[qidx]; 909 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 910 /* Get memory to put this msg */ 911 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 912 if (!aq) 913 return -ENOMEM; 914 915 aq->sq.cq = pfvf->hw.rx_queues + qidx; 916 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 917 aq->sq.cq_ena = 1; 918 aq->sq.ena = 1; 919 aq->sq.smq = otx2_get_smq_idx(pfvf, qidx); 920 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 921 aq->sq.default_chan = pfvf->hw.tx_chan_base; 922 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 923 aq->sq.sqb_aura = sqb_aura; 924 aq->sq.sq_int_ena = NIX_SQINT_BITS; 925 aq->sq.qint_idx = 0; 926 /* Due pipelining impact minimum 2000 unused SQ CQE's 927 * need to maintain to avoid CQ overflow. 928 */ 929 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 930 931 /* Fill AQ info */ 932 aq->qidx = qidx; 933 aq->ctype = NIX_AQ_CTYPE_SQ; 934 aq->op = NIX_AQ_INSTOP_INIT; 935 936 return otx2_sync_mbox_msg(&pfvf->mbox); 937 } 938 939 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 940 { 941 struct otx2_qset *qset = &pfvf->qset; 942 struct otx2_snd_queue *sq; 943 struct otx2_pool *pool; 944 int err; 945 946 pool = &pfvf->qset.pool[sqb_aura]; 947 sq = &qset->sq[qidx]; 948 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 949 sq->sqe_cnt = qset->sqe_cnt; 950 951 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 952 if (err) 953 return err; 954 955 if (qidx < pfvf->hw.tx_queues) { 956 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 957 TSO_HEADER_SIZE); 958 if (err) 959 return err; 960 } 961 962 sq->sqe_base = sq->sqe->base; 963 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 964 if (!sq->sg) 965 return -ENOMEM; 966 967 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) { 968 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 969 sizeof(*sq->timestamps)); 970 if (err) 971 return err; 972 } 973 974 sq->head = 0; 975 sq->cons_head = 0; 976 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 977 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 978 /* Set SQE threshold to 10% of total SQEs */ 979 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 980 sq->aura_id = sqb_aura; 981 sq->aura_fc_addr = pool->fc_addr->base; 982 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 983 984 sq->stats.bytes = 0; 985 sq->stats.pkts = 0; 986 987 return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); 988 989 } 990 991 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 992 { 993 struct otx2_qset *qset = &pfvf->qset; 994 int err, pool_id, non_xdp_queues; 995 struct nix_aq_enq_req *aq; 996 struct otx2_cq_queue *cq; 997 998 cq = &qset->cq[qidx]; 999 cq->cq_idx = qidx; 1000 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues; 1001 if (qidx < pfvf->hw.rx_queues) { 1002 cq->cq_type = CQ_RX; 1003 cq->cint_idx = qidx; 1004 cq->cqe_cnt = qset->rqe_cnt; 1005 if (pfvf->xdp_prog) 1006 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0); 1007 } else if (qidx < non_xdp_queues) { 1008 cq->cq_type = CQ_TX; 1009 cq->cint_idx = qidx - pfvf->hw.rx_queues; 1010 cq->cqe_cnt = qset->sqe_cnt; 1011 } else { 1012 if (pfvf->hw.xdp_queues && 1013 qidx < non_xdp_queues + pfvf->hw.xdp_queues) { 1014 cq->cq_type = CQ_XDP; 1015 cq->cint_idx = qidx - non_xdp_queues; 1016 cq->cqe_cnt = qset->sqe_cnt; 1017 } else { 1018 cq->cq_type = CQ_QOS; 1019 cq->cint_idx = qidx - non_xdp_queues - 1020 pfvf->hw.xdp_queues; 1021 cq->cqe_cnt = qset->sqe_cnt; 1022 } 1023 } 1024 cq->cqe_size = pfvf->qset.xqe_size; 1025 1026 /* Allocate memory for CQEs */ 1027 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 1028 if (err) 1029 return err; 1030 1031 /* Save CQE CPU base for faster reference */ 1032 cq->cqe_base = cq->cqe->base; 1033 /* In case where all RQs auras point to single pool, 1034 * all CQs receive buffer pool also point to same pool. 1035 */ 1036 pool_id = ((cq->cq_type == CQ_RX) && 1037 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 1038 cq->rbpool = &qset->pool[pool_id]; 1039 cq->refill_task_sched = false; 1040 1041 /* Get memory to put this msg */ 1042 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 1043 if (!aq) 1044 return -ENOMEM; 1045 1046 aq->cq.ena = 1; 1047 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 1048 aq->cq.caching = 1; 1049 aq->cq.base = cq->cqe->iova; 1050 aq->cq.cint_idx = cq->cint_idx; 1051 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 1052 aq->cq.qint_idx = 0; 1053 aq->cq.avg_level = 255; 1054 1055 if (qidx < pfvf->hw.rx_queues) { 1056 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 1057 aq->cq.drop_ena = 1; 1058 1059 if (!is_otx2_lbkvf(pfvf->pdev)) { 1060 /* Enable receive CQ backpressure */ 1061 aq->cq.bp_ena = 1; 1062 #ifdef CONFIG_DCB 1063 aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]]; 1064 #else 1065 aq->cq.bpid = pfvf->bpid[0]; 1066 #endif 1067 1068 /* Set backpressure level is same as cq pass level */ 1069 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 1070 } 1071 } 1072 1073 /* Fill AQ info */ 1074 aq->qidx = qidx; 1075 aq->ctype = NIX_AQ_CTYPE_CQ; 1076 aq->op = NIX_AQ_INSTOP_INIT; 1077 1078 return otx2_sync_mbox_msg(&pfvf->mbox); 1079 } 1080 1081 static void otx2_pool_refill_task(struct work_struct *work) 1082 { 1083 struct otx2_cq_queue *cq; 1084 struct otx2_pool *rbpool; 1085 struct refill_work *wrk; 1086 int qidx, free_ptrs = 0; 1087 struct otx2_nic *pfvf; 1088 dma_addr_t bufptr; 1089 1090 wrk = container_of(work, struct refill_work, pool_refill_work.work); 1091 pfvf = wrk->pf; 1092 qidx = wrk - pfvf->refill_wrk; 1093 cq = &pfvf->qset.cq[qidx]; 1094 rbpool = cq->rbpool; 1095 free_ptrs = cq->pool_ptrs; 1096 1097 while (cq->pool_ptrs) { 1098 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) { 1099 /* Schedule a WQ if we fails to free atleast half of the 1100 * pointers else enable napi for this RQ. 1101 */ 1102 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 1103 struct delayed_work *dwork; 1104 1105 dwork = &wrk->pool_refill_work; 1106 schedule_delayed_work(dwork, 1107 msecs_to_jiffies(100)); 1108 } else { 1109 cq->refill_task_sched = false; 1110 } 1111 return; 1112 } 1113 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 1114 cq->pool_ptrs--; 1115 } 1116 cq->refill_task_sched = false; 1117 } 1118 1119 int otx2_config_nix_queues(struct otx2_nic *pfvf) 1120 { 1121 int qidx, err; 1122 1123 /* Initialize RX queues */ 1124 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 1125 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 1126 1127 err = otx2_rq_init(pfvf, qidx, lpb_aura); 1128 if (err) 1129 return err; 1130 } 1131 1132 /* Initialize TX queues */ 1133 for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) { 1134 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1135 1136 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1137 if (err) 1138 return err; 1139 } 1140 1141 /* Initialize completion queues */ 1142 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1143 err = otx2_cq_init(pfvf, qidx); 1144 if (err) 1145 return err; 1146 } 1147 1148 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, 1149 NIX_LF_CQ_OP_STATUS); 1150 1151 /* Initialize work queue for receive buffer refill */ 1152 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1153 sizeof(struct refill_work), GFP_KERNEL); 1154 if (!pfvf->refill_wrk) 1155 return -ENOMEM; 1156 1157 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1158 pfvf->refill_wrk[qidx].pf = pfvf; 1159 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1160 otx2_pool_refill_task); 1161 } 1162 return 0; 1163 } 1164 1165 int otx2_config_nix(struct otx2_nic *pfvf) 1166 { 1167 struct nix_lf_alloc_req *nixlf; 1168 struct nix_lf_alloc_rsp *rsp; 1169 int err; 1170 1171 pfvf->qset.xqe_size = pfvf->hw.xqe_size; 1172 1173 /* Get memory to put this msg */ 1174 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1175 if (!nixlf) 1176 return -ENOMEM; 1177 1178 /* Set RQ/SQ/CQ counts */ 1179 nixlf->rq_cnt = pfvf->hw.rx_queues; 1180 nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf); 1181 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1182 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1183 nixlf->rss_grps = MAX_RSS_GROUPS; 1184 nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64; 1185 /* We don't know absolute NPA LF idx attached. 1186 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1187 * NPA LF attached to this RVU PF/VF. 1188 */ 1189 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1190 /* Disable alignment pad, enable L2 length check, 1191 * enable L4 TCP/UDP checksum verification. 1192 */ 1193 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1194 1195 err = otx2_sync_mbox_msg(&pfvf->mbox); 1196 if (err) 1197 return err; 1198 1199 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1200 &nixlf->hdr); 1201 if (IS_ERR(rsp)) 1202 return PTR_ERR(rsp); 1203 1204 if (rsp->qints < 1) 1205 return -ENXIO; 1206 1207 return rsp->hdr.rc; 1208 } 1209 1210 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1211 { 1212 struct otx2_qset *qset = &pfvf->qset; 1213 struct otx2_hw *hw = &pfvf->hw; 1214 struct otx2_snd_queue *sq; 1215 int sqb, qidx; 1216 u64 iova, pa; 1217 1218 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 1219 sq = &qset->sq[qidx]; 1220 if (!sq->sqb_ptrs) 1221 continue; 1222 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1223 if (!sq->sqb_ptrs[sqb]) 1224 continue; 1225 iova = sq->sqb_ptrs[sqb]; 1226 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1227 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1228 DMA_FROM_DEVICE, 1229 DMA_ATTR_SKIP_CPU_SYNC); 1230 put_page(virt_to_page(phys_to_virt(pa))); 1231 } 1232 sq->sqb_count = 0; 1233 } 1234 } 1235 1236 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1237 u64 iova, int size) 1238 { 1239 struct page *page; 1240 u64 pa; 1241 1242 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1243 page = virt_to_head_page(phys_to_virt(pa)); 1244 1245 if (pool->page_pool) { 1246 page_pool_put_full_page(pool->page_pool, page, true); 1247 } else { 1248 dma_unmap_page_attrs(pfvf->dev, iova, size, 1249 DMA_FROM_DEVICE, 1250 DMA_ATTR_SKIP_CPU_SYNC); 1251 1252 put_page(page); 1253 } 1254 } 1255 1256 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1257 { 1258 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1259 struct otx2_pool *pool; 1260 u64 iova; 1261 1262 if (type == AURA_NIX_SQ) { 1263 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1264 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1265 size = pfvf->hw.sqb_size; 1266 } 1267 if (type == AURA_NIX_RQ) { 1268 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1269 pool_end = pfvf->hw.rqpool_cnt; 1270 size = pfvf->rbsize; 1271 } 1272 1273 /* Free SQB and RQB pointers from the aura pool */ 1274 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1275 iova = otx2_aura_allocptr(pfvf, pool_id); 1276 pool = &pfvf->qset.pool[pool_id]; 1277 while (iova) { 1278 if (type == AURA_NIX_RQ) 1279 iova -= OTX2_HEAD_ROOM; 1280 1281 otx2_free_bufs(pfvf, pool, iova, size); 1282 1283 iova = otx2_aura_allocptr(pfvf, pool_id); 1284 } 1285 } 1286 } 1287 1288 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1289 { 1290 struct otx2_pool *pool; 1291 int pool_id; 1292 1293 if (!pfvf->qset.pool) 1294 return; 1295 1296 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1297 pool = &pfvf->qset.pool[pool_id]; 1298 qmem_free(pfvf->dev, pool->stack); 1299 qmem_free(pfvf->dev, pool->fc_addr); 1300 page_pool_destroy(pool->page_pool); 1301 pool->page_pool = NULL; 1302 } 1303 devm_kfree(pfvf->dev, pfvf->qset.pool); 1304 pfvf->qset.pool = NULL; 1305 } 1306 1307 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1308 int pool_id, int numptrs) 1309 { 1310 struct npa_aq_enq_req *aq; 1311 struct otx2_pool *pool; 1312 int err; 1313 1314 pool = &pfvf->qset.pool[pool_id]; 1315 1316 /* Allocate memory for HW to update Aura count. 1317 * Alloc one cache line, so that it fits all FC_STYPE modes. 1318 */ 1319 if (!pool->fc_addr) { 1320 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1321 if (err) 1322 return err; 1323 } 1324 1325 /* Initialize this aura's context via AF */ 1326 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1327 if (!aq) { 1328 /* Shared mbox memory buffer is full, flush it and retry */ 1329 err = otx2_sync_mbox_msg(&pfvf->mbox); 1330 if (err) 1331 return err; 1332 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1333 if (!aq) 1334 return -ENOMEM; 1335 } 1336 1337 aq->aura_id = aura_id; 1338 /* Will be filled by AF with correct pool context address */ 1339 aq->aura.pool_addr = pool_id; 1340 aq->aura.pool_caching = 1; 1341 aq->aura.shift = ilog2(numptrs) - 8; 1342 aq->aura.count = numptrs; 1343 aq->aura.limit = numptrs; 1344 aq->aura.avg_level = 255; 1345 aq->aura.ena = 1; 1346 aq->aura.fc_ena = 1; 1347 aq->aura.fc_addr = pool->fc_addr->iova; 1348 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1349 1350 /* Enable backpressure for RQ aura */ 1351 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1352 aq->aura.bp_ena = 0; 1353 /* If NIX1 LF is attached then specify NIX1_RX. 1354 * 1355 * Below NPA_AURA_S[BP_ENA] is set according to the 1356 * NPA_BPINTF_E enumeration given as: 1357 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1358 * NIX0_RX is 0x0 + 0*0x1 = 0 1359 * NIX1_RX is 0x0 + 1*0x1 = 1 1360 * But in HRM it is given that 1361 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1362 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1363 * enumerated by NPA_BPINTF_E." 1364 */ 1365 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1366 aq->aura.bp_ena = 1; 1367 #ifdef CONFIG_DCB 1368 aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]]; 1369 #else 1370 aq->aura.nix0_bpid = pfvf->bpid[0]; 1371 #endif 1372 1373 /* Set backpressure level for RQ's Aura */ 1374 aq->aura.bp = RQ_BP_LVL_AURA; 1375 } 1376 1377 /* Fill AQ info */ 1378 aq->ctype = NPA_AQ_CTYPE_AURA; 1379 aq->op = NPA_AQ_INSTOP_INIT; 1380 1381 return 0; 1382 } 1383 1384 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1385 int stack_pages, int numptrs, int buf_size, int type) 1386 { 1387 struct page_pool_params pp_params = { 0 }; 1388 struct npa_aq_enq_req *aq; 1389 struct otx2_pool *pool; 1390 int err; 1391 1392 pool = &pfvf->qset.pool[pool_id]; 1393 /* Alloc memory for stack which is used to store buffer pointers */ 1394 err = qmem_alloc(pfvf->dev, &pool->stack, 1395 stack_pages, pfvf->hw.stack_pg_bytes); 1396 if (err) 1397 return err; 1398 1399 pool->rbsize = buf_size; 1400 1401 /* Initialize this pool's context via AF */ 1402 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1403 if (!aq) { 1404 /* Shared mbox memory buffer is full, flush it and retry */ 1405 err = otx2_sync_mbox_msg(&pfvf->mbox); 1406 if (err) { 1407 qmem_free(pfvf->dev, pool->stack); 1408 return err; 1409 } 1410 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1411 if (!aq) { 1412 qmem_free(pfvf->dev, pool->stack); 1413 return -ENOMEM; 1414 } 1415 } 1416 1417 aq->aura_id = pool_id; 1418 aq->pool.stack_base = pool->stack->iova; 1419 aq->pool.stack_caching = 1; 1420 aq->pool.ena = 1; 1421 aq->pool.buf_size = buf_size / 128; 1422 aq->pool.stack_max_pages = stack_pages; 1423 aq->pool.shift = ilog2(numptrs) - 8; 1424 aq->pool.ptr_start = 0; 1425 aq->pool.ptr_end = ~0ULL; 1426 1427 /* Fill AQ info */ 1428 aq->ctype = NPA_AQ_CTYPE_POOL; 1429 aq->op = NPA_AQ_INSTOP_INIT; 1430 1431 if (type != AURA_NIX_RQ) { 1432 pool->page_pool = NULL; 1433 return 0; 1434 } 1435 1436 pp_params.flags = PP_FLAG_PAGE_FRAG | PP_FLAG_DMA_MAP; 1437 pp_params.pool_size = numptrs; 1438 pp_params.nid = NUMA_NO_NODE; 1439 pp_params.dev = pfvf->dev; 1440 pp_params.dma_dir = DMA_FROM_DEVICE; 1441 pool->page_pool = page_pool_create(&pp_params); 1442 if (IS_ERR(pool->page_pool)) { 1443 netdev_err(pfvf->netdev, "Creation of page pool failed\n"); 1444 return PTR_ERR(pool->page_pool); 1445 } 1446 1447 return 0; 1448 } 1449 1450 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1451 { 1452 int qidx, pool_id, stack_pages, num_sqbs; 1453 struct otx2_qset *qset = &pfvf->qset; 1454 struct otx2_hw *hw = &pfvf->hw; 1455 struct otx2_snd_queue *sq; 1456 struct otx2_pool *pool; 1457 dma_addr_t bufptr; 1458 int err, ptr; 1459 1460 /* Calculate number of SQBs needed. 1461 * 1462 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1463 * Last SQE is used for pointing to next SQB. 1464 */ 1465 num_sqbs = (hw->sqb_size / 128) - 1; 1466 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1467 1468 /* Get no of stack pages needed */ 1469 stack_pages = 1470 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1471 1472 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1473 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1474 /* Initialize aura context */ 1475 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1476 if (err) 1477 goto fail; 1478 1479 /* Initialize pool context */ 1480 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1481 num_sqbs, hw->sqb_size, AURA_NIX_SQ); 1482 if (err) 1483 goto fail; 1484 } 1485 1486 /* Flush accumulated messages */ 1487 err = otx2_sync_mbox_msg(&pfvf->mbox); 1488 if (err) 1489 goto fail; 1490 1491 /* Allocate pointers and free them to aura/pool */ 1492 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1493 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1494 pool = &pfvf->qset.pool[pool_id]; 1495 1496 sq = &qset->sq[qidx]; 1497 sq->sqb_count = 0; 1498 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1499 if (!sq->sqb_ptrs) { 1500 err = -ENOMEM; 1501 goto err_mem; 1502 } 1503 1504 for (ptr = 0; ptr < num_sqbs; ptr++) { 1505 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1506 if (err) 1507 goto err_mem; 1508 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1509 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1510 } 1511 } 1512 1513 err_mem: 1514 return err ? -ENOMEM : 0; 1515 1516 fail: 1517 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1518 otx2_aura_pool_free(pfvf); 1519 return err; 1520 } 1521 1522 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1523 { 1524 struct otx2_hw *hw = &pfvf->hw; 1525 int stack_pages, pool_id, rq; 1526 struct otx2_pool *pool; 1527 int err, ptr, num_ptrs; 1528 dma_addr_t bufptr; 1529 1530 num_ptrs = pfvf->qset.rqe_cnt; 1531 1532 stack_pages = 1533 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1534 1535 for (rq = 0; rq < hw->rx_queues; rq++) { 1536 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1537 /* Initialize aura context */ 1538 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1539 if (err) 1540 goto fail; 1541 } 1542 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1543 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1544 num_ptrs, pfvf->rbsize, AURA_NIX_RQ); 1545 if (err) 1546 goto fail; 1547 } 1548 1549 /* Flush accumulated messages */ 1550 err = otx2_sync_mbox_msg(&pfvf->mbox); 1551 if (err) 1552 goto fail; 1553 1554 /* Allocate pointers and free them to aura/pool */ 1555 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1556 pool = &pfvf->qset.pool[pool_id]; 1557 for (ptr = 0; ptr < num_ptrs; ptr++) { 1558 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1559 if (err) 1560 return -ENOMEM; 1561 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1562 bufptr + OTX2_HEAD_ROOM); 1563 } 1564 } 1565 return 0; 1566 fail: 1567 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1568 otx2_aura_pool_free(pfvf); 1569 return err; 1570 } 1571 1572 int otx2_config_npa(struct otx2_nic *pfvf) 1573 { 1574 struct otx2_qset *qset = &pfvf->qset; 1575 struct npa_lf_alloc_req *npalf; 1576 struct otx2_hw *hw = &pfvf->hw; 1577 int aura_cnt; 1578 1579 /* Pool - Stack of free buffer pointers 1580 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1581 */ 1582 1583 if (!hw->pool_cnt) 1584 return -EINVAL; 1585 1586 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1587 sizeof(struct otx2_pool), GFP_KERNEL); 1588 if (!qset->pool) 1589 return -ENOMEM; 1590 1591 /* Get memory to put this msg */ 1592 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1593 if (!npalf) 1594 return -ENOMEM; 1595 1596 /* Set aura and pool counts */ 1597 npalf->nr_pools = hw->pool_cnt; 1598 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1599 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1600 1601 return otx2_sync_mbox_msg(&pfvf->mbox); 1602 } 1603 1604 int otx2_detach_resources(struct mbox *mbox) 1605 { 1606 struct rsrc_detach *detach; 1607 1608 mutex_lock(&mbox->lock); 1609 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1610 if (!detach) { 1611 mutex_unlock(&mbox->lock); 1612 return -ENOMEM; 1613 } 1614 1615 /* detach all */ 1616 detach->partial = false; 1617 1618 /* Send detach request to AF */ 1619 otx2_mbox_msg_send(&mbox->mbox, 0); 1620 mutex_unlock(&mbox->lock); 1621 return 0; 1622 } 1623 EXPORT_SYMBOL(otx2_detach_resources); 1624 1625 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1626 { 1627 struct rsrc_attach *attach; 1628 struct msg_req *msix; 1629 int err; 1630 1631 mutex_lock(&pfvf->mbox.lock); 1632 /* Get memory to put this msg */ 1633 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1634 if (!attach) { 1635 mutex_unlock(&pfvf->mbox.lock); 1636 return -ENOMEM; 1637 } 1638 1639 attach->npalf = true; 1640 attach->nixlf = true; 1641 1642 /* Send attach request to AF */ 1643 err = otx2_sync_mbox_msg(&pfvf->mbox); 1644 if (err) { 1645 mutex_unlock(&pfvf->mbox.lock); 1646 return err; 1647 } 1648 1649 pfvf->nix_blkaddr = BLKADDR_NIX0; 1650 1651 /* If the platform has two NIX blocks then LF may be 1652 * allocated from NIX1. 1653 */ 1654 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1655 pfvf->nix_blkaddr = BLKADDR_NIX1; 1656 1657 /* Get NPA and NIX MSIX vector offsets */ 1658 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1659 if (!msix) { 1660 mutex_unlock(&pfvf->mbox.lock); 1661 return -ENOMEM; 1662 } 1663 1664 err = otx2_sync_mbox_msg(&pfvf->mbox); 1665 if (err) { 1666 mutex_unlock(&pfvf->mbox.lock); 1667 return err; 1668 } 1669 mutex_unlock(&pfvf->mbox.lock); 1670 1671 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1672 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1673 dev_err(pfvf->dev, 1674 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1675 return -EINVAL; 1676 } 1677 1678 return 0; 1679 } 1680 EXPORT_SYMBOL(otx2_attach_npa_nix); 1681 1682 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1683 { 1684 struct hwctx_disable_req *req; 1685 1686 mutex_lock(&mbox->lock); 1687 /* Request AQ to disable this context */ 1688 if (npa) 1689 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1690 else 1691 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1692 1693 if (!req) { 1694 mutex_unlock(&mbox->lock); 1695 return; 1696 } 1697 1698 req->ctype = type; 1699 1700 if (otx2_sync_mbox_msg(mbox)) 1701 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1702 __func__); 1703 1704 mutex_unlock(&mbox->lock); 1705 } 1706 1707 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1708 { 1709 struct nix_bp_cfg_req *req; 1710 1711 if (enable) 1712 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1713 else 1714 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1715 1716 if (!req) 1717 return -ENOMEM; 1718 1719 req->chan_base = 0; 1720 #ifdef CONFIG_DCB 1721 req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1; 1722 req->bpid_per_chan = pfvf->pfc_en ? 1 : 0; 1723 #else 1724 req->chan_cnt = 1; 1725 req->bpid_per_chan = 0; 1726 #endif 1727 1728 return otx2_sync_mbox_msg(&pfvf->mbox); 1729 } 1730 EXPORT_SYMBOL(otx2_nix_config_bp); 1731 1732 /* Mbox message handlers */ 1733 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1734 struct cgx_stats_rsp *rsp) 1735 { 1736 int id; 1737 1738 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1739 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1740 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1741 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1742 } 1743 1744 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1745 struct cgx_fec_stats_rsp *rsp) 1746 { 1747 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1748 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1749 } 1750 1751 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1752 struct npa_lf_alloc_rsp *rsp) 1753 { 1754 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1755 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1756 } 1757 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1758 1759 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1760 struct nix_lf_alloc_rsp *rsp) 1761 { 1762 pfvf->hw.sqb_size = rsp->sqb_size; 1763 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1764 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1765 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1766 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1767 pfvf->hw.cgx_links = rsp->cgx_links; 1768 pfvf->hw.lbk_links = rsp->lbk_links; 1769 pfvf->hw.tx_link = rsp->tx_link; 1770 } 1771 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1772 1773 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1774 struct msix_offset_rsp *rsp) 1775 { 1776 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1777 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1778 } 1779 EXPORT_SYMBOL(mbox_handler_msix_offset); 1780 1781 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1782 struct nix_bp_cfg_rsp *rsp) 1783 { 1784 int chan, chan_id; 1785 1786 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1787 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1788 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1789 } 1790 } 1791 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1792 1793 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1794 { 1795 struct otx2_qset *qset = &pfvf->qset; 1796 struct otx2_hw *hw = &pfvf->hw; 1797 int irq, qidx; 1798 1799 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1800 qidx < n; 1801 qidx++, irq++) { 1802 int vector = pci_irq_vector(pfvf->pdev, irq); 1803 1804 irq_set_affinity_hint(vector, NULL); 1805 free_cpumask_var(hw->affinity_mask[irq]); 1806 free_irq(vector, &qset->napi[qidx]); 1807 } 1808 } 1809 1810 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1811 { 1812 struct otx2_hw *hw = &pfvf->hw; 1813 int vec, cpu, irq, cint; 1814 1815 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1816 cpu = cpumask_first(cpu_online_mask); 1817 1818 /* CQ interrupts */ 1819 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1820 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1821 return; 1822 1823 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1824 1825 irq = pci_irq_vector(pfvf->pdev, vec); 1826 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1827 1828 cpu = cpumask_next(cpu, cpu_online_mask); 1829 if (unlikely(cpu >= nr_cpu_ids)) 1830 cpu = 0; 1831 } 1832 } 1833 1834 static u32 get_dwrr_mtu(struct otx2_nic *pfvf, struct nix_hw_info *hw) 1835 { 1836 if (is_otx2_lbkvf(pfvf->pdev)) { 1837 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_LBK; 1838 return hw->lbk_dwrr_mtu; 1839 } 1840 1841 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_RPM; 1842 return hw->rpm_dwrr_mtu; 1843 } 1844 1845 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1846 { 1847 struct nix_hw_info *rsp; 1848 struct msg_req *req; 1849 u16 max_mtu; 1850 int rc; 1851 1852 mutex_lock(&pfvf->mbox.lock); 1853 1854 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1855 if (!req) { 1856 rc = -ENOMEM; 1857 goto out; 1858 } 1859 1860 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1861 if (!rc) { 1862 rsp = (struct nix_hw_info *) 1863 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1864 1865 /* HW counts VLAN insertion bytes (8 for double tag) 1866 * irrespective of whether SQE is requesting to insert VLAN 1867 * in the packet or not. Hence these 8 bytes have to be 1868 * discounted from max packet size otherwise HW will throw 1869 * SMQ errors 1870 */ 1871 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1872 1873 /* Also save DWRR MTU, needed for DWRR weight calculation */ 1874 pfvf->hw.dwrr_mtu = get_dwrr_mtu(pfvf, rsp); 1875 if (!pfvf->hw.dwrr_mtu) 1876 pfvf->hw.dwrr_mtu = 1; 1877 } 1878 1879 out: 1880 mutex_unlock(&pfvf->mbox.lock); 1881 if (rc) { 1882 dev_warn(pfvf->dev, 1883 "Failed to get MTU from hardware setting default value(1500)\n"); 1884 max_mtu = 1500; 1885 } 1886 return max_mtu; 1887 } 1888 EXPORT_SYMBOL(otx2_get_max_mtu); 1889 1890 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features) 1891 { 1892 netdev_features_t changed = features ^ netdev->features; 1893 struct otx2_nic *pfvf = netdev_priv(netdev); 1894 bool ntuple = !!(features & NETIF_F_NTUPLE); 1895 bool tc = !!(features & NETIF_F_HW_TC); 1896 1897 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1898 otx2_destroy_ntuple_flows(pfvf); 1899 1900 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1901 if (!pfvf->flow_cfg->max_flows) { 1902 netdev_err(netdev, 1903 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1904 return -EINVAL; 1905 } 1906 } 1907 1908 if ((changed & NETIF_F_HW_TC) && !tc && 1909 otx2_tc_flower_rule_cnt(pfvf)) { 1910 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1911 return -EBUSY; 1912 } 1913 1914 if ((changed & NETIF_F_NTUPLE) && ntuple && 1915 otx2_tc_flower_rule_cnt(pfvf) && !(changed & NETIF_F_HW_TC)) { 1916 netdev_err(netdev, 1917 "Can't enable NTUPLE when TC flower offload is active, disable TC rules and retry\n"); 1918 return -EINVAL; 1919 } 1920 1921 return 0; 1922 } 1923 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features); 1924 1925 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1926 int __weak \ 1927 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1928 struct _req_type *req, \ 1929 struct _rsp_type *rsp) \ 1930 { \ 1931 /* Nothing to do here */ \ 1932 return 0; \ 1933 } \ 1934 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1935 MBOX_UP_CGX_MESSAGES 1936 MBOX_UP_MCS_MESSAGES 1937 #undef M 1938