1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 #include <net/tso.h> 11 12 #include "otx2_reg.h" 13 #include "otx2_common.h" 14 #include "otx2_struct.h" 15 #include "cn10k.h" 16 17 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 18 struct otx2_nic *pfvf, int qidx) 19 { 20 u64 incr = (u64)qidx << 32; 21 u64 *ptr; 22 23 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 24 stats->bytes = otx2_atomic64_add(incr, ptr); 25 26 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 27 stats->pkts = otx2_atomic64_add(incr, ptr); 28 } 29 30 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 31 struct otx2_nic *pfvf, int qidx) 32 { 33 u64 incr = (u64)qidx << 32; 34 u64 *ptr; 35 36 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 37 stats->bytes = otx2_atomic64_add(incr, ptr); 38 39 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 40 stats->pkts = otx2_atomic64_add(incr, ptr); 41 } 42 43 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 44 { 45 struct msg_req *req; 46 47 if (!netif_running(pfvf->netdev)) 48 return; 49 50 mutex_lock(&pfvf->mbox.lock); 51 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 52 if (!req) { 53 mutex_unlock(&pfvf->mbox.lock); 54 return; 55 } 56 57 otx2_sync_mbox_msg(&pfvf->mbox); 58 mutex_unlock(&pfvf->mbox.lock); 59 } 60 61 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 62 { 63 struct msg_req *req; 64 65 if (!netif_running(pfvf->netdev)) 66 return; 67 mutex_lock(&pfvf->mbox.lock); 68 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 69 if (req) 70 otx2_sync_mbox_msg(&pfvf->mbox); 71 mutex_unlock(&pfvf->mbox.lock); 72 } 73 74 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 75 { 76 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 77 78 if (!pfvf->qset.rq) 79 return 0; 80 81 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 82 return 1; 83 } 84 85 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 86 { 87 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 88 89 if (!pfvf->qset.sq) 90 return 0; 91 92 if (qidx >= pfvf->hw.non_qos_queues) { 93 if (!test_bit(qidx - pfvf->hw.non_qos_queues, pfvf->qos.qos_sq_bmap)) 94 return 0; 95 } 96 97 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 98 return 1; 99 } 100 101 void otx2_get_dev_stats(struct otx2_nic *pfvf) 102 { 103 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 104 105 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 106 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 107 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 108 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 109 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 110 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 111 dev_stats->rx_mcast_frames + 112 dev_stats->rx_ucast_frames; 113 114 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 115 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 116 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 117 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 118 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 119 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 120 dev_stats->tx_mcast_frames + 121 dev_stats->tx_ucast_frames; 122 } 123 124 void otx2_get_stats64(struct net_device *netdev, 125 struct rtnl_link_stats64 *stats) 126 { 127 struct otx2_nic *pfvf = netdev_priv(netdev); 128 struct otx2_dev_stats *dev_stats; 129 130 otx2_get_dev_stats(pfvf); 131 132 dev_stats = &pfvf->hw.dev_stats; 133 stats->rx_bytes = dev_stats->rx_bytes; 134 stats->rx_packets = dev_stats->rx_frames; 135 stats->rx_dropped = dev_stats->rx_drops; 136 stats->multicast = dev_stats->rx_mcast_frames; 137 138 stats->tx_bytes = dev_stats->tx_bytes; 139 stats->tx_packets = dev_stats->tx_frames; 140 stats->tx_dropped = dev_stats->tx_drops; 141 } 142 EXPORT_SYMBOL(otx2_get_stats64); 143 144 /* Sync MAC address with RVU AF */ 145 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 146 { 147 struct nix_set_mac_addr *req; 148 int err; 149 150 mutex_lock(&pfvf->mbox.lock); 151 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 152 if (!req) { 153 mutex_unlock(&pfvf->mbox.lock); 154 return -ENOMEM; 155 } 156 157 ether_addr_copy(req->mac_addr, mac); 158 159 err = otx2_sync_mbox_msg(&pfvf->mbox); 160 mutex_unlock(&pfvf->mbox.lock); 161 return err; 162 } 163 164 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 165 struct net_device *netdev) 166 { 167 struct nix_get_mac_addr_rsp *rsp; 168 struct mbox_msghdr *msghdr; 169 struct msg_req *req; 170 int err; 171 172 mutex_lock(&pfvf->mbox.lock); 173 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 174 if (!req) { 175 mutex_unlock(&pfvf->mbox.lock); 176 return -ENOMEM; 177 } 178 179 err = otx2_sync_mbox_msg(&pfvf->mbox); 180 if (err) { 181 mutex_unlock(&pfvf->mbox.lock); 182 return err; 183 } 184 185 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 186 if (IS_ERR(msghdr)) { 187 mutex_unlock(&pfvf->mbox.lock); 188 return PTR_ERR(msghdr); 189 } 190 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 191 eth_hw_addr_set(netdev, rsp->mac_addr); 192 mutex_unlock(&pfvf->mbox.lock); 193 194 return 0; 195 } 196 197 int otx2_set_mac_address(struct net_device *netdev, void *p) 198 { 199 struct otx2_nic *pfvf = netdev_priv(netdev); 200 struct sockaddr *addr = p; 201 202 if (!is_valid_ether_addr(addr->sa_data)) 203 return -EADDRNOTAVAIL; 204 205 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 206 eth_hw_addr_set(netdev, addr->sa_data); 207 /* update dmac field in vlan offload rule */ 208 if (netif_running(netdev) && 209 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 210 otx2_install_rxvlan_offload_flow(pfvf); 211 /* update dmac address in ntuple and DMAC filter list */ 212 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 213 otx2_dmacflt_update_pfmac_flow(pfvf); 214 } else { 215 return -EPERM; 216 } 217 218 return 0; 219 } 220 EXPORT_SYMBOL(otx2_set_mac_address); 221 222 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 223 { 224 struct nix_frs_cfg *req; 225 u16 maxlen; 226 int err; 227 228 maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 229 230 mutex_lock(&pfvf->mbox.lock); 231 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 232 if (!req) { 233 mutex_unlock(&pfvf->mbox.lock); 234 return -ENOMEM; 235 } 236 237 req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 238 239 /* Use max receive length supported by hardware for loopback devices */ 240 if (is_otx2_lbkvf(pfvf->pdev)) 241 req->maxlen = maxlen; 242 243 err = otx2_sync_mbox_msg(&pfvf->mbox); 244 mutex_unlock(&pfvf->mbox.lock); 245 return err; 246 } 247 248 int otx2_config_pause_frm(struct otx2_nic *pfvf) 249 { 250 struct cgx_pause_frm_cfg *req; 251 int err; 252 253 if (is_otx2_lbkvf(pfvf->pdev)) 254 return 0; 255 256 mutex_lock(&pfvf->mbox.lock); 257 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 258 if (!req) { 259 err = -ENOMEM; 260 goto unlock; 261 } 262 263 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 264 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 265 req->set = 1; 266 267 err = otx2_sync_mbox_msg(&pfvf->mbox); 268 unlock: 269 mutex_unlock(&pfvf->mbox.lock); 270 return err; 271 } 272 EXPORT_SYMBOL(otx2_config_pause_frm); 273 274 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 275 { 276 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 277 struct nix_rss_flowkey_cfg_rsp *rsp; 278 struct nix_rss_flowkey_cfg *req; 279 int err; 280 281 mutex_lock(&pfvf->mbox.lock); 282 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 283 if (!req) { 284 mutex_unlock(&pfvf->mbox.lock); 285 return -ENOMEM; 286 } 287 req->mcam_index = -1; /* Default or reserved index */ 288 req->flowkey_cfg = rss->flowkey_cfg; 289 req->group = DEFAULT_RSS_CONTEXT_GROUP; 290 291 err = otx2_sync_mbox_msg(&pfvf->mbox); 292 if (err) 293 goto fail; 294 295 rsp = (struct nix_rss_flowkey_cfg_rsp *) 296 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 297 if (IS_ERR(rsp)) { 298 err = PTR_ERR(rsp); 299 goto fail; 300 } 301 302 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 303 fail: 304 mutex_unlock(&pfvf->mbox.lock); 305 return err; 306 } 307 308 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 309 { 310 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 311 const int index = rss->rss_size * ctx_id; 312 struct mbox *mbox = &pfvf->mbox; 313 struct otx2_rss_ctx *rss_ctx; 314 struct nix_aq_enq_req *aq; 315 int idx, err; 316 317 mutex_lock(&mbox->lock); 318 rss_ctx = rss->rss_ctx[ctx_id]; 319 /* Get memory to put this msg */ 320 for (idx = 0; idx < rss->rss_size; idx++) { 321 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 322 if (!aq) { 323 /* The shared memory buffer can be full. 324 * Flush it and retry 325 */ 326 err = otx2_sync_mbox_msg(mbox); 327 if (err) { 328 mutex_unlock(&mbox->lock); 329 return err; 330 } 331 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 332 if (!aq) { 333 mutex_unlock(&mbox->lock); 334 return -ENOMEM; 335 } 336 } 337 338 aq->rss.rq = rss_ctx->ind_tbl[idx]; 339 340 /* Fill AQ info */ 341 aq->qidx = index + idx; 342 aq->ctype = NIX_AQ_CTYPE_RSS; 343 aq->op = NIX_AQ_INSTOP_INIT; 344 } 345 err = otx2_sync_mbox_msg(mbox); 346 mutex_unlock(&mbox->lock); 347 return err; 348 } 349 350 void otx2_set_rss_key(struct otx2_nic *pfvf) 351 { 352 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 353 u64 *key = (u64 *)&rss->key[4]; 354 int idx; 355 356 /* 352bit or 44byte key needs to be configured as below 357 * NIX_LF_RX_SECRETX0 = key<351:288> 358 * NIX_LF_RX_SECRETX1 = key<287:224> 359 * NIX_LF_RX_SECRETX2 = key<223:160> 360 * NIX_LF_RX_SECRETX3 = key<159:96> 361 * NIX_LF_RX_SECRETX4 = key<95:32> 362 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 363 */ 364 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 365 (u64)(*((u32 *)&rss->key)) << 32); 366 idx = sizeof(rss->key) / sizeof(u64); 367 while (idx > 0) { 368 idx--; 369 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 370 } 371 } 372 373 int otx2_rss_init(struct otx2_nic *pfvf) 374 { 375 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 376 struct otx2_rss_ctx *rss_ctx; 377 int idx, ret = 0; 378 379 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 380 381 /* Init RSS key if it is not setup already */ 382 if (!rss->enable) 383 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 384 otx2_set_rss_key(pfvf); 385 386 if (!netif_is_rxfh_configured(pfvf->netdev)) { 387 /* Set RSS group 0 as default indirection table */ 388 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 389 GFP_KERNEL); 390 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 391 return -ENOMEM; 392 393 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 394 for (idx = 0; idx < rss->rss_size; idx++) 395 rss_ctx->ind_tbl[idx] = 396 ethtool_rxfh_indir_default(idx, 397 pfvf->hw.rx_queues); 398 } 399 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 400 if (ret) 401 return ret; 402 403 /* Flowkey or hash config to be used for generating flow tag */ 404 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 405 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 406 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 407 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 408 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 409 410 ret = otx2_set_flowkey_cfg(pfvf); 411 if (ret) 412 return ret; 413 414 rss->enable = true; 415 return 0; 416 } 417 418 /* Setup UDP segmentation algorithm in HW */ 419 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 420 { 421 struct nix_lso_format *field; 422 423 field = (struct nix_lso_format *)&lso->fields[0]; 424 lso->field_mask = GENMASK(18, 0); 425 426 /* IP's Length field */ 427 field->layer = NIX_TXLAYER_OL3; 428 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 429 field->offset = v4 ? 2 : 4; 430 field->sizem1 = 1; /* i.e 2 bytes */ 431 field->alg = NIX_LSOALG_ADD_PAYLEN; 432 field++; 433 434 /* No ID field in IPv6 header */ 435 if (v4) { 436 /* Increment IPID */ 437 field->layer = NIX_TXLAYER_OL3; 438 field->offset = 4; 439 field->sizem1 = 1; /* i.e 2 bytes */ 440 field->alg = NIX_LSOALG_ADD_SEGNUM; 441 field++; 442 } 443 444 /* Update length in UDP header */ 445 field->layer = NIX_TXLAYER_OL4; 446 field->offset = 4; 447 field->sizem1 = 1; 448 field->alg = NIX_LSOALG_ADD_PAYLEN; 449 } 450 451 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 452 void otx2_setup_segmentation(struct otx2_nic *pfvf) 453 { 454 struct nix_lso_format_cfg_rsp *rsp; 455 struct nix_lso_format_cfg *lso; 456 struct otx2_hw *hw = &pfvf->hw; 457 int err; 458 459 mutex_lock(&pfvf->mbox.lock); 460 461 /* UDPv4 segmentation */ 462 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 463 if (!lso) 464 goto fail; 465 466 /* Setup UDP/IP header fields that HW should update per segment */ 467 otx2_setup_udp_segmentation(lso, true); 468 469 err = otx2_sync_mbox_msg(&pfvf->mbox); 470 if (err) 471 goto fail; 472 473 rsp = (struct nix_lso_format_cfg_rsp *) 474 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 475 if (IS_ERR(rsp)) 476 goto fail; 477 478 hw->lso_udpv4_idx = rsp->lso_format_idx; 479 480 /* UDPv6 segmentation */ 481 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 482 if (!lso) 483 goto fail; 484 485 /* Setup UDP/IP header fields that HW should update per segment */ 486 otx2_setup_udp_segmentation(lso, false); 487 488 err = otx2_sync_mbox_msg(&pfvf->mbox); 489 if (err) 490 goto fail; 491 492 rsp = (struct nix_lso_format_cfg_rsp *) 493 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 494 if (IS_ERR(rsp)) 495 goto fail; 496 497 hw->lso_udpv6_idx = rsp->lso_format_idx; 498 mutex_unlock(&pfvf->mbox.lock); 499 return; 500 fail: 501 mutex_unlock(&pfvf->mbox.lock); 502 netdev_info(pfvf->netdev, 503 "Failed to get LSO index for UDP GSO offload, disabling\n"); 504 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 505 } 506 507 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 508 { 509 /* Configure CQE interrupt coalescing parameters 510 * 511 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 512 * set 1 less than cq_ecount_wait. And cq_time_wait is in 513 * usecs, convert that to 100ns count. 514 */ 515 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 516 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 517 ((u64)pfvf->hw.cq_qcount_wait << 32) | 518 (pfvf->hw.cq_ecount_wait - 1)); 519 } 520 521 static int otx2_alloc_pool_buf(struct otx2_nic *pfvf, struct otx2_pool *pool, 522 dma_addr_t *dma) 523 { 524 unsigned int offset = 0; 525 struct page *page; 526 size_t sz; 527 528 sz = SKB_DATA_ALIGN(pool->rbsize); 529 sz = ALIGN(sz, OTX2_ALIGN); 530 531 page = page_pool_alloc_frag(pool->page_pool, &offset, sz, GFP_ATOMIC); 532 if (unlikely(!page)) 533 return -ENOMEM; 534 535 *dma = page_pool_get_dma_addr(page) + offset; 536 return 0; 537 } 538 539 static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 540 dma_addr_t *dma) 541 { 542 u8 *buf; 543 544 if (pool->page_pool) 545 return otx2_alloc_pool_buf(pfvf, pool, dma); 546 547 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 548 if (unlikely(!buf)) 549 return -ENOMEM; 550 551 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 552 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 553 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 554 page_frag_free(buf); 555 return -ENOMEM; 556 } 557 558 return 0; 559 } 560 561 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 562 dma_addr_t *dma) 563 { 564 int ret; 565 566 local_bh_disable(); 567 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 568 local_bh_enable(); 569 return ret; 570 } 571 572 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 573 dma_addr_t *dma) 574 { 575 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) { 576 struct refill_work *work; 577 struct delayed_work *dwork; 578 579 work = &pfvf->refill_wrk[cq->cq_idx]; 580 dwork = &work->pool_refill_work; 581 /* Schedule a task if no other task is running */ 582 if (!cq->refill_task_sched) { 583 cq->refill_task_sched = true; 584 schedule_delayed_work(dwork, 585 msecs_to_jiffies(100)); 586 } 587 return -ENOMEM; 588 } 589 return 0; 590 } 591 592 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 593 { 594 struct otx2_nic *pfvf = netdev_priv(netdev); 595 596 schedule_work(&pfvf->reset_task); 597 } 598 EXPORT_SYMBOL(otx2_tx_timeout); 599 600 void otx2_get_mac_from_af(struct net_device *netdev) 601 { 602 struct otx2_nic *pfvf = netdev_priv(netdev); 603 int err; 604 605 err = otx2_hw_get_mac_addr(pfvf, netdev); 606 if (err) 607 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 608 609 /* If AF doesn't provide a valid MAC, generate a random one */ 610 if (!is_valid_ether_addr(netdev->dev_addr)) 611 eth_hw_addr_random(netdev); 612 } 613 EXPORT_SYMBOL(otx2_get_mac_from_af); 614 615 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc) 616 { 617 u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC]; 618 struct otx2_hw *hw = &pfvf->hw; 619 struct nix_txschq_config *req; 620 u64 schq, parent; 621 u64 dwrr_val; 622 623 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 624 625 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 626 if (!req) 627 return -ENOMEM; 628 629 req->lvl = lvl; 630 req->num_regs = 1; 631 632 schq_list = hw->txschq_list; 633 #ifdef CONFIG_DCB 634 if (txschq_for_pfc) 635 schq_list = pfvf->pfc_schq_list; 636 #endif 637 638 schq = schq_list[lvl][prio]; 639 /* Set topology e.t.c configuration */ 640 if (lvl == NIX_TXSCH_LVL_SMQ) { 641 req->reg[0] = NIX_AF_SMQX_CFG(schq); 642 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU; 643 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 644 (0x2ULL << 36); 645 req->num_regs++; 646 /* MDQ config */ 647 parent = schq_list[NIX_TXSCH_LVL_TL4][prio]; 648 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 649 req->regval[1] = parent << 16; 650 req->num_regs++; 651 /* Set DWRR quantum */ 652 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 653 req->regval[2] = dwrr_val; 654 } else if (lvl == NIX_TXSCH_LVL_TL4) { 655 parent = schq_list[NIX_TXSCH_LVL_TL3][prio]; 656 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 657 req->regval[0] = parent << 16; 658 req->num_regs++; 659 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 660 req->regval[1] = dwrr_val; 661 } else if (lvl == NIX_TXSCH_LVL_TL3) { 662 parent = schq_list[NIX_TXSCH_LVL_TL2][prio]; 663 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 664 req->regval[0] = parent << 16; 665 req->num_regs++; 666 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 667 req->regval[1] = dwrr_val; 668 if (lvl == hw->txschq_link_cfg_lvl) { 669 req->num_regs++; 670 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 671 /* Enable this queue and backpressure 672 * and set relative channel 673 */ 674 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 675 } 676 } else if (lvl == NIX_TXSCH_LVL_TL2) { 677 parent = schq_list[NIX_TXSCH_LVL_TL1][prio]; 678 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 679 req->regval[0] = parent << 16; 680 681 req->num_regs++; 682 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 683 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val; 684 685 if (lvl == hw->txschq_link_cfg_lvl) { 686 req->num_regs++; 687 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 688 /* Enable this queue and backpressure 689 * and set relative channel 690 */ 691 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 692 } 693 } else if (lvl == NIX_TXSCH_LVL_TL1) { 694 /* Default config for TL1. 695 * For VF this is always ignored. 696 */ 697 698 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 699 * clip it to 16384, so configuring a 24bit max value 700 * will work on both OTx2 and CN10K. 701 */ 702 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 703 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 704 705 req->num_regs++; 706 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 707 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 708 709 req->num_regs++; 710 req->reg[2] = NIX_AF_TL1X_CIR(schq); 711 req->regval[2] = 0; 712 } 713 714 return otx2_sync_mbox_msg(&pfvf->mbox); 715 } 716 EXPORT_SYMBOL(otx2_txschq_config); 717 718 int otx2_smq_flush(struct otx2_nic *pfvf, int smq) 719 { 720 struct nix_txschq_config *req; 721 int rc; 722 723 mutex_lock(&pfvf->mbox.lock); 724 725 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 726 if (!req) { 727 mutex_unlock(&pfvf->mbox.lock); 728 return -ENOMEM; 729 } 730 731 req->lvl = NIX_TXSCH_LVL_SMQ; 732 req->reg[0] = NIX_AF_SMQX_CFG(smq); 733 req->regval[0] |= BIT_ULL(49); 734 req->num_regs++; 735 736 rc = otx2_sync_mbox_msg(&pfvf->mbox); 737 mutex_unlock(&pfvf->mbox.lock); 738 return rc; 739 } 740 EXPORT_SYMBOL(otx2_smq_flush); 741 742 int otx2_txsch_alloc(struct otx2_nic *pfvf) 743 { 744 struct nix_txsch_alloc_req *req; 745 struct nix_txsch_alloc_rsp *rsp; 746 int lvl, schq, rc; 747 748 /* Get memory to put this msg */ 749 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 750 if (!req) 751 return -ENOMEM; 752 753 /* Request one schq per level */ 754 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 755 req->schq[lvl] = 1; 756 rc = otx2_sync_mbox_msg(&pfvf->mbox); 757 if (rc) 758 return rc; 759 760 rsp = (struct nix_txsch_alloc_rsp *) 761 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 762 if (IS_ERR(rsp)) 763 return PTR_ERR(rsp); 764 765 /* Setup transmit scheduler list */ 766 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 767 for (schq = 0; schq < rsp->schq[lvl]; schq++) 768 pfvf->hw.txschq_list[lvl][schq] = 769 rsp->schq_list[lvl][schq]; 770 771 pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl; 772 773 return 0; 774 } 775 776 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq) 777 { 778 struct nix_txsch_free_req *free_req; 779 int err; 780 781 mutex_lock(&pfvf->mbox.lock); 782 783 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 784 if (!free_req) { 785 mutex_unlock(&pfvf->mbox.lock); 786 netdev_err(pfvf->netdev, 787 "Failed alloc txschq free req\n"); 788 return; 789 } 790 791 free_req->schq_lvl = lvl; 792 free_req->schq = schq; 793 794 err = otx2_sync_mbox_msg(&pfvf->mbox); 795 if (err) { 796 netdev_err(pfvf->netdev, 797 "Failed stop txschq %d at level %d\n", schq, lvl); 798 } 799 800 mutex_unlock(&pfvf->mbox.lock); 801 } 802 803 void otx2_txschq_stop(struct otx2_nic *pfvf) 804 { 805 int lvl, schq; 806 807 /* free non QOS TLx nodes */ 808 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 809 otx2_txschq_free_one(pfvf, lvl, 810 pfvf->hw.txschq_list[lvl][0]); 811 812 /* Clear the txschq list */ 813 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 814 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 815 pfvf->hw.txschq_list[lvl][schq] = 0; 816 } 817 818 } 819 820 void otx2_sqb_flush(struct otx2_nic *pfvf) 821 { 822 int qidx, sqe_tail, sqe_head; 823 struct otx2_snd_queue *sq; 824 u64 incr, *ptr, val; 825 int timeout = 1000; 826 827 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 828 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 829 sq = &pfvf->qset.sq[qidx]; 830 if (!sq->sqb_ptrs) 831 continue; 832 833 incr = (u64)qidx << 32; 834 while (timeout) { 835 val = otx2_atomic64_add(incr, ptr); 836 sqe_head = (val >> 20) & 0x3F; 837 sqe_tail = (val >> 28) & 0x3F; 838 if (sqe_head == sqe_tail) 839 break; 840 usleep_range(1, 3); 841 timeout--; 842 } 843 } 844 } 845 846 /* RED and drop levels of CQ on packet reception. 847 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 848 */ 849 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 850 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 851 852 /* RED and drop levels of AURA for packet reception. 853 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 854 * Eg: For RQ length 1K, for pass/drop level 204/230. 855 * RED accepts pkts if free pointers > 102 & <= 205. 856 * Drops pkts if free pointers < 102. 857 */ 858 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 859 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 860 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 861 862 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 863 { 864 struct otx2_qset *qset = &pfvf->qset; 865 struct nix_aq_enq_req *aq; 866 867 /* Get memory to put this msg */ 868 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 869 if (!aq) 870 return -ENOMEM; 871 872 aq->rq.cq = qidx; 873 aq->rq.ena = 1; 874 aq->rq.pb_caching = 1; 875 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 876 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 877 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 878 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 879 aq->rq.qint_idx = 0; 880 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 881 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 882 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 883 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 884 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 885 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 886 887 /* Fill AQ info */ 888 aq->qidx = qidx; 889 aq->ctype = NIX_AQ_CTYPE_RQ; 890 aq->op = NIX_AQ_INSTOP_INIT; 891 892 return otx2_sync_mbox_msg(&pfvf->mbox); 893 } 894 895 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 896 { 897 struct otx2_nic *pfvf = dev; 898 struct otx2_snd_queue *sq; 899 struct nix_aq_enq_req *aq; 900 901 sq = &pfvf->qset.sq[qidx]; 902 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 903 /* Get memory to put this msg */ 904 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 905 if (!aq) 906 return -ENOMEM; 907 908 aq->sq.cq = pfvf->hw.rx_queues + qidx; 909 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 910 aq->sq.cq_ena = 1; 911 aq->sq.ena = 1; 912 aq->sq.smq = otx2_get_smq_idx(pfvf, qidx); 913 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 914 aq->sq.default_chan = pfvf->hw.tx_chan_base; 915 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 916 aq->sq.sqb_aura = sqb_aura; 917 aq->sq.sq_int_ena = NIX_SQINT_BITS; 918 aq->sq.qint_idx = 0; 919 /* Due pipelining impact minimum 2000 unused SQ CQE's 920 * need to maintain to avoid CQ overflow. 921 */ 922 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 923 924 /* Fill AQ info */ 925 aq->qidx = qidx; 926 aq->ctype = NIX_AQ_CTYPE_SQ; 927 aq->op = NIX_AQ_INSTOP_INIT; 928 929 return otx2_sync_mbox_msg(&pfvf->mbox); 930 } 931 932 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 933 { 934 struct otx2_qset *qset = &pfvf->qset; 935 struct otx2_snd_queue *sq; 936 struct otx2_pool *pool; 937 int err; 938 939 pool = &pfvf->qset.pool[sqb_aura]; 940 sq = &qset->sq[qidx]; 941 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 942 sq->sqe_cnt = qset->sqe_cnt; 943 944 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 945 if (err) 946 return err; 947 948 if (qidx < pfvf->hw.tx_queues) { 949 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 950 TSO_HEADER_SIZE); 951 if (err) 952 return err; 953 } 954 955 sq->sqe_base = sq->sqe->base; 956 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 957 if (!sq->sg) 958 return -ENOMEM; 959 960 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) { 961 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 962 sizeof(*sq->timestamps)); 963 if (err) 964 return err; 965 } 966 967 sq->head = 0; 968 sq->cons_head = 0; 969 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 970 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 971 /* Set SQE threshold to 10% of total SQEs */ 972 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 973 sq->aura_id = sqb_aura; 974 sq->aura_fc_addr = pool->fc_addr->base; 975 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 976 977 sq->stats.bytes = 0; 978 sq->stats.pkts = 0; 979 980 return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); 981 982 } 983 984 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 985 { 986 struct otx2_qset *qset = &pfvf->qset; 987 int err, pool_id, non_xdp_queues; 988 struct nix_aq_enq_req *aq; 989 struct otx2_cq_queue *cq; 990 991 cq = &qset->cq[qidx]; 992 cq->cq_idx = qidx; 993 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues; 994 if (qidx < pfvf->hw.rx_queues) { 995 cq->cq_type = CQ_RX; 996 cq->cint_idx = qidx; 997 cq->cqe_cnt = qset->rqe_cnt; 998 if (pfvf->xdp_prog) 999 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0); 1000 } else if (qidx < non_xdp_queues) { 1001 cq->cq_type = CQ_TX; 1002 cq->cint_idx = qidx - pfvf->hw.rx_queues; 1003 cq->cqe_cnt = qset->sqe_cnt; 1004 } else { 1005 if (pfvf->hw.xdp_queues && 1006 qidx < non_xdp_queues + pfvf->hw.xdp_queues) { 1007 cq->cq_type = CQ_XDP; 1008 cq->cint_idx = qidx - non_xdp_queues; 1009 cq->cqe_cnt = qset->sqe_cnt; 1010 } else { 1011 cq->cq_type = CQ_QOS; 1012 cq->cint_idx = qidx - non_xdp_queues - 1013 pfvf->hw.xdp_queues; 1014 cq->cqe_cnt = qset->sqe_cnt; 1015 } 1016 } 1017 cq->cqe_size = pfvf->qset.xqe_size; 1018 1019 /* Allocate memory for CQEs */ 1020 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 1021 if (err) 1022 return err; 1023 1024 /* Save CQE CPU base for faster reference */ 1025 cq->cqe_base = cq->cqe->base; 1026 /* In case where all RQs auras point to single pool, 1027 * all CQs receive buffer pool also point to same pool. 1028 */ 1029 pool_id = ((cq->cq_type == CQ_RX) && 1030 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 1031 cq->rbpool = &qset->pool[pool_id]; 1032 cq->refill_task_sched = false; 1033 1034 /* Get memory to put this msg */ 1035 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 1036 if (!aq) 1037 return -ENOMEM; 1038 1039 aq->cq.ena = 1; 1040 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 1041 aq->cq.caching = 1; 1042 aq->cq.base = cq->cqe->iova; 1043 aq->cq.cint_idx = cq->cint_idx; 1044 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 1045 aq->cq.qint_idx = 0; 1046 aq->cq.avg_level = 255; 1047 1048 if (qidx < pfvf->hw.rx_queues) { 1049 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 1050 aq->cq.drop_ena = 1; 1051 1052 if (!is_otx2_lbkvf(pfvf->pdev)) { 1053 /* Enable receive CQ backpressure */ 1054 aq->cq.bp_ena = 1; 1055 #ifdef CONFIG_DCB 1056 aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]]; 1057 #else 1058 aq->cq.bpid = pfvf->bpid[0]; 1059 #endif 1060 1061 /* Set backpressure level is same as cq pass level */ 1062 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 1063 } 1064 } 1065 1066 /* Fill AQ info */ 1067 aq->qidx = qidx; 1068 aq->ctype = NIX_AQ_CTYPE_CQ; 1069 aq->op = NIX_AQ_INSTOP_INIT; 1070 1071 return otx2_sync_mbox_msg(&pfvf->mbox); 1072 } 1073 1074 static void otx2_pool_refill_task(struct work_struct *work) 1075 { 1076 struct otx2_cq_queue *cq; 1077 struct otx2_pool *rbpool; 1078 struct refill_work *wrk; 1079 int qidx, free_ptrs = 0; 1080 struct otx2_nic *pfvf; 1081 dma_addr_t bufptr; 1082 1083 wrk = container_of(work, struct refill_work, pool_refill_work.work); 1084 pfvf = wrk->pf; 1085 qidx = wrk - pfvf->refill_wrk; 1086 cq = &pfvf->qset.cq[qidx]; 1087 rbpool = cq->rbpool; 1088 free_ptrs = cq->pool_ptrs; 1089 1090 while (cq->pool_ptrs) { 1091 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) { 1092 /* Schedule a WQ if we fails to free atleast half of the 1093 * pointers else enable napi for this RQ. 1094 */ 1095 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 1096 struct delayed_work *dwork; 1097 1098 dwork = &wrk->pool_refill_work; 1099 schedule_delayed_work(dwork, 1100 msecs_to_jiffies(100)); 1101 } else { 1102 cq->refill_task_sched = false; 1103 } 1104 return; 1105 } 1106 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 1107 cq->pool_ptrs--; 1108 } 1109 cq->refill_task_sched = false; 1110 } 1111 1112 int otx2_config_nix_queues(struct otx2_nic *pfvf) 1113 { 1114 int qidx, err; 1115 1116 /* Initialize RX queues */ 1117 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 1118 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 1119 1120 err = otx2_rq_init(pfvf, qidx, lpb_aura); 1121 if (err) 1122 return err; 1123 } 1124 1125 /* Initialize TX queues */ 1126 for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) { 1127 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1128 1129 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1130 if (err) 1131 return err; 1132 } 1133 1134 /* Initialize completion queues */ 1135 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1136 err = otx2_cq_init(pfvf, qidx); 1137 if (err) 1138 return err; 1139 } 1140 1141 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, 1142 NIX_LF_CQ_OP_STATUS); 1143 1144 /* Initialize work queue for receive buffer refill */ 1145 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1146 sizeof(struct refill_work), GFP_KERNEL); 1147 if (!pfvf->refill_wrk) 1148 return -ENOMEM; 1149 1150 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1151 pfvf->refill_wrk[qidx].pf = pfvf; 1152 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1153 otx2_pool_refill_task); 1154 } 1155 return 0; 1156 } 1157 1158 int otx2_config_nix(struct otx2_nic *pfvf) 1159 { 1160 struct nix_lf_alloc_req *nixlf; 1161 struct nix_lf_alloc_rsp *rsp; 1162 int err; 1163 1164 pfvf->qset.xqe_size = pfvf->hw.xqe_size; 1165 1166 /* Get memory to put this msg */ 1167 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1168 if (!nixlf) 1169 return -ENOMEM; 1170 1171 /* Set RQ/SQ/CQ counts */ 1172 nixlf->rq_cnt = pfvf->hw.rx_queues; 1173 nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf); 1174 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1175 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1176 nixlf->rss_grps = MAX_RSS_GROUPS; 1177 nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64; 1178 /* We don't know absolute NPA LF idx attached. 1179 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1180 * NPA LF attached to this RVU PF/VF. 1181 */ 1182 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1183 /* Disable alignment pad, enable L2 length check, 1184 * enable L4 TCP/UDP checksum verification. 1185 */ 1186 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1187 1188 err = otx2_sync_mbox_msg(&pfvf->mbox); 1189 if (err) 1190 return err; 1191 1192 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1193 &nixlf->hdr); 1194 if (IS_ERR(rsp)) 1195 return PTR_ERR(rsp); 1196 1197 if (rsp->qints < 1) 1198 return -ENXIO; 1199 1200 return rsp->hdr.rc; 1201 } 1202 1203 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1204 { 1205 struct otx2_qset *qset = &pfvf->qset; 1206 struct otx2_hw *hw = &pfvf->hw; 1207 struct otx2_snd_queue *sq; 1208 int sqb, qidx; 1209 u64 iova, pa; 1210 1211 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 1212 sq = &qset->sq[qidx]; 1213 if (!sq->sqb_ptrs) 1214 continue; 1215 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1216 if (!sq->sqb_ptrs[sqb]) 1217 continue; 1218 iova = sq->sqb_ptrs[sqb]; 1219 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1220 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1221 DMA_FROM_DEVICE, 1222 DMA_ATTR_SKIP_CPU_SYNC); 1223 put_page(virt_to_page(phys_to_virt(pa))); 1224 } 1225 sq->sqb_count = 0; 1226 } 1227 } 1228 1229 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1230 u64 iova, int size) 1231 { 1232 struct page *page; 1233 u64 pa; 1234 1235 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1236 page = virt_to_head_page(phys_to_virt(pa)); 1237 1238 if (pool->page_pool) { 1239 page_pool_put_full_page(pool->page_pool, page, true); 1240 } else { 1241 dma_unmap_page_attrs(pfvf->dev, iova, size, 1242 DMA_FROM_DEVICE, 1243 DMA_ATTR_SKIP_CPU_SYNC); 1244 1245 put_page(page); 1246 } 1247 } 1248 1249 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1250 { 1251 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1252 struct otx2_pool *pool; 1253 u64 iova; 1254 1255 if (type == AURA_NIX_SQ) { 1256 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1257 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1258 size = pfvf->hw.sqb_size; 1259 } 1260 if (type == AURA_NIX_RQ) { 1261 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1262 pool_end = pfvf->hw.rqpool_cnt; 1263 size = pfvf->rbsize; 1264 } 1265 1266 /* Free SQB and RQB pointers from the aura pool */ 1267 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1268 iova = otx2_aura_allocptr(pfvf, pool_id); 1269 pool = &pfvf->qset.pool[pool_id]; 1270 while (iova) { 1271 if (type == AURA_NIX_RQ) 1272 iova -= OTX2_HEAD_ROOM; 1273 1274 otx2_free_bufs(pfvf, pool, iova, size); 1275 1276 iova = otx2_aura_allocptr(pfvf, pool_id); 1277 } 1278 } 1279 } 1280 1281 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1282 { 1283 struct otx2_pool *pool; 1284 int pool_id; 1285 1286 if (!pfvf->qset.pool) 1287 return; 1288 1289 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1290 pool = &pfvf->qset.pool[pool_id]; 1291 qmem_free(pfvf->dev, pool->stack); 1292 qmem_free(pfvf->dev, pool->fc_addr); 1293 page_pool_destroy(pool->page_pool); 1294 pool->page_pool = NULL; 1295 } 1296 devm_kfree(pfvf->dev, pfvf->qset.pool); 1297 pfvf->qset.pool = NULL; 1298 } 1299 1300 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1301 int pool_id, int numptrs) 1302 { 1303 struct npa_aq_enq_req *aq; 1304 struct otx2_pool *pool; 1305 int err; 1306 1307 pool = &pfvf->qset.pool[pool_id]; 1308 1309 /* Allocate memory for HW to update Aura count. 1310 * Alloc one cache line, so that it fits all FC_STYPE modes. 1311 */ 1312 if (!pool->fc_addr) { 1313 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1314 if (err) 1315 return err; 1316 } 1317 1318 /* Initialize this aura's context via AF */ 1319 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1320 if (!aq) { 1321 /* Shared mbox memory buffer is full, flush it and retry */ 1322 err = otx2_sync_mbox_msg(&pfvf->mbox); 1323 if (err) 1324 return err; 1325 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1326 if (!aq) 1327 return -ENOMEM; 1328 } 1329 1330 aq->aura_id = aura_id; 1331 /* Will be filled by AF with correct pool context address */ 1332 aq->aura.pool_addr = pool_id; 1333 aq->aura.pool_caching = 1; 1334 aq->aura.shift = ilog2(numptrs) - 8; 1335 aq->aura.count = numptrs; 1336 aq->aura.limit = numptrs; 1337 aq->aura.avg_level = 255; 1338 aq->aura.ena = 1; 1339 aq->aura.fc_ena = 1; 1340 aq->aura.fc_addr = pool->fc_addr->iova; 1341 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1342 1343 /* Enable backpressure for RQ aura */ 1344 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1345 aq->aura.bp_ena = 0; 1346 /* If NIX1 LF is attached then specify NIX1_RX. 1347 * 1348 * Below NPA_AURA_S[BP_ENA] is set according to the 1349 * NPA_BPINTF_E enumeration given as: 1350 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1351 * NIX0_RX is 0x0 + 0*0x1 = 0 1352 * NIX1_RX is 0x0 + 1*0x1 = 1 1353 * But in HRM it is given that 1354 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1355 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1356 * enumerated by NPA_BPINTF_E." 1357 */ 1358 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1359 aq->aura.bp_ena = 1; 1360 #ifdef CONFIG_DCB 1361 aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]]; 1362 #else 1363 aq->aura.nix0_bpid = pfvf->bpid[0]; 1364 #endif 1365 1366 /* Set backpressure level for RQ's Aura */ 1367 aq->aura.bp = RQ_BP_LVL_AURA; 1368 } 1369 1370 /* Fill AQ info */ 1371 aq->ctype = NPA_AQ_CTYPE_AURA; 1372 aq->op = NPA_AQ_INSTOP_INIT; 1373 1374 return 0; 1375 } 1376 1377 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1378 int stack_pages, int numptrs, int buf_size, int type) 1379 { 1380 struct page_pool_params pp_params = { 0 }; 1381 struct npa_aq_enq_req *aq; 1382 struct otx2_pool *pool; 1383 int err; 1384 1385 pool = &pfvf->qset.pool[pool_id]; 1386 /* Alloc memory for stack which is used to store buffer pointers */ 1387 err = qmem_alloc(pfvf->dev, &pool->stack, 1388 stack_pages, pfvf->hw.stack_pg_bytes); 1389 if (err) 1390 return err; 1391 1392 pool->rbsize = buf_size; 1393 1394 /* Initialize this pool's context via AF */ 1395 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1396 if (!aq) { 1397 /* Shared mbox memory buffer is full, flush it and retry */ 1398 err = otx2_sync_mbox_msg(&pfvf->mbox); 1399 if (err) { 1400 qmem_free(pfvf->dev, pool->stack); 1401 return err; 1402 } 1403 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1404 if (!aq) { 1405 qmem_free(pfvf->dev, pool->stack); 1406 return -ENOMEM; 1407 } 1408 } 1409 1410 aq->aura_id = pool_id; 1411 aq->pool.stack_base = pool->stack->iova; 1412 aq->pool.stack_caching = 1; 1413 aq->pool.ena = 1; 1414 aq->pool.buf_size = buf_size / 128; 1415 aq->pool.stack_max_pages = stack_pages; 1416 aq->pool.shift = ilog2(numptrs) - 8; 1417 aq->pool.ptr_start = 0; 1418 aq->pool.ptr_end = ~0ULL; 1419 1420 /* Fill AQ info */ 1421 aq->ctype = NPA_AQ_CTYPE_POOL; 1422 aq->op = NPA_AQ_INSTOP_INIT; 1423 1424 if (type != AURA_NIX_RQ) { 1425 pool->page_pool = NULL; 1426 return 0; 1427 } 1428 1429 pp_params.flags = PP_FLAG_PAGE_FRAG | PP_FLAG_DMA_MAP; 1430 pp_params.pool_size = numptrs; 1431 pp_params.nid = NUMA_NO_NODE; 1432 pp_params.dev = pfvf->dev; 1433 pp_params.dma_dir = DMA_FROM_DEVICE; 1434 pool->page_pool = page_pool_create(&pp_params); 1435 if (IS_ERR(pool->page_pool)) { 1436 netdev_err(pfvf->netdev, "Creation of page pool failed\n"); 1437 return PTR_ERR(pool->page_pool); 1438 } 1439 1440 return 0; 1441 } 1442 1443 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1444 { 1445 int qidx, pool_id, stack_pages, num_sqbs; 1446 struct otx2_qset *qset = &pfvf->qset; 1447 struct otx2_hw *hw = &pfvf->hw; 1448 struct otx2_snd_queue *sq; 1449 struct otx2_pool *pool; 1450 dma_addr_t bufptr; 1451 int err, ptr; 1452 1453 /* Calculate number of SQBs needed. 1454 * 1455 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1456 * Last SQE is used for pointing to next SQB. 1457 */ 1458 num_sqbs = (hw->sqb_size / 128) - 1; 1459 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1460 1461 /* Get no of stack pages needed */ 1462 stack_pages = 1463 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1464 1465 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1466 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1467 /* Initialize aura context */ 1468 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1469 if (err) 1470 goto fail; 1471 1472 /* Initialize pool context */ 1473 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1474 num_sqbs, hw->sqb_size, AURA_NIX_SQ); 1475 if (err) 1476 goto fail; 1477 } 1478 1479 /* Flush accumulated messages */ 1480 err = otx2_sync_mbox_msg(&pfvf->mbox); 1481 if (err) 1482 goto fail; 1483 1484 /* Allocate pointers and free them to aura/pool */ 1485 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1486 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1487 pool = &pfvf->qset.pool[pool_id]; 1488 1489 sq = &qset->sq[qidx]; 1490 sq->sqb_count = 0; 1491 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1492 if (!sq->sqb_ptrs) { 1493 err = -ENOMEM; 1494 goto err_mem; 1495 } 1496 1497 for (ptr = 0; ptr < num_sqbs; ptr++) { 1498 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1499 if (err) 1500 goto err_mem; 1501 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1502 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1503 } 1504 } 1505 1506 err_mem: 1507 return err ? -ENOMEM : 0; 1508 1509 fail: 1510 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1511 otx2_aura_pool_free(pfvf); 1512 return err; 1513 } 1514 1515 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1516 { 1517 struct otx2_hw *hw = &pfvf->hw; 1518 int stack_pages, pool_id, rq; 1519 struct otx2_pool *pool; 1520 int err, ptr, num_ptrs; 1521 dma_addr_t bufptr; 1522 1523 num_ptrs = pfvf->qset.rqe_cnt; 1524 1525 stack_pages = 1526 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1527 1528 for (rq = 0; rq < hw->rx_queues; rq++) { 1529 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1530 /* Initialize aura context */ 1531 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1532 if (err) 1533 goto fail; 1534 } 1535 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1536 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1537 num_ptrs, pfvf->rbsize, AURA_NIX_RQ); 1538 if (err) 1539 goto fail; 1540 } 1541 1542 /* Flush accumulated messages */ 1543 err = otx2_sync_mbox_msg(&pfvf->mbox); 1544 if (err) 1545 goto fail; 1546 1547 /* Allocate pointers and free them to aura/pool */ 1548 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1549 pool = &pfvf->qset.pool[pool_id]; 1550 for (ptr = 0; ptr < num_ptrs; ptr++) { 1551 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1552 if (err) 1553 return -ENOMEM; 1554 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1555 bufptr + OTX2_HEAD_ROOM); 1556 } 1557 } 1558 return 0; 1559 fail: 1560 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1561 otx2_aura_pool_free(pfvf); 1562 return err; 1563 } 1564 1565 int otx2_config_npa(struct otx2_nic *pfvf) 1566 { 1567 struct otx2_qset *qset = &pfvf->qset; 1568 struct npa_lf_alloc_req *npalf; 1569 struct otx2_hw *hw = &pfvf->hw; 1570 int aura_cnt; 1571 1572 /* Pool - Stack of free buffer pointers 1573 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1574 */ 1575 1576 if (!hw->pool_cnt) 1577 return -EINVAL; 1578 1579 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1580 sizeof(struct otx2_pool), GFP_KERNEL); 1581 if (!qset->pool) 1582 return -ENOMEM; 1583 1584 /* Get memory to put this msg */ 1585 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1586 if (!npalf) 1587 return -ENOMEM; 1588 1589 /* Set aura and pool counts */ 1590 npalf->nr_pools = hw->pool_cnt; 1591 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1592 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1593 1594 return otx2_sync_mbox_msg(&pfvf->mbox); 1595 } 1596 1597 int otx2_detach_resources(struct mbox *mbox) 1598 { 1599 struct rsrc_detach *detach; 1600 1601 mutex_lock(&mbox->lock); 1602 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1603 if (!detach) { 1604 mutex_unlock(&mbox->lock); 1605 return -ENOMEM; 1606 } 1607 1608 /* detach all */ 1609 detach->partial = false; 1610 1611 /* Send detach request to AF */ 1612 otx2_mbox_msg_send(&mbox->mbox, 0); 1613 mutex_unlock(&mbox->lock); 1614 return 0; 1615 } 1616 EXPORT_SYMBOL(otx2_detach_resources); 1617 1618 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1619 { 1620 struct rsrc_attach *attach; 1621 struct msg_req *msix; 1622 int err; 1623 1624 mutex_lock(&pfvf->mbox.lock); 1625 /* Get memory to put this msg */ 1626 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1627 if (!attach) { 1628 mutex_unlock(&pfvf->mbox.lock); 1629 return -ENOMEM; 1630 } 1631 1632 attach->npalf = true; 1633 attach->nixlf = true; 1634 1635 /* Send attach request to AF */ 1636 err = otx2_sync_mbox_msg(&pfvf->mbox); 1637 if (err) { 1638 mutex_unlock(&pfvf->mbox.lock); 1639 return err; 1640 } 1641 1642 pfvf->nix_blkaddr = BLKADDR_NIX0; 1643 1644 /* If the platform has two NIX blocks then LF may be 1645 * allocated from NIX1. 1646 */ 1647 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1648 pfvf->nix_blkaddr = BLKADDR_NIX1; 1649 1650 /* Get NPA and NIX MSIX vector offsets */ 1651 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1652 if (!msix) { 1653 mutex_unlock(&pfvf->mbox.lock); 1654 return -ENOMEM; 1655 } 1656 1657 err = otx2_sync_mbox_msg(&pfvf->mbox); 1658 if (err) { 1659 mutex_unlock(&pfvf->mbox.lock); 1660 return err; 1661 } 1662 mutex_unlock(&pfvf->mbox.lock); 1663 1664 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1665 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1666 dev_err(pfvf->dev, 1667 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1668 return -EINVAL; 1669 } 1670 1671 return 0; 1672 } 1673 EXPORT_SYMBOL(otx2_attach_npa_nix); 1674 1675 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1676 { 1677 struct hwctx_disable_req *req; 1678 1679 mutex_lock(&mbox->lock); 1680 /* Request AQ to disable this context */ 1681 if (npa) 1682 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1683 else 1684 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1685 1686 if (!req) { 1687 mutex_unlock(&mbox->lock); 1688 return; 1689 } 1690 1691 req->ctype = type; 1692 1693 if (otx2_sync_mbox_msg(mbox)) 1694 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1695 __func__); 1696 1697 mutex_unlock(&mbox->lock); 1698 } 1699 1700 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1701 { 1702 struct nix_bp_cfg_req *req; 1703 1704 if (enable) 1705 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1706 else 1707 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1708 1709 if (!req) 1710 return -ENOMEM; 1711 1712 req->chan_base = 0; 1713 #ifdef CONFIG_DCB 1714 req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1; 1715 req->bpid_per_chan = pfvf->pfc_en ? 1 : 0; 1716 #else 1717 req->chan_cnt = 1; 1718 req->bpid_per_chan = 0; 1719 #endif 1720 1721 return otx2_sync_mbox_msg(&pfvf->mbox); 1722 } 1723 EXPORT_SYMBOL(otx2_nix_config_bp); 1724 1725 /* Mbox message handlers */ 1726 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1727 struct cgx_stats_rsp *rsp) 1728 { 1729 int id; 1730 1731 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1732 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1733 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1734 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1735 } 1736 1737 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1738 struct cgx_fec_stats_rsp *rsp) 1739 { 1740 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1741 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1742 } 1743 1744 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1745 struct npa_lf_alloc_rsp *rsp) 1746 { 1747 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1748 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1749 } 1750 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1751 1752 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1753 struct nix_lf_alloc_rsp *rsp) 1754 { 1755 pfvf->hw.sqb_size = rsp->sqb_size; 1756 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1757 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1758 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1759 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1760 pfvf->hw.cgx_links = rsp->cgx_links; 1761 pfvf->hw.lbk_links = rsp->lbk_links; 1762 pfvf->hw.tx_link = rsp->tx_link; 1763 } 1764 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1765 1766 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1767 struct msix_offset_rsp *rsp) 1768 { 1769 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1770 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1771 } 1772 EXPORT_SYMBOL(mbox_handler_msix_offset); 1773 1774 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1775 struct nix_bp_cfg_rsp *rsp) 1776 { 1777 int chan, chan_id; 1778 1779 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1780 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1781 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1782 } 1783 } 1784 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1785 1786 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1787 { 1788 struct otx2_qset *qset = &pfvf->qset; 1789 struct otx2_hw *hw = &pfvf->hw; 1790 int irq, qidx; 1791 1792 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1793 qidx < n; 1794 qidx++, irq++) { 1795 int vector = pci_irq_vector(pfvf->pdev, irq); 1796 1797 irq_set_affinity_hint(vector, NULL); 1798 free_cpumask_var(hw->affinity_mask[irq]); 1799 free_irq(vector, &qset->napi[qidx]); 1800 } 1801 } 1802 1803 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1804 { 1805 struct otx2_hw *hw = &pfvf->hw; 1806 int vec, cpu, irq, cint; 1807 1808 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1809 cpu = cpumask_first(cpu_online_mask); 1810 1811 /* CQ interrupts */ 1812 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1813 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1814 return; 1815 1816 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1817 1818 irq = pci_irq_vector(pfvf->pdev, vec); 1819 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1820 1821 cpu = cpumask_next(cpu, cpu_online_mask); 1822 if (unlikely(cpu >= nr_cpu_ids)) 1823 cpu = 0; 1824 } 1825 } 1826 1827 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1828 { 1829 struct nix_hw_info *rsp; 1830 struct msg_req *req; 1831 u16 max_mtu; 1832 int rc; 1833 1834 mutex_lock(&pfvf->mbox.lock); 1835 1836 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1837 if (!req) { 1838 rc = -ENOMEM; 1839 goto out; 1840 } 1841 1842 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1843 if (!rc) { 1844 rsp = (struct nix_hw_info *) 1845 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1846 1847 /* HW counts VLAN insertion bytes (8 for double tag) 1848 * irrespective of whether SQE is requesting to insert VLAN 1849 * in the packet or not. Hence these 8 bytes have to be 1850 * discounted from max packet size otherwise HW will throw 1851 * SMQ errors 1852 */ 1853 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1854 1855 /* Also save DWRR MTU, needed for DWRR weight calculation */ 1856 pfvf->hw.dwrr_mtu = rsp->rpm_dwrr_mtu; 1857 if (!pfvf->hw.dwrr_mtu) 1858 pfvf->hw.dwrr_mtu = 1; 1859 } 1860 1861 out: 1862 mutex_unlock(&pfvf->mbox.lock); 1863 if (rc) { 1864 dev_warn(pfvf->dev, 1865 "Failed to get MTU from hardware setting default value(1500)\n"); 1866 max_mtu = 1500; 1867 } 1868 return max_mtu; 1869 } 1870 EXPORT_SYMBOL(otx2_get_max_mtu); 1871 1872 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features) 1873 { 1874 netdev_features_t changed = features ^ netdev->features; 1875 struct otx2_nic *pfvf = netdev_priv(netdev); 1876 bool ntuple = !!(features & NETIF_F_NTUPLE); 1877 bool tc = !!(features & NETIF_F_HW_TC); 1878 1879 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1880 otx2_destroy_ntuple_flows(pfvf); 1881 1882 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1883 if (!pfvf->flow_cfg->max_flows) { 1884 netdev_err(netdev, 1885 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1886 return -EINVAL; 1887 } 1888 } 1889 1890 if ((changed & NETIF_F_HW_TC) && tc) { 1891 if (!pfvf->flow_cfg->max_flows) { 1892 netdev_err(netdev, 1893 "Can't enable TC, MCAM entries not allocated\n"); 1894 return -EINVAL; 1895 } 1896 } 1897 1898 if ((changed & NETIF_F_HW_TC) && !tc && 1899 pfvf->flow_cfg && pfvf->flow_cfg->nr_flows) { 1900 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1901 return -EBUSY; 1902 } 1903 1904 if ((changed & NETIF_F_NTUPLE) && ntuple && 1905 (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) { 1906 netdev_err(netdev, 1907 "Can't enable NTUPLE when TC is active, disable TC and retry\n"); 1908 return -EINVAL; 1909 } 1910 1911 if ((changed & NETIF_F_HW_TC) && tc && 1912 (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) { 1913 netdev_err(netdev, 1914 "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n"); 1915 return -EINVAL; 1916 } 1917 1918 return 0; 1919 } 1920 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features); 1921 1922 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1923 int __weak \ 1924 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1925 struct _req_type *req, \ 1926 struct _rsp_type *rsp) \ 1927 { \ 1928 /* Nothing to do here */ \ 1929 return 0; \ 1930 } \ 1931 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1932 MBOX_UP_CGX_MESSAGES 1933 MBOX_UP_MCS_MESSAGES 1934 #undef M 1935