1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <net/tso.h> 14 15 #include "otx2_reg.h" 16 #include "otx2_common.h" 17 #include "otx2_struct.h" 18 19 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 20 struct otx2_nic *pfvf, int qidx) 21 { 22 u64 incr = (u64)qidx << 32; 23 u64 *ptr; 24 25 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 26 stats->bytes = otx2_atomic64_add(incr, ptr); 27 28 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 29 stats->pkts = otx2_atomic64_add(incr, ptr); 30 } 31 32 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 33 struct otx2_nic *pfvf, int qidx) 34 { 35 u64 incr = (u64)qidx << 32; 36 u64 *ptr; 37 38 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 39 stats->bytes = otx2_atomic64_add(incr, ptr); 40 41 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 42 stats->pkts = otx2_atomic64_add(incr, ptr); 43 } 44 45 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 46 { 47 struct msg_req *req; 48 49 if (!netif_running(pfvf->netdev)) 50 return; 51 52 otx2_mbox_lock(&pfvf->mbox); 53 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 54 if (!req) { 55 otx2_mbox_unlock(&pfvf->mbox); 56 return; 57 } 58 59 otx2_sync_mbox_msg(&pfvf->mbox); 60 otx2_mbox_unlock(&pfvf->mbox); 61 } 62 63 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 64 { 65 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 66 67 if (!pfvf->qset.rq) 68 return 0; 69 70 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 71 return 1; 72 } 73 74 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 75 { 76 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 77 78 if (!pfvf->qset.sq) 79 return 0; 80 81 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 82 return 1; 83 } 84 85 void otx2_get_dev_stats(struct otx2_nic *pfvf) 86 { 87 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 88 89 #define OTX2_GET_RX_STATS(reg) \ 90 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 91 #define OTX2_GET_TX_STATS(reg) \ 92 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 93 94 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 95 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 96 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 97 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 98 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 99 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 100 dev_stats->rx_mcast_frames + 101 dev_stats->rx_ucast_frames; 102 103 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 104 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 105 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 106 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 107 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 108 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 109 dev_stats->tx_mcast_frames + 110 dev_stats->tx_ucast_frames; 111 } 112 113 void otx2_get_stats64(struct net_device *netdev, 114 struct rtnl_link_stats64 *stats) 115 { 116 struct otx2_nic *pfvf = netdev_priv(netdev); 117 struct otx2_dev_stats *dev_stats; 118 119 otx2_get_dev_stats(pfvf); 120 121 dev_stats = &pfvf->hw.dev_stats; 122 stats->rx_bytes = dev_stats->rx_bytes; 123 stats->rx_packets = dev_stats->rx_frames; 124 stats->rx_dropped = dev_stats->rx_drops; 125 stats->multicast = dev_stats->rx_mcast_frames; 126 127 stats->tx_bytes = dev_stats->tx_bytes; 128 stats->tx_packets = dev_stats->tx_frames; 129 stats->tx_dropped = dev_stats->tx_drops; 130 } 131 132 /* Sync MAC address with RVU AF */ 133 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 134 { 135 struct nix_set_mac_addr *req; 136 int err; 137 138 otx2_mbox_lock(&pfvf->mbox); 139 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 140 if (!req) { 141 otx2_mbox_unlock(&pfvf->mbox); 142 return -ENOMEM; 143 } 144 145 ether_addr_copy(req->mac_addr, mac); 146 147 err = otx2_sync_mbox_msg(&pfvf->mbox); 148 otx2_mbox_unlock(&pfvf->mbox); 149 return err; 150 } 151 152 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 153 struct net_device *netdev) 154 { 155 struct nix_get_mac_addr_rsp *rsp; 156 struct mbox_msghdr *msghdr; 157 struct msg_req *req; 158 int err; 159 160 otx2_mbox_lock(&pfvf->mbox); 161 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 162 if (!req) { 163 otx2_mbox_unlock(&pfvf->mbox); 164 return -ENOMEM; 165 } 166 167 err = otx2_sync_mbox_msg(&pfvf->mbox); 168 if (err) { 169 otx2_mbox_unlock(&pfvf->mbox); 170 return err; 171 } 172 173 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 174 if (IS_ERR(msghdr)) { 175 otx2_mbox_unlock(&pfvf->mbox); 176 return PTR_ERR(msghdr); 177 } 178 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 179 ether_addr_copy(netdev->dev_addr, rsp->mac_addr); 180 otx2_mbox_unlock(&pfvf->mbox); 181 182 return 0; 183 } 184 185 int otx2_set_mac_address(struct net_device *netdev, void *p) 186 { 187 struct otx2_nic *pfvf = netdev_priv(netdev); 188 struct sockaddr *addr = p; 189 190 if (!is_valid_ether_addr(addr->sa_data)) 191 return -EADDRNOTAVAIL; 192 193 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) 194 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 195 else 196 return -EPERM; 197 198 return 0; 199 } 200 201 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 202 { 203 struct nix_frs_cfg *req; 204 int err; 205 206 otx2_mbox_lock(&pfvf->mbox); 207 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 208 if (!req) { 209 otx2_mbox_unlock(&pfvf->mbox); 210 return -ENOMEM; 211 } 212 213 /* SMQ config limits maximum pkt size that can be transmitted */ 214 req->update_smq = true; 215 pfvf->max_frs = mtu + OTX2_ETH_HLEN; 216 req->maxlen = pfvf->max_frs; 217 218 err = otx2_sync_mbox_msg(&pfvf->mbox); 219 otx2_mbox_unlock(&pfvf->mbox); 220 return err; 221 } 222 223 int otx2_config_pause_frm(struct otx2_nic *pfvf) 224 { 225 struct cgx_pause_frm_cfg *req; 226 int err; 227 228 otx2_mbox_lock(&pfvf->mbox); 229 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 230 if (!req) 231 return -ENOMEM; 232 233 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 234 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 235 req->set = 1; 236 237 err = otx2_sync_mbox_msg(&pfvf->mbox); 238 otx2_mbox_unlock(&pfvf->mbox); 239 return err; 240 } 241 242 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 243 { 244 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 245 struct nix_rss_flowkey_cfg *req; 246 int err; 247 248 otx2_mbox_lock(&pfvf->mbox); 249 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 250 if (!req) { 251 otx2_mbox_unlock(&pfvf->mbox); 252 return -ENOMEM; 253 } 254 req->mcam_index = -1; /* Default or reserved index */ 255 req->flowkey_cfg = rss->flowkey_cfg; 256 req->group = DEFAULT_RSS_CONTEXT_GROUP; 257 258 err = otx2_sync_mbox_msg(&pfvf->mbox); 259 otx2_mbox_unlock(&pfvf->mbox); 260 return err; 261 } 262 263 int otx2_set_rss_table(struct otx2_nic *pfvf) 264 { 265 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 266 struct mbox *mbox = &pfvf->mbox; 267 struct nix_aq_enq_req *aq; 268 int idx, err; 269 270 otx2_mbox_lock(mbox); 271 /* Get memory to put this msg */ 272 for (idx = 0; idx < rss->rss_size; idx++) { 273 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 274 if (!aq) { 275 /* The shared memory buffer can be full. 276 * Flush it and retry 277 */ 278 err = otx2_sync_mbox_msg(mbox); 279 if (err) { 280 otx2_mbox_unlock(mbox); 281 return err; 282 } 283 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 284 if (!aq) { 285 otx2_mbox_unlock(mbox); 286 return -ENOMEM; 287 } 288 } 289 290 aq->rss.rq = rss->ind_tbl[idx]; 291 292 /* Fill AQ info */ 293 aq->qidx = idx; 294 aq->ctype = NIX_AQ_CTYPE_RSS; 295 aq->op = NIX_AQ_INSTOP_INIT; 296 } 297 err = otx2_sync_mbox_msg(mbox); 298 otx2_mbox_unlock(mbox); 299 return err; 300 } 301 302 void otx2_set_rss_key(struct otx2_nic *pfvf) 303 { 304 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 305 u64 *key = (u64 *)&rss->key[4]; 306 int idx; 307 308 /* 352bit or 44byte key needs to be configured as below 309 * NIX_LF_RX_SECRETX0 = key<351:288> 310 * NIX_LF_RX_SECRETX1 = key<287:224> 311 * NIX_LF_RX_SECRETX2 = key<223:160> 312 * NIX_LF_RX_SECRETX3 = key<159:96> 313 * NIX_LF_RX_SECRETX4 = key<95:32> 314 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 315 */ 316 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 317 (u64)(*((u32 *)&rss->key)) << 32); 318 idx = sizeof(rss->key) / sizeof(u64); 319 while (idx > 0) { 320 idx--; 321 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 322 } 323 } 324 325 int otx2_rss_init(struct otx2_nic *pfvf) 326 { 327 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 328 int idx, ret = 0; 329 330 rss->rss_size = sizeof(rss->ind_tbl); 331 332 /* Init RSS key if it is not setup already */ 333 if (!rss->enable) 334 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 335 otx2_set_rss_key(pfvf); 336 337 if (!netif_is_rxfh_configured(pfvf->netdev)) { 338 /* Default indirection table */ 339 for (idx = 0; idx < rss->rss_size; idx++) 340 rss->ind_tbl[idx] = 341 ethtool_rxfh_indir_default(idx, 342 pfvf->hw.rx_queues); 343 } 344 ret = otx2_set_rss_table(pfvf); 345 if (ret) 346 return ret; 347 348 /* Flowkey or hash config to be used for generating flow tag */ 349 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 350 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 351 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 352 NIX_FLOW_KEY_TYPE_SCTP; 353 354 ret = otx2_set_flowkey_cfg(pfvf); 355 if (ret) 356 return ret; 357 358 rss->enable = true; 359 return 0; 360 } 361 362 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 363 { 364 /* Configure CQE interrupt coalescing parameters 365 * 366 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 367 * set 1 less than cq_ecount_wait. And cq_time_wait is in 368 * usecs, convert that to 100ns count. 369 */ 370 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 371 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 372 ((u64)pfvf->hw.cq_qcount_wait << 32) | 373 (pfvf->hw.cq_ecount_wait - 1)); 374 } 375 376 dma_addr_t otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 377 gfp_t gfp) 378 { 379 dma_addr_t iova; 380 381 /* Check if request can be accommodated in previous allocated page */ 382 if (pool->page && ((pool->page_offset + pool->rbsize) <= 383 (PAGE_SIZE << pool->rbpage_order))) { 384 pool->pageref++; 385 goto ret; 386 } 387 388 otx2_get_page(pool); 389 390 /* Allocate a new page */ 391 pool->page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN, 392 pool->rbpage_order); 393 if (unlikely(!pool->page)) 394 return -ENOMEM; 395 396 pool->page_offset = 0; 397 ret: 398 iova = (u64)otx2_dma_map_page(pfvf, pool->page, pool->page_offset, 399 pool->rbsize, DMA_FROM_DEVICE); 400 if (!iova) { 401 if (!pool->page_offset) 402 __free_pages(pool->page, pool->rbpage_order); 403 pool->page = NULL; 404 return -ENOMEM; 405 } 406 pool->page_offset += pool->rbsize; 407 return iova; 408 } 409 410 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 411 { 412 struct otx2_nic *pfvf = netdev_priv(netdev); 413 414 schedule_work(&pfvf->reset_task); 415 } 416 417 void otx2_get_mac_from_af(struct net_device *netdev) 418 { 419 struct otx2_nic *pfvf = netdev_priv(netdev); 420 int err; 421 422 err = otx2_hw_get_mac_addr(pfvf, netdev); 423 if (err) 424 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 425 426 /* If AF doesn't provide a valid MAC, generate a random one */ 427 if (!is_valid_ether_addr(netdev->dev_addr)) 428 eth_hw_addr_random(netdev); 429 } 430 431 static int otx2_get_link(struct otx2_nic *pfvf) 432 { 433 int link = 0; 434 u16 map; 435 436 /* cgx lmac link */ 437 if (pfvf->hw.tx_chan_base >= CGX_CHAN_BASE) { 438 map = pfvf->hw.tx_chan_base & 0x7FF; 439 link = 4 * ((map >> 8) & 0xF) + ((map >> 4) & 0xF); 440 } 441 /* LBK channel */ 442 if (pfvf->hw.tx_chan_base < SDP_CHAN_BASE) 443 link = 12; 444 445 return link; 446 } 447 448 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl) 449 { 450 struct otx2_hw *hw = &pfvf->hw; 451 struct nix_txschq_config *req; 452 u64 schq, parent; 453 454 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 455 if (!req) 456 return -ENOMEM; 457 458 req->lvl = lvl; 459 req->num_regs = 1; 460 461 schq = hw->txschq_list[lvl][0]; 462 /* Set topology e.t.c configuration */ 463 if (lvl == NIX_TXSCH_LVL_SMQ) { 464 req->reg[0] = NIX_AF_SMQX_CFG(schq); 465 req->regval[0] = ((pfvf->netdev->mtu + OTX2_ETH_HLEN) << 8) | 466 OTX2_MIN_MTU; 467 468 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 469 (0x2ULL << 36); 470 req->num_regs++; 471 /* MDQ config */ 472 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0]; 473 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 474 req->regval[1] = parent << 16; 475 req->num_regs++; 476 /* Set DWRR quantum */ 477 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 478 req->regval[2] = DFLT_RR_QTM; 479 } else if (lvl == NIX_TXSCH_LVL_TL4) { 480 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0]; 481 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 482 req->regval[0] = parent << 16; 483 req->num_regs++; 484 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 485 req->regval[1] = DFLT_RR_QTM; 486 } else if (lvl == NIX_TXSCH_LVL_TL3) { 487 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0]; 488 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 489 req->regval[0] = parent << 16; 490 req->num_regs++; 491 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 492 req->regval[1] = DFLT_RR_QTM; 493 } else if (lvl == NIX_TXSCH_LVL_TL2) { 494 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0]; 495 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 496 req->regval[0] = parent << 16; 497 498 req->num_regs++; 499 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 500 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | DFLT_RR_QTM; 501 502 req->num_regs++; 503 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, 504 otx2_get_link(pfvf)); 505 /* Enable this queue and backpressure */ 506 req->regval[2] = BIT_ULL(13) | BIT_ULL(12); 507 508 } else if (lvl == NIX_TXSCH_LVL_TL1) { 509 /* Default config for TL1. 510 * For VF this is always ignored. 511 */ 512 513 /* Set DWRR quantum */ 514 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 515 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 516 517 req->num_regs++; 518 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 519 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 520 521 req->num_regs++; 522 req->reg[2] = NIX_AF_TL1X_CIR(schq); 523 req->regval[2] = 0; 524 } 525 526 return otx2_sync_mbox_msg(&pfvf->mbox); 527 } 528 529 int otx2_txsch_alloc(struct otx2_nic *pfvf) 530 { 531 struct nix_txsch_alloc_req *req; 532 int lvl; 533 534 /* Get memory to put this msg */ 535 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 536 if (!req) 537 return -ENOMEM; 538 539 /* Request one schq per level */ 540 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 541 req->schq[lvl] = 1; 542 543 return otx2_sync_mbox_msg(&pfvf->mbox); 544 } 545 546 int otx2_txschq_stop(struct otx2_nic *pfvf) 547 { 548 struct nix_txsch_free_req *free_req; 549 int lvl, schq, err; 550 551 otx2_mbox_lock(&pfvf->mbox); 552 /* Free the transmit schedulers */ 553 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 554 if (!free_req) { 555 otx2_mbox_unlock(&pfvf->mbox); 556 return -ENOMEM; 557 } 558 559 free_req->flags = TXSCHQ_FREE_ALL; 560 err = otx2_sync_mbox_msg(&pfvf->mbox); 561 otx2_mbox_unlock(&pfvf->mbox); 562 563 /* Clear the txschq list */ 564 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 565 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 566 pfvf->hw.txschq_list[lvl][schq] = 0; 567 } 568 return err; 569 } 570 571 void otx2_sqb_flush(struct otx2_nic *pfvf) 572 { 573 int qidx, sqe_tail, sqe_head; 574 u64 incr, *ptr, val; 575 576 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 577 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 578 incr = (u64)qidx << 32; 579 while (1) { 580 val = otx2_atomic64_add(incr, ptr); 581 sqe_head = (val >> 20) & 0x3F; 582 sqe_tail = (val >> 28) & 0x3F; 583 if (sqe_head == sqe_tail) 584 break; 585 usleep_range(1, 3); 586 } 587 } 588 } 589 590 /* RED and drop levels of CQ on packet reception. 591 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 592 */ 593 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 594 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 595 596 /* RED and drop levels of AURA for packet reception. 597 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 598 * Eg: For RQ length 1K, for pass/drop level 204/230. 599 * RED accepts pkts if free pointers > 102 & <= 205. 600 * Drops pkts if free pointers < 102. 601 */ 602 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 603 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 604 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 605 606 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 607 #define SEND_CQ_SKID 2000 608 609 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 610 { 611 struct otx2_qset *qset = &pfvf->qset; 612 struct nix_aq_enq_req *aq; 613 614 /* Get memory to put this msg */ 615 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 616 if (!aq) 617 return -ENOMEM; 618 619 aq->rq.cq = qidx; 620 aq->rq.ena = 1; 621 aq->rq.pb_caching = 1; 622 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 623 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 624 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 625 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 626 aq->rq.qint_idx = 0; 627 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 628 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 629 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 630 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 631 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 632 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 633 634 /* Fill AQ info */ 635 aq->qidx = qidx; 636 aq->ctype = NIX_AQ_CTYPE_RQ; 637 aq->op = NIX_AQ_INSTOP_INIT; 638 639 return otx2_sync_mbox_msg(&pfvf->mbox); 640 } 641 642 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 643 { 644 struct otx2_qset *qset = &pfvf->qset; 645 struct otx2_snd_queue *sq; 646 struct nix_aq_enq_req *aq; 647 struct otx2_pool *pool; 648 int err; 649 650 pool = &pfvf->qset.pool[sqb_aura]; 651 sq = &qset->sq[qidx]; 652 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 653 sq->sqe_cnt = qset->sqe_cnt; 654 655 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 656 if (err) 657 return err; 658 659 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 660 TSO_HEADER_SIZE); 661 if (err) 662 return err; 663 664 sq->sqe_base = sq->sqe->base; 665 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 666 if (!sq->sg) 667 return -ENOMEM; 668 669 sq->head = 0; 670 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 671 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 672 /* Set SQE threshold to 10% of total SQEs */ 673 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 674 sq->aura_id = sqb_aura; 675 sq->aura_fc_addr = pool->fc_addr->base; 676 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 677 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 678 679 sq->stats.bytes = 0; 680 sq->stats.pkts = 0; 681 682 /* Get memory to put this msg */ 683 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 684 if (!aq) 685 return -ENOMEM; 686 687 aq->sq.cq = pfvf->hw.rx_queues + qidx; 688 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 689 aq->sq.cq_ena = 1; 690 aq->sq.ena = 1; 691 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 692 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 693 aq->sq.smq_rr_quantum = DFLT_RR_QTM; 694 aq->sq.default_chan = pfvf->hw.tx_chan_base; 695 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 696 aq->sq.sqb_aura = sqb_aura; 697 aq->sq.sq_int_ena = NIX_SQINT_BITS; 698 aq->sq.qint_idx = 0; 699 /* Due pipelining impact minimum 2000 unused SQ CQE's 700 * need to maintain to avoid CQ overflow. 701 */ 702 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (sq->sqe_cnt)); 703 704 /* Fill AQ info */ 705 aq->qidx = qidx; 706 aq->ctype = NIX_AQ_CTYPE_SQ; 707 aq->op = NIX_AQ_INSTOP_INIT; 708 709 return otx2_sync_mbox_msg(&pfvf->mbox); 710 } 711 712 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 713 { 714 struct otx2_qset *qset = &pfvf->qset; 715 struct nix_aq_enq_req *aq; 716 struct otx2_cq_queue *cq; 717 int err, pool_id; 718 719 cq = &qset->cq[qidx]; 720 cq->cq_idx = qidx; 721 if (qidx < pfvf->hw.rx_queues) { 722 cq->cq_type = CQ_RX; 723 cq->cint_idx = qidx; 724 cq->cqe_cnt = qset->rqe_cnt; 725 } else { 726 cq->cq_type = CQ_TX; 727 cq->cint_idx = qidx - pfvf->hw.rx_queues; 728 cq->cqe_cnt = qset->sqe_cnt; 729 } 730 cq->cqe_size = pfvf->qset.xqe_size; 731 732 /* Allocate memory for CQEs */ 733 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 734 if (err) 735 return err; 736 737 /* Save CQE CPU base for faster reference */ 738 cq->cqe_base = cq->cqe->base; 739 /* In case where all RQs auras point to single pool, 740 * all CQs receive buffer pool also point to same pool. 741 */ 742 pool_id = ((cq->cq_type == CQ_RX) && 743 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 744 cq->rbpool = &qset->pool[pool_id]; 745 cq->refill_task_sched = false; 746 747 /* Get memory to put this msg */ 748 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 749 if (!aq) 750 return -ENOMEM; 751 752 aq->cq.ena = 1; 753 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 754 aq->cq.caching = 1; 755 aq->cq.base = cq->cqe->iova; 756 aq->cq.cint_idx = cq->cint_idx; 757 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 758 aq->cq.qint_idx = 0; 759 aq->cq.avg_level = 255; 760 761 if (qidx < pfvf->hw.rx_queues) { 762 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 763 aq->cq.drop_ena = 1; 764 765 /* Enable receive CQ backpressure */ 766 aq->cq.bp_ena = 1; 767 aq->cq.bpid = pfvf->bpid[0]; 768 769 /* Set backpressure level is same as cq pass level */ 770 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 771 } 772 773 /* Fill AQ info */ 774 aq->qidx = qidx; 775 aq->ctype = NIX_AQ_CTYPE_CQ; 776 aq->op = NIX_AQ_INSTOP_INIT; 777 778 return otx2_sync_mbox_msg(&pfvf->mbox); 779 } 780 781 static void otx2_pool_refill_task(struct work_struct *work) 782 { 783 struct otx2_cq_queue *cq; 784 struct otx2_pool *rbpool; 785 struct refill_work *wrk; 786 int qidx, free_ptrs = 0; 787 struct otx2_nic *pfvf; 788 s64 bufptr; 789 790 wrk = container_of(work, struct refill_work, pool_refill_work.work); 791 pfvf = wrk->pf; 792 qidx = wrk - pfvf->refill_wrk; 793 cq = &pfvf->qset.cq[qidx]; 794 rbpool = cq->rbpool; 795 free_ptrs = cq->pool_ptrs; 796 797 while (cq->pool_ptrs) { 798 bufptr = otx2_alloc_rbuf(pfvf, rbpool, GFP_KERNEL); 799 if (bufptr <= 0) { 800 /* Schedule a WQ if we fails to free atleast half of the 801 * pointers else enable napi for this RQ. 802 */ 803 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 804 struct delayed_work *dwork; 805 806 dwork = &wrk->pool_refill_work; 807 schedule_delayed_work(dwork, 808 msecs_to_jiffies(100)); 809 } else { 810 cq->refill_task_sched = false; 811 } 812 return; 813 } 814 otx2_aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 815 cq->pool_ptrs--; 816 } 817 cq->refill_task_sched = false; 818 } 819 820 int otx2_config_nix_queues(struct otx2_nic *pfvf) 821 { 822 int qidx, err; 823 824 /* Initialize RX queues */ 825 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 826 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 827 828 err = otx2_rq_init(pfvf, qidx, lpb_aura); 829 if (err) 830 return err; 831 } 832 833 /* Initialize TX queues */ 834 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 835 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 836 837 err = otx2_sq_init(pfvf, qidx, sqb_aura); 838 if (err) 839 return err; 840 } 841 842 /* Initialize completion queues */ 843 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 844 err = otx2_cq_init(pfvf, qidx); 845 if (err) 846 return err; 847 } 848 849 /* Initialize work queue for receive buffer refill */ 850 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 851 sizeof(struct refill_work), GFP_KERNEL); 852 if (!pfvf->refill_wrk) 853 return -ENOMEM; 854 855 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 856 pfvf->refill_wrk[qidx].pf = pfvf; 857 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 858 otx2_pool_refill_task); 859 } 860 return 0; 861 } 862 863 int otx2_config_nix(struct otx2_nic *pfvf) 864 { 865 struct nix_lf_alloc_req *nixlf; 866 struct nix_lf_alloc_rsp *rsp; 867 int err; 868 869 pfvf->qset.xqe_size = NIX_XQESZ_W16 ? 128 : 512; 870 871 /* Get memory to put this msg */ 872 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 873 if (!nixlf) 874 return -ENOMEM; 875 876 /* Set RQ/SQ/CQ counts */ 877 nixlf->rq_cnt = pfvf->hw.rx_queues; 878 nixlf->sq_cnt = pfvf->hw.tx_queues; 879 nixlf->cq_cnt = pfvf->qset.cq_cnt; 880 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 881 nixlf->rss_grps = 1; /* Single RSS indir table supported, for now */ 882 nixlf->xqe_sz = NIX_XQESZ_W16; 883 /* We don't know absolute NPA LF idx attached. 884 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 885 * NPA LF attached to this RVU PF/VF. 886 */ 887 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 888 /* Disable alignment pad, enable L2 length check, 889 * enable L4 TCP/UDP checksum verification. 890 */ 891 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 892 893 err = otx2_sync_mbox_msg(&pfvf->mbox); 894 if (err) 895 return err; 896 897 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 898 &nixlf->hdr); 899 if (IS_ERR(rsp)) 900 return PTR_ERR(rsp); 901 902 if (rsp->qints < 1) 903 return -ENXIO; 904 905 return rsp->hdr.rc; 906 } 907 908 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 909 { 910 struct otx2_qset *qset = &pfvf->qset; 911 struct otx2_hw *hw = &pfvf->hw; 912 struct otx2_snd_queue *sq; 913 int sqb, qidx; 914 u64 iova, pa; 915 916 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 917 sq = &qset->sq[qidx]; 918 if (!sq->sqb_ptrs) 919 continue; 920 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 921 if (!sq->sqb_ptrs[sqb]) 922 continue; 923 iova = sq->sqb_ptrs[sqb]; 924 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 925 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 926 DMA_FROM_DEVICE, 927 DMA_ATTR_SKIP_CPU_SYNC); 928 put_page(virt_to_page(phys_to_virt(pa))); 929 } 930 sq->sqb_count = 0; 931 } 932 } 933 934 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 935 { 936 int pool_id, pool_start = 0, pool_end = 0, size = 0; 937 u64 iova, pa; 938 939 if (type == AURA_NIX_SQ) { 940 pool_start = otx2_get_pool_idx(pfvf, type, 0); 941 pool_end = pool_start + pfvf->hw.sqpool_cnt; 942 size = pfvf->hw.sqb_size; 943 } 944 if (type == AURA_NIX_RQ) { 945 pool_start = otx2_get_pool_idx(pfvf, type, 0); 946 pool_end = pfvf->hw.rqpool_cnt; 947 size = pfvf->rbsize; 948 } 949 950 /* Free SQB and RQB pointers from the aura pool */ 951 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 952 iova = otx2_aura_allocptr(pfvf, pool_id); 953 while (iova) { 954 if (type == AURA_NIX_RQ) 955 iova -= OTX2_HEAD_ROOM; 956 957 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 958 dma_unmap_page_attrs(pfvf->dev, iova, size, 959 DMA_FROM_DEVICE, 960 DMA_ATTR_SKIP_CPU_SYNC); 961 put_page(virt_to_page(phys_to_virt(pa))); 962 iova = otx2_aura_allocptr(pfvf, pool_id); 963 } 964 } 965 } 966 967 void otx2_aura_pool_free(struct otx2_nic *pfvf) 968 { 969 struct otx2_pool *pool; 970 int pool_id; 971 972 if (!pfvf->qset.pool) 973 return; 974 975 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 976 pool = &pfvf->qset.pool[pool_id]; 977 qmem_free(pfvf->dev, pool->stack); 978 qmem_free(pfvf->dev, pool->fc_addr); 979 } 980 devm_kfree(pfvf->dev, pfvf->qset.pool); 981 } 982 983 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 984 int pool_id, int numptrs) 985 { 986 struct npa_aq_enq_req *aq; 987 struct otx2_pool *pool; 988 int err; 989 990 pool = &pfvf->qset.pool[pool_id]; 991 992 /* Allocate memory for HW to update Aura count. 993 * Alloc one cache line, so that it fits all FC_STYPE modes. 994 */ 995 if (!pool->fc_addr) { 996 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 997 if (err) 998 return err; 999 } 1000 1001 /* Initialize this aura's context via AF */ 1002 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1003 if (!aq) { 1004 /* Shared mbox memory buffer is full, flush it and retry */ 1005 err = otx2_sync_mbox_msg(&pfvf->mbox); 1006 if (err) 1007 return err; 1008 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1009 if (!aq) 1010 return -ENOMEM; 1011 } 1012 1013 aq->aura_id = aura_id; 1014 /* Will be filled by AF with correct pool context address */ 1015 aq->aura.pool_addr = pool_id; 1016 aq->aura.pool_caching = 1; 1017 aq->aura.shift = ilog2(numptrs) - 8; 1018 aq->aura.count = numptrs; 1019 aq->aura.limit = numptrs; 1020 aq->aura.avg_level = 255; 1021 aq->aura.ena = 1; 1022 aq->aura.fc_ena = 1; 1023 aq->aura.fc_addr = pool->fc_addr->iova; 1024 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1025 1026 /* Enable backpressure for RQ aura */ 1027 if (aura_id < pfvf->hw.rqpool_cnt) { 1028 aq->aura.bp_ena = 0; 1029 aq->aura.nix0_bpid = pfvf->bpid[0]; 1030 /* Set backpressure level for RQ's Aura */ 1031 aq->aura.bp = RQ_BP_LVL_AURA; 1032 } 1033 1034 /* Fill AQ info */ 1035 aq->ctype = NPA_AQ_CTYPE_AURA; 1036 aq->op = NPA_AQ_INSTOP_INIT; 1037 1038 return 0; 1039 } 1040 1041 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1042 int stack_pages, int numptrs, int buf_size) 1043 { 1044 struct npa_aq_enq_req *aq; 1045 struct otx2_pool *pool; 1046 int err; 1047 1048 pool = &pfvf->qset.pool[pool_id]; 1049 /* Alloc memory for stack which is used to store buffer pointers */ 1050 err = qmem_alloc(pfvf->dev, &pool->stack, 1051 stack_pages, pfvf->hw.stack_pg_bytes); 1052 if (err) 1053 return err; 1054 1055 pool->rbsize = buf_size; 1056 pool->rbpage_order = get_order(buf_size); 1057 1058 /* Initialize this pool's context via AF */ 1059 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1060 if (!aq) { 1061 /* Shared mbox memory buffer is full, flush it and retry */ 1062 err = otx2_sync_mbox_msg(&pfvf->mbox); 1063 if (err) { 1064 qmem_free(pfvf->dev, pool->stack); 1065 return err; 1066 } 1067 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1068 if (!aq) { 1069 qmem_free(pfvf->dev, pool->stack); 1070 return -ENOMEM; 1071 } 1072 } 1073 1074 aq->aura_id = pool_id; 1075 aq->pool.stack_base = pool->stack->iova; 1076 aq->pool.stack_caching = 1; 1077 aq->pool.ena = 1; 1078 aq->pool.buf_size = buf_size / 128; 1079 aq->pool.stack_max_pages = stack_pages; 1080 aq->pool.shift = ilog2(numptrs) - 8; 1081 aq->pool.ptr_start = 0; 1082 aq->pool.ptr_end = ~0ULL; 1083 1084 /* Fill AQ info */ 1085 aq->ctype = NPA_AQ_CTYPE_POOL; 1086 aq->op = NPA_AQ_INSTOP_INIT; 1087 1088 return 0; 1089 } 1090 1091 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1092 { 1093 int qidx, pool_id, stack_pages, num_sqbs; 1094 struct otx2_qset *qset = &pfvf->qset; 1095 struct otx2_hw *hw = &pfvf->hw; 1096 struct otx2_snd_queue *sq; 1097 struct otx2_pool *pool; 1098 int err, ptr; 1099 s64 bufptr; 1100 1101 /* Calculate number of SQBs needed. 1102 * 1103 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1104 * Last SQE is used for pointing to next SQB. 1105 */ 1106 num_sqbs = (hw->sqb_size / 128) - 1; 1107 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1108 1109 /* Get no of stack pages needed */ 1110 stack_pages = 1111 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1112 1113 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1114 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1115 /* Initialize aura context */ 1116 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1117 if (err) 1118 goto fail; 1119 1120 /* Initialize pool context */ 1121 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1122 num_sqbs, hw->sqb_size); 1123 if (err) 1124 goto fail; 1125 } 1126 1127 /* Flush accumulated messages */ 1128 err = otx2_sync_mbox_msg(&pfvf->mbox); 1129 if (err) 1130 goto fail; 1131 1132 /* Allocate pointers and free them to aura/pool */ 1133 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1134 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1135 pool = &pfvf->qset.pool[pool_id]; 1136 1137 sq = &qset->sq[qidx]; 1138 sq->sqb_count = 0; 1139 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(u64 *), GFP_KERNEL); 1140 if (!sq->sqb_ptrs) 1141 return -ENOMEM; 1142 1143 for (ptr = 0; ptr < num_sqbs; ptr++) { 1144 bufptr = otx2_alloc_rbuf(pfvf, pool, GFP_KERNEL); 1145 if (bufptr <= 0) 1146 return bufptr; 1147 otx2_aura_freeptr(pfvf, pool_id, bufptr); 1148 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1149 } 1150 otx2_get_page(pool); 1151 } 1152 1153 return 0; 1154 fail: 1155 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1156 otx2_aura_pool_free(pfvf); 1157 return err; 1158 } 1159 1160 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1161 { 1162 struct otx2_hw *hw = &pfvf->hw; 1163 int stack_pages, pool_id, rq; 1164 struct otx2_pool *pool; 1165 int err, ptr, num_ptrs; 1166 s64 bufptr; 1167 1168 num_ptrs = pfvf->qset.rqe_cnt; 1169 1170 stack_pages = 1171 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1172 1173 for (rq = 0; rq < hw->rx_queues; rq++) { 1174 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1175 /* Initialize aura context */ 1176 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1177 if (err) 1178 goto fail; 1179 } 1180 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1181 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1182 num_ptrs, pfvf->rbsize); 1183 if (err) 1184 goto fail; 1185 } 1186 1187 /* Flush accumulated messages */ 1188 err = otx2_sync_mbox_msg(&pfvf->mbox); 1189 if (err) 1190 goto fail; 1191 1192 /* Allocate pointers and free them to aura/pool */ 1193 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1194 pool = &pfvf->qset.pool[pool_id]; 1195 for (ptr = 0; ptr < num_ptrs; ptr++) { 1196 bufptr = otx2_alloc_rbuf(pfvf, pool, GFP_KERNEL); 1197 if (bufptr <= 0) 1198 return bufptr; 1199 otx2_aura_freeptr(pfvf, pool_id, 1200 bufptr + OTX2_HEAD_ROOM); 1201 } 1202 otx2_get_page(pool); 1203 } 1204 1205 return 0; 1206 fail: 1207 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1208 otx2_aura_pool_free(pfvf); 1209 return err; 1210 } 1211 1212 int otx2_config_npa(struct otx2_nic *pfvf) 1213 { 1214 struct otx2_qset *qset = &pfvf->qset; 1215 struct npa_lf_alloc_req *npalf; 1216 struct otx2_hw *hw = &pfvf->hw; 1217 int aura_cnt; 1218 1219 /* Pool - Stack of free buffer pointers 1220 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1221 */ 1222 1223 if (!hw->pool_cnt) 1224 return -EINVAL; 1225 1226 qset->pool = devm_kzalloc(pfvf->dev, sizeof(struct otx2_pool) * 1227 hw->pool_cnt, GFP_KERNEL); 1228 if (!qset->pool) 1229 return -ENOMEM; 1230 1231 /* Get memory to put this msg */ 1232 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1233 if (!npalf) 1234 return -ENOMEM; 1235 1236 /* Set aura and pool counts */ 1237 npalf->nr_pools = hw->pool_cnt; 1238 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1239 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1240 1241 return otx2_sync_mbox_msg(&pfvf->mbox); 1242 } 1243 1244 int otx2_detach_resources(struct mbox *mbox) 1245 { 1246 struct rsrc_detach *detach; 1247 1248 otx2_mbox_lock(mbox); 1249 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1250 if (!detach) { 1251 otx2_mbox_unlock(mbox); 1252 return -ENOMEM; 1253 } 1254 1255 /* detach all */ 1256 detach->partial = false; 1257 1258 /* Send detach request to AF */ 1259 otx2_mbox_msg_send(&mbox->mbox, 0); 1260 otx2_mbox_unlock(mbox); 1261 return 0; 1262 } 1263 1264 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1265 { 1266 struct rsrc_attach *attach; 1267 struct msg_req *msix; 1268 int err; 1269 1270 otx2_mbox_lock(&pfvf->mbox); 1271 /* Get memory to put this msg */ 1272 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1273 if (!attach) { 1274 otx2_mbox_unlock(&pfvf->mbox); 1275 return -ENOMEM; 1276 } 1277 1278 attach->npalf = true; 1279 attach->nixlf = true; 1280 1281 /* Send attach request to AF */ 1282 err = otx2_sync_mbox_msg(&pfvf->mbox); 1283 if (err) { 1284 otx2_mbox_unlock(&pfvf->mbox); 1285 return err; 1286 } 1287 1288 pfvf->nix_blkaddr = BLKADDR_NIX0; 1289 1290 /* If the platform has two NIX blocks then LF may be 1291 * allocated from NIX1. 1292 */ 1293 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1294 pfvf->nix_blkaddr = BLKADDR_NIX1; 1295 1296 /* Get NPA and NIX MSIX vector offsets */ 1297 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1298 if (!msix) { 1299 otx2_mbox_unlock(&pfvf->mbox); 1300 return -ENOMEM; 1301 } 1302 1303 err = otx2_sync_mbox_msg(&pfvf->mbox); 1304 if (err) { 1305 otx2_mbox_unlock(&pfvf->mbox); 1306 return err; 1307 } 1308 otx2_mbox_unlock(&pfvf->mbox); 1309 1310 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1311 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1312 dev_err(pfvf->dev, 1313 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1314 return -EINVAL; 1315 } 1316 1317 return 0; 1318 } 1319 1320 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1321 { 1322 struct hwctx_disable_req *req; 1323 1324 otx2_mbox_lock(mbox); 1325 /* Request AQ to disable this context */ 1326 if (npa) 1327 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1328 else 1329 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1330 1331 if (!req) { 1332 otx2_mbox_unlock(mbox); 1333 return; 1334 } 1335 1336 req->ctype = type; 1337 1338 if (otx2_sync_mbox_msg(mbox)) 1339 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1340 __func__); 1341 1342 otx2_mbox_unlock(mbox); 1343 } 1344 1345 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1346 { 1347 struct nix_bp_cfg_req *req; 1348 1349 if (enable) 1350 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1351 else 1352 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1353 1354 if (!req) 1355 return -ENOMEM; 1356 1357 req->chan_base = 0; 1358 req->chan_cnt = 1; 1359 req->bpid_per_chan = 0; 1360 1361 return otx2_sync_mbox_msg(&pfvf->mbox); 1362 } 1363 1364 /* Mbox message handlers */ 1365 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1366 struct cgx_stats_rsp *rsp) 1367 { 1368 int id; 1369 1370 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1371 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1372 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1373 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1374 } 1375 1376 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1377 struct nix_txsch_alloc_rsp *rsp) 1378 { 1379 int lvl, schq; 1380 1381 /* Setup transmit scheduler list */ 1382 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 1383 for (schq = 0; schq < rsp->schq[lvl]; schq++) 1384 pf->hw.txschq_list[lvl][schq] = 1385 rsp->schq_list[lvl][schq]; 1386 } 1387 1388 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1389 struct npa_lf_alloc_rsp *rsp) 1390 { 1391 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1392 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1393 } 1394 1395 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1396 struct nix_lf_alloc_rsp *rsp) 1397 { 1398 pfvf->hw.sqb_size = rsp->sqb_size; 1399 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1400 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1401 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1402 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1403 } 1404 1405 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1406 struct msix_offset_rsp *rsp) 1407 { 1408 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1409 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1410 } 1411 1412 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1413 struct nix_bp_cfg_rsp *rsp) 1414 { 1415 int chan, chan_id; 1416 1417 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1418 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1419 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1420 } 1421 } 1422 1423 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1424 { 1425 struct otx2_qset *qset = &pfvf->qset; 1426 struct otx2_hw *hw = &pfvf->hw; 1427 int irq, qidx; 1428 1429 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1430 qidx < n; 1431 qidx++, irq++) { 1432 int vector = pci_irq_vector(pfvf->pdev, irq); 1433 1434 irq_set_affinity_hint(vector, NULL); 1435 free_cpumask_var(hw->affinity_mask[irq]); 1436 free_irq(vector, &qset->napi[qidx]); 1437 } 1438 } 1439 1440 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1441 { 1442 struct otx2_hw *hw = &pfvf->hw; 1443 int vec, cpu, irq, cint; 1444 1445 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1446 cpu = cpumask_first(cpu_online_mask); 1447 1448 /* CQ interrupts */ 1449 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1450 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1451 return; 1452 1453 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1454 1455 irq = pci_irq_vector(pfvf->pdev, vec); 1456 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1457 1458 cpu = cpumask_next(cpu, cpu_online_mask); 1459 if (unlikely(cpu >= nr_cpu_ids)) 1460 cpu = 0; 1461 } 1462 } 1463 1464 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1465 int __weak \ 1466 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1467 struct _req_type *req, \ 1468 struct _rsp_type *rsp) \ 1469 { \ 1470 /* Nothing to do here */ \ 1471 return 0; \ 1472 } \ 1473 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1474 MBOX_UP_CGX_MESSAGES 1475 #undef M 1476