1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <net/tso.h> 14 15 #include "otx2_reg.h" 16 #include "otx2_common.h" 17 #include "otx2_struct.h" 18 19 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 20 struct otx2_nic *pfvf, int qidx) 21 { 22 u64 incr = (u64)qidx << 32; 23 u64 *ptr; 24 25 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 26 stats->bytes = otx2_atomic64_add(incr, ptr); 27 28 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 29 stats->pkts = otx2_atomic64_add(incr, ptr); 30 } 31 32 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 33 struct otx2_nic *pfvf, int qidx) 34 { 35 u64 incr = (u64)qidx << 32; 36 u64 *ptr; 37 38 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 39 stats->bytes = otx2_atomic64_add(incr, ptr); 40 41 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 42 stats->pkts = otx2_atomic64_add(incr, ptr); 43 } 44 45 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 46 { 47 struct msg_req *req; 48 49 if (!netif_running(pfvf->netdev)) 50 return; 51 52 mutex_lock(&pfvf->mbox.lock); 53 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 54 if (!req) { 55 mutex_unlock(&pfvf->mbox.lock); 56 return; 57 } 58 59 otx2_sync_mbox_msg(&pfvf->mbox); 60 mutex_unlock(&pfvf->mbox.lock); 61 } 62 63 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 64 { 65 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 66 67 if (!pfvf->qset.rq) 68 return 0; 69 70 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 71 return 1; 72 } 73 74 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 75 { 76 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 77 78 if (!pfvf->qset.sq) 79 return 0; 80 81 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 82 return 1; 83 } 84 85 void otx2_get_dev_stats(struct otx2_nic *pfvf) 86 { 87 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 88 89 #define OTX2_GET_RX_STATS(reg) \ 90 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 91 #define OTX2_GET_TX_STATS(reg) \ 92 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 93 94 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 95 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 96 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 97 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 98 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 99 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 100 dev_stats->rx_mcast_frames + 101 dev_stats->rx_ucast_frames; 102 103 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 104 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 105 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 106 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 107 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 108 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 109 dev_stats->tx_mcast_frames + 110 dev_stats->tx_ucast_frames; 111 } 112 113 void otx2_get_stats64(struct net_device *netdev, 114 struct rtnl_link_stats64 *stats) 115 { 116 struct otx2_nic *pfvf = netdev_priv(netdev); 117 struct otx2_dev_stats *dev_stats; 118 119 otx2_get_dev_stats(pfvf); 120 121 dev_stats = &pfvf->hw.dev_stats; 122 stats->rx_bytes = dev_stats->rx_bytes; 123 stats->rx_packets = dev_stats->rx_frames; 124 stats->rx_dropped = dev_stats->rx_drops; 125 stats->multicast = dev_stats->rx_mcast_frames; 126 127 stats->tx_bytes = dev_stats->tx_bytes; 128 stats->tx_packets = dev_stats->tx_frames; 129 stats->tx_dropped = dev_stats->tx_drops; 130 } 131 EXPORT_SYMBOL(otx2_get_stats64); 132 133 /* Sync MAC address with RVU AF */ 134 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 135 { 136 struct nix_set_mac_addr *req; 137 int err; 138 139 mutex_lock(&pfvf->mbox.lock); 140 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 141 if (!req) { 142 mutex_unlock(&pfvf->mbox.lock); 143 return -ENOMEM; 144 } 145 146 ether_addr_copy(req->mac_addr, mac); 147 148 err = otx2_sync_mbox_msg(&pfvf->mbox); 149 mutex_unlock(&pfvf->mbox.lock); 150 return err; 151 } 152 153 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 154 struct net_device *netdev) 155 { 156 struct nix_get_mac_addr_rsp *rsp; 157 struct mbox_msghdr *msghdr; 158 struct msg_req *req; 159 int err; 160 161 mutex_lock(&pfvf->mbox.lock); 162 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 163 if (!req) { 164 mutex_unlock(&pfvf->mbox.lock); 165 return -ENOMEM; 166 } 167 168 err = otx2_sync_mbox_msg(&pfvf->mbox); 169 if (err) { 170 mutex_unlock(&pfvf->mbox.lock); 171 return err; 172 } 173 174 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 175 if (IS_ERR(msghdr)) { 176 mutex_unlock(&pfvf->mbox.lock); 177 return PTR_ERR(msghdr); 178 } 179 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 180 ether_addr_copy(netdev->dev_addr, rsp->mac_addr); 181 mutex_unlock(&pfvf->mbox.lock); 182 183 return 0; 184 } 185 186 int otx2_set_mac_address(struct net_device *netdev, void *p) 187 { 188 struct otx2_nic *pfvf = netdev_priv(netdev); 189 struct sockaddr *addr = p; 190 191 if (!is_valid_ether_addr(addr->sa_data)) 192 return -EADDRNOTAVAIL; 193 194 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) 195 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 196 else 197 return -EPERM; 198 199 return 0; 200 } 201 EXPORT_SYMBOL(otx2_set_mac_address); 202 203 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 204 { 205 struct nix_frs_cfg *req; 206 int err; 207 208 mutex_lock(&pfvf->mbox.lock); 209 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 210 if (!req) { 211 mutex_unlock(&pfvf->mbox.lock); 212 return -ENOMEM; 213 } 214 215 pfvf->max_frs = mtu + OTX2_ETH_HLEN; 216 req->maxlen = pfvf->max_frs; 217 218 err = otx2_sync_mbox_msg(&pfvf->mbox); 219 mutex_unlock(&pfvf->mbox.lock); 220 return err; 221 } 222 223 int otx2_config_pause_frm(struct otx2_nic *pfvf) 224 { 225 struct cgx_pause_frm_cfg *req; 226 int err; 227 228 if (is_otx2_lbkvf(pfvf->pdev)) 229 return 0; 230 231 mutex_lock(&pfvf->mbox.lock); 232 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 233 if (!req) { 234 err = -ENOMEM; 235 goto unlock; 236 } 237 238 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 239 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 240 req->set = 1; 241 242 err = otx2_sync_mbox_msg(&pfvf->mbox); 243 unlock: 244 mutex_unlock(&pfvf->mbox.lock); 245 return err; 246 } 247 248 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 249 { 250 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 251 struct nix_rss_flowkey_cfg *req; 252 int err; 253 254 mutex_lock(&pfvf->mbox.lock); 255 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 256 if (!req) { 257 mutex_unlock(&pfvf->mbox.lock); 258 return -ENOMEM; 259 } 260 req->mcam_index = -1; /* Default or reserved index */ 261 req->flowkey_cfg = rss->flowkey_cfg; 262 req->group = DEFAULT_RSS_CONTEXT_GROUP; 263 264 err = otx2_sync_mbox_msg(&pfvf->mbox); 265 mutex_unlock(&pfvf->mbox.lock); 266 return err; 267 } 268 269 int otx2_set_rss_table(struct otx2_nic *pfvf) 270 { 271 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 272 struct mbox *mbox = &pfvf->mbox; 273 struct nix_aq_enq_req *aq; 274 int idx, err; 275 276 mutex_lock(&mbox->lock); 277 /* Get memory to put this msg */ 278 for (idx = 0; idx < rss->rss_size; idx++) { 279 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 280 if (!aq) { 281 /* The shared memory buffer can be full. 282 * Flush it and retry 283 */ 284 err = otx2_sync_mbox_msg(mbox); 285 if (err) { 286 mutex_unlock(&mbox->lock); 287 return err; 288 } 289 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 290 if (!aq) { 291 mutex_unlock(&mbox->lock); 292 return -ENOMEM; 293 } 294 } 295 296 aq->rss.rq = rss->ind_tbl[idx]; 297 298 /* Fill AQ info */ 299 aq->qidx = idx; 300 aq->ctype = NIX_AQ_CTYPE_RSS; 301 aq->op = NIX_AQ_INSTOP_INIT; 302 } 303 err = otx2_sync_mbox_msg(mbox); 304 mutex_unlock(&mbox->lock); 305 return err; 306 } 307 308 void otx2_set_rss_key(struct otx2_nic *pfvf) 309 { 310 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 311 u64 *key = (u64 *)&rss->key[4]; 312 int idx; 313 314 /* 352bit or 44byte key needs to be configured as below 315 * NIX_LF_RX_SECRETX0 = key<351:288> 316 * NIX_LF_RX_SECRETX1 = key<287:224> 317 * NIX_LF_RX_SECRETX2 = key<223:160> 318 * NIX_LF_RX_SECRETX3 = key<159:96> 319 * NIX_LF_RX_SECRETX4 = key<95:32> 320 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 321 */ 322 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 323 (u64)(*((u32 *)&rss->key)) << 32); 324 idx = sizeof(rss->key) / sizeof(u64); 325 while (idx > 0) { 326 idx--; 327 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 328 } 329 } 330 331 int otx2_rss_init(struct otx2_nic *pfvf) 332 { 333 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 334 int idx, ret = 0; 335 336 rss->rss_size = sizeof(rss->ind_tbl); 337 338 /* Init RSS key if it is not setup already */ 339 if (!rss->enable) 340 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 341 otx2_set_rss_key(pfvf); 342 343 if (!netif_is_rxfh_configured(pfvf->netdev)) { 344 /* Default indirection table */ 345 for (idx = 0; idx < rss->rss_size; idx++) 346 rss->ind_tbl[idx] = 347 ethtool_rxfh_indir_default(idx, 348 pfvf->hw.rx_queues); 349 } 350 ret = otx2_set_rss_table(pfvf); 351 if (ret) 352 return ret; 353 354 /* Flowkey or hash config to be used for generating flow tag */ 355 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 356 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 357 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 358 NIX_FLOW_KEY_TYPE_SCTP; 359 360 ret = otx2_set_flowkey_cfg(pfvf); 361 if (ret) 362 return ret; 363 364 rss->enable = true; 365 return 0; 366 } 367 368 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 369 { 370 /* Configure CQE interrupt coalescing parameters 371 * 372 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 373 * set 1 less than cq_ecount_wait. And cq_time_wait is in 374 * usecs, convert that to 100ns count. 375 */ 376 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 377 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 378 ((u64)pfvf->hw.cq_qcount_wait << 32) | 379 (pfvf->hw.cq_ecount_wait - 1)); 380 } 381 382 dma_addr_t __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool) 383 { 384 dma_addr_t iova; 385 u8 *buf; 386 387 buf = napi_alloc_frag(pool->rbsize); 388 if (unlikely(!buf)) 389 return -ENOMEM; 390 391 iova = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 392 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 393 if (unlikely(dma_mapping_error(pfvf->dev, iova))) { 394 page_frag_free(buf); 395 return -ENOMEM; 396 } 397 398 return iova; 399 } 400 401 static dma_addr_t otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool) 402 { 403 dma_addr_t addr; 404 405 local_bh_disable(); 406 addr = __otx2_alloc_rbuf(pfvf, pool); 407 local_bh_enable(); 408 return addr; 409 } 410 411 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 412 { 413 struct otx2_nic *pfvf = netdev_priv(netdev); 414 415 schedule_work(&pfvf->reset_task); 416 } 417 EXPORT_SYMBOL(otx2_tx_timeout); 418 419 void otx2_get_mac_from_af(struct net_device *netdev) 420 { 421 struct otx2_nic *pfvf = netdev_priv(netdev); 422 int err; 423 424 err = otx2_hw_get_mac_addr(pfvf, netdev); 425 if (err) 426 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 427 428 /* If AF doesn't provide a valid MAC, generate a random one */ 429 if (!is_valid_ether_addr(netdev->dev_addr)) 430 eth_hw_addr_random(netdev); 431 } 432 EXPORT_SYMBOL(otx2_get_mac_from_af); 433 434 static int otx2_get_link(struct otx2_nic *pfvf) 435 { 436 int link = 0; 437 u16 map; 438 439 /* cgx lmac link */ 440 if (pfvf->hw.tx_chan_base >= CGX_CHAN_BASE) { 441 map = pfvf->hw.tx_chan_base & 0x7FF; 442 link = 4 * ((map >> 8) & 0xF) + ((map >> 4) & 0xF); 443 } 444 /* LBK channel */ 445 if (pfvf->hw.tx_chan_base < SDP_CHAN_BASE) 446 link = 12; 447 448 return link; 449 } 450 451 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl) 452 { 453 struct otx2_hw *hw = &pfvf->hw; 454 struct nix_txschq_config *req; 455 u64 schq, parent; 456 457 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 458 if (!req) 459 return -ENOMEM; 460 461 req->lvl = lvl; 462 req->num_regs = 1; 463 464 schq = hw->txschq_list[lvl][0]; 465 /* Set topology e.t.c configuration */ 466 if (lvl == NIX_TXSCH_LVL_SMQ) { 467 req->reg[0] = NIX_AF_SMQX_CFG(schq); 468 req->regval[0] = ((OTX2_MAX_MTU + OTX2_ETH_HLEN) << 8) | 469 OTX2_MIN_MTU; 470 471 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 472 (0x2ULL << 36); 473 req->num_regs++; 474 /* MDQ config */ 475 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0]; 476 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 477 req->regval[1] = parent << 16; 478 req->num_regs++; 479 /* Set DWRR quantum */ 480 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 481 req->regval[2] = DFLT_RR_QTM; 482 } else if (lvl == NIX_TXSCH_LVL_TL4) { 483 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0]; 484 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 485 req->regval[0] = parent << 16; 486 req->num_regs++; 487 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 488 req->regval[1] = DFLT_RR_QTM; 489 } else if (lvl == NIX_TXSCH_LVL_TL3) { 490 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0]; 491 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 492 req->regval[0] = parent << 16; 493 req->num_regs++; 494 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 495 req->regval[1] = DFLT_RR_QTM; 496 } else if (lvl == NIX_TXSCH_LVL_TL2) { 497 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0]; 498 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 499 req->regval[0] = parent << 16; 500 501 req->num_regs++; 502 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 503 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | DFLT_RR_QTM; 504 505 req->num_regs++; 506 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, 507 otx2_get_link(pfvf)); 508 /* Enable this queue and backpressure */ 509 req->regval[2] = BIT_ULL(13) | BIT_ULL(12); 510 511 } else if (lvl == NIX_TXSCH_LVL_TL1) { 512 /* Default config for TL1. 513 * For VF this is always ignored. 514 */ 515 516 /* Set DWRR quantum */ 517 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 518 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 519 520 req->num_regs++; 521 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 522 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 523 524 req->num_regs++; 525 req->reg[2] = NIX_AF_TL1X_CIR(schq); 526 req->regval[2] = 0; 527 } 528 529 return otx2_sync_mbox_msg(&pfvf->mbox); 530 } 531 532 int otx2_txsch_alloc(struct otx2_nic *pfvf) 533 { 534 struct nix_txsch_alloc_req *req; 535 int lvl; 536 537 /* Get memory to put this msg */ 538 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 539 if (!req) 540 return -ENOMEM; 541 542 /* Request one schq per level */ 543 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 544 req->schq[lvl] = 1; 545 546 return otx2_sync_mbox_msg(&pfvf->mbox); 547 } 548 549 int otx2_txschq_stop(struct otx2_nic *pfvf) 550 { 551 struct nix_txsch_free_req *free_req; 552 int lvl, schq, err; 553 554 mutex_lock(&pfvf->mbox.lock); 555 /* Free the transmit schedulers */ 556 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 557 if (!free_req) { 558 mutex_unlock(&pfvf->mbox.lock); 559 return -ENOMEM; 560 } 561 562 free_req->flags = TXSCHQ_FREE_ALL; 563 err = otx2_sync_mbox_msg(&pfvf->mbox); 564 mutex_unlock(&pfvf->mbox.lock); 565 566 /* Clear the txschq list */ 567 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 568 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 569 pfvf->hw.txschq_list[lvl][schq] = 0; 570 } 571 return err; 572 } 573 574 void otx2_sqb_flush(struct otx2_nic *pfvf) 575 { 576 int qidx, sqe_tail, sqe_head; 577 u64 incr, *ptr, val; 578 int timeout = 1000; 579 580 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 581 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 582 incr = (u64)qidx << 32; 583 while (timeout) { 584 val = otx2_atomic64_add(incr, ptr); 585 sqe_head = (val >> 20) & 0x3F; 586 sqe_tail = (val >> 28) & 0x3F; 587 if (sqe_head == sqe_tail) 588 break; 589 usleep_range(1, 3); 590 timeout--; 591 } 592 } 593 } 594 595 /* RED and drop levels of CQ on packet reception. 596 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 597 */ 598 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 599 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 600 601 /* RED and drop levels of AURA for packet reception. 602 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 603 * Eg: For RQ length 1K, for pass/drop level 204/230. 604 * RED accepts pkts if free pointers > 102 & <= 205. 605 * Drops pkts if free pointers < 102. 606 */ 607 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 608 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 609 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 610 611 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 612 #define SEND_CQ_SKID 2000 613 614 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 615 { 616 struct otx2_qset *qset = &pfvf->qset; 617 struct nix_aq_enq_req *aq; 618 619 /* Get memory to put this msg */ 620 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 621 if (!aq) 622 return -ENOMEM; 623 624 aq->rq.cq = qidx; 625 aq->rq.ena = 1; 626 aq->rq.pb_caching = 1; 627 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 628 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 629 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 630 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 631 aq->rq.qint_idx = 0; 632 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 633 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 634 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 635 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 636 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 637 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 638 639 /* Fill AQ info */ 640 aq->qidx = qidx; 641 aq->ctype = NIX_AQ_CTYPE_RQ; 642 aq->op = NIX_AQ_INSTOP_INIT; 643 644 return otx2_sync_mbox_msg(&pfvf->mbox); 645 } 646 647 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 648 { 649 struct otx2_qset *qset = &pfvf->qset; 650 struct otx2_snd_queue *sq; 651 struct nix_aq_enq_req *aq; 652 struct otx2_pool *pool; 653 int err; 654 655 pool = &pfvf->qset.pool[sqb_aura]; 656 sq = &qset->sq[qidx]; 657 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 658 sq->sqe_cnt = qset->sqe_cnt; 659 660 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 661 if (err) 662 return err; 663 664 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 665 TSO_HEADER_SIZE); 666 if (err) 667 return err; 668 669 sq->sqe_base = sq->sqe->base; 670 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 671 if (!sq->sg) 672 return -ENOMEM; 673 674 sq->head = 0; 675 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 676 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 677 /* Set SQE threshold to 10% of total SQEs */ 678 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 679 sq->aura_id = sqb_aura; 680 sq->aura_fc_addr = pool->fc_addr->base; 681 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 682 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 683 684 sq->stats.bytes = 0; 685 sq->stats.pkts = 0; 686 687 /* Get memory to put this msg */ 688 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 689 if (!aq) 690 return -ENOMEM; 691 692 aq->sq.cq = pfvf->hw.rx_queues + qidx; 693 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 694 aq->sq.cq_ena = 1; 695 aq->sq.ena = 1; 696 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 697 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 698 aq->sq.smq_rr_quantum = DFLT_RR_QTM; 699 aq->sq.default_chan = pfvf->hw.tx_chan_base; 700 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 701 aq->sq.sqb_aura = sqb_aura; 702 aq->sq.sq_int_ena = NIX_SQINT_BITS; 703 aq->sq.qint_idx = 0; 704 /* Due pipelining impact minimum 2000 unused SQ CQE's 705 * need to maintain to avoid CQ overflow. 706 */ 707 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (sq->sqe_cnt)); 708 709 /* Fill AQ info */ 710 aq->qidx = qidx; 711 aq->ctype = NIX_AQ_CTYPE_SQ; 712 aq->op = NIX_AQ_INSTOP_INIT; 713 714 return otx2_sync_mbox_msg(&pfvf->mbox); 715 } 716 717 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 718 { 719 struct otx2_qset *qset = &pfvf->qset; 720 struct nix_aq_enq_req *aq; 721 struct otx2_cq_queue *cq; 722 int err, pool_id; 723 724 cq = &qset->cq[qidx]; 725 cq->cq_idx = qidx; 726 if (qidx < pfvf->hw.rx_queues) { 727 cq->cq_type = CQ_RX; 728 cq->cint_idx = qidx; 729 cq->cqe_cnt = qset->rqe_cnt; 730 } else { 731 cq->cq_type = CQ_TX; 732 cq->cint_idx = qidx - pfvf->hw.rx_queues; 733 cq->cqe_cnt = qset->sqe_cnt; 734 } 735 cq->cqe_size = pfvf->qset.xqe_size; 736 737 /* Allocate memory for CQEs */ 738 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 739 if (err) 740 return err; 741 742 /* Save CQE CPU base for faster reference */ 743 cq->cqe_base = cq->cqe->base; 744 /* In case where all RQs auras point to single pool, 745 * all CQs receive buffer pool also point to same pool. 746 */ 747 pool_id = ((cq->cq_type == CQ_RX) && 748 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 749 cq->rbpool = &qset->pool[pool_id]; 750 cq->refill_task_sched = false; 751 752 /* Get memory to put this msg */ 753 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 754 if (!aq) 755 return -ENOMEM; 756 757 aq->cq.ena = 1; 758 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 759 aq->cq.caching = 1; 760 aq->cq.base = cq->cqe->iova; 761 aq->cq.cint_idx = cq->cint_idx; 762 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 763 aq->cq.qint_idx = 0; 764 aq->cq.avg_level = 255; 765 766 if (qidx < pfvf->hw.rx_queues) { 767 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 768 aq->cq.drop_ena = 1; 769 770 /* Enable receive CQ backpressure */ 771 aq->cq.bp_ena = 1; 772 aq->cq.bpid = pfvf->bpid[0]; 773 774 /* Set backpressure level is same as cq pass level */ 775 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 776 } 777 778 /* Fill AQ info */ 779 aq->qidx = qidx; 780 aq->ctype = NIX_AQ_CTYPE_CQ; 781 aq->op = NIX_AQ_INSTOP_INIT; 782 783 return otx2_sync_mbox_msg(&pfvf->mbox); 784 } 785 786 static void otx2_pool_refill_task(struct work_struct *work) 787 { 788 struct otx2_cq_queue *cq; 789 struct otx2_pool *rbpool; 790 struct refill_work *wrk; 791 int qidx, free_ptrs = 0; 792 struct otx2_nic *pfvf; 793 s64 bufptr; 794 795 wrk = container_of(work, struct refill_work, pool_refill_work.work); 796 pfvf = wrk->pf; 797 qidx = wrk - pfvf->refill_wrk; 798 cq = &pfvf->qset.cq[qidx]; 799 rbpool = cq->rbpool; 800 free_ptrs = cq->pool_ptrs; 801 802 while (cq->pool_ptrs) { 803 bufptr = otx2_alloc_rbuf(pfvf, rbpool); 804 if (bufptr <= 0) { 805 /* Schedule a WQ if we fails to free atleast half of the 806 * pointers else enable napi for this RQ. 807 */ 808 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 809 struct delayed_work *dwork; 810 811 dwork = &wrk->pool_refill_work; 812 schedule_delayed_work(dwork, 813 msecs_to_jiffies(100)); 814 } else { 815 cq->refill_task_sched = false; 816 } 817 return; 818 } 819 otx2_aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 820 cq->pool_ptrs--; 821 } 822 cq->refill_task_sched = false; 823 } 824 825 int otx2_config_nix_queues(struct otx2_nic *pfvf) 826 { 827 int qidx, err; 828 829 /* Initialize RX queues */ 830 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 831 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 832 833 err = otx2_rq_init(pfvf, qidx, lpb_aura); 834 if (err) 835 return err; 836 } 837 838 /* Initialize TX queues */ 839 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 840 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 841 842 err = otx2_sq_init(pfvf, qidx, sqb_aura); 843 if (err) 844 return err; 845 } 846 847 /* Initialize completion queues */ 848 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 849 err = otx2_cq_init(pfvf, qidx); 850 if (err) 851 return err; 852 } 853 854 /* Initialize work queue for receive buffer refill */ 855 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 856 sizeof(struct refill_work), GFP_KERNEL); 857 if (!pfvf->refill_wrk) 858 return -ENOMEM; 859 860 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 861 pfvf->refill_wrk[qidx].pf = pfvf; 862 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 863 otx2_pool_refill_task); 864 } 865 return 0; 866 } 867 868 int otx2_config_nix(struct otx2_nic *pfvf) 869 { 870 struct nix_lf_alloc_req *nixlf; 871 struct nix_lf_alloc_rsp *rsp; 872 int err; 873 874 pfvf->qset.xqe_size = NIX_XQESZ_W16 ? 128 : 512; 875 876 /* Get memory to put this msg */ 877 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 878 if (!nixlf) 879 return -ENOMEM; 880 881 /* Set RQ/SQ/CQ counts */ 882 nixlf->rq_cnt = pfvf->hw.rx_queues; 883 nixlf->sq_cnt = pfvf->hw.tx_queues; 884 nixlf->cq_cnt = pfvf->qset.cq_cnt; 885 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 886 nixlf->rss_grps = 1; /* Single RSS indir table supported, for now */ 887 nixlf->xqe_sz = NIX_XQESZ_W16; 888 /* We don't know absolute NPA LF idx attached. 889 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 890 * NPA LF attached to this RVU PF/VF. 891 */ 892 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 893 /* Disable alignment pad, enable L2 length check, 894 * enable L4 TCP/UDP checksum verification. 895 */ 896 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 897 898 err = otx2_sync_mbox_msg(&pfvf->mbox); 899 if (err) 900 return err; 901 902 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 903 &nixlf->hdr); 904 if (IS_ERR(rsp)) 905 return PTR_ERR(rsp); 906 907 if (rsp->qints < 1) 908 return -ENXIO; 909 910 return rsp->hdr.rc; 911 } 912 913 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 914 { 915 struct otx2_qset *qset = &pfvf->qset; 916 struct otx2_hw *hw = &pfvf->hw; 917 struct otx2_snd_queue *sq; 918 int sqb, qidx; 919 u64 iova, pa; 920 921 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 922 sq = &qset->sq[qidx]; 923 if (!sq->sqb_ptrs) 924 continue; 925 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 926 if (!sq->sqb_ptrs[sqb]) 927 continue; 928 iova = sq->sqb_ptrs[sqb]; 929 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 930 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 931 DMA_FROM_DEVICE, 932 DMA_ATTR_SKIP_CPU_SYNC); 933 put_page(virt_to_page(phys_to_virt(pa))); 934 } 935 sq->sqb_count = 0; 936 } 937 } 938 939 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 940 { 941 int pool_id, pool_start = 0, pool_end = 0, size = 0; 942 u64 iova, pa; 943 944 if (type == AURA_NIX_SQ) { 945 pool_start = otx2_get_pool_idx(pfvf, type, 0); 946 pool_end = pool_start + pfvf->hw.sqpool_cnt; 947 size = pfvf->hw.sqb_size; 948 } 949 if (type == AURA_NIX_RQ) { 950 pool_start = otx2_get_pool_idx(pfvf, type, 0); 951 pool_end = pfvf->hw.rqpool_cnt; 952 size = pfvf->rbsize; 953 } 954 955 /* Free SQB and RQB pointers from the aura pool */ 956 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 957 iova = otx2_aura_allocptr(pfvf, pool_id); 958 while (iova) { 959 if (type == AURA_NIX_RQ) 960 iova -= OTX2_HEAD_ROOM; 961 962 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 963 dma_unmap_page_attrs(pfvf->dev, iova, size, 964 DMA_FROM_DEVICE, 965 DMA_ATTR_SKIP_CPU_SYNC); 966 put_page(virt_to_page(phys_to_virt(pa))); 967 iova = otx2_aura_allocptr(pfvf, pool_id); 968 } 969 } 970 } 971 972 void otx2_aura_pool_free(struct otx2_nic *pfvf) 973 { 974 struct otx2_pool *pool; 975 int pool_id; 976 977 if (!pfvf->qset.pool) 978 return; 979 980 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 981 pool = &pfvf->qset.pool[pool_id]; 982 qmem_free(pfvf->dev, pool->stack); 983 qmem_free(pfvf->dev, pool->fc_addr); 984 } 985 devm_kfree(pfvf->dev, pfvf->qset.pool); 986 pfvf->qset.pool = NULL; 987 } 988 989 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 990 int pool_id, int numptrs) 991 { 992 struct npa_aq_enq_req *aq; 993 struct otx2_pool *pool; 994 int err; 995 996 pool = &pfvf->qset.pool[pool_id]; 997 998 /* Allocate memory for HW to update Aura count. 999 * Alloc one cache line, so that it fits all FC_STYPE modes. 1000 */ 1001 if (!pool->fc_addr) { 1002 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1003 if (err) 1004 return err; 1005 } 1006 1007 /* Initialize this aura's context via AF */ 1008 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1009 if (!aq) { 1010 /* Shared mbox memory buffer is full, flush it and retry */ 1011 err = otx2_sync_mbox_msg(&pfvf->mbox); 1012 if (err) 1013 return err; 1014 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1015 if (!aq) 1016 return -ENOMEM; 1017 } 1018 1019 aq->aura_id = aura_id; 1020 /* Will be filled by AF with correct pool context address */ 1021 aq->aura.pool_addr = pool_id; 1022 aq->aura.pool_caching = 1; 1023 aq->aura.shift = ilog2(numptrs) - 8; 1024 aq->aura.count = numptrs; 1025 aq->aura.limit = numptrs; 1026 aq->aura.avg_level = 255; 1027 aq->aura.ena = 1; 1028 aq->aura.fc_ena = 1; 1029 aq->aura.fc_addr = pool->fc_addr->iova; 1030 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1031 1032 /* Enable backpressure for RQ aura */ 1033 if (aura_id < pfvf->hw.rqpool_cnt) { 1034 aq->aura.bp_ena = 0; 1035 aq->aura.nix0_bpid = pfvf->bpid[0]; 1036 /* Set backpressure level for RQ's Aura */ 1037 aq->aura.bp = RQ_BP_LVL_AURA; 1038 } 1039 1040 /* Fill AQ info */ 1041 aq->ctype = NPA_AQ_CTYPE_AURA; 1042 aq->op = NPA_AQ_INSTOP_INIT; 1043 1044 return 0; 1045 } 1046 1047 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1048 int stack_pages, int numptrs, int buf_size) 1049 { 1050 struct npa_aq_enq_req *aq; 1051 struct otx2_pool *pool; 1052 int err; 1053 1054 pool = &pfvf->qset.pool[pool_id]; 1055 /* Alloc memory for stack which is used to store buffer pointers */ 1056 err = qmem_alloc(pfvf->dev, &pool->stack, 1057 stack_pages, pfvf->hw.stack_pg_bytes); 1058 if (err) 1059 return err; 1060 1061 pool->rbsize = buf_size; 1062 1063 /* Initialize this pool's context via AF */ 1064 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1065 if (!aq) { 1066 /* Shared mbox memory buffer is full, flush it and retry */ 1067 err = otx2_sync_mbox_msg(&pfvf->mbox); 1068 if (err) { 1069 qmem_free(pfvf->dev, pool->stack); 1070 return err; 1071 } 1072 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1073 if (!aq) { 1074 qmem_free(pfvf->dev, pool->stack); 1075 return -ENOMEM; 1076 } 1077 } 1078 1079 aq->aura_id = pool_id; 1080 aq->pool.stack_base = pool->stack->iova; 1081 aq->pool.stack_caching = 1; 1082 aq->pool.ena = 1; 1083 aq->pool.buf_size = buf_size / 128; 1084 aq->pool.stack_max_pages = stack_pages; 1085 aq->pool.shift = ilog2(numptrs) - 8; 1086 aq->pool.ptr_start = 0; 1087 aq->pool.ptr_end = ~0ULL; 1088 1089 /* Fill AQ info */ 1090 aq->ctype = NPA_AQ_CTYPE_POOL; 1091 aq->op = NPA_AQ_INSTOP_INIT; 1092 1093 return 0; 1094 } 1095 1096 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1097 { 1098 int qidx, pool_id, stack_pages, num_sqbs; 1099 struct otx2_qset *qset = &pfvf->qset; 1100 struct otx2_hw *hw = &pfvf->hw; 1101 struct otx2_snd_queue *sq; 1102 struct otx2_pool *pool; 1103 int err, ptr; 1104 s64 bufptr; 1105 1106 /* Calculate number of SQBs needed. 1107 * 1108 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1109 * Last SQE is used for pointing to next SQB. 1110 */ 1111 num_sqbs = (hw->sqb_size / 128) - 1; 1112 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1113 1114 /* Get no of stack pages needed */ 1115 stack_pages = 1116 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1117 1118 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1119 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1120 /* Initialize aura context */ 1121 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1122 if (err) 1123 goto fail; 1124 1125 /* Initialize pool context */ 1126 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1127 num_sqbs, hw->sqb_size); 1128 if (err) 1129 goto fail; 1130 } 1131 1132 /* Flush accumulated messages */ 1133 err = otx2_sync_mbox_msg(&pfvf->mbox); 1134 if (err) 1135 goto fail; 1136 1137 /* Allocate pointers and free them to aura/pool */ 1138 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1139 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1140 pool = &pfvf->qset.pool[pool_id]; 1141 1142 sq = &qset->sq[qidx]; 1143 sq->sqb_count = 0; 1144 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(u64 *), GFP_KERNEL); 1145 if (!sq->sqb_ptrs) 1146 return -ENOMEM; 1147 1148 for (ptr = 0; ptr < num_sqbs; ptr++) { 1149 bufptr = otx2_alloc_rbuf(pfvf, pool); 1150 if (bufptr <= 0) 1151 return bufptr; 1152 otx2_aura_freeptr(pfvf, pool_id, bufptr); 1153 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1154 } 1155 } 1156 1157 return 0; 1158 fail: 1159 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1160 otx2_aura_pool_free(pfvf); 1161 return err; 1162 } 1163 1164 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1165 { 1166 struct otx2_hw *hw = &pfvf->hw; 1167 int stack_pages, pool_id, rq; 1168 struct otx2_pool *pool; 1169 int err, ptr, num_ptrs; 1170 s64 bufptr; 1171 1172 num_ptrs = pfvf->qset.rqe_cnt; 1173 1174 stack_pages = 1175 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1176 1177 for (rq = 0; rq < hw->rx_queues; rq++) { 1178 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1179 /* Initialize aura context */ 1180 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1181 if (err) 1182 goto fail; 1183 } 1184 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1185 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1186 num_ptrs, pfvf->rbsize); 1187 if (err) 1188 goto fail; 1189 } 1190 1191 /* Flush accumulated messages */ 1192 err = otx2_sync_mbox_msg(&pfvf->mbox); 1193 if (err) 1194 goto fail; 1195 1196 /* Allocate pointers and free them to aura/pool */ 1197 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1198 pool = &pfvf->qset.pool[pool_id]; 1199 for (ptr = 0; ptr < num_ptrs; ptr++) { 1200 bufptr = otx2_alloc_rbuf(pfvf, pool); 1201 if (bufptr <= 0) 1202 return bufptr; 1203 otx2_aura_freeptr(pfvf, pool_id, 1204 bufptr + OTX2_HEAD_ROOM); 1205 } 1206 } 1207 1208 return 0; 1209 fail: 1210 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1211 otx2_aura_pool_free(pfvf); 1212 return err; 1213 } 1214 1215 int otx2_config_npa(struct otx2_nic *pfvf) 1216 { 1217 struct otx2_qset *qset = &pfvf->qset; 1218 struct npa_lf_alloc_req *npalf; 1219 struct otx2_hw *hw = &pfvf->hw; 1220 int aura_cnt; 1221 1222 /* Pool - Stack of free buffer pointers 1223 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1224 */ 1225 1226 if (!hw->pool_cnt) 1227 return -EINVAL; 1228 1229 qset->pool = devm_kzalloc(pfvf->dev, sizeof(struct otx2_pool) * 1230 hw->pool_cnt, GFP_KERNEL); 1231 if (!qset->pool) 1232 return -ENOMEM; 1233 1234 /* Get memory to put this msg */ 1235 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1236 if (!npalf) 1237 return -ENOMEM; 1238 1239 /* Set aura and pool counts */ 1240 npalf->nr_pools = hw->pool_cnt; 1241 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1242 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1243 1244 return otx2_sync_mbox_msg(&pfvf->mbox); 1245 } 1246 1247 int otx2_detach_resources(struct mbox *mbox) 1248 { 1249 struct rsrc_detach *detach; 1250 1251 mutex_lock(&mbox->lock); 1252 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1253 if (!detach) { 1254 mutex_unlock(&mbox->lock); 1255 return -ENOMEM; 1256 } 1257 1258 /* detach all */ 1259 detach->partial = false; 1260 1261 /* Send detach request to AF */ 1262 otx2_mbox_msg_send(&mbox->mbox, 0); 1263 mutex_unlock(&mbox->lock); 1264 return 0; 1265 } 1266 EXPORT_SYMBOL(otx2_detach_resources); 1267 1268 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1269 { 1270 struct rsrc_attach *attach; 1271 struct msg_req *msix; 1272 int err; 1273 1274 mutex_lock(&pfvf->mbox.lock); 1275 /* Get memory to put this msg */ 1276 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1277 if (!attach) { 1278 mutex_unlock(&pfvf->mbox.lock); 1279 return -ENOMEM; 1280 } 1281 1282 attach->npalf = true; 1283 attach->nixlf = true; 1284 1285 /* Send attach request to AF */ 1286 err = otx2_sync_mbox_msg(&pfvf->mbox); 1287 if (err) { 1288 mutex_unlock(&pfvf->mbox.lock); 1289 return err; 1290 } 1291 1292 pfvf->nix_blkaddr = BLKADDR_NIX0; 1293 1294 /* If the platform has two NIX blocks then LF may be 1295 * allocated from NIX1. 1296 */ 1297 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1298 pfvf->nix_blkaddr = BLKADDR_NIX1; 1299 1300 /* Get NPA and NIX MSIX vector offsets */ 1301 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1302 if (!msix) { 1303 mutex_unlock(&pfvf->mbox.lock); 1304 return -ENOMEM; 1305 } 1306 1307 err = otx2_sync_mbox_msg(&pfvf->mbox); 1308 if (err) { 1309 mutex_unlock(&pfvf->mbox.lock); 1310 return err; 1311 } 1312 mutex_unlock(&pfvf->mbox.lock); 1313 1314 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1315 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1316 dev_err(pfvf->dev, 1317 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1318 return -EINVAL; 1319 } 1320 1321 return 0; 1322 } 1323 EXPORT_SYMBOL(otx2_attach_npa_nix); 1324 1325 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1326 { 1327 struct hwctx_disable_req *req; 1328 1329 mutex_lock(&mbox->lock); 1330 /* Request AQ to disable this context */ 1331 if (npa) 1332 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1333 else 1334 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1335 1336 if (!req) { 1337 mutex_unlock(&mbox->lock); 1338 return; 1339 } 1340 1341 req->ctype = type; 1342 1343 if (otx2_sync_mbox_msg(mbox)) 1344 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1345 __func__); 1346 1347 mutex_unlock(&mbox->lock); 1348 } 1349 1350 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1351 { 1352 struct nix_bp_cfg_req *req; 1353 1354 if (enable) 1355 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1356 else 1357 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1358 1359 if (!req) 1360 return -ENOMEM; 1361 1362 req->chan_base = 0; 1363 req->chan_cnt = 1; 1364 req->bpid_per_chan = 0; 1365 1366 return otx2_sync_mbox_msg(&pfvf->mbox); 1367 } 1368 1369 /* Mbox message handlers */ 1370 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1371 struct cgx_stats_rsp *rsp) 1372 { 1373 int id; 1374 1375 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1376 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1377 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1378 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1379 } 1380 1381 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1382 struct nix_txsch_alloc_rsp *rsp) 1383 { 1384 int lvl, schq; 1385 1386 /* Setup transmit scheduler list */ 1387 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 1388 for (schq = 0; schq < rsp->schq[lvl]; schq++) 1389 pf->hw.txschq_list[lvl][schq] = 1390 rsp->schq_list[lvl][schq]; 1391 } 1392 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc); 1393 1394 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1395 struct npa_lf_alloc_rsp *rsp) 1396 { 1397 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1398 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1399 } 1400 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1401 1402 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1403 struct nix_lf_alloc_rsp *rsp) 1404 { 1405 pfvf->hw.sqb_size = rsp->sqb_size; 1406 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1407 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1408 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1409 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1410 } 1411 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1412 1413 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1414 struct msix_offset_rsp *rsp) 1415 { 1416 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1417 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1418 } 1419 EXPORT_SYMBOL(mbox_handler_msix_offset); 1420 1421 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1422 struct nix_bp_cfg_rsp *rsp) 1423 { 1424 int chan, chan_id; 1425 1426 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1427 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1428 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1429 } 1430 } 1431 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1432 1433 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1434 { 1435 struct otx2_qset *qset = &pfvf->qset; 1436 struct otx2_hw *hw = &pfvf->hw; 1437 int irq, qidx; 1438 1439 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1440 qidx < n; 1441 qidx++, irq++) { 1442 int vector = pci_irq_vector(pfvf->pdev, irq); 1443 1444 irq_set_affinity_hint(vector, NULL); 1445 free_cpumask_var(hw->affinity_mask[irq]); 1446 free_irq(vector, &qset->napi[qidx]); 1447 } 1448 } 1449 1450 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1451 { 1452 struct otx2_hw *hw = &pfvf->hw; 1453 int vec, cpu, irq, cint; 1454 1455 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1456 cpu = cpumask_first(cpu_online_mask); 1457 1458 /* CQ interrupts */ 1459 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1460 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1461 return; 1462 1463 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1464 1465 irq = pci_irq_vector(pfvf->pdev, vec); 1466 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1467 1468 cpu = cpumask_next(cpu, cpu_online_mask); 1469 if (unlikely(cpu >= nr_cpu_ids)) 1470 cpu = 0; 1471 } 1472 } 1473 1474 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1475 int __weak \ 1476 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1477 struct _req_type *req, \ 1478 struct _rsp_type *rsp) \ 1479 { \ 1480 /* Nothing to do here */ \ 1481 return 0; \ 1482 } \ 1483 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1484 MBOX_UP_CGX_MESSAGES 1485 #undef M 1486