1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <net/tso.h> 14 15 #include "otx2_reg.h" 16 #include "otx2_common.h" 17 #include "otx2_struct.h" 18 #include "cn10k.h" 19 20 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 21 struct otx2_nic *pfvf, int qidx) 22 { 23 u64 incr = (u64)qidx << 32; 24 u64 *ptr; 25 26 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 27 stats->bytes = otx2_atomic64_add(incr, ptr); 28 29 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 30 stats->pkts = otx2_atomic64_add(incr, ptr); 31 } 32 33 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 34 struct otx2_nic *pfvf, int qidx) 35 { 36 u64 incr = (u64)qidx << 32; 37 u64 *ptr; 38 39 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 40 stats->bytes = otx2_atomic64_add(incr, ptr); 41 42 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 43 stats->pkts = otx2_atomic64_add(incr, ptr); 44 } 45 46 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 47 { 48 struct msg_req *req; 49 50 if (!netif_running(pfvf->netdev)) 51 return; 52 53 mutex_lock(&pfvf->mbox.lock); 54 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 55 if (!req) { 56 mutex_unlock(&pfvf->mbox.lock); 57 return; 58 } 59 60 otx2_sync_mbox_msg(&pfvf->mbox); 61 mutex_unlock(&pfvf->mbox.lock); 62 } 63 64 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 65 { 66 struct msg_req *req; 67 68 if (!netif_running(pfvf->netdev)) 69 return; 70 mutex_lock(&pfvf->mbox.lock); 71 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 72 if (req) 73 otx2_sync_mbox_msg(&pfvf->mbox); 74 mutex_unlock(&pfvf->mbox.lock); 75 } 76 77 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 78 { 79 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 80 81 if (!pfvf->qset.rq) 82 return 0; 83 84 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 85 return 1; 86 } 87 88 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 89 { 90 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 91 92 if (!pfvf->qset.sq) 93 return 0; 94 95 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 96 return 1; 97 } 98 99 void otx2_get_dev_stats(struct otx2_nic *pfvf) 100 { 101 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 102 103 #define OTX2_GET_RX_STATS(reg) \ 104 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 105 #define OTX2_GET_TX_STATS(reg) \ 106 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 107 108 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 109 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 110 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 111 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 112 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 113 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 114 dev_stats->rx_mcast_frames + 115 dev_stats->rx_ucast_frames; 116 117 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 118 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 119 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 120 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 121 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 122 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 123 dev_stats->tx_mcast_frames + 124 dev_stats->tx_ucast_frames; 125 } 126 127 void otx2_get_stats64(struct net_device *netdev, 128 struct rtnl_link_stats64 *stats) 129 { 130 struct otx2_nic *pfvf = netdev_priv(netdev); 131 struct otx2_dev_stats *dev_stats; 132 133 otx2_get_dev_stats(pfvf); 134 135 dev_stats = &pfvf->hw.dev_stats; 136 stats->rx_bytes = dev_stats->rx_bytes; 137 stats->rx_packets = dev_stats->rx_frames; 138 stats->rx_dropped = dev_stats->rx_drops; 139 stats->multicast = dev_stats->rx_mcast_frames; 140 141 stats->tx_bytes = dev_stats->tx_bytes; 142 stats->tx_packets = dev_stats->tx_frames; 143 stats->tx_dropped = dev_stats->tx_drops; 144 } 145 EXPORT_SYMBOL(otx2_get_stats64); 146 147 /* Sync MAC address with RVU AF */ 148 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 149 { 150 struct nix_set_mac_addr *req; 151 int err; 152 153 mutex_lock(&pfvf->mbox.lock); 154 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 155 if (!req) { 156 mutex_unlock(&pfvf->mbox.lock); 157 return -ENOMEM; 158 } 159 160 ether_addr_copy(req->mac_addr, mac); 161 162 err = otx2_sync_mbox_msg(&pfvf->mbox); 163 mutex_unlock(&pfvf->mbox.lock); 164 return err; 165 } 166 167 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 168 struct net_device *netdev) 169 { 170 struct nix_get_mac_addr_rsp *rsp; 171 struct mbox_msghdr *msghdr; 172 struct msg_req *req; 173 int err; 174 175 mutex_lock(&pfvf->mbox.lock); 176 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 177 if (!req) { 178 mutex_unlock(&pfvf->mbox.lock); 179 return -ENOMEM; 180 } 181 182 err = otx2_sync_mbox_msg(&pfvf->mbox); 183 if (err) { 184 mutex_unlock(&pfvf->mbox.lock); 185 return err; 186 } 187 188 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 189 if (IS_ERR(msghdr)) { 190 mutex_unlock(&pfvf->mbox.lock); 191 return PTR_ERR(msghdr); 192 } 193 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 194 ether_addr_copy(netdev->dev_addr, rsp->mac_addr); 195 mutex_unlock(&pfvf->mbox.lock); 196 197 return 0; 198 } 199 200 int otx2_set_mac_address(struct net_device *netdev, void *p) 201 { 202 struct otx2_nic *pfvf = netdev_priv(netdev); 203 struct sockaddr *addr = p; 204 205 if (!is_valid_ether_addr(addr->sa_data)) 206 return -EADDRNOTAVAIL; 207 208 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 209 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 210 /* update dmac field in vlan offload rule */ 211 if (pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 212 otx2_install_rxvlan_offload_flow(pfvf); 213 /* update dmac address in ntuple and DMAC filter list */ 214 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 215 otx2_dmacflt_update_pfmac_flow(pfvf); 216 } else { 217 return -EPERM; 218 } 219 220 return 0; 221 } 222 EXPORT_SYMBOL(otx2_set_mac_address); 223 224 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 225 { 226 struct nix_frs_cfg *req; 227 int err; 228 229 mutex_lock(&pfvf->mbox.lock); 230 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 231 if (!req) { 232 mutex_unlock(&pfvf->mbox.lock); 233 return -ENOMEM; 234 } 235 236 req->maxlen = pfvf->max_frs; 237 238 err = otx2_sync_mbox_msg(&pfvf->mbox); 239 mutex_unlock(&pfvf->mbox.lock); 240 return err; 241 } 242 243 int otx2_config_pause_frm(struct otx2_nic *pfvf) 244 { 245 struct cgx_pause_frm_cfg *req; 246 int err; 247 248 if (is_otx2_lbkvf(pfvf->pdev)) 249 return 0; 250 251 mutex_lock(&pfvf->mbox.lock); 252 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 253 if (!req) { 254 err = -ENOMEM; 255 goto unlock; 256 } 257 258 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 259 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 260 req->set = 1; 261 262 err = otx2_sync_mbox_msg(&pfvf->mbox); 263 unlock: 264 mutex_unlock(&pfvf->mbox.lock); 265 return err; 266 } 267 268 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 269 { 270 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 271 struct nix_rss_flowkey_cfg *req; 272 int err; 273 274 mutex_lock(&pfvf->mbox.lock); 275 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 276 if (!req) { 277 mutex_unlock(&pfvf->mbox.lock); 278 return -ENOMEM; 279 } 280 req->mcam_index = -1; /* Default or reserved index */ 281 req->flowkey_cfg = rss->flowkey_cfg; 282 req->group = DEFAULT_RSS_CONTEXT_GROUP; 283 284 err = otx2_sync_mbox_msg(&pfvf->mbox); 285 mutex_unlock(&pfvf->mbox.lock); 286 return err; 287 } 288 289 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 290 { 291 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 292 const int index = rss->rss_size * ctx_id; 293 struct mbox *mbox = &pfvf->mbox; 294 struct otx2_rss_ctx *rss_ctx; 295 struct nix_aq_enq_req *aq; 296 int idx, err; 297 298 mutex_lock(&mbox->lock); 299 rss_ctx = rss->rss_ctx[ctx_id]; 300 /* Get memory to put this msg */ 301 for (idx = 0; idx < rss->rss_size; idx++) { 302 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 303 if (!aq) { 304 /* The shared memory buffer can be full. 305 * Flush it and retry 306 */ 307 err = otx2_sync_mbox_msg(mbox); 308 if (err) { 309 mutex_unlock(&mbox->lock); 310 return err; 311 } 312 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 313 if (!aq) { 314 mutex_unlock(&mbox->lock); 315 return -ENOMEM; 316 } 317 } 318 319 aq->rss.rq = rss_ctx->ind_tbl[idx]; 320 321 /* Fill AQ info */ 322 aq->qidx = index + idx; 323 aq->ctype = NIX_AQ_CTYPE_RSS; 324 aq->op = NIX_AQ_INSTOP_INIT; 325 } 326 err = otx2_sync_mbox_msg(mbox); 327 mutex_unlock(&mbox->lock); 328 return err; 329 } 330 331 void otx2_set_rss_key(struct otx2_nic *pfvf) 332 { 333 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 334 u64 *key = (u64 *)&rss->key[4]; 335 int idx; 336 337 /* 352bit or 44byte key needs to be configured as below 338 * NIX_LF_RX_SECRETX0 = key<351:288> 339 * NIX_LF_RX_SECRETX1 = key<287:224> 340 * NIX_LF_RX_SECRETX2 = key<223:160> 341 * NIX_LF_RX_SECRETX3 = key<159:96> 342 * NIX_LF_RX_SECRETX4 = key<95:32> 343 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 344 */ 345 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 346 (u64)(*((u32 *)&rss->key)) << 32); 347 idx = sizeof(rss->key) / sizeof(u64); 348 while (idx > 0) { 349 idx--; 350 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 351 } 352 } 353 354 int otx2_rss_init(struct otx2_nic *pfvf) 355 { 356 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 357 struct otx2_rss_ctx *rss_ctx; 358 int idx, ret = 0; 359 360 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 361 362 /* Init RSS key if it is not setup already */ 363 if (!rss->enable) 364 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 365 otx2_set_rss_key(pfvf); 366 367 if (!netif_is_rxfh_configured(pfvf->netdev)) { 368 /* Set RSS group 0 as default indirection table */ 369 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 370 GFP_KERNEL); 371 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 372 return -ENOMEM; 373 374 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 375 for (idx = 0; idx < rss->rss_size; idx++) 376 rss_ctx->ind_tbl[idx] = 377 ethtool_rxfh_indir_default(idx, 378 pfvf->hw.rx_queues); 379 } 380 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 381 if (ret) 382 return ret; 383 384 /* Flowkey or hash config to be used for generating flow tag */ 385 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 386 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 387 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 388 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 389 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 390 391 ret = otx2_set_flowkey_cfg(pfvf); 392 if (ret) 393 return ret; 394 395 rss->enable = true; 396 return 0; 397 } 398 399 /* Setup UDP segmentation algorithm in HW */ 400 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 401 { 402 struct nix_lso_format *field; 403 404 field = (struct nix_lso_format *)&lso->fields[0]; 405 lso->field_mask = GENMASK(18, 0); 406 407 /* IP's Length field */ 408 field->layer = NIX_TXLAYER_OL3; 409 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 410 field->offset = v4 ? 2 : 4; 411 field->sizem1 = 1; /* i.e 2 bytes */ 412 field->alg = NIX_LSOALG_ADD_PAYLEN; 413 field++; 414 415 /* No ID field in IPv6 header */ 416 if (v4) { 417 /* Increment IPID */ 418 field->layer = NIX_TXLAYER_OL3; 419 field->offset = 4; 420 field->sizem1 = 1; /* i.e 2 bytes */ 421 field->alg = NIX_LSOALG_ADD_SEGNUM; 422 field++; 423 } 424 425 /* Update length in UDP header */ 426 field->layer = NIX_TXLAYER_OL4; 427 field->offset = 4; 428 field->sizem1 = 1; 429 field->alg = NIX_LSOALG_ADD_PAYLEN; 430 } 431 432 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 433 void otx2_setup_segmentation(struct otx2_nic *pfvf) 434 { 435 struct nix_lso_format_cfg_rsp *rsp; 436 struct nix_lso_format_cfg *lso; 437 struct otx2_hw *hw = &pfvf->hw; 438 int err; 439 440 mutex_lock(&pfvf->mbox.lock); 441 442 /* UDPv4 segmentation */ 443 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 444 if (!lso) 445 goto fail; 446 447 /* Setup UDP/IP header fields that HW should update per segment */ 448 otx2_setup_udp_segmentation(lso, true); 449 450 err = otx2_sync_mbox_msg(&pfvf->mbox); 451 if (err) 452 goto fail; 453 454 rsp = (struct nix_lso_format_cfg_rsp *) 455 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 456 if (IS_ERR(rsp)) 457 goto fail; 458 459 hw->lso_udpv4_idx = rsp->lso_format_idx; 460 461 /* UDPv6 segmentation */ 462 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 463 if (!lso) 464 goto fail; 465 466 /* Setup UDP/IP header fields that HW should update per segment */ 467 otx2_setup_udp_segmentation(lso, false); 468 469 err = otx2_sync_mbox_msg(&pfvf->mbox); 470 if (err) 471 goto fail; 472 473 rsp = (struct nix_lso_format_cfg_rsp *) 474 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 475 if (IS_ERR(rsp)) 476 goto fail; 477 478 hw->lso_udpv6_idx = rsp->lso_format_idx; 479 mutex_unlock(&pfvf->mbox.lock); 480 return; 481 fail: 482 mutex_unlock(&pfvf->mbox.lock); 483 netdev_info(pfvf->netdev, 484 "Failed to get LSO index for UDP GSO offload, disabling\n"); 485 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 486 } 487 488 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 489 { 490 /* Configure CQE interrupt coalescing parameters 491 * 492 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 493 * set 1 less than cq_ecount_wait. And cq_time_wait is in 494 * usecs, convert that to 100ns count. 495 */ 496 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 497 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 498 ((u64)pfvf->hw.cq_qcount_wait << 32) | 499 (pfvf->hw.cq_ecount_wait - 1)); 500 } 501 502 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 503 dma_addr_t *dma) 504 { 505 u8 *buf; 506 507 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 508 if (unlikely(!buf)) 509 return -ENOMEM; 510 511 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 512 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 513 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 514 page_frag_free(buf); 515 return -ENOMEM; 516 } 517 518 return 0; 519 } 520 521 static int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 522 dma_addr_t *dma) 523 { 524 int ret; 525 526 local_bh_disable(); 527 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 528 local_bh_enable(); 529 return ret; 530 } 531 532 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 533 dma_addr_t *dma) 534 { 535 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) { 536 struct refill_work *work; 537 struct delayed_work *dwork; 538 539 work = &pfvf->refill_wrk[cq->cq_idx]; 540 dwork = &work->pool_refill_work; 541 /* Schedule a task if no other task is running */ 542 if (!cq->refill_task_sched) { 543 cq->refill_task_sched = true; 544 schedule_delayed_work(dwork, 545 msecs_to_jiffies(100)); 546 } 547 return -ENOMEM; 548 } 549 return 0; 550 } 551 552 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 553 { 554 struct otx2_nic *pfvf = netdev_priv(netdev); 555 556 schedule_work(&pfvf->reset_task); 557 } 558 EXPORT_SYMBOL(otx2_tx_timeout); 559 560 void otx2_get_mac_from_af(struct net_device *netdev) 561 { 562 struct otx2_nic *pfvf = netdev_priv(netdev); 563 int err; 564 565 err = otx2_hw_get_mac_addr(pfvf, netdev); 566 if (err) 567 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 568 569 /* If AF doesn't provide a valid MAC, generate a random one */ 570 if (!is_valid_ether_addr(netdev->dev_addr)) 571 eth_hw_addr_random(netdev); 572 } 573 EXPORT_SYMBOL(otx2_get_mac_from_af); 574 575 static int otx2_get_link(struct otx2_nic *pfvf) 576 { 577 int link = 0; 578 u16 map; 579 580 /* cgx lmac link */ 581 if (pfvf->hw.tx_chan_base >= CGX_CHAN_BASE) { 582 map = pfvf->hw.tx_chan_base & 0x7FF; 583 link = 4 * ((map >> 8) & 0xF) + ((map >> 4) & 0xF); 584 } 585 /* LBK channel */ 586 if (pfvf->hw.tx_chan_base < SDP_CHAN_BASE) { 587 map = pfvf->hw.tx_chan_base & 0x7FF; 588 link = pfvf->hw.cgx_links | ((map >> 8) & 0xF); 589 } 590 591 return link; 592 } 593 594 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl) 595 { 596 struct otx2_hw *hw = &pfvf->hw; 597 struct nix_txschq_config *req; 598 u64 schq, parent; 599 600 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 601 if (!req) 602 return -ENOMEM; 603 604 req->lvl = lvl; 605 req->num_regs = 1; 606 607 schq = hw->txschq_list[lvl][0]; 608 /* Set topology e.t.c configuration */ 609 if (lvl == NIX_TXSCH_LVL_SMQ) { 610 req->reg[0] = NIX_AF_SMQX_CFG(schq); 611 req->regval[0] = ((pfvf->netdev->max_mtu + OTX2_ETH_HLEN) << 8) 612 | OTX2_MIN_MTU; 613 614 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 615 (0x2ULL << 36); 616 req->num_regs++; 617 /* MDQ config */ 618 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0]; 619 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 620 req->regval[1] = parent << 16; 621 req->num_regs++; 622 /* Set DWRR quantum */ 623 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 624 req->regval[2] = DFLT_RR_QTM; 625 } else if (lvl == NIX_TXSCH_LVL_TL4) { 626 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0]; 627 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 628 req->regval[0] = parent << 16; 629 req->num_regs++; 630 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 631 req->regval[1] = DFLT_RR_QTM; 632 } else if (lvl == NIX_TXSCH_LVL_TL3) { 633 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0]; 634 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 635 req->regval[0] = parent << 16; 636 req->num_regs++; 637 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 638 req->regval[1] = DFLT_RR_QTM; 639 } else if (lvl == NIX_TXSCH_LVL_TL2) { 640 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0]; 641 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 642 req->regval[0] = parent << 16; 643 644 req->num_regs++; 645 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 646 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | DFLT_RR_QTM; 647 648 req->num_regs++; 649 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, 650 otx2_get_link(pfvf)); 651 /* Enable this queue and backpressure */ 652 req->regval[2] = BIT_ULL(13) | BIT_ULL(12); 653 654 } else if (lvl == NIX_TXSCH_LVL_TL1) { 655 /* Default config for TL1. 656 * For VF this is always ignored. 657 */ 658 659 /* Set DWRR quantum */ 660 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 661 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 662 663 req->num_regs++; 664 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 665 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 666 667 req->num_regs++; 668 req->reg[2] = NIX_AF_TL1X_CIR(schq); 669 req->regval[2] = 0; 670 } 671 672 return otx2_sync_mbox_msg(&pfvf->mbox); 673 } 674 675 int otx2_txsch_alloc(struct otx2_nic *pfvf) 676 { 677 struct nix_txsch_alloc_req *req; 678 int lvl; 679 680 /* Get memory to put this msg */ 681 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 682 if (!req) 683 return -ENOMEM; 684 685 /* Request one schq per level */ 686 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 687 req->schq[lvl] = 1; 688 689 return otx2_sync_mbox_msg(&pfvf->mbox); 690 } 691 692 int otx2_txschq_stop(struct otx2_nic *pfvf) 693 { 694 struct nix_txsch_free_req *free_req; 695 int lvl, schq, err; 696 697 mutex_lock(&pfvf->mbox.lock); 698 /* Free the transmit schedulers */ 699 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 700 if (!free_req) { 701 mutex_unlock(&pfvf->mbox.lock); 702 return -ENOMEM; 703 } 704 705 free_req->flags = TXSCHQ_FREE_ALL; 706 err = otx2_sync_mbox_msg(&pfvf->mbox); 707 mutex_unlock(&pfvf->mbox.lock); 708 709 /* Clear the txschq list */ 710 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 711 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 712 pfvf->hw.txschq_list[lvl][schq] = 0; 713 } 714 return err; 715 } 716 717 void otx2_sqb_flush(struct otx2_nic *pfvf) 718 { 719 int qidx, sqe_tail, sqe_head; 720 u64 incr, *ptr, val; 721 int timeout = 1000; 722 723 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 724 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 725 incr = (u64)qidx << 32; 726 while (timeout) { 727 val = otx2_atomic64_add(incr, ptr); 728 sqe_head = (val >> 20) & 0x3F; 729 sqe_tail = (val >> 28) & 0x3F; 730 if (sqe_head == sqe_tail) 731 break; 732 usleep_range(1, 3); 733 timeout--; 734 } 735 } 736 } 737 738 /* RED and drop levels of CQ on packet reception. 739 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 740 */ 741 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 742 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 743 744 /* RED and drop levels of AURA for packet reception. 745 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 746 * Eg: For RQ length 1K, for pass/drop level 204/230. 747 * RED accepts pkts if free pointers > 102 & <= 205. 748 * Drops pkts if free pointers < 102. 749 */ 750 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 751 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 752 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 753 754 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 755 { 756 struct otx2_qset *qset = &pfvf->qset; 757 struct nix_aq_enq_req *aq; 758 759 /* Get memory to put this msg */ 760 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 761 if (!aq) 762 return -ENOMEM; 763 764 aq->rq.cq = qidx; 765 aq->rq.ena = 1; 766 aq->rq.pb_caching = 1; 767 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 768 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 769 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 770 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 771 aq->rq.qint_idx = 0; 772 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 773 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 774 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 775 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 776 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 777 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 778 779 /* Fill AQ info */ 780 aq->qidx = qidx; 781 aq->ctype = NIX_AQ_CTYPE_RQ; 782 aq->op = NIX_AQ_INSTOP_INIT; 783 784 return otx2_sync_mbox_msg(&pfvf->mbox); 785 } 786 787 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 788 { 789 struct otx2_nic *pfvf = dev; 790 struct otx2_snd_queue *sq; 791 struct nix_aq_enq_req *aq; 792 793 sq = &pfvf->qset.sq[qidx]; 794 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 795 /* Get memory to put this msg */ 796 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 797 if (!aq) 798 return -ENOMEM; 799 800 aq->sq.cq = pfvf->hw.rx_queues + qidx; 801 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 802 aq->sq.cq_ena = 1; 803 aq->sq.ena = 1; 804 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 805 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 806 aq->sq.smq_rr_quantum = DFLT_RR_QTM; 807 aq->sq.default_chan = pfvf->hw.tx_chan_base; 808 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 809 aq->sq.sqb_aura = sqb_aura; 810 aq->sq.sq_int_ena = NIX_SQINT_BITS; 811 aq->sq.qint_idx = 0; 812 /* Due pipelining impact minimum 2000 unused SQ CQE's 813 * need to maintain to avoid CQ overflow. 814 */ 815 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 816 817 /* Fill AQ info */ 818 aq->qidx = qidx; 819 aq->ctype = NIX_AQ_CTYPE_SQ; 820 aq->op = NIX_AQ_INSTOP_INIT; 821 822 return otx2_sync_mbox_msg(&pfvf->mbox); 823 } 824 825 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 826 { 827 struct otx2_qset *qset = &pfvf->qset; 828 struct otx2_snd_queue *sq; 829 struct otx2_pool *pool; 830 int err; 831 832 pool = &pfvf->qset.pool[sqb_aura]; 833 sq = &qset->sq[qidx]; 834 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 835 sq->sqe_cnt = qset->sqe_cnt; 836 837 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 838 if (err) 839 return err; 840 841 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 842 TSO_HEADER_SIZE); 843 if (err) 844 return err; 845 846 sq->sqe_base = sq->sqe->base; 847 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 848 if (!sq->sg) 849 return -ENOMEM; 850 851 if (pfvf->ptp) { 852 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 853 sizeof(*sq->timestamps)); 854 if (err) 855 return err; 856 } 857 858 sq->head = 0; 859 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 860 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 861 /* Set SQE threshold to 10% of total SQEs */ 862 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 863 sq->aura_id = sqb_aura; 864 sq->aura_fc_addr = pool->fc_addr->base; 865 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 866 867 sq->stats.bytes = 0; 868 sq->stats.pkts = 0; 869 870 return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); 871 872 } 873 874 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 875 { 876 struct otx2_qset *qset = &pfvf->qset; 877 struct nix_aq_enq_req *aq; 878 struct otx2_cq_queue *cq; 879 int err, pool_id; 880 881 cq = &qset->cq[qidx]; 882 cq->cq_idx = qidx; 883 if (qidx < pfvf->hw.rx_queues) { 884 cq->cq_type = CQ_RX; 885 cq->cint_idx = qidx; 886 cq->cqe_cnt = qset->rqe_cnt; 887 } else { 888 cq->cq_type = CQ_TX; 889 cq->cint_idx = qidx - pfvf->hw.rx_queues; 890 cq->cqe_cnt = qset->sqe_cnt; 891 } 892 cq->cqe_size = pfvf->qset.xqe_size; 893 894 /* Allocate memory for CQEs */ 895 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 896 if (err) 897 return err; 898 899 /* Save CQE CPU base for faster reference */ 900 cq->cqe_base = cq->cqe->base; 901 /* In case where all RQs auras point to single pool, 902 * all CQs receive buffer pool also point to same pool. 903 */ 904 pool_id = ((cq->cq_type == CQ_RX) && 905 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 906 cq->rbpool = &qset->pool[pool_id]; 907 cq->refill_task_sched = false; 908 909 /* Get memory to put this msg */ 910 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 911 if (!aq) 912 return -ENOMEM; 913 914 aq->cq.ena = 1; 915 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 916 aq->cq.caching = 1; 917 aq->cq.base = cq->cqe->iova; 918 aq->cq.cint_idx = cq->cint_idx; 919 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 920 aq->cq.qint_idx = 0; 921 aq->cq.avg_level = 255; 922 923 if (qidx < pfvf->hw.rx_queues) { 924 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 925 aq->cq.drop_ena = 1; 926 927 /* Enable receive CQ backpressure */ 928 aq->cq.bp_ena = 1; 929 aq->cq.bpid = pfvf->bpid[0]; 930 931 /* Set backpressure level is same as cq pass level */ 932 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 933 } 934 935 /* Fill AQ info */ 936 aq->qidx = qidx; 937 aq->ctype = NIX_AQ_CTYPE_CQ; 938 aq->op = NIX_AQ_INSTOP_INIT; 939 940 return otx2_sync_mbox_msg(&pfvf->mbox); 941 } 942 943 static void otx2_pool_refill_task(struct work_struct *work) 944 { 945 struct otx2_cq_queue *cq; 946 struct otx2_pool *rbpool; 947 struct refill_work *wrk; 948 int qidx, free_ptrs = 0; 949 struct otx2_nic *pfvf; 950 dma_addr_t bufptr; 951 952 wrk = container_of(work, struct refill_work, pool_refill_work.work); 953 pfvf = wrk->pf; 954 qidx = wrk - pfvf->refill_wrk; 955 cq = &pfvf->qset.cq[qidx]; 956 rbpool = cq->rbpool; 957 free_ptrs = cq->pool_ptrs; 958 959 while (cq->pool_ptrs) { 960 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) { 961 /* Schedule a WQ if we fails to free atleast half of the 962 * pointers else enable napi for this RQ. 963 */ 964 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 965 struct delayed_work *dwork; 966 967 dwork = &wrk->pool_refill_work; 968 schedule_delayed_work(dwork, 969 msecs_to_jiffies(100)); 970 } else { 971 cq->refill_task_sched = false; 972 } 973 return; 974 } 975 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 976 cq->pool_ptrs--; 977 } 978 cq->refill_task_sched = false; 979 } 980 981 int otx2_config_nix_queues(struct otx2_nic *pfvf) 982 { 983 int qidx, err; 984 985 /* Initialize RX queues */ 986 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 987 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 988 989 err = otx2_rq_init(pfvf, qidx, lpb_aura); 990 if (err) 991 return err; 992 } 993 994 /* Initialize TX queues */ 995 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 996 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 997 998 err = otx2_sq_init(pfvf, qidx, sqb_aura); 999 if (err) 1000 return err; 1001 } 1002 1003 /* Initialize completion queues */ 1004 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1005 err = otx2_cq_init(pfvf, qidx); 1006 if (err) 1007 return err; 1008 } 1009 1010 /* Initialize work queue for receive buffer refill */ 1011 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1012 sizeof(struct refill_work), GFP_KERNEL); 1013 if (!pfvf->refill_wrk) 1014 return -ENOMEM; 1015 1016 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1017 pfvf->refill_wrk[qidx].pf = pfvf; 1018 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1019 otx2_pool_refill_task); 1020 } 1021 return 0; 1022 } 1023 1024 int otx2_config_nix(struct otx2_nic *pfvf) 1025 { 1026 struct nix_lf_alloc_req *nixlf; 1027 struct nix_lf_alloc_rsp *rsp; 1028 int err; 1029 1030 pfvf->qset.xqe_size = NIX_XQESZ_W16 ? 128 : 512; 1031 1032 /* Get memory to put this msg */ 1033 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1034 if (!nixlf) 1035 return -ENOMEM; 1036 1037 /* Set RQ/SQ/CQ counts */ 1038 nixlf->rq_cnt = pfvf->hw.rx_queues; 1039 nixlf->sq_cnt = pfvf->hw.tx_queues; 1040 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1041 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1042 nixlf->rss_grps = MAX_RSS_GROUPS; 1043 nixlf->xqe_sz = NIX_XQESZ_W16; 1044 /* We don't know absolute NPA LF idx attached. 1045 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1046 * NPA LF attached to this RVU PF/VF. 1047 */ 1048 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1049 /* Disable alignment pad, enable L2 length check, 1050 * enable L4 TCP/UDP checksum verification. 1051 */ 1052 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1053 1054 err = otx2_sync_mbox_msg(&pfvf->mbox); 1055 if (err) 1056 return err; 1057 1058 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1059 &nixlf->hdr); 1060 if (IS_ERR(rsp)) 1061 return PTR_ERR(rsp); 1062 1063 if (rsp->qints < 1) 1064 return -ENXIO; 1065 1066 return rsp->hdr.rc; 1067 } 1068 1069 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1070 { 1071 struct otx2_qset *qset = &pfvf->qset; 1072 struct otx2_hw *hw = &pfvf->hw; 1073 struct otx2_snd_queue *sq; 1074 int sqb, qidx; 1075 u64 iova, pa; 1076 1077 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1078 sq = &qset->sq[qidx]; 1079 if (!sq->sqb_ptrs) 1080 continue; 1081 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1082 if (!sq->sqb_ptrs[sqb]) 1083 continue; 1084 iova = sq->sqb_ptrs[sqb]; 1085 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1086 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1087 DMA_FROM_DEVICE, 1088 DMA_ATTR_SKIP_CPU_SYNC); 1089 put_page(virt_to_page(phys_to_virt(pa))); 1090 } 1091 sq->sqb_count = 0; 1092 } 1093 } 1094 1095 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1096 { 1097 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1098 u64 iova, pa; 1099 1100 if (type == AURA_NIX_SQ) { 1101 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1102 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1103 size = pfvf->hw.sqb_size; 1104 } 1105 if (type == AURA_NIX_RQ) { 1106 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1107 pool_end = pfvf->hw.rqpool_cnt; 1108 size = pfvf->rbsize; 1109 } 1110 1111 /* Free SQB and RQB pointers from the aura pool */ 1112 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1113 iova = otx2_aura_allocptr(pfvf, pool_id); 1114 while (iova) { 1115 if (type == AURA_NIX_RQ) 1116 iova -= OTX2_HEAD_ROOM; 1117 1118 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1119 dma_unmap_page_attrs(pfvf->dev, iova, size, 1120 DMA_FROM_DEVICE, 1121 DMA_ATTR_SKIP_CPU_SYNC); 1122 put_page(virt_to_page(phys_to_virt(pa))); 1123 iova = otx2_aura_allocptr(pfvf, pool_id); 1124 } 1125 } 1126 } 1127 1128 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1129 { 1130 struct otx2_pool *pool; 1131 int pool_id; 1132 1133 if (!pfvf->qset.pool) 1134 return; 1135 1136 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1137 pool = &pfvf->qset.pool[pool_id]; 1138 qmem_free(pfvf->dev, pool->stack); 1139 qmem_free(pfvf->dev, pool->fc_addr); 1140 } 1141 devm_kfree(pfvf->dev, pfvf->qset.pool); 1142 pfvf->qset.pool = NULL; 1143 } 1144 1145 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1146 int pool_id, int numptrs) 1147 { 1148 struct npa_aq_enq_req *aq; 1149 struct otx2_pool *pool; 1150 int err; 1151 1152 pool = &pfvf->qset.pool[pool_id]; 1153 1154 /* Allocate memory for HW to update Aura count. 1155 * Alloc one cache line, so that it fits all FC_STYPE modes. 1156 */ 1157 if (!pool->fc_addr) { 1158 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1159 if (err) 1160 return err; 1161 } 1162 1163 /* Initialize this aura's context via AF */ 1164 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1165 if (!aq) { 1166 /* Shared mbox memory buffer is full, flush it and retry */ 1167 err = otx2_sync_mbox_msg(&pfvf->mbox); 1168 if (err) 1169 return err; 1170 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1171 if (!aq) 1172 return -ENOMEM; 1173 } 1174 1175 aq->aura_id = aura_id; 1176 /* Will be filled by AF with correct pool context address */ 1177 aq->aura.pool_addr = pool_id; 1178 aq->aura.pool_caching = 1; 1179 aq->aura.shift = ilog2(numptrs) - 8; 1180 aq->aura.count = numptrs; 1181 aq->aura.limit = numptrs; 1182 aq->aura.avg_level = 255; 1183 aq->aura.ena = 1; 1184 aq->aura.fc_ena = 1; 1185 aq->aura.fc_addr = pool->fc_addr->iova; 1186 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1187 1188 /* Enable backpressure for RQ aura */ 1189 if (aura_id < pfvf->hw.rqpool_cnt) { 1190 aq->aura.bp_ena = 0; 1191 aq->aura.nix0_bpid = pfvf->bpid[0]; 1192 /* Set backpressure level for RQ's Aura */ 1193 aq->aura.bp = RQ_BP_LVL_AURA; 1194 } 1195 1196 /* Fill AQ info */ 1197 aq->ctype = NPA_AQ_CTYPE_AURA; 1198 aq->op = NPA_AQ_INSTOP_INIT; 1199 1200 return 0; 1201 } 1202 1203 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1204 int stack_pages, int numptrs, int buf_size) 1205 { 1206 struct npa_aq_enq_req *aq; 1207 struct otx2_pool *pool; 1208 int err; 1209 1210 pool = &pfvf->qset.pool[pool_id]; 1211 /* Alloc memory for stack which is used to store buffer pointers */ 1212 err = qmem_alloc(pfvf->dev, &pool->stack, 1213 stack_pages, pfvf->hw.stack_pg_bytes); 1214 if (err) 1215 return err; 1216 1217 pool->rbsize = buf_size; 1218 1219 /* Set LMTST addr for NPA batch free */ 1220 if (test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) 1221 pool->lmt_addr = (__force u64 *)((u64)pfvf->hw.npa_lmt_base + 1222 (pool_id * LMT_LINE_SIZE)); 1223 1224 /* Initialize this pool's context via AF */ 1225 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1226 if (!aq) { 1227 /* Shared mbox memory buffer is full, flush it and retry */ 1228 err = otx2_sync_mbox_msg(&pfvf->mbox); 1229 if (err) { 1230 qmem_free(pfvf->dev, pool->stack); 1231 return err; 1232 } 1233 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1234 if (!aq) { 1235 qmem_free(pfvf->dev, pool->stack); 1236 return -ENOMEM; 1237 } 1238 } 1239 1240 aq->aura_id = pool_id; 1241 aq->pool.stack_base = pool->stack->iova; 1242 aq->pool.stack_caching = 1; 1243 aq->pool.ena = 1; 1244 aq->pool.buf_size = buf_size / 128; 1245 aq->pool.stack_max_pages = stack_pages; 1246 aq->pool.shift = ilog2(numptrs) - 8; 1247 aq->pool.ptr_start = 0; 1248 aq->pool.ptr_end = ~0ULL; 1249 1250 /* Fill AQ info */ 1251 aq->ctype = NPA_AQ_CTYPE_POOL; 1252 aq->op = NPA_AQ_INSTOP_INIT; 1253 1254 return 0; 1255 } 1256 1257 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1258 { 1259 int qidx, pool_id, stack_pages, num_sqbs; 1260 struct otx2_qset *qset = &pfvf->qset; 1261 struct otx2_hw *hw = &pfvf->hw; 1262 struct otx2_snd_queue *sq; 1263 struct otx2_pool *pool; 1264 dma_addr_t bufptr; 1265 int err, ptr; 1266 1267 /* Calculate number of SQBs needed. 1268 * 1269 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1270 * Last SQE is used for pointing to next SQB. 1271 */ 1272 num_sqbs = (hw->sqb_size / 128) - 1; 1273 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1274 1275 /* Get no of stack pages needed */ 1276 stack_pages = 1277 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1278 1279 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1280 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1281 /* Initialize aura context */ 1282 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1283 if (err) 1284 goto fail; 1285 1286 /* Initialize pool context */ 1287 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1288 num_sqbs, hw->sqb_size); 1289 if (err) 1290 goto fail; 1291 } 1292 1293 /* Flush accumulated messages */ 1294 err = otx2_sync_mbox_msg(&pfvf->mbox); 1295 if (err) 1296 goto fail; 1297 1298 /* Allocate pointers and free them to aura/pool */ 1299 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1300 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1301 pool = &pfvf->qset.pool[pool_id]; 1302 1303 sq = &qset->sq[qidx]; 1304 sq->sqb_count = 0; 1305 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1306 if (!sq->sqb_ptrs) 1307 return -ENOMEM; 1308 1309 for (ptr = 0; ptr < num_sqbs; ptr++) { 1310 if (otx2_alloc_rbuf(pfvf, pool, &bufptr)) 1311 return -ENOMEM; 1312 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1313 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1314 } 1315 } 1316 1317 return 0; 1318 fail: 1319 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1320 otx2_aura_pool_free(pfvf); 1321 return err; 1322 } 1323 1324 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1325 { 1326 struct otx2_hw *hw = &pfvf->hw; 1327 int stack_pages, pool_id, rq; 1328 struct otx2_pool *pool; 1329 int err, ptr, num_ptrs; 1330 dma_addr_t bufptr; 1331 1332 num_ptrs = pfvf->qset.rqe_cnt; 1333 1334 stack_pages = 1335 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1336 1337 for (rq = 0; rq < hw->rx_queues; rq++) { 1338 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1339 /* Initialize aura context */ 1340 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1341 if (err) 1342 goto fail; 1343 } 1344 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1345 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1346 num_ptrs, pfvf->rbsize); 1347 if (err) 1348 goto fail; 1349 } 1350 1351 /* Flush accumulated messages */ 1352 err = otx2_sync_mbox_msg(&pfvf->mbox); 1353 if (err) 1354 goto fail; 1355 1356 /* Allocate pointers and free them to aura/pool */ 1357 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1358 pool = &pfvf->qset.pool[pool_id]; 1359 for (ptr = 0; ptr < num_ptrs; ptr++) { 1360 if (otx2_alloc_rbuf(pfvf, pool, &bufptr)) 1361 return -ENOMEM; 1362 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1363 bufptr + OTX2_HEAD_ROOM); 1364 } 1365 } 1366 1367 return 0; 1368 fail: 1369 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1370 otx2_aura_pool_free(pfvf); 1371 return err; 1372 } 1373 1374 int otx2_config_npa(struct otx2_nic *pfvf) 1375 { 1376 struct otx2_qset *qset = &pfvf->qset; 1377 struct npa_lf_alloc_req *npalf; 1378 struct otx2_hw *hw = &pfvf->hw; 1379 int aura_cnt; 1380 1381 /* Pool - Stack of free buffer pointers 1382 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1383 */ 1384 1385 if (!hw->pool_cnt) 1386 return -EINVAL; 1387 1388 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1389 sizeof(struct otx2_pool), GFP_KERNEL); 1390 if (!qset->pool) 1391 return -ENOMEM; 1392 1393 /* Get memory to put this msg */ 1394 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1395 if (!npalf) 1396 return -ENOMEM; 1397 1398 /* Set aura and pool counts */ 1399 npalf->nr_pools = hw->pool_cnt; 1400 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1401 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1402 1403 return otx2_sync_mbox_msg(&pfvf->mbox); 1404 } 1405 1406 int otx2_detach_resources(struct mbox *mbox) 1407 { 1408 struct rsrc_detach *detach; 1409 1410 mutex_lock(&mbox->lock); 1411 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1412 if (!detach) { 1413 mutex_unlock(&mbox->lock); 1414 return -ENOMEM; 1415 } 1416 1417 /* detach all */ 1418 detach->partial = false; 1419 1420 /* Send detach request to AF */ 1421 otx2_mbox_msg_send(&mbox->mbox, 0); 1422 mutex_unlock(&mbox->lock); 1423 return 0; 1424 } 1425 EXPORT_SYMBOL(otx2_detach_resources); 1426 1427 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1428 { 1429 struct rsrc_attach *attach; 1430 struct msg_req *msix; 1431 int err; 1432 1433 mutex_lock(&pfvf->mbox.lock); 1434 /* Get memory to put this msg */ 1435 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1436 if (!attach) { 1437 mutex_unlock(&pfvf->mbox.lock); 1438 return -ENOMEM; 1439 } 1440 1441 attach->npalf = true; 1442 attach->nixlf = true; 1443 1444 /* Send attach request to AF */ 1445 err = otx2_sync_mbox_msg(&pfvf->mbox); 1446 if (err) { 1447 mutex_unlock(&pfvf->mbox.lock); 1448 return err; 1449 } 1450 1451 pfvf->nix_blkaddr = BLKADDR_NIX0; 1452 1453 /* If the platform has two NIX blocks then LF may be 1454 * allocated from NIX1. 1455 */ 1456 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1457 pfvf->nix_blkaddr = BLKADDR_NIX1; 1458 1459 /* Get NPA and NIX MSIX vector offsets */ 1460 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1461 if (!msix) { 1462 mutex_unlock(&pfvf->mbox.lock); 1463 return -ENOMEM; 1464 } 1465 1466 err = otx2_sync_mbox_msg(&pfvf->mbox); 1467 if (err) { 1468 mutex_unlock(&pfvf->mbox.lock); 1469 return err; 1470 } 1471 mutex_unlock(&pfvf->mbox.lock); 1472 1473 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1474 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1475 dev_err(pfvf->dev, 1476 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1477 return -EINVAL; 1478 } 1479 1480 return 0; 1481 } 1482 EXPORT_SYMBOL(otx2_attach_npa_nix); 1483 1484 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1485 { 1486 struct hwctx_disable_req *req; 1487 1488 mutex_lock(&mbox->lock); 1489 /* Request AQ to disable this context */ 1490 if (npa) 1491 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1492 else 1493 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1494 1495 if (!req) { 1496 mutex_unlock(&mbox->lock); 1497 return; 1498 } 1499 1500 req->ctype = type; 1501 1502 if (otx2_sync_mbox_msg(mbox)) 1503 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1504 __func__); 1505 1506 mutex_unlock(&mbox->lock); 1507 } 1508 1509 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1510 { 1511 struct nix_bp_cfg_req *req; 1512 1513 if (enable) 1514 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1515 else 1516 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1517 1518 if (!req) 1519 return -ENOMEM; 1520 1521 req->chan_base = 0; 1522 req->chan_cnt = 1; 1523 req->bpid_per_chan = 0; 1524 1525 return otx2_sync_mbox_msg(&pfvf->mbox); 1526 } 1527 1528 /* Mbox message handlers */ 1529 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1530 struct cgx_stats_rsp *rsp) 1531 { 1532 int id; 1533 1534 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1535 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1536 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1537 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1538 } 1539 1540 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1541 struct cgx_fec_stats_rsp *rsp) 1542 { 1543 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1544 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1545 } 1546 1547 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1548 struct nix_txsch_alloc_rsp *rsp) 1549 { 1550 int lvl, schq; 1551 1552 /* Setup transmit scheduler list */ 1553 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 1554 for (schq = 0; schq < rsp->schq[lvl]; schq++) 1555 pf->hw.txschq_list[lvl][schq] = 1556 rsp->schq_list[lvl][schq]; 1557 } 1558 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc); 1559 1560 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1561 struct npa_lf_alloc_rsp *rsp) 1562 { 1563 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1564 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1565 } 1566 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1567 1568 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1569 struct nix_lf_alloc_rsp *rsp) 1570 { 1571 pfvf->hw.sqb_size = rsp->sqb_size; 1572 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1573 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1574 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1575 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1576 pfvf->hw.cgx_links = rsp->cgx_links; 1577 pfvf->hw.lbk_links = rsp->lbk_links; 1578 } 1579 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1580 1581 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1582 struct msix_offset_rsp *rsp) 1583 { 1584 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1585 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1586 } 1587 EXPORT_SYMBOL(mbox_handler_msix_offset); 1588 1589 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1590 struct nix_bp_cfg_rsp *rsp) 1591 { 1592 int chan, chan_id; 1593 1594 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1595 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1596 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1597 } 1598 } 1599 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1600 1601 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1602 { 1603 struct otx2_qset *qset = &pfvf->qset; 1604 struct otx2_hw *hw = &pfvf->hw; 1605 int irq, qidx; 1606 1607 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1608 qidx < n; 1609 qidx++, irq++) { 1610 int vector = pci_irq_vector(pfvf->pdev, irq); 1611 1612 irq_set_affinity_hint(vector, NULL); 1613 free_cpumask_var(hw->affinity_mask[irq]); 1614 free_irq(vector, &qset->napi[qidx]); 1615 } 1616 } 1617 1618 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1619 { 1620 struct otx2_hw *hw = &pfvf->hw; 1621 int vec, cpu, irq, cint; 1622 1623 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1624 cpu = cpumask_first(cpu_online_mask); 1625 1626 /* CQ interrupts */ 1627 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1628 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1629 return; 1630 1631 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1632 1633 irq = pci_irq_vector(pfvf->pdev, vec); 1634 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1635 1636 cpu = cpumask_next(cpu, cpu_online_mask); 1637 if (unlikely(cpu >= nr_cpu_ids)) 1638 cpu = 0; 1639 } 1640 } 1641 1642 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1643 { 1644 struct nix_hw_info *rsp; 1645 struct msg_req *req; 1646 u16 max_mtu; 1647 int rc; 1648 1649 mutex_lock(&pfvf->mbox.lock); 1650 1651 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1652 if (!req) { 1653 rc = -ENOMEM; 1654 goto out; 1655 } 1656 1657 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1658 if (!rc) { 1659 rsp = (struct nix_hw_info *) 1660 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1661 1662 /* HW counts VLAN insertion bytes (8 for double tag) 1663 * irrespective of whether SQE is requesting to insert VLAN 1664 * in the packet or not. Hence these 8 bytes have to be 1665 * discounted from max packet size otherwise HW will throw 1666 * SMQ errors 1667 */ 1668 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1669 } 1670 1671 out: 1672 mutex_unlock(&pfvf->mbox.lock); 1673 if (rc) { 1674 dev_warn(pfvf->dev, 1675 "Failed to get MTU from hardware setting default value(1500)\n"); 1676 max_mtu = 1500; 1677 } 1678 return max_mtu; 1679 } 1680 EXPORT_SYMBOL(otx2_get_max_mtu); 1681 1682 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1683 int __weak \ 1684 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1685 struct _req_type *req, \ 1686 struct _rsp_type *rsp) \ 1687 { \ 1688 /* Nothing to do here */ \ 1689 return 0; \ 1690 } \ 1691 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1692 MBOX_UP_CGX_MESSAGES 1693 #undef M 1694