1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Ethernet driver
3  *
4  * Copyright (C) 2020 Marvell.
5  *
6  */
7 
8 #include <linux/interrupt.h>
9 #include <linux/pci.h>
10 #include <net/page_pool/helpers.h>
11 #include <net/tso.h>
12 #include <linux/bitfield.h>
13 
14 #include "otx2_reg.h"
15 #include "otx2_common.h"
16 #include "otx2_struct.h"
17 #include "cn10k.h"
18 
19 static void otx2_nix_rq_op_stats(struct queue_stats *stats,
20 				 struct otx2_nic *pfvf, int qidx)
21 {
22 	u64 incr = (u64)qidx << 32;
23 	u64 *ptr;
24 
25 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS);
26 	stats->bytes = otx2_atomic64_add(incr, ptr);
27 
28 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS);
29 	stats->pkts = otx2_atomic64_add(incr, ptr);
30 }
31 
32 static void otx2_nix_sq_op_stats(struct queue_stats *stats,
33 				 struct otx2_nic *pfvf, int qidx)
34 {
35 	u64 incr = (u64)qidx << 32;
36 	u64 *ptr;
37 
38 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS);
39 	stats->bytes = otx2_atomic64_add(incr, ptr);
40 
41 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS);
42 	stats->pkts = otx2_atomic64_add(incr, ptr);
43 }
44 
45 void otx2_update_lmac_stats(struct otx2_nic *pfvf)
46 {
47 	struct msg_req *req;
48 
49 	if (!netif_running(pfvf->netdev))
50 		return;
51 
52 	mutex_lock(&pfvf->mbox.lock);
53 	req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox);
54 	if (!req) {
55 		mutex_unlock(&pfvf->mbox.lock);
56 		return;
57 	}
58 
59 	otx2_sync_mbox_msg(&pfvf->mbox);
60 	mutex_unlock(&pfvf->mbox.lock);
61 }
62 
63 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf)
64 {
65 	struct msg_req *req;
66 
67 	if (!netif_running(pfvf->netdev))
68 		return;
69 	mutex_lock(&pfvf->mbox.lock);
70 	req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox);
71 	if (req)
72 		otx2_sync_mbox_msg(&pfvf->mbox);
73 	mutex_unlock(&pfvf->mbox.lock);
74 }
75 
76 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx)
77 {
78 	struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx];
79 
80 	if (!pfvf->qset.rq)
81 		return 0;
82 
83 	otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx);
84 	return 1;
85 }
86 
87 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx)
88 {
89 	struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx];
90 
91 	if (!pfvf->qset.sq)
92 		return 0;
93 
94 	if (qidx >= pfvf->hw.non_qos_queues) {
95 		if (!test_bit(qidx - pfvf->hw.non_qos_queues, pfvf->qos.qos_sq_bmap))
96 			return 0;
97 	}
98 
99 	otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx);
100 	return 1;
101 }
102 
103 void otx2_get_dev_stats(struct otx2_nic *pfvf)
104 {
105 	struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats;
106 
107 	dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
108 	dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP);
109 	dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST);
110 	dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST);
111 	dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST);
112 	dev_stats->rx_frames = dev_stats->rx_bcast_frames +
113 			       dev_stats->rx_mcast_frames +
114 			       dev_stats->rx_ucast_frames;
115 
116 	dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);
117 	dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP);
118 	dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST);
119 	dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST);
120 	dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST);
121 	dev_stats->tx_frames = dev_stats->tx_bcast_frames +
122 			       dev_stats->tx_mcast_frames +
123 			       dev_stats->tx_ucast_frames;
124 }
125 
126 void otx2_get_stats64(struct net_device *netdev,
127 		      struct rtnl_link_stats64 *stats)
128 {
129 	struct otx2_nic *pfvf = netdev_priv(netdev);
130 	struct otx2_dev_stats *dev_stats;
131 
132 	otx2_get_dev_stats(pfvf);
133 
134 	dev_stats = &pfvf->hw.dev_stats;
135 	stats->rx_bytes = dev_stats->rx_bytes;
136 	stats->rx_packets = dev_stats->rx_frames;
137 	stats->rx_dropped = dev_stats->rx_drops;
138 	stats->multicast = dev_stats->rx_mcast_frames;
139 
140 	stats->tx_bytes = dev_stats->tx_bytes;
141 	stats->tx_packets = dev_stats->tx_frames;
142 	stats->tx_dropped = dev_stats->tx_drops;
143 }
144 EXPORT_SYMBOL(otx2_get_stats64);
145 
146 /* Sync MAC address with RVU AF */
147 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac)
148 {
149 	struct nix_set_mac_addr *req;
150 	int err;
151 
152 	mutex_lock(&pfvf->mbox.lock);
153 	req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox);
154 	if (!req) {
155 		mutex_unlock(&pfvf->mbox.lock);
156 		return -ENOMEM;
157 	}
158 
159 	ether_addr_copy(req->mac_addr, mac);
160 
161 	err = otx2_sync_mbox_msg(&pfvf->mbox);
162 	mutex_unlock(&pfvf->mbox.lock);
163 	return err;
164 }
165 
166 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf,
167 				struct net_device *netdev)
168 {
169 	struct nix_get_mac_addr_rsp *rsp;
170 	struct mbox_msghdr *msghdr;
171 	struct msg_req *req;
172 	int err;
173 
174 	mutex_lock(&pfvf->mbox.lock);
175 	req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox);
176 	if (!req) {
177 		mutex_unlock(&pfvf->mbox.lock);
178 		return -ENOMEM;
179 	}
180 
181 	err = otx2_sync_mbox_msg(&pfvf->mbox);
182 	if (err) {
183 		mutex_unlock(&pfvf->mbox.lock);
184 		return err;
185 	}
186 
187 	msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
188 	if (IS_ERR(msghdr)) {
189 		mutex_unlock(&pfvf->mbox.lock);
190 		return PTR_ERR(msghdr);
191 	}
192 	rsp = (struct nix_get_mac_addr_rsp *)msghdr;
193 	eth_hw_addr_set(netdev, rsp->mac_addr);
194 	mutex_unlock(&pfvf->mbox.lock);
195 
196 	return 0;
197 }
198 
199 int otx2_set_mac_address(struct net_device *netdev, void *p)
200 {
201 	struct otx2_nic *pfvf = netdev_priv(netdev);
202 	struct sockaddr *addr = p;
203 
204 	if (!is_valid_ether_addr(addr->sa_data))
205 		return -EADDRNOTAVAIL;
206 
207 	if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) {
208 		eth_hw_addr_set(netdev, addr->sa_data);
209 		/* update dmac field in vlan offload rule */
210 		if (netif_running(netdev) &&
211 		    pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT)
212 			otx2_install_rxvlan_offload_flow(pfvf);
213 		/* update dmac address in ntuple and DMAC filter list */
214 		if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT)
215 			otx2_dmacflt_update_pfmac_flow(pfvf);
216 	} else {
217 		return -EPERM;
218 	}
219 
220 	return 0;
221 }
222 EXPORT_SYMBOL(otx2_set_mac_address);
223 
224 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu)
225 {
226 	struct nix_frs_cfg *req;
227 	u16 maxlen;
228 	int err;
229 
230 	maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
231 
232 	mutex_lock(&pfvf->mbox.lock);
233 	req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox);
234 	if (!req) {
235 		mutex_unlock(&pfvf->mbox.lock);
236 		return -ENOMEM;
237 	}
238 
239 	req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN;
240 
241 	/* Use max receive length supported by hardware for loopback devices */
242 	if (is_otx2_lbkvf(pfvf->pdev))
243 		req->maxlen = maxlen;
244 
245 	err = otx2_sync_mbox_msg(&pfvf->mbox);
246 	mutex_unlock(&pfvf->mbox.lock);
247 	return err;
248 }
249 
250 int otx2_config_pause_frm(struct otx2_nic *pfvf)
251 {
252 	struct cgx_pause_frm_cfg *req;
253 	int err;
254 
255 	if (is_otx2_lbkvf(pfvf->pdev))
256 		return 0;
257 
258 	mutex_lock(&pfvf->mbox.lock);
259 	req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox);
260 	if (!req) {
261 		err = -ENOMEM;
262 		goto unlock;
263 	}
264 
265 	req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED);
266 	req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED);
267 	req->set = 1;
268 
269 	err = otx2_sync_mbox_msg(&pfvf->mbox);
270 unlock:
271 	mutex_unlock(&pfvf->mbox.lock);
272 	return err;
273 }
274 EXPORT_SYMBOL(otx2_config_pause_frm);
275 
276 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf)
277 {
278 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
279 	struct nix_rss_flowkey_cfg_rsp *rsp;
280 	struct nix_rss_flowkey_cfg *req;
281 	int err;
282 
283 	mutex_lock(&pfvf->mbox.lock);
284 	req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox);
285 	if (!req) {
286 		mutex_unlock(&pfvf->mbox.lock);
287 		return -ENOMEM;
288 	}
289 	req->mcam_index = -1; /* Default or reserved index */
290 	req->flowkey_cfg = rss->flowkey_cfg;
291 	req->group = DEFAULT_RSS_CONTEXT_GROUP;
292 
293 	err = otx2_sync_mbox_msg(&pfvf->mbox);
294 	if (err)
295 		goto fail;
296 
297 	rsp = (struct nix_rss_flowkey_cfg_rsp *)
298 			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
299 	if (IS_ERR(rsp)) {
300 		err = PTR_ERR(rsp);
301 		goto fail;
302 	}
303 
304 	pfvf->hw.flowkey_alg_idx = rsp->alg_idx;
305 fail:
306 	mutex_unlock(&pfvf->mbox.lock);
307 	return err;
308 }
309 
310 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id)
311 {
312 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
313 	const int index = rss->rss_size * ctx_id;
314 	struct mbox *mbox = &pfvf->mbox;
315 	struct otx2_rss_ctx *rss_ctx;
316 	struct nix_aq_enq_req *aq;
317 	int idx, err;
318 
319 	mutex_lock(&mbox->lock);
320 	rss_ctx = rss->rss_ctx[ctx_id];
321 	/* Get memory to put this msg */
322 	for (idx = 0; idx < rss->rss_size; idx++) {
323 		aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
324 		if (!aq) {
325 			/* The shared memory buffer can be full.
326 			 * Flush it and retry
327 			 */
328 			err = otx2_sync_mbox_msg(mbox);
329 			if (err) {
330 				mutex_unlock(&mbox->lock);
331 				return err;
332 			}
333 			aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
334 			if (!aq) {
335 				mutex_unlock(&mbox->lock);
336 				return -ENOMEM;
337 			}
338 		}
339 
340 		aq->rss.rq = rss_ctx->ind_tbl[idx];
341 
342 		/* Fill AQ info */
343 		aq->qidx = index + idx;
344 		aq->ctype = NIX_AQ_CTYPE_RSS;
345 		aq->op = NIX_AQ_INSTOP_INIT;
346 	}
347 	err = otx2_sync_mbox_msg(mbox);
348 	mutex_unlock(&mbox->lock);
349 	return err;
350 }
351 
352 void otx2_set_rss_key(struct otx2_nic *pfvf)
353 {
354 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
355 	u64 *key = (u64 *)&rss->key[4];
356 	int idx;
357 
358 	/* 352bit or 44byte key needs to be configured as below
359 	 * NIX_LF_RX_SECRETX0 = key<351:288>
360 	 * NIX_LF_RX_SECRETX1 = key<287:224>
361 	 * NIX_LF_RX_SECRETX2 = key<223:160>
362 	 * NIX_LF_RX_SECRETX3 = key<159:96>
363 	 * NIX_LF_RX_SECRETX4 = key<95:32>
364 	 * NIX_LF_RX_SECRETX5<63:32> = key<31:0>
365 	 */
366 	otx2_write64(pfvf, NIX_LF_RX_SECRETX(5),
367 		     (u64)(*((u32 *)&rss->key)) << 32);
368 	idx = sizeof(rss->key) / sizeof(u64);
369 	while (idx > 0) {
370 		idx--;
371 		otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++);
372 	}
373 }
374 
375 int otx2_rss_init(struct otx2_nic *pfvf)
376 {
377 	struct otx2_rss_info *rss = &pfvf->hw.rss_info;
378 	struct otx2_rss_ctx *rss_ctx;
379 	int idx, ret = 0;
380 
381 	rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]);
382 
383 	/* Init RSS key if it is not setup already */
384 	if (!rss->enable)
385 		netdev_rss_key_fill(rss->key, sizeof(rss->key));
386 	otx2_set_rss_key(pfvf);
387 
388 	if (!netif_is_rxfh_configured(pfvf->netdev)) {
389 		/* Set RSS group 0 as default indirection table */
390 		rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size,
391 								  GFP_KERNEL);
392 		if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP])
393 			return -ENOMEM;
394 
395 		rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP];
396 		for (idx = 0; idx < rss->rss_size; idx++)
397 			rss_ctx->ind_tbl[idx] =
398 				ethtool_rxfh_indir_default(idx,
399 							   pfvf->hw.rx_queues);
400 	}
401 	ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP);
402 	if (ret)
403 		return ret;
404 
405 	/* Flowkey or hash config to be used for generating flow tag */
406 	rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg :
407 			   NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 |
408 			   NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP |
409 			   NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN |
410 			   NIX_FLOW_KEY_TYPE_IPV4_PROTO;
411 
412 	ret = otx2_set_flowkey_cfg(pfvf);
413 	if (ret)
414 		return ret;
415 
416 	rss->enable = true;
417 	return 0;
418 }
419 
420 /* Setup UDP segmentation algorithm in HW */
421 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4)
422 {
423 	struct nix_lso_format *field;
424 
425 	field = (struct nix_lso_format *)&lso->fields[0];
426 	lso->field_mask = GENMASK(18, 0);
427 
428 	/* IP's Length field */
429 	field->layer = NIX_TXLAYER_OL3;
430 	/* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */
431 	field->offset = v4 ? 2 : 4;
432 	field->sizem1 = 1; /* i.e 2 bytes */
433 	field->alg = NIX_LSOALG_ADD_PAYLEN;
434 	field++;
435 
436 	/* No ID field in IPv6 header */
437 	if (v4) {
438 		/* Increment IPID */
439 		field->layer = NIX_TXLAYER_OL3;
440 		field->offset = 4;
441 		field->sizem1 = 1; /* i.e 2 bytes */
442 		field->alg = NIX_LSOALG_ADD_SEGNUM;
443 		field++;
444 	}
445 
446 	/* Update length in UDP header */
447 	field->layer = NIX_TXLAYER_OL4;
448 	field->offset = 4;
449 	field->sizem1 = 1;
450 	field->alg = NIX_LSOALG_ADD_PAYLEN;
451 }
452 
453 /* Setup segmentation algorithms in HW and retrieve algorithm index */
454 void otx2_setup_segmentation(struct otx2_nic *pfvf)
455 {
456 	struct nix_lso_format_cfg_rsp *rsp;
457 	struct nix_lso_format_cfg *lso;
458 	struct otx2_hw *hw = &pfvf->hw;
459 	int err;
460 
461 	mutex_lock(&pfvf->mbox.lock);
462 
463 	/* UDPv4 segmentation */
464 	lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
465 	if (!lso)
466 		goto fail;
467 
468 	/* Setup UDP/IP header fields that HW should update per segment */
469 	otx2_setup_udp_segmentation(lso, true);
470 
471 	err = otx2_sync_mbox_msg(&pfvf->mbox);
472 	if (err)
473 		goto fail;
474 
475 	rsp = (struct nix_lso_format_cfg_rsp *)
476 			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
477 	if (IS_ERR(rsp))
478 		goto fail;
479 
480 	hw->lso_udpv4_idx = rsp->lso_format_idx;
481 
482 	/* UDPv6 segmentation */
483 	lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox);
484 	if (!lso)
485 		goto fail;
486 
487 	/* Setup UDP/IP header fields that HW should update per segment */
488 	otx2_setup_udp_segmentation(lso, false);
489 
490 	err = otx2_sync_mbox_msg(&pfvf->mbox);
491 	if (err)
492 		goto fail;
493 
494 	rsp = (struct nix_lso_format_cfg_rsp *)
495 			otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr);
496 	if (IS_ERR(rsp))
497 		goto fail;
498 
499 	hw->lso_udpv6_idx = rsp->lso_format_idx;
500 	mutex_unlock(&pfvf->mbox.lock);
501 	return;
502 fail:
503 	mutex_unlock(&pfvf->mbox.lock);
504 	netdev_info(pfvf->netdev,
505 		    "Failed to get LSO index for UDP GSO offload, disabling\n");
506 	pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4;
507 }
508 
509 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx)
510 {
511 	/* Configure CQE interrupt coalescing parameters
512 	 *
513 	 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence
514 	 * set 1 less than cq_ecount_wait. And cq_time_wait is in
515 	 * usecs, convert that to 100ns count.
516 	 */
517 	otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx),
518 		     ((u64)(pfvf->hw.cq_time_wait * 10) << 48) |
519 		     ((u64)pfvf->hw.cq_qcount_wait << 32) |
520 		     (pfvf->hw.cq_ecount_wait - 1));
521 }
522 
523 static int otx2_alloc_pool_buf(struct otx2_nic *pfvf, struct otx2_pool *pool,
524 			       dma_addr_t *dma)
525 {
526 	unsigned int offset = 0;
527 	struct page *page;
528 	size_t sz;
529 
530 	sz = SKB_DATA_ALIGN(pool->rbsize);
531 	sz = ALIGN(sz, OTX2_ALIGN);
532 
533 	page = page_pool_alloc_frag(pool->page_pool, &offset, sz, GFP_ATOMIC);
534 	if (unlikely(!page))
535 		return -ENOMEM;
536 
537 	*dma = page_pool_get_dma_addr(page) + offset;
538 	return 0;
539 }
540 
541 static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
542 			     dma_addr_t *dma)
543 {
544 	u8 *buf;
545 
546 	if (pool->page_pool)
547 		return otx2_alloc_pool_buf(pfvf, pool, dma);
548 
549 	buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN);
550 	if (unlikely(!buf))
551 		return -ENOMEM;
552 
553 	*dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize,
554 				    DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
555 	if (unlikely(dma_mapping_error(pfvf->dev, *dma))) {
556 		page_frag_free(buf);
557 		return -ENOMEM;
558 	}
559 
560 	return 0;
561 }
562 
563 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
564 		    dma_addr_t *dma)
565 {
566 	int ret;
567 
568 	local_bh_disable();
569 	ret = __otx2_alloc_rbuf(pfvf, pool, dma);
570 	local_bh_enable();
571 	return ret;
572 }
573 
574 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
575 		      dma_addr_t *dma)
576 {
577 	if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma)))
578 		return -ENOMEM;
579 	return 0;
580 }
581 
582 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq)
583 {
584 	struct otx2_nic *pfvf = netdev_priv(netdev);
585 
586 	schedule_work(&pfvf->reset_task);
587 }
588 EXPORT_SYMBOL(otx2_tx_timeout);
589 
590 void otx2_get_mac_from_af(struct net_device *netdev)
591 {
592 	struct otx2_nic *pfvf = netdev_priv(netdev);
593 	int err;
594 
595 	err = otx2_hw_get_mac_addr(pfvf, netdev);
596 	if (err)
597 		dev_warn(pfvf->dev, "Failed to read mac from hardware\n");
598 
599 	/* If AF doesn't provide a valid MAC, generate a random one */
600 	if (!is_valid_ether_addr(netdev->dev_addr))
601 		eth_hw_addr_random(netdev);
602 }
603 EXPORT_SYMBOL(otx2_get_mac_from_af);
604 
605 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc)
606 {
607 	u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC];
608 	struct otx2_hw *hw = &pfvf->hw;
609 	struct nix_txschq_config *req;
610 	u64 schq, parent;
611 	u64 dwrr_val;
612 
613 	dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
614 
615 	req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
616 	if (!req)
617 		return -ENOMEM;
618 
619 	req->lvl = lvl;
620 	req->num_regs = 1;
621 
622 	schq_list = hw->txschq_list;
623 #ifdef CONFIG_DCB
624 	if (txschq_for_pfc)
625 		schq_list = pfvf->pfc_schq_list;
626 #endif
627 
628 	schq = schq_list[lvl][prio];
629 	/* Set topology e.t.c configuration */
630 	if (lvl == NIX_TXSCH_LVL_SMQ) {
631 		req->reg[0] = NIX_AF_SMQX_CFG(schq);
632 		req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU;
633 		req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) |
634 				  (0x2ULL << 36);
635 		/* Set link type for DWRR MTU selection on CN10K silicons */
636 		if (!is_dev_otx2(pfvf->pdev))
637 			req->regval[0] |= FIELD_PREP(GENMASK_ULL(58, 57),
638 						(u64)hw->smq_link_type);
639 		req->num_regs++;
640 		/* MDQ config */
641 		parent = schq_list[NIX_TXSCH_LVL_TL4][prio];
642 		req->reg[1] = NIX_AF_MDQX_PARENT(schq);
643 		req->regval[1] = parent << 16;
644 		req->num_regs++;
645 		/* Set DWRR quantum */
646 		req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq);
647 		req->regval[2] =  dwrr_val;
648 	} else if (lvl == NIX_TXSCH_LVL_TL4) {
649 		parent = schq_list[NIX_TXSCH_LVL_TL3][prio];
650 		req->reg[0] = NIX_AF_TL4X_PARENT(schq);
651 		req->regval[0] = parent << 16;
652 		req->num_regs++;
653 		req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq);
654 		req->regval[1] = dwrr_val;
655 	} else if (lvl == NIX_TXSCH_LVL_TL3) {
656 		parent = schq_list[NIX_TXSCH_LVL_TL2][prio];
657 		req->reg[0] = NIX_AF_TL3X_PARENT(schq);
658 		req->regval[0] = parent << 16;
659 		req->num_regs++;
660 		req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq);
661 		req->regval[1] = dwrr_val;
662 		if (lvl == hw->txschq_link_cfg_lvl) {
663 			req->num_regs++;
664 			req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
665 			/* Enable this queue and backpressure
666 			 * and set relative channel
667 			 */
668 			req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;
669 		}
670 	} else if (lvl == NIX_TXSCH_LVL_TL2) {
671 		parent = schq_list[NIX_TXSCH_LVL_TL1][prio];
672 		req->reg[0] = NIX_AF_TL2X_PARENT(schq);
673 		req->regval[0] = parent << 16;
674 
675 		req->num_regs++;
676 		req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq);
677 		req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val;
678 
679 		if (lvl == hw->txschq_link_cfg_lvl) {
680 			req->num_regs++;
681 			req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link);
682 			/* Enable this queue and backpressure
683 			 * and set relative channel
684 			 */
685 			req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio;
686 		}
687 	} else if (lvl == NIX_TXSCH_LVL_TL1) {
688 		/* Default config for TL1.
689 		 * For VF this is always ignored.
690 		 */
691 
692 		/* On CN10K, if RR_WEIGHT is greater than 16384, HW will
693 		 * clip it to 16384, so configuring a 24bit max value
694 		 * will work on both OTx2 and CN10K.
695 		 */
696 		req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);
697 		req->regval[0] = TXSCH_TL1_DFLT_RR_QTM;
698 
699 		req->num_regs++;
700 		req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);
701 		req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);
702 
703 		req->num_regs++;
704 		req->reg[2] = NIX_AF_TL1X_CIR(schq);
705 		req->regval[2] = 0;
706 	}
707 
708 	return otx2_sync_mbox_msg(&pfvf->mbox);
709 }
710 EXPORT_SYMBOL(otx2_txschq_config);
711 
712 int otx2_smq_flush(struct otx2_nic *pfvf, int smq)
713 {
714 	struct nix_txschq_config *req;
715 	int rc;
716 
717 	mutex_lock(&pfvf->mbox.lock);
718 
719 	req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox);
720 	if (!req) {
721 		mutex_unlock(&pfvf->mbox.lock);
722 		return -ENOMEM;
723 	}
724 
725 	req->lvl = NIX_TXSCH_LVL_SMQ;
726 	req->reg[0] = NIX_AF_SMQX_CFG(smq);
727 	req->regval[0] |= BIT_ULL(49);
728 	req->num_regs++;
729 
730 	rc = otx2_sync_mbox_msg(&pfvf->mbox);
731 	mutex_unlock(&pfvf->mbox.lock);
732 	return rc;
733 }
734 EXPORT_SYMBOL(otx2_smq_flush);
735 
736 int otx2_txsch_alloc(struct otx2_nic *pfvf)
737 {
738 	struct nix_txsch_alloc_req *req;
739 	struct nix_txsch_alloc_rsp *rsp;
740 	int lvl, schq, rc;
741 
742 	/* Get memory to put this msg */
743 	req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox);
744 	if (!req)
745 		return -ENOMEM;
746 
747 	/* Request one schq per level */
748 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
749 		req->schq[lvl] = 1;
750 	rc = otx2_sync_mbox_msg(&pfvf->mbox);
751 	if (rc)
752 		return rc;
753 
754 	rsp = (struct nix_txsch_alloc_rsp *)
755 	      otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
756 	if (IS_ERR(rsp))
757 		return PTR_ERR(rsp);
758 
759 	/* Setup transmit scheduler list */
760 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
761 		for (schq = 0; schq < rsp->schq[lvl]; schq++)
762 			pfvf->hw.txschq_list[lvl][schq] =
763 				rsp->schq_list[lvl][schq];
764 
765 	pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl;
766 	pfvf->hw.txschq_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio;
767 
768 	return 0;
769 }
770 
771 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq)
772 {
773 	struct nix_txsch_free_req *free_req;
774 	int err;
775 
776 	mutex_lock(&pfvf->mbox.lock);
777 
778 	free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox);
779 	if (!free_req) {
780 		mutex_unlock(&pfvf->mbox.lock);
781 		netdev_err(pfvf->netdev,
782 			   "Failed alloc txschq free req\n");
783 		return;
784 	}
785 
786 	free_req->schq_lvl = lvl;
787 	free_req->schq = schq;
788 
789 	err = otx2_sync_mbox_msg(&pfvf->mbox);
790 	if (err) {
791 		netdev_err(pfvf->netdev,
792 			   "Failed stop txschq %d at level %d\n", schq, lvl);
793 	}
794 
795 	mutex_unlock(&pfvf->mbox.lock);
796 }
797 EXPORT_SYMBOL(otx2_txschq_free_one);
798 
799 void otx2_txschq_stop(struct otx2_nic *pfvf)
800 {
801 	int lvl, schq;
802 
803 	/* free non QOS TLx nodes */
804 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++)
805 		otx2_txschq_free_one(pfvf, lvl,
806 				     pfvf->hw.txschq_list[lvl][0]);
807 
808 	/* Clear the txschq list */
809 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
810 		for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++)
811 			pfvf->hw.txschq_list[lvl][schq] = 0;
812 	}
813 
814 }
815 
816 void otx2_sqb_flush(struct otx2_nic *pfvf)
817 {
818 	int qidx, sqe_tail, sqe_head;
819 	struct otx2_snd_queue *sq;
820 	u64 incr, *ptr, val;
821 
822 	ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS);
823 	for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) {
824 		sq = &pfvf->qset.sq[qidx];
825 		if (!sq->sqb_ptrs)
826 			continue;
827 
828 		incr = (u64)qidx << 32;
829 		val = otx2_atomic64_add(incr, ptr);
830 		sqe_head = (val >> 20) & 0x3F;
831 		sqe_tail = (val >> 28) & 0x3F;
832 		if (sqe_head != sqe_tail)
833 			usleep_range(50, 60);
834 	}
835 }
836 
837 /* RED and drop levels of CQ on packet reception.
838  * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty).
839  */
840 #define RQ_PASS_LVL_CQ(skid, qsize)	((((skid) + 16) * 256) / (qsize))
841 #define RQ_DROP_LVL_CQ(skid, qsize)	(((skid) * 256) / (qsize))
842 
843 /* RED and drop levels of AURA for packet reception.
844  * For AURA level is measure of fullness (0x0 = empty, 255 = full).
845  * Eg: For RQ length 1K, for pass/drop level 204/230.
846  * RED accepts pkts if free pointers > 102 & <= 205.
847  * Drops pkts if free pointers < 102.
848  */
849 #define RQ_BP_LVL_AURA   (255 - ((85 * 256) / 100)) /* BP when 85% is full */
850 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */
851 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */
852 
853 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura)
854 {
855 	struct otx2_qset *qset = &pfvf->qset;
856 	struct nix_aq_enq_req *aq;
857 
858 	/* Get memory to put this msg */
859 	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
860 	if (!aq)
861 		return -ENOMEM;
862 
863 	aq->rq.cq = qidx;
864 	aq->rq.ena = 1;
865 	aq->rq.pb_caching = 1;
866 	aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */
867 	aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1;
868 	aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */
869 	aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */
870 	aq->rq.qint_idx = 0;
871 	aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */
872 	aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */
873 	aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
874 	aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
875 	aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA;
876 	aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA;
877 
878 	/* Fill AQ info */
879 	aq->qidx = qidx;
880 	aq->ctype = NIX_AQ_CTYPE_RQ;
881 	aq->op = NIX_AQ_INSTOP_INIT;
882 
883 	return otx2_sync_mbox_msg(&pfvf->mbox);
884 }
885 
886 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura)
887 {
888 	struct otx2_nic *pfvf = dev;
889 	struct otx2_snd_queue *sq;
890 	struct nix_aq_enq_req *aq;
891 
892 	sq = &pfvf->qset.sq[qidx];
893 	sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx));
894 	/* Get memory to put this msg */
895 	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
896 	if (!aq)
897 		return -ENOMEM;
898 
899 	aq->sq.cq = pfvf->hw.rx_queues + qidx;
900 	aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */
901 	aq->sq.cq_ena = 1;
902 	aq->sq.ena = 1;
903 	aq->sq.smq = otx2_get_smq_idx(pfvf, qidx);
904 	aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen);
905 	aq->sq.default_chan = pfvf->hw.tx_chan_base;
906 	aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */
907 	aq->sq.sqb_aura = sqb_aura;
908 	aq->sq.sq_int_ena = NIX_SQINT_BITS;
909 	aq->sq.qint_idx = 0;
910 	/* Due pipelining impact minimum 2000 unused SQ CQE's
911 	 * need to maintain to avoid CQ overflow.
912 	 */
913 	aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt));
914 
915 	/* Fill AQ info */
916 	aq->qidx = qidx;
917 	aq->ctype = NIX_AQ_CTYPE_SQ;
918 	aq->op = NIX_AQ_INSTOP_INIT;
919 
920 	return otx2_sync_mbox_msg(&pfvf->mbox);
921 }
922 
923 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura)
924 {
925 	struct otx2_qset *qset = &pfvf->qset;
926 	struct otx2_snd_queue *sq;
927 	struct otx2_pool *pool;
928 	int err;
929 
930 	pool = &pfvf->qset.pool[sqb_aura];
931 	sq = &qset->sq[qidx];
932 	sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128;
933 	sq->sqe_cnt = qset->sqe_cnt;
934 
935 	err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size);
936 	if (err)
937 		return err;
938 
939 	if (qidx < pfvf->hw.tx_queues) {
940 		err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt,
941 				 TSO_HEADER_SIZE);
942 		if (err)
943 			return err;
944 	}
945 
946 	sq->sqe_base = sq->sqe->base;
947 	sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL);
948 	if (!sq->sg)
949 		return -ENOMEM;
950 
951 	if (pfvf->ptp && qidx < pfvf->hw.tx_queues) {
952 		err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt,
953 				 sizeof(*sq->timestamps));
954 		if (err)
955 			return err;
956 	}
957 
958 	sq->head = 0;
959 	sq->cons_head = 0;
960 	sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1;
961 	sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb;
962 	/* Set SQE threshold to 10% of total SQEs */
963 	sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100;
964 	sq->aura_id = sqb_aura;
965 	sq->aura_fc_addr = pool->fc_addr->base;
966 	sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0));
967 
968 	sq->stats.bytes = 0;
969 	sq->stats.pkts = 0;
970 
971 	return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura);
972 
973 }
974 
975 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
976 {
977 	struct otx2_qset *qset = &pfvf->qset;
978 	int err, pool_id, non_xdp_queues;
979 	struct nix_aq_enq_req *aq;
980 	struct otx2_cq_queue *cq;
981 
982 	cq = &qset->cq[qidx];
983 	cq->cq_idx = qidx;
984 	non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues;
985 	if (qidx < pfvf->hw.rx_queues) {
986 		cq->cq_type = CQ_RX;
987 		cq->cint_idx = qidx;
988 		cq->cqe_cnt = qset->rqe_cnt;
989 		if (pfvf->xdp_prog)
990 			xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0);
991 	} else if (qidx < non_xdp_queues) {
992 		cq->cq_type = CQ_TX;
993 		cq->cint_idx = qidx - pfvf->hw.rx_queues;
994 		cq->cqe_cnt = qset->sqe_cnt;
995 	} else {
996 		if (pfvf->hw.xdp_queues &&
997 		    qidx < non_xdp_queues + pfvf->hw.xdp_queues) {
998 			cq->cq_type = CQ_XDP;
999 			cq->cint_idx = qidx - non_xdp_queues;
1000 			cq->cqe_cnt = qset->sqe_cnt;
1001 		} else {
1002 			cq->cq_type = CQ_QOS;
1003 			cq->cint_idx = qidx - non_xdp_queues -
1004 				       pfvf->hw.xdp_queues;
1005 			cq->cqe_cnt = qset->sqe_cnt;
1006 		}
1007 	}
1008 	cq->cqe_size = pfvf->qset.xqe_size;
1009 
1010 	/* Allocate memory for CQEs */
1011 	err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size);
1012 	if (err)
1013 		return err;
1014 
1015 	/* Save CQE CPU base for faster reference */
1016 	cq->cqe_base = cq->cqe->base;
1017 	/* In case where all RQs auras point to single pool,
1018 	 * all CQs receive buffer pool also point to same pool.
1019 	 */
1020 	pool_id = ((cq->cq_type == CQ_RX) &&
1021 		   (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx;
1022 	cq->rbpool = &qset->pool[pool_id];
1023 	cq->refill_task_sched = false;
1024 
1025 	/* Get memory to put this msg */
1026 	aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox);
1027 	if (!aq)
1028 		return -ENOMEM;
1029 
1030 	aq->cq.ena = 1;
1031 	aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4);
1032 	aq->cq.caching = 1;
1033 	aq->cq.base = cq->cqe->iova;
1034 	aq->cq.cint_idx = cq->cint_idx;
1035 	aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS;
1036 	aq->cq.qint_idx = 0;
1037 	aq->cq.avg_level = 255;
1038 
1039 	if (qidx < pfvf->hw.rx_queues) {
1040 		aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt);
1041 		aq->cq.drop_ena = 1;
1042 
1043 		if (!is_otx2_lbkvf(pfvf->pdev)) {
1044 			/* Enable receive CQ backpressure */
1045 			aq->cq.bp_ena = 1;
1046 #ifdef CONFIG_DCB
1047 			aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]];
1048 #else
1049 			aq->cq.bpid = pfvf->bpid[0];
1050 #endif
1051 
1052 			/* Set backpressure level is same as cq pass level */
1053 			aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt);
1054 		}
1055 	}
1056 
1057 	/* Fill AQ info */
1058 	aq->qidx = qidx;
1059 	aq->ctype = NIX_AQ_CTYPE_CQ;
1060 	aq->op = NIX_AQ_INSTOP_INIT;
1061 
1062 	return otx2_sync_mbox_msg(&pfvf->mbox);
1063 }
1064 
1065 static void otx2_pool_refill_task(struct work_struct *work)
1066 {
1067 	struct otx2_cq_queue *cq;
1068 	struct refill_work *wrk;
1069 	struct otx2_nic *pfvf;
1070 	int qidx;
1071 
1072 	wrk = container_of(work, struct refill_work, pool_refill_work.work);
1073 	pfvf = wrk->pf;
1074 	qidx = wrk - pfvf->refill_wrk;
1075 	cq = &pfvf->qset.cq[qidx];
1076 
1077 	cq->refill_task_sched = false;
1078 
1079 	local_bh_disable();
1080 	napi_schedule(wrk->napi);
1081 	local_bh_enable();
1082 }
1083 
1084 int otx2_config_nix_queues(struct otx2_nic *pfvf)
1085 {
1086 	int qidx, err;
1087 
1088 	/* Initialize RX queues */
1089 	for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) {
1090 		u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx);
1091 
1092 		err = otx2_rq_init(pfvf, qidx, lpb_aura);
1093 		if (err)
1094 			return err;
1095 	}
1096 
1097 	/* Initialize TX queues */
1098 	for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) {
1099 		u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1100 
1101 		err = otx2_sq_init(pfvf, qidx, sqb_aura);
1102 		if (err)
1103 			return err;
1104 	}
1105 
1106 	/* Initialize completion queues */
1107 	for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1108 		err = otx2_cq_init(pfvf, qidx);
1109 		if (err)
1110 			return err;
1111 	}
1112 
1113 	pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf,
1114 							   NIX_LF_CQ_OP_STATUS);
1115 
1116 	/* Initialize work queue for receive buffer refill */
1117 	pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt,
1118 					sizeof(struct refill_work), GFP_KERNEL);
1119 	if (!pfvf->refill_wrk)
1120 		return -ENOMEM;
1121 
1122 	for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) {
1123 		pfvf->refill_wrk[qidx].pf = pfvf;
1124 		INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work,
1125 				  otx2_pool_refill_task);
1126 	}
1127 	return 0;
1128 }
1129 
1130 int otx2_config_nix(struct otx2_nic *pfvf)
1131 {
1132 	struct nix_lf_alloc_req  *nixlf;
1133 	struct nix_lf_alloc_rsp *rsp;
1134 	int err;
1135 
1136 	pfvf->qset.xqe_size = pfvf->hw.xqe_size;
1137 
1138 	/* Get memory to put this msg */
1139 	nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox);
1140 	if (!nixlf)
1141 		return -ENOMEM;
1142 
1143 	/* Set RQ/SQ/CQ counts */
1144 	nixlf->rq_cnt = pfvf->hw.rx_queues;
1145 	nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf);
1146 	nixlf->cq_cnt = pfvf->qset.cq_cnt;
1147 	nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE;
1148 	nixlf->rss_grps = MAX_RSS_GROUPS;
1149 	nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64;
1150 	/* We don't know absolute NPA LF idx attached.
1151 	 * AF will replace 'RVU_DEFAULT_PF_FUNC' with
1152 	 * NPA LF attached to this RVU PF/VF.
1153 	 */
1154 	nixlf->npa_func = RVU_DEFAULT_PF_FUNC;
1155 	/* Disable alignment pad, enable L2 length check,
1156 	 * enable L4 TCP/UDP checksum verification.
1157 	 */
1158 	nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37);
1159 
1160 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1161 	if (err)
1162 		return err;
1163 
1164 	rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0,
1165 							   &nixlf->hdr);
1166 	if (IS_ERR(rsp))
1167 		return PTR_ERR(rsp);
1168 
1169 	if (rsp->qints < 1)
1170 		return -ENXIO;
1171 
1172 	return rsp->hdr.rc;
1173 }
1174 
1175 void otx2_sq_free_sqbs(struct otx2_nic *pfvf)
1176 {
1177 	struct otx2_qset *qset = &pfvf->qset;
1178 	struct otx2_hw *hw = &pfvf->hw;
1179 	struct otx2_snd_queue *sq;
1180 	int sqb, qidx;
1181 	u64 iova, pa;
1182 
1183 	for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) {
1184 		sq = &qset->sq[qidx];
1185 		if (!sq->sqb_ptrs)
1186 			continue;
1187 		for (sqb = 0; sqb < sq->sqb_count; sqb++) {
1188 			if (!sq->sqb_ptrs[sqb])
1189 				continue;
1190 			iova = sq->sqb_ptrs[sqb];
1191 			pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1192 			dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size,
1193 					     DMA_FROM_DEVICE,
1194 					     DMA_ATTR_SKIP_CPU_SYNC);
1195 			put_page(virt_to_page(phys_to_virt(pa)));
1196 		}
1197 		sq->sqb_count = 0;
1198 	}
1199 }
1200 
1201 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool,
1202 		    u64 iova, int size)
1203 {
1204 	struct page *page;
1205 	u64 pa;
1206 
1207 	pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1208 	page = virt_to_head_page(phys_to_virt(pa));
1209 
1210 	if (pool->page_pool) {
1211 		page_pool_put_full_page(pool->page_pool, page, true);
1212 	} else {
1213 		dma_unmap_page_attrs(pfvf->dev, iova, size,
1214 				     DMA_FROM_DEVICE,
1215 				     DMA_ATTR_SKIP_CPU_SYNC);
1216 
1217 		put_page(page);
1218 	}
1219 }
1220 
1221 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type)
1222 {
1223 	int pool_id, pool_start = 0, pool_end = 0, size = 0;
1224 	struct otx2_pool *pool;
1225 	u64 iova;
1226 
1227 	if (type == AURA_NIX_SQ) {
1228 		pool_start = otx2_get_pool_idx(pfvf, type, 0);
1229 		pool_end =  pool_start + pfvf->hw.sqpool_cnt;
1230 		size = pfvf->hw.sqb_size;
1231 	}
1232 	if (type == AURA_NIX_RQ) {
1233 		pool_start = otx2_get_pool_idx(pfvf, type, 0);
1234 		pool_end = pfvf->hw.rqpool_cnt;
1235 		size = pfvf->rbsize;
1236 	}
1237 
1238 	/* Free SQB and RQB pointers from the aura pool */
1239 	for (pool_id = pool_start; pool_id < pool_end; pool_id++) {
1240 		iova = otx2_aura_allocptr(pfvf, pool_id);
1241 		pool = &pfvf->qset.pool[pool_id];
1242 		while (iova) {
1243 			if (type == AURA_NIX_RQ)
1244 				iova -= OTX2_HEAD_ROOM;
1245 
1246 			otx2_free_bufs(pfvf, pool, iova, size);
1247 
1248 			iova = otx2_aura_allocptr(pfvf, pool_id);
1249 		}
1250 	}
1251 }
1252 
1253 void otx2_aura_pool_free(struct otx2_nic *pfvf)
1254 {
1255 	struct otx2_pool *pool;
1256 	int pool_id;
1257 
1258 	if (!pfvf->qset.pool)
1259 		return;
1260 
1261 	for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) {
1262 		pool = &pfvf->qset.pool[pool_id];
1263 		qmem_free(pfvf->dev, pool->stack);
1264 		qmem_free(pfvf->dev, pool->fc_addr);
1265 		page_pool_destroy(pool->page_pool);
1266 		pool->page_pool = NULL;
1267 	}
1268 	devm_kfree(pfvf->dev, pfvf->qset.pool);
1269 	pfvf->qset.pool = NULL;
1270 }
1271 
1272 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id,
1273 		   int pool_id, int numptrs)
1274 {
1275 	struct npa_aq_enq_req *aq;
1276 	struct otx2_pool *pool;
1277 	int err;
1278 
1279 	pool = &pfvf->qset.pool[pool_id];
1280 
1281 	/* Allocate memory for HW to update Aura count.
1282 	 * Alloc one cache line, so that it fits all FC_STYPE modes.
1283 	 */
1284 	if (!pool->fc_addr) {
1285 		err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN);
1286 		if (err)
1287 			return err;
1288 	}
1289 
1290 	/* Initialize this aura's context via AF */
1291 	aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1292 	if (!aq) {
1293 		/* Shared mbox memory buffer is full, flush it and retry */
1294 		err = otx2_sync_mbox_msg(&pfvf->mbox);
1295 		if (err)
1296 			return err;
1297 		aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1298 		if (!aq)
1299 			return -ENOMEM;
1300 	}
1301 
1302 	aq->aura_id = aura_id;
1303 	/* Will be filled by AF with correct pool context address */
1304 	aq->aura.pool_addr = pool_id;
1305 	aq->aura.pool_caching = 1;
1306 	aq->aura.shift = ilog2(numptrs) - 8;
1307 	aq->aura.count = numptrs;
1308 	aq->aura.limit = numptrs;
1309 	aq->aura.avg_level = 255;
1310 	aq->aura.ena = 1;
1311 	aq->aura.fc_ena = 1;
1312 	aq->aura.fc_addr = pool->fc_addr->iova;
1313 	aq->aura.fc_hyst_bits = 0; /* Store count on all updates */
1314 
1315 	/* Enable backpressure for RQ aura */
1316 	if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) {
1317 		aq->aura.bp_ena = 0;
1318 		/* If NIX1 LF is attached then specify NIX1_RX.
1319 		 *
1320 		 * Below NPA_AURA_S[BP_ENA] is set according to the
1321 		 * NPA_BPINTF_E enumeration given as:
1322 		 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so
1323 		 * NIX0_RX is 0x0 + 0*0x1 = 0
1324 		 * NIX1_RX is 0x0 + 1*0x1 = 1
1325 		 * But in HRM it is given that
1326 		 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to
1327 		 * NIX-RX based on [BP] level. One bit per NIX-RX; index
1328 		 * enumerated by NPA_BPINTF_E."
1329 		 */
1330 		if (pfvf->nix_blkaddr == BLKADDR_NIX1)
1331 			aq->aura.bp_ena = 1;
1332 #ifdef CONFIG_DCB
1333 		aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]];
1334 #else
1335 		aq->aura.nix0_bpid = pfvf->bpid[0];
1336 #endif
1337 
1338 		/* Set backpressure level for RQ's Aura */
1339 		aq->aura.bp = RQ_BP_LVL_AURA;
1340 	}
1341 
1342 	/* Fill AQ info */
1343 	aq->ctype = NPA_AQ_CTYPE_AURA;
1344 	aq->op = NPA_AQ_INSTOP_INIT;
1345 
1346 	return 0;
1347 }
1348 
1349 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id,
1350 		   int stack_pages, int numptrs, int buf_size, int type)
1351 {
1352 	struct page_pool_params pp_params = { 0 };
1353 	struct npa_aq_enq_req *aq;
1354 	struct otx2_pool *pool;
1355 	int err;
1356 
1357 	pool = &pfvf->qset.pool[pool_id];
1358 	/* Alloc memory for stack which is used to store buffer pointers */
1359 	err = qmem_alloc(pfvf->dev, &pool->stack,
1360 			 stack_pages, pfvf->hw.stack_pg_bytes);
1361 	if (err)
1362 		return err;
1363 
1364 	pool->rbsize = buf_size;
1365 
1366 	/* Initialize this pool's context via AF */
1367 	aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1368 	if (!aq) {
1369 		/* Shared mbox memory buffer is full, flush it and retry */
1370 		err = otx2_sync_mbox_msg(&pfvf->mbox);
1371 		if (err) {
1372 			qmem_free(pfvf->dev, pool->stack);
1373 			return err;
1374 		}
1375 		aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox);
1376 		if (!aq) {
1377 			qmem_free(pfvf->dev, pool->stack);
1378 			return -ENOMEM;
1379 		}
1380 	}
1381 
1382 	aq->aura_id = pool_id;
1383 	aq->pool.stack_base = pool->stack->iova;
1384 	aq->pool.stack_caching = 1;
1385 	aq->pool.ena = 1;
1386 	aq->pool.buf_size = buf_size / 128;
1387 	aq->pool.stack_max_pages = stack_pages;
1388 	aq->pool.shift = ilog2(numptrs) - 8;
1389 	aq->pool.ptr_start = 0;
1390 	aq->pool.ptr_end = ~0ULL;
1391 
1392 	/* Fill AQ info */
1393 	aq->ctype = NPA_AQ_CTYPE_POOL;
1394 	aq->op = NPA_AQ_INSTOP_INIT;
1395 
1396 	if (type != AURA_NIX_RQ) {
1397 		pool->page_pool = NULL;
1398 		return 0;
1399 	}
1400 
1401 	pp_params.order = get_order(buf_size);
1402 	pp_params.flags = PP_FLAG_PAGE_FRAG | PP_FLAG_DMA_MAP;
1403 	pp_params.pool_size = min(OTX2_PAGE_POOL_SZ, numptrs);
1404 	pp_params.nid = NUMA_NO_NODE;
1405 	pp_params.dev = pfvf->dev;
1406 	pp_params.dma_dir = DMA_FROM_DEVICE;
1407 	pool->page_pool = page_pool_create(&pp_params);
1408 	if (IS_ERR(pool->page_pool)) {
1409 		netdev_err(pfvf->netdev, "Creation of page pool failed\n");
1410 		return PTR_ERR(pool->page_pool);
1411 	}
1412 
1413 	return 0;
1414 }
1415 
1416 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf)
1417 {
1418 	int qidx, pool_id, stack_pages, num_sqbs;
1419 	struct otx2_qset *qset = &pfvf->qset;
1420 	struct otx2_hw *hw = &pfvf->hw;
1421 	struct otx2_snd_queue *sq;
1422 	struct otx2_pool *pool;
1423 	dma_addr_t bufptr;
1424 	int err, ptr;
1425 
1426 	/* Calculate number of SQBs needed.
1427 	 *
1428 	 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB.
1429 	 * Last SQE is used for pointing to next SQB.
1430 	 */
1431 	num_sqbs = (hw->sqb_size / 128) - 1;
1432 	num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs;
1433 
1434 	/* Get no of stack pages needed */
1435 	stack_pages =
1436 		(num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1437 
1438 	for (qidx = 0; qidx < hw->non_qos_queues; qidx++) {
1439 		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1440 		/* Initialize aura context */
1441 		err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs);
1442 		if (err)
1443 			goto fail;
1444 
1445 		/* Initialize pool context */
1446 		err = otx2_pool_init(pfvf, pool_id, stack_pages,
1447 				     num_sqbs, hw->sqb_size, AURA_NIX_SQ);
1448 		if (err)
1449 			goto fail;
1450 	}
1451 
1452 	/* Flush accumulated messages */
1453 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1454 	if (err)
1455 		goto fail;
1456 
1457 	/* Allocate pointers and free them to aura/pool */
1458 	for (qidx = 0; qidx < hw->non_qos_queues; qidx++) {
1459 		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx);
1460 		pool = &pfvf->qset.pool[pool_id];
1461 
1462 		sq = &qset->sq[qidx];
1463 		sq->sqb_count = 0;
1464 		sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL);
1465 		if (!sq->sqb_ptrs) {
1466 			err = -ENOMEM;
1467 			goto err_mem;
1468 		}
1469 
1470 		for (ptr = 0; ptr < num_sqbs; ptr++) {
1471 			err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
1472 			if (err)
1473 				goto err_mem;
1474 			pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr);
1475 			sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr;
1476 		}
1477 	}
1478 
1479 err_mem:
1480 	return err ? -ENOMEM : 0;
1481 
1482 fail:
1483 	otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1484 	otx2_aura_pool_free(pfvf);
1485 	return err;
1486 }
1487 
1488 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf)
1489 {
1490 	struct otx2_hw *hw = &pfvf->hw;
1491 	int stack_pages, pool_id, rq;
1492 	struct otx2_pool *pool;
1493 	int err, ptr, num_ptrs;
1494 	dma_addr_t bufptr;
1495 
1496 	num_ptrs = pfvf->qset.rqe_cnt;
1497 
1498 	stack_pages =
1499 		(num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs;
1500 
1501 	for (rq = 0; rq < hw->rx_queues; rq++) {
1502 		pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq);
1503 		/* Initialize aura context */
1504 		err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs);
1505 		if (err)
1506 			goto fail;
1507 	}
1508 	for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1509 		err = otx2_pool_init(pfvf, pool_id, stack_pages,
1510 				     num_ptrs, pfvf->rbsize, AURA_NIX_RQ);
1511 		if (err)
1512 			goto fail;
1513 	}
1514 
1515 	/* Flush accumulated messages */
1516 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1517 	if (err)
1518 		goto fail;
1519 
1520 	/* Allocate pointers and free them to aura/pool */
1521 	for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) {
1522 		pool = &pfvf->qset.pool[pool_id];
1523 		for (ptr = 0; ptr < num_ptrs; ptr++) {
1524 			err = otx2_alloc_rbuf(pfvf, pool, &bufptr);
1525 			if (err)
1526 				return -ENOMEM;
1527 			pfvf->hw_ops->aura_freeptr(pfvf, pool_id,
1528 						   bufptr + OTX2_HEAD_ROOM);
1529 		}
1530 	}
1531 	return 0;
1532 fail:
1533 	otx2_mbox_reset(&pfvf->mbox.mbox, 0);
1534 	otx2_aura_pool_free(pfvf);
1535 	return err;
1536 }
1537 
1538 int otx2_config_npa(struct otx2_nic *pfvf)
1539 {
1540 	struct otx2_qset *qset = &pfvf->qset;
1541 	struct npa_lf_alloc_req  *npalf;
1542 	struct otx2_hw *hw = &pfvf->hw;
1543 	int aura_cnt;
1544 
1545 	/* Pool - Stack of free buffer pointers
1546 	 * Aura - Alloc/frees pointers from/to pool for NIX DMA.
1547 	 */
1548 
1549 	if (!hw->pool_cnt)
1550 		return -EINVAL;
1551 
1552 	qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt,
1553 				  sizeof(struct otx2_pool), GFP_KERNEL);
1554 	if (!qset->pool)
1555 		return -ENOMEM;
1556 
1557 	/* Get memory to put this msg */
1558 	npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox);
1559 	if (!npalf)
1560 		return -ENOMEM;
1561 
1562 	/* Set aura and pool counts */
1563 	npalf->nr_pools = hw->pool_cnt;
1564 	aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt));
1565 	npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1;
1566 
1567 	return otx2_sync_mbox_msg(&pfvf->mbox);
1568 }
1569 
1570 int otx2_detach_resources(struct mbox *mbox)
1571 {
1572 	struct rsrc_detach *detach;
1573 
1574 	mutex_lock(&mbox->lock);
1575 	detach = otx2_mbox_alloc_msg_detach_resources(mbox);
1576 	if (!detach) {
1577 		mutex_unlock(&mbox->lock);
1578 		return -ENOMEM;
1579 	}
1580 
1581 	/* detach all */
1582 	detach->partial = false;
1583 
1584 	/* Send detach request to AF */
1585 	otx2_mbox_msg_send(&mbox->mbox, 0);
1586 	mutex_unlock(&mbox->lock);
1587 	return 0;
1588 }
1589 EXPORT_SYMBOL(otx2_detach_resources);
1590 
1591 int otx2_attach_npa_nix(struct otx2_nic *pfvf)
1592 {
1593 	struct rsrc_attach *attach;
1594 	struct msg_req *msix;
1595 	int err;
1596 
1597 	mutex_lock(&pfvf->mbox.lock);
1598 	/* Get memory to put this msg */
1599 	attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox);
1600 	if (!attach) {
1601 		mutex_unlock(&pfvf->mbox.lock);
1602 		return -ENOMEM;
1603 	}
1604 
1605 	attach->npalf = true;
1606 	attach->nixlf = true;
1607 
1608 	/* Send attach request to AF */
1609 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1610 	if (err) {
1611 		mutex_unlock(&pfvf->mbox.lock);
1612 		return err;
1613 	}
1614 
1615 	pfvf->nix_blkaddr = BLKADDR_NIX0;
1616 
1617 	/* If the platform has two NIX blocks then LF may be
1618 	 * allocated from NIX1.
1619 	 */
1620 	if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL)
1621 		pfvf->nix_blkaddr = BLKADDR_NIX1;
1622 
1623 	/* Get NPA and NIX MSIX vector offsets */
1624 	msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox);
1625 	if (!msix) {
1626 		mutex_unlock(&pfvf->mbox.lock);
1627 		return -ENOMEM;
1628 	}
1629 
1630 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1631 	if (err) {
1632 		mutex_unlock(&pfvf->mbox.lock);
1633 		return err;
1634 	}
1635 	mutex_unlock(&pfvf->mbox.lock);
1636 
1637 	if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID ||
1638 	    pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) {
1639 		dev_err(pfvf->dev,
1640 			"RVUPF: Invalid MSIX vector offset for NPA/NIX\n");
1641 		return -EINVAL;
1642 	}
1643 
1644 	return 0;
1645 }
1646 EXPORT_SYMBOL(otx2_attach_npa_nix);
1647 
1648 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa)
1649 {
1650 	struct hwctx_disable_req *req;
1651 
1652 	mutex_lock(&mbox->lock);
1653 	/* Request AQ to disable this context */
1654 	if (npa)
1655 		req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox);
1656 	else
1657 		req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox);
1658 
1659 	if (!req) {
1660 		mutex_unlock(&mbox->lock);
1661 		return;
1662 	}
1663 
1664 	req->ctype = type;
1665 
1666 	if (otx2_sync_mbox_msg(mbox))
1667 		dev_err(mbox->pfvf->dev, "%s failed to disable context\n",
1668 			__func__);
1669 
1670 	mutex_unlock(&mbox->lock);
1671 }
1672 
1673 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable)
1674 {
1675 	struct nix_bp_cfg_req *req;
1676 
1677 	if (enable)
1678 		req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox);
1679 	else
1680 		req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox);
1681 
1682 	if (!req)
1683 		return -ENOMEM;
1684 
1685 	req->chan_base = 0;
1686 #ifdef CONFIG_DCB
1687 	req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1;
1688 	req->bpid_per_chan = pfvf->pfc_en ? 1 : 0;
1689 #else
1690 	req->chan_cnt =  1;
1691 	req->bpid_per_chan = 0;
1692 #endif
1693 
1694 	return otx2_sync_mbox_msg(&pfvf->mbox);
1695 }
1696 EXPORT_SYMBOL(otx2_nix_config_bp);
1697 
1698 /* Mbox message handlers */
1699 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
1700 			    struct cgx_stats_rsp *rsp)
1701 {
1702 	int id;
1703 
1704 	for (id = 0; id < CGX_RX_STATS_COUNT; id++)
1705 		pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id];
1706 	for (id = 0; id < CGX_TX_STATS_COUNT; id++)
1707 		pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id];
1708 }
1709 
1710 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
1711 				struct cgx_fec_stats_rsp *rsp)
1712 {
1713 	pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks;
1714 	pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks;
1715 }
1716 
1717 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
1718 			       struct npa_lf_alloc_rsp *rsp)
1719 {
1720 	pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs;
1721 	pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes;
1722 }
1723 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc);
1724 
1725 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
1726 			       struct nix_lf_alloc_rsp *rsp)
1727 {
1728 	pfvf->hw.sqb_size = rsp->sqb_size;
1729 	pfvf->hw.rx_chan_base = rsp->rx_chan_base;
1730 	pfvf->hw.tx_chan_base = rsp->tx_chan_base;
1731 	pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx;
1732 	pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx;
1733 	pfvf->hw.cgx_links = rsp->cgx_links;
1734 	pfvf->hw.lbk_links = rsp->lbk_links;
1735 	pfvf->hw.tx_link = rsp->tx_link;
1736 }
1737 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc);
1738 
1739 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
1740 			      struct msix_offset_rsp *rsp)
1741 {
1742 	pfvf->hw.npa_msixoff = rsp->npa_msixoff;
1743 	pfvf->hw.nix_msixoff = rsp->nix_msixoff;
1744 }
1745 EXPORT_SYMBOL(mbox_handler_msix_offset);
1746 
1747 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
1748 				struct nix_bp_cfg_rsp *rsp)
1749 {
1750 	int chan, chan_id;
1751 
1752 	for (chan = 0; chan < rsp->chan_cnt; chan++) {
1753 		chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F);
1754 		pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF;
1755 	}
1756 }
1757 EXPORT_SYMBOL(mbox_handler_nix_bp_enable);
1758 
1759 void otx2_free_cints(struct otx2_nic *pfvf, int n)
1760 {
1761 	struct otx2_qset *qset = &pfvf->qset;
1762 	struct otx2_hw *hw = &pfvf->hw;
1763 	int irq, qidx;
1764 
1765 	for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1766 	     qidx < n;
1767 	     qidx++, irq++) {
1768 		int vector = pci_irq_vector(pfvf->pdev, irq);
1769 
1770 		irq_set_affinity_hint(vector, NULL);
1771 		free_cpumask_var(hw->affinity_mask[irq]);
1772 		free_irq(vector, &qset->napi[qidx]);
1773 	}
1774 }
1775 
1776 void otx2_set_cints_affinity(struct otx2_nic *pfvf)
1777 {
1778 	struct otx2_hw *hw = &pfvf->hw;
1779 	int vec, cpu, irq, cint;
1780 
1781 	vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START;
1782 	cpu = cpumask_first(cpu_online_mask);
1783 
1784 	/* CQ interrupts */
1785 	for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) {
1786 		if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL))
1787 			return;
1788 
1789 		cpumask_set_cpu(cpu, hw->affinity_mask[vec]);
1790 
1791 		irq = pci_irq_vector(pfvf->pdev, vec);
1792 		irq_set_affinity_hint(irq, hw->affinity_mask[vec]);
1793 
1794 		cpu = cpumask_next(cpu, cpu_online_mask);
1795 		if (unlikely(cpu >= nr_cpu_ids))
1796 			cpu = 0;
1797 	}
1798 }
1799 
1800 static u32 get_dwrr_mtu(struct otx2_nic *pfvf, struct nix_hw_info *hw)
1801 {
1802 	if (is_otx2_lbkvf(pfvf->pdev)) {
1803 		pfvf->hw.smq_link_type = SMQ_LINK_TYPE_LBK;
1804 		return hw->lbk_dwrr_mtu;
1805 	}
1806 
1807 	pfvf->hw.smq_link_type = SMQ_LINK_TYPE_RPM;
1808 	return hw->rpm_dwrr_mtu;
1809 }
1810 
1811 u16 otx2_get_max_mtu(struct otx2_nic *pfvf)
1812 {
1813 	struct nix_hw_info *rsp;
1814 	struct msg_req *req;
1815 	u16 max_mtu;
1816 	int rc;
1817 
1818 	mutex_lock(&pfvf->mbox.lock);
1819 
1820 	req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox);
1821 	if (!req) {
1822 		rc =  -ENOMEM;
1823 		goto out;
1824 	}
1825 
1826 	rc = otx2_sync_mbox_msg(&pfvf->mbox);
1827 	if (!rc) {
1828 		rsp = (struct nix_hw_info *)
1829 		       otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr);
1830 
1831 		/* HW counts VLAN insertion bytes (8 for double tag)
1832 		 * irrespective of whether SQE is requesting to insert VLAN
1833 		 * in the packet or not. Hence these 8 bytes have to be
1834 		 * discounted from max packet size otherwise HW will throw
1835 		 * SMQ errors
1836 		 */
1837 		max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN;
1838 
1839 		/* Also save DWRR MTU, needed for DWRR weight calculation */
1840 		pfvf->hw.dwrr_mtu = get_dwrr_mtu(pfvf, rsp);
1841 		if (!pfvf->hw.dwrr_mtu)
1842 			pfvf->hw.dwrr_mtu = 1;
1843 	}
1844 
1845 out:
1846 	mutex_unlock(&pfvf->mbox.lock);
1847 	if (rc) {
1848 		dev_warn(pfvf->dev,
1849 			 "Failed to get MTU from hardware setting default value(1500)\n");
1850 		max_mtu = 1500;
1851 	}
1852 	return max_mtu;
1853 }
1854 EXPORT_SYMBOL(otx2_get_max_mtu);
1855 
1856 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features)
1857 {
1858 	netdev_features_t changed = features ^ netdev->features;
1859 	struct otx2_nic *pfvf = netdev_priv(netdev);
1860 	bool ntuple = !!(features & NETIF_F_NTUPLE);
1861 	bool tc = !!(features & NETIF_F_HW_TC);
1862 
1863 	if ((changed & NETIF_F_NTUPLE) && !ntuple)
1864 		otx2_destroy_ntuple_flows(pfvf);
1865 
1866 	if ((changed & NETIF_F_NTUPLE) && ntuple) {
1867 		if (!pfvf->flow_cfg->max_flows) {
1868 			netdev_err(netdev,
1869 				   "Can't enable NTUPLE, MCAM entries not allocated\n");
1870 			return -EINVAL;
1871 		}
1872 	}
1873 
1874 	if ((changed & NETIF_F_HW_TC) && !tc &&
1875 	    otx2_tc_flower_rule_cnt(pfvf)) {
1876 		netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n");
1877 		return -EBUSY;
1878 	}
1879 
1880 	if ((changed & NETIF_F_NTUPLE) && ntuple &&
1881 	    otx2_tc_flower_rule_cnt(pfvf) && !(changed & NETIF_F_HW_TC)) {
1882 		netdev_err(netdev,
1883 			   "Can't enable NTUPLE when TC flower offload is active, disable TC rules and retry\n");
1884 		return -EINVAL;
1885 	}
1886 
1887 	return 0;
1888 }
1889 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features);
1890 
1891 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
1892 int __weak								\
1893 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf,		\
1894 				struct _req_type *req,			\
1895 				struct _rsp_type *rsp)			\
1896 {									\
1897 	/* Nothing to do here */					\
1898 	return 0;							\
1899 }									\
1900 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name);
1901 MBOX_UP_CGX_MESSAGES
1902 MBOX_UP_MCS_MESSAGES
1903 #undef M
1904