1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 #include <net/tso.h> 11 12 #include "otx2_reg.h" 13 #include "otx2_common.h" 14 #include "otx2_struct.h" 15 #include "cn10k.h" 16 17 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 18 struct otx2_nic *pfvf, int qidx) 19 { 20 u64 incr = (u64)qidx << 32; 21 u64 *ptr; 22 23 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 24 stats->bytes = otx2_atomic64_add(incr, ptr); 25 26 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 27 stats->pkts = otx2_atomic64_add(incr, ptr); 28 } 29 30 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 31 struct otx2_nic *pfvf, int qidx) 32 { 33 u64 incr = (u64)qidx << 32; 34 u64 *ptr; 35 36 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 37 stats->bytes = otx2_atomic64_add(incr, ptr); 38 39 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 40 stats->pkts = otx2_atomic64_add(incr, ptr); 41 } 42 43 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 44 { 45 struct msg_req *req; 46 47 if (!netif_running(pfvf->netdev)) 48 return; 49 50 mutex_lock(&pfvf->mbox.lock); 51 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 52 if (!req) { 53 mutex_unlock(&pfvf->mbox.lock); 54 return; 55 } 56 57 otx2_sync_mbox_msg(&pfvf->mbox); 58 mutex_unlock(&pfvf->mbox.lock); 59 } 60 61 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 62 { 63 struct msg_req *req; 64 65 if (!netif_running(pfvf->netdev)) 66 return; 67 mutex_lock(&pfvf->mbox.lock); 68 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 69 if (req) 70 otx2_sync_mbox_msg(&pfvf->mbox); 71 mutex_unlock(&pfvf->mbox.lock); 72 } 73 74 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 75 { 76 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 77 78 if (!pfvf->qset.rq) 79 return 0; 80 81 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 82 return 1; 83 } 84 85 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 86 { 87 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 88 89 if (!pfvf->qset.sq) 90 return 0; 91 92 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 93 return 1; 94 } 95 96 void otx2_get_dev_stats(struct otx2_nic *pfvf) 97 { 98 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 99 100 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 101 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 102 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 103 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 104 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 105 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 106 dev_stats->rx_mcast_frames + 107 dev_stats->rx_ucast_frames; 108 109 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 110 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 111 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 112 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 113 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 114 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 115 dev_stats->tx_mcast_frames + 116 dev_stats->tx_ucast_frames; 117 } 118 119 void otx2_get_stats64(struct net_device *netdev, 120 struct rtnl_link_stats64 *stats) 121 { 122 struct otx2_nic *pfvf = netdev_priv(netdev); 123 struct otx2_dev_stats *dev_stats; 124 125 otx2_get_dev_stats(pfvf); 126 127 dev_stats = &pfvf->hw.dev_stats; 128 stats->rx_bytes = dev_stats->rx_bytes; 129 stats->rx_packets = dev_stats->rx_frames; 130 stats->rx_dropped = dev_stats->rx_drops; 131 stats->multicast = dev_stats->rx_mcast_frames; 132 133 stats->tx_bytes = dev_stats->tx_bytes; 134 stats->tx_packets = dev_stats->tx_frames; 135 stats->tx_dropped = dev_stats->tx_drops; 136 } 137 EXPORT_SYMBOL(otx2_get_stats64); 138 139 /* Sync MAC address with RVU AF */ 140 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 141 { 142 struct nix_set_mac_addr *req; 143 int err; 144 145 mutex_lock(&pfvf->mbox.lock); 146 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 147 if (!req) { 148 mutex_unlock(&pfvf->mbox.lock); 149 return -ENOMEM; 150 } 151 152 ether_addr_copy(req->mac_addr, mac); 153 154 err = otx2_sync_mbox_msg(&pfvf->mbox); 155 mutex_unlock(&pfvf->mbox.lock); 156 return err; 157 } 158 159 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 160 struct net_device *netdev) 161 { 162 struct nix_get_mac_addr_rsp *rsp; 163 struct mbox_msghdr *msghdr; 164 struct msg_req *req; 165 int err; 166 167 mutex_lock(&pfvf->mbox.lock); 168 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 169 if (!req) { 170 mutex_unlock(&pfvf->mbox.lock); 171 return -ENOMEM; 172 } 173 174 err = otx2_sync_mbox_msg(&pfvf->mbox); 175 if (err) { 176 mutex_unlock(&pfvf->mbox.lock); 177 return err; 178 } 179 180 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 181 if (IS_ERR(msghdr)) { 182 mutex_unlock(&pfvf->mbox.lock); 183 return PTR_ERR(msghdr); 184 } 185 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 186 eth_hw_addr_set(netdev, rsp->mac_addr); 187 mutex_unlock(&pfvf->mbox.lock); 188 189 return 0; 190 } 191 192 int otx2_set_mac_address(struct net_device *netdev, void *p) 193 { 194 struct otx2_nic *pfvf = netdev_priv(netdev); 195 struct sockaddr *addr = p; 196 197 if (!is_valid_ether_addr(addr->sa_data)) 198 return -EADDRNOTAVAIL; 199 200 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 201 eth_hw_addr_set(netdev, addr->sa_data); 202 /* update dmac field in vlan offload rule */ 203 if (netif_running(netdev) && 204 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 205 otx2_install_rxvlan_offload_flow(pfvf); 206 /* update dmac address in ntuple and DMAC filter list */ 207 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 208 otx2_dmacflt_update_pfmac_flow(pfvf); 209 } else { 210 return -EPERM; 211 } 212 213 return 0; 214 } 215 EXPORT_SYMBOL(otx2_set_mac_address); 216 217 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 218 { 219 struct nix_frs_cfg *req; 220 u16 maxlen; 221 int err; 222 223 maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 224 225 mutex_lock(&pfvf->mbox.lock); 226 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 227 if (!req) { 228 mutex_unlock(&pfvf->mbox.lock); 229 return -ENOMEM; 230 } 231 232 req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 233 234 /* Use max receive length supported by hardware for loopback devices */ 235 if (is_otx2_lbkvf(pfvf->pdev)) 236 req->maxlen = maxlen; 237 238 err = otx2_sync_mbox_msg(&pfvf->mbox); 239 mutex_unlock(&pfvf->mbox.lock); 240 return err; 241 } 242 243 int otx2_config_pause_frm(struct otx2_nic *pfvf) 244 { 245 struct cgx_pause_frm_cfg *req; 246 int err; 247 248 if (is_otx2_lbkvf(pfvf->pdev)) 249 return 0; 250 251 mutex_lock(&pfvf->mbox.lock); 252 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 253 if (!req) { 254 err = -ENOMEM; 255 goto unlock; 256 } 257 258 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 259 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 260 req->set = 1; 261 262 err = otx2_sync_mbox_msg(&pfvf->mbox); 263 unlock: 264 mutex_unlock(&pfvf->mbox.lock); 265 return err; 266 } 267 EXPORT_SYMBOL(otx2_config_pause_frm); 268 269 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 270 { 271 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 272 struct nix_rss_flowkey_cfg_rsp *rsp; 273 struct nix_rss_flowkey_cfg *req; 274 int err; 275 276 mutex_lock(&pfvf->mbox.lock); 277 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 278 if (!req) { 279 mutex_unlock(&pfvf->mbox.lock); 280 return -ENOMEM; 281 } 282 req->mcam_index = -1; /* Default or reserved index */ 283 req->flowkey_cfg = rss->flowkey_cfg; 284 req->group = DEFAULT_RSS_CONTEXT_GROUP; 285 286 err = otx2_sync_mbox_msg(&pfvf->mbox); 287 if (err) 288 goto fail; 289 290 rsp = (struct nix_rss_flowkey_cfg_rsp *) 291 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 292 if (IS_ERR(rsp)) { 293 err = PTR_ERR(rsp); 294 goto fail; 295 } 296 297 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 298 fail: 299 mutex_unlock(&pfvf->mbox.lock); 300 return err; 301 } 302 303 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 304 { 305 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 306 const int index = rss->rss_size * ctx_id; 307 struct mbox *mbox = &pfvf->mbox; 308 struct otx2_rss_ctx *rss_ctx; 309 struct nix_aq_enq_req *aq; 310 int idx, err; 311 312 mutex_lock(&mbox->lock); 313 rss_ctx = rss->rss_ctx[ctx_id]; 314 /* Get memory to put this msg */ 315 for (idx = 0; idx < rss->rss_size; idx++) { 316 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 317 if (!aq) { 318 /* The shared memory buffer can be full. 319 * Flush it and retry 320 */ 321 err = otx2_sync_mbox_msg(mbox); 322 if (err) { 323 mutex_unlock(&mbox->lock); 324 return err; 325 } 326 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 327 if (!aq) { 328 mutex_unlock(&mbox->lock); 329 return -ENOMEM; 330 } 331 } 332 333 aq->rss.rq = rss_ctx->ind_tbl[idx]; 334 335 /* Fill AQ info */ 336 aq->qidx = index + idx; 337 aq->ctype = NIX_AQ_CTYPE_RSS; 338 aq->op = NIX_AQ_INSTOP_INIT; 339 } 340 err = otx2_sync_mbox_msg(mbox); 341 mutex_unlock(&mbox->lock); 342 return err; 343 } 344 345 void otx2_set_rss_key(struct otx2_nic *pfvf) 346 { 347 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 348 u64 *key = (u64 *)&rss->key[4]; 349 int idx; 350 351 /* 352bit or 44byte key needs to be configured as below 352 * NIX_LF_RX_SECRETX0 = key<351:288> 353 * NIX_LF_RX_SECRETX1 = key<287:224> 354 * NIX_LF_RX_SECRETX2 = key<223:160> 355 * NIX_LF_RX_SECRETX3 = key<159:96> 356 * NIX_LF_RX_SECRETX4 = key<95:32> 357 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 358 */ 359 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 360 (u64)(*((u32 *)&rss->key)) << 32); 361 idx = sizeof(rss->key) / sizeof(u64); 362 while (idx > 0) { 363 idx--; 364 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 365 } 366 } 367 368 int otx2_rss_init(struct otx2_nic *pfvf) 369 { 370 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 371 struct otx2_rss_ctx *rss_ctx; 372 int idx, ret = 0; 373 374 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 375 376 /* Init RSS key if it is not setup already */ 377 if (!rss->enable) 378 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 379 otx2_set_rss_key(pfvf); 380 381 if (!netif_is_rxfh_configured(pfvf->netdev)) { 382 /* Set RSS group 0 as default indirection table */ 383 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 384 GFP_KERNEL); 385 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 386 return -ENOMEM; 387 388 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 389 for (idx = 0; idx < rss->rss_size; idx++) 390 rss_ctx->ind_tbl[idx] = 391 ethtool_rxfh_indir_default(idx, 392 pfvf->hw.rx_queues); 393 } 394 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 395 if (ret) 396 return ret; 397 398 /* Flowkey or hash config to be used for generating flow tag */ 399 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 400 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 401 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 402 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 403 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 404 405 ret = otx2_set_flowkey_cfg(pfvf); 406 if (ret) 407 return ret; 408 409 rss->enable = true; 410 return 0; 411 } 412 413 /* Setup UDP segmentation algorithm in HW */ 414 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 415 { 416 struct nix_lso_format *field; 417 418 field = (struct nix_lso_format *)&lso->fields[0]; 419 lso->field_mask = GENMASK(18, 0); 420 421 /* IP's Length field */ 422 field->layer = NIX_TXLAYER_OL3; 423 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 424 field->offset = v4 ? 2 : 4; 425 field->sizem1 = 1; /* i.e 2 bytes */ 426 field->alg = NIX_LSOALG_ADD_PAYLEN; 427 field++; 428 429 /* No ID field in IPv6 header */ 430 if (v4) { 431 /* Increment IPID */ 432 field->layer = NIX_TXLAYER_OL3; 433 field->offset = 4; 434 field->sizem1 = 1; /* i.e 2 bytes */ 435 field->alg = NIX_LSOALG_ADD_SEGNUM; 436 field++; 437 } 438 439 /* Update length in UDP header */ 440 field->layer = NIX_TXLAYER_OL4; 441 field->offset = 4; 442 field->sizem1 = 1; 443 field->alg = NIX_LSOALG_ADD_PAYLEN; 444 } 445 446 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 447 void otx2_setup_segmentation(struct otx2_nic *pfvf) 448 { 449 struct nix_lso_format_cfg_rsp *rsp; 450 struct nix_lso_format_cfg *lso; 451 struct otx2_hw *hw = &pfvf->hw; 452 int err; 453 454 mutex_lock(&pfvf->mbox.lock); 455 456 /* UDPv4 segmentation */ 457 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 458 if (!lso) 459 goto fail; 460 461 /* Setup UDP/IP header fields that HW should update per segment */ 462 otx2_setup_udp_segmentation(lso, true); 463 464 err = otx2_sync_mbox_msg(&pfvf->mbox); 465 if (err) 466 goto fail; 467 468 rsp = (struct nix_lso_format_cfg_rsp *) 469 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 470 if (IS_ERR(rsp)) 471 goto fail; 472 473 hw->lso_udpv4_idx = rsp->lso_format_idx; 474 475 /* UDPv6 segmentation */ 476 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 477 if (!lso) 478 goto fail; 479 480 /* Setup UDP/IP header fields that HW should update per segment */ 481 otx2_setup_udp_segmentation(lso, false); 482 483 err = otx2_sync_mbox_msg(&pfvf->mbox); 484 if (err) 485 goto fail; 486 487 rsp = (struct nix_lso_format_cfg_rsp *) 488 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 489 if (IS_ERR(rsp)) 490 goto fail; 491 492 hw->lso_udpv6_idx = rsp->lso_format_idx; 493 mutex_unlock(&pfvf->mbox.lock); 494 return; 495 fail: 496 mutex_unlock(&pfvf->mbox.lock); 497 netdev_info(pfvf->netdev, 498 "Failed to get LSO index for UDP GSO offload, disabling\n"); 499 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 500 } 501 502 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 503 { 504 /* Configure CQE interrupt coalescing parameters 505 * 506 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 507 * set 1 less than cq_ecount_wait. And cq_time_wait is in 508 * usecs, convert that to 100ns count. 509 */ 510 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 511 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 512 ((u64)pfvf->hw.cq_qcount_wait << 32) | 513 (pfvf->hw.cq_ecount_wait - 1)); 514 } 515 516 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 517 dma_addr_t *dma) 518 { 519 u8 *buf; 520 521 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 522 if (unlikely(!buf)) 523 return -ENOMEM; 524 525 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 526 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 527 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 528 page_frag_free(buf); 529 return -ENOMEM; 530 } 531 532 return 0; 533 } 534 535 static int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 536 dma_addr_t *dma) 537 { 538 int ret; 539 540 local_bh_disable(); 541 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 542 local_bh_enable(); 543 return ret; 544 } 545 546 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 547 dma_addr_t *dma) 548 { 549 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) { 550 struct refill_work *work; 551 struct delayed_work *dwork; 552 553 work = &pfvf->refill_wrk[cq->cq_idx]; 554 dwork = &work->pool_refill_work; 555 /* Schedule a task if no other task is running */ 556 if (!cq->refill_task_sched) { 557 cq->refill_task_sched = true; 558 schedule_delayed_work(dwork, 559 msecs_to_jiffies(100)); 560 } 561 return -ENOMEM; 562 } 563 return 0; 564 } 565 566 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 567 { 568 struct otx2_nic *pfvf = netdev_priv(netdev); 569 570 schedule_work(&pfvf->reset_task); 571 } 572 EXPORT_SYMBOL(otx2_tx_timeout); 573 574 void otx2_get_mac_from_af(struct net_device *netdev) 575 { 576 struct otx2_nic *pfvf = netdev_priv(netdev); 577 int err; 578 579 err = otx2_hw_get_mac_addr(pfvf, netdev); 580 if (err) 581 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 582 583 /* If AF doesn't provide a valid MAC, generate a random one */ 584 if (!is_valid_ether_addr(netdev->dev_addr)) 585 eth_hw_addr_random(netdev); 586 } 587 EXPORT_SYMBOL(otx2_get_mac_from_af); 588 589 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl) 590 { 591 struct otx2_hw *hw = &pfvf->hw; 592 struct nix_txschq_config *req; 593 u64 schq, parent; 594 u64 dwrr_val; 595 596 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 597 598 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 599 if (!req) 600 return -ENOMEM; 601 602 req->lvl = lvl; 603 req->num_regs = 1; 604 605 schq = hw->txschq_list[lvl][0]; 606 /* Set topology e.t.c configuration */ 607 if (lvl == NIX_TXSCH_LVL_SMQ) { 608 req->reg[0] = NIX_AF_SMQX_CFG(schq); 609 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU; 610 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 611 (0x2ULL << 36); 612 req->num_regs++; 613 /* MDQ config */ 614 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0]; 615 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 616 req->regval[1] = parent << 16; 617 req->num_regs++; 618 /* Set DWRR quantum */ 619 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 620 req->regval[2] = dwrr_val; 621 } else if (lvl == NIX_TXSCH_LVL_TL4) { 622 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0]; 623 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 624 req->regval[0] = parent << 16; 625 req->num_regs++; 626 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 627 req->regval[1] = dwrr_val; 628 } else if (lvl == NIX_TXSCH_LVL_TL3) { 629 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0]; 630 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 631 req->regval[0] = parent << 16; 632 req->num_regs++; 633 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 634 req->regval[1] = dwrr_val; 635 } else if (lvl == NIX_TXSCH_LVL_TL2) { 636 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0]; 637 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 638 req->regval[0] = parent << 16; 639 640 req->num_regs++; 641 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 642 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val; 643 644 req->num_regs++; 645 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 646 /* Enable this queue and backpressure */ 647 req->regval[2] = BIT_ULL(13) | BIT_ULL(12); 648 649 } else if (lvl == NIX_TXSCH_LVL_TL1) { 650 /* Default config for TL1. 651 * For VF this is always ignored. 652 */ 653 654 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 655 * clip it to 16384, so configuring a 24bit max value 656 * will work on both OTx2 and CN10K. 657 */ 658 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 659 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 660 661 req->num_regs++; 662 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 663 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 664 665 req->num_regs++; 666 req->reg[2] = NIX_AF_TL1X_CIR(schq); 667 req->regval[2] = 0; 668 } 669 670 return otx2_sync_mbox_msg(&pfvf->mbox); 671 } 672 673 int otx2_txsch_alloc(struct otx2_nic *pfvf) 674 { 675 struct nix_txsch_alloc_req *req; 676 int lvl; 677 678 /* Get memory to put this msg */ 679 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 680 if (!req) 681 return -ENOMEM; 682 683 /* Request one schq per level */ 684 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 685 req->schq[lvl] = 1; 686 687 return otx2_sync_mbox_msg(&pfvf->mbox); 688 } 689 690 int otx2_txschq_stop(struct otx2_nic *pfvf) 691 { 692 struct nix_txsch_free_req *free_req; 693 int lvl, schq, err; 694 695 mutex_lock(&pfvf->mbox.lock); 696 /* Free the transmit schedulers */ 697 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 698 if (!free_req) { 699 mutex_unlock(&pfvf->mbox.lock); 700 return -ENOMEM; 701 } 702 703 free_req->flags = TXSCHQ_FREE_ALL; 704 err = otx2_sync_mbox_msg(&pfvf->mbox); 705 mutex_unlock(&pfvf->mbox.lock); 706 707 /* Clear the txschq list */ 708 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 709 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 710 pfvf->hw.txschq_list[lvl][schq] = 0; 711 } 712 return err; 713 } 714 715 void otx2_sqb_flush(struct otx2_nic *pfvf) 716 { 717 int qidx, sqe_tail, sqe_head; 718 u64 incr, *ptr, val; 719 int timeout = 1000; 720 721 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 722 for (qidx = 0; qidx < pfvf->hw.tot_tx_queues; qidx++) { 723 incr = (u64)qidx << 32; 724 while (timeout) { 725 val = otx2_atomic64_add(incr, ptr); 726 sqe_head = (val >> 20) & 0x3F; 727 sqe_tail = (val >> 28) & 0x3F; 728 if (sqe_head == sqe_tail) 729 break; 730 usleep_range(1, 3); 731 timeout--; 732 } 733 } 734 } 735 736 /* RED and drop levels of CQ on packet reception. 737 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 738 */ 739 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 740 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 741 742 /* RED and drop levels of AURA for packet reception. 743 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 744 * Eg: For RQ length 1K, for pass/drop level 204/230. 745 * RED accepts pkts if free pointers > 102 & <= 205. 746 * Drops pkts if free pointers < 102. 747 */ 748 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 749 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 750 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 751 752 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 753 { 754 struct otx2_qset *qset = &pfvf->qset; 755 struct nix_aq_enq_req *aq; 756 757 /* Get memory to put this msg */ 758 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 759 if (!aq) 760 return -ENOMEM; 761 762 aq->rq.cq = qidx; 763 aq->rq.ena = 1; 764 aq->rq.pb_caching = 1; 765 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 766 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 767 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 768 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 769 aq->rq.qint_idx = 0; 770 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 771 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 772 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 773 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 774 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 775 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 776 777 /* Fill AQ info */ 778 aq->qidx = qidx; 779 aq->ctype = NIX_AQ_CTYPE_RQ; 780 aq->op = NIX_AQ_INSTOP_INIT; 781 782 return otx2_sync_mbox_msg(&pfvf->mbox); 783 } 784 785 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 786 { 787 struct otx2_nic *pfvf = dev; 788 struct otx2_snd_queue *sq; 789 struct nix_aq_enq_req *aq; 790 791 sq = &pfvf->qset.sq[qidx]; 792 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 793 /* Get memory to put this msg */ 794 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 795 if (!aq) 796 return -ENOMEM; 797 798 aq->sq.cq = pfvf->hw.rx_queues + qidx; 799 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 800 aq->sq.cq_ena = 1; 801 aq->sq.ena = 1; 802 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 803 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 804 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 805 aq->sq.default_chan = pfvf->hw.tx_chan_base; 806 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 807 aq->sq.sqb_aura = sqb_aura; 808 aq->sq.sq_int_ena = NIX_SQINT_BITS; 809 aq->sq.qint_idx = 0; 810 /* Due pipelining impact minimum 2000 unused SQ CQE's 811 * need to maintain to avoid CQ overflow. 812 */ 813 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 814 815 /* Fill AQ info */ 816 aq->qidx = qidx; 817 aq->ctype = NIX_AQ_CTYPE_SQ; 818 aq->op = NIX_AQ_INSTOP_INIT; 819 820 return otx2_sync_mbox_msg(&pfvf->mbox); 821 } 822 823 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 824 { 825 struct otx2_qset *qset = &pfvf->qset; 826 struct otx2_snd_queue *sq; 827 struct otx2_pool *pool; 828 int err; 829 830 pool = &pfvf->qset.pool[sqb_aura]; 831 sq = &qset->sq[qidx]; 832 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 833 sq->sqe_cnt = qset->sqe_cnt; 834 835 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 836 if (err) 837 return err; 838 839 if (qidx < pfvf->hw.tx_queues) { 840 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 841 TSO_HEADER_SIZE); 842 if (err) 843 return err; 844 } 845 846 sq->sqe_base = sq->sqe->base; 847 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 848 if (!sq->sg) 849 return -ENOMEM; 850 851 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) { 852 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 853 sizeof(*sq->timestamps)); 854 if (err) 855 return err; 856 } 857 858 sq->head = 0; 859 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 860 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 861 /* Set SQE threshold to 10% of total SQEs */ 862 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 863 sq->aura_id = sqb_aura; 864 sq->aura_fc_addr = pool->fc_addr->base; 865 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 866 867 sq->stats.bytes = 0; 868 sq->stats.pkts = 0; 869 870 return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); 871 872 } 873 874 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 875 { 876 struct otx2_qset *qset = &pfvf->qset; 877 int err, pool_id, non_xdp_queues; 878 struct nix_aq_enq_req *aq; 879 struct otx2_cq_queue *cq; 880 881 cq = &qset->cq[qidx]; 882 cq->cq_idx = qidx; 883 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues; 884 if (qidx < pfvf->hw.rx_queues) { 885 cq->cq_type = CQ_RX; 886 cq->cint_idx = qidx; 887 cq->cqe_cnt = qset->rqe_cnt; 888 if (pfvf->xdp_prog) 889 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0); 890 } else if (qidx < non_xdp_queues) { 891 cq->cq_type = CQ_TX; 892 cq->cint_idx = qidx - pfvf->hw.rx_queues; 893 cq->cqe_cnt = qset->sqe_cnt; 894 } else { 895 cq->cq_type = CQ_XDP; 896 cq->cint_idx = qidx - non_xdp_queues; 897 cq->cqe_cnt = qset->sqe_cnt; 898 } 899 cq->cqe_size = pfvf->qset.xqe_size; 900 901 /* Allocate memory for CQEs */ 902 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 903 if (err) 904 return err; 905 906 /* Save CQE CPU base for faster reference */ 907 cq->cqe_base = cq->cqe->base; 908 /* In case where all RQs auras point to single pool, 909 * all CQs receive buffer pool also point to same pool. 910 */ 911 pool_id = ((cq->cq_type == CQ_RX) && 912 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 913 cq->rbpool = &qset->pool[pool_id]; 914 cq->refill_task_sched = false; 915 916 /* Get memory to put this msg */ 917 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 918 if (!aq) 919 return -ENOMEM; 920 921 aq->cq.ena = 1; 922 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 923 aq->cq.caching = 1; 924 aq->cq.base = cq->cqe->iova; 925 aq->cq.cint_idx = cq->cint_idx; 926 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 927 aq->cq.qint_idx = 0; 928 aq->cq.avg_level = 255; 929 930 if (qidx < pfvf->hw.rx_queues) { 931 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 932 aq->cq.drop_ena = 1; 933 934 if (!is_otx2_lbkvf(pfvf->pdev)) { 935 /* Enable receive CQ backpressure */ 936 aq->cq.bp_ena = 1; 937 #ifdef CONFIG_DCB 938 aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]]; 939 #else 940 aq->cq.bpid = pfvf->bpid[0]; 941 #endif 942 943 /* Set backpressure level is same as cq pass level */ 944 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 945 } 946 } 947 948 /* Fill AQ info */ 949 aq->qidx = qidx; 950 aq->ctype = NIX_AQ_CTYPE_CQ; 951 aq->op = NIX_AQ_INSTOP_INIT; 952 953 return otx2_sync_mbox_msg(&pfvf->mbox); 954 } 955 956 static void otx2_pool_refill_task(struct work_struct *work) 957 { 958 struct otx2_cq_queue *cq; 959 struct otx2_pool *rbpool; 960 struct refill_work *wrk; 961 int qidx, free_ptrs = 0; 962 struct otx2_nic *pfvf; 963 dma_addr_t bufptr; 964 965 wrk = container_of(work, struct refill_work, pool_refill_work.work); 966 pfvf = wrk->pf; 967 qidx = wrk - pfvf->refill_wrk; 968 cq = &pfvf->qset.cq[qidx]; 969 rbpool = cq->rbpool; 970 free_ptrs = cq->pool_ptrs; 971 972 while (cq->pool_ptrs) { 973 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) { 974 /* Schedule a WQ if we fails to free atleast half of the 975 * pointers else enable napi for this RQ. 976 */ 977 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 978 struct delayed_work *dwork; 979 980 dwork = &wrk->pool_refill_work; 981 schedule_delayed_work(dwork, 982 msecs_to_jiffies(100)); 983 } else { 984 cq->refill_task_sched = false; 985 } 986 return; 987 } 988 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 989 cq->pool_ptrs--; 990 } 991 cq->refill_task_sched = false; 992 } 993 994 int otx2_config_nix_queues(struct otx2_nic *pfvf) 995 { 996 int qidx, err; 997 998 /* Initialize RX queues */ 999 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 1000 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 1001 1002 err = otx2_rq_init(pfvf, qidx, lpb_aura); 1003 if (err) 1004 return err; 1005 } 1006 1007 /* Initialize TX queues */ 1008 for (qidx = 0; qidx < pfvf->hw.tot_tx_queues; qidx++) { 1009 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1010 1011 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1012 if (err) 1013 return err; 1014 } 1015 1016 /* Initialize completion queues */ 1017 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1018 err = otx2_cq_init(pfvf, qidx); 1019 if (err) 1020 return err; 1021 } 1022 1023 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, 1024 NIX_LF_CQ_OP_STATUS); 1025 1026 /* Initialize work queue for receive buffer refill */ 1027 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1028 sizeof(struct refill_work), GFP_KERNEL); 1029 if (!pfvf->refill_wrk) 1030 return -ENOMEM; 1031 1032 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1033 pfvf->refill_wrk[qidx].pf = pfvf; 1034 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1035 otx2_pool_refill_task); 1036 } 1037 return 0; 1038 } 1039 1040 int otx2_config_nix(struct otx2_nic *pfvf) 1041 { 1042 struct nix_lf_alloc_req *nixlf; 1043 struct nix_lf_alloc_rsp *rsp; 1044 int err; 1045 1046 pfvf->qset.xqe_size = pfvf->hw.xqe_size; 1047 1048 /* Get memory to put this msg */ 1049 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1050 if (!nixlf) 1051 return -ENOMEM; 1052 1053 /* Set RQ/SQ/CQ counts */ 1054 nixlf->rq_cnt = pfvf->hw.rx_queues; 1055 nixlf->sq_cnt = pfvf->hw.tot_tx_queues; 1056 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1057 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1058 nixlf->rss_grps = MAX_RSS_GROUPS; 1059 nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64; 1060 /* We don't know absolute NPA LF idx attached. 1061 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1062 * NPA LF attached to this RVU PF/VF. 1063 */ 1064 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1065 /* Disable alignment pad, enable L2 length check, 1066 * enable L4 TCP/UDP checksum verification. 1067 */ 1068 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1069 1070 err = otx2_sync_mbox_msg(&pfvf->mbox); 1071 if (err) 1072 return err; 1073 1074 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1075 &nixlf->hdr); 1076 if (IS_ERR(rsp)) 1077 return PTR_ERR(rsp); 1078 1079 if (rsp->qints < 1) 1080 return -ENXIO; 1081 1082 return rsp->hdr.rc; 1083 } 1084 1085 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1086 { 1087 struct otx2_qset *qset = &pfvf->qset; 1088 struct otx2_hw *hw = &pfvf->hw; 1089 struct otx2_snd_queue *sq; 1090 int sqb, qidx; 1091 u64 iova, pa; 1092 1093 for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) { 1094 sq = &qset->sq[qidx]; 1095 if (!sq->sqb_ptrs) 1096 continue; 1097 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1098 if (!sq->sqb_ptrs[sqb]) 1099 continue; 1100 iova = sq->sqb_ptrs[sqb]; 1101 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1102 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1103 DMA_FROM_DEVICE, 1104 DMA_ATTR_SKIP_CPU_SYNC); 1105 put_page(virt_to_page(phys_to_virt(pa))); 1106 } 1107 sq->sqb_count = 0; 1108 } 1109 } 1110 1111 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1112 { 1113 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1114 u64 iova, pa; 1115 1116 if (type == AURA_NIX_SQ) { 1117 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1118 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1119 size = pfvf->hw.sqb_size; 1120 } 1121 if (type == AURA_NIX_RQ) { 1122 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1123 pool_end = pfvf->hw.rqpool_cnt; 1124 size = pfvf->rbsize; 1125 } 1126 1127 /* Free SQB and RQB pointers from the aura pool */ 1128 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1129 iova = otx2_aura_allocptr(pfvf, pool_id); 1130 while (iova) { 1131 if (type == AURA_NIX_RQ) 1132 iova -= OTX2_HEAD_ROOM; 1133 1134 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1135 dma_unmap_page_attrs(pfvf->dev, iova, size, 1136 DMA_FROM_DEVICE, 1137 DMA_ATTR_SKIP_CPU_SYNC); 1138 put_page(virt_to_page(phys_to_virt(pa))); 1139 iova = otx2_aura_allocptr(pfvf, pool_id); 1140 } 1141 } 1142 } 1143 1144 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1145 { 1146 struct otx2_pool *pool; 1147 int pool_id; 1148 1149 if (!pfvf->qset.pool) 1150 return; 1151 1152 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1153 pool = &pfvf->qset.pool[pool_id]; 1154 qmem_free(pfvf->dev, pool->stack); 1155 qmem_free(pfvf->dev, pool->fc_addr); 1156 } 1157 devm_kfree(pfvf->dev, pfvf->qset.pool); 1158 pfvf->qset.pool = NULL; 1159 } 1160 1161 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1162 int pool_id, int numptrs) 1163 { 1164 struct npa_aq_enq_req *aq; 1165 struct otx2_pool *pool; 1166 int err; 1167 1168 pool = &pfvf->qset.pool[pool_id]; 1169 1170 /* Allocate memory for HW to update Aura count. 1171 * Alloc one cache line, so that it fits all FC_STYPE modes. 1172 */ 1173 if (!pool->fc_addr) { 1174 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1175 if (err) 1176 return err; 1177 } 1178 1179 /* Initialize this aura's context via AF */ 1180 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1181 if (!aq) { 1182 /* Shared mbox memory buffer is full, flush it and retry */ 1183 err = otx2_sync_mbox_msg(&pfvf->mbox); 1184 if (err) 1185 return err; 1186 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1187 if (!aq) 1188 return -ENOMEM; 1189 } 1190 1191 aq->aura_id = aura_id; 1192 /* Will be filled by AF with correct pool context address */ 1193 aq->aura.pool_addr = pool_id; 1194 aq->aura.pool_caching = 1; 1195 aq->aura.shift = ilog2(numptrs) - 8; 1196 aq->aura.count = numptrs; 1197 aq->aura.limit = numptrs; 1198 aq->aura.avg_level = 255; 1199 aq->aura.ena = 1; 1200 aq->aura.fc_ena = 1; 1201 aq->aura.fc_addr = pool->fc_addr->iova; 1202 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1203 1204 /* Enable backpressure for RQ aura */ 1205 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1206 aq->aura.bp_ena = 0; 1207 /* If NIX1 LF is attached then specify NIX1_RX. 1208 * 1209 * Below NPA_AURA_S[BP_ENA] is set according to the 1210 * NPA_BPINTF_E enumeration given as: 1211 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1212 * NIX0_RX is 0x0 + 0*0x1 = 0 1213 * NIX1_RX is 0x0 + 1*0x1 = 1 1214 * But in HRM it is given that 1215 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1216 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1217 * enumerated by NPA_BPINTF_E." 1218 */ 1219 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1220 aq->aura.bp_ena = 1; 1221 #ifdef CONFIG_DCB 1222 aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]]; 1223 #else 1224 aq->aura.nix0_bpid = pfvf->bpid[0]; 1225 #endif 1226 1227 /* Set backpressure level for RQ's Aura */ 1228 aq->aura.bp = RQ_BP_LVL_AURA; 1229 } 1230 1231 /* Fill AQ info */ 1232 aq->ctype = NPA_AQ_CTYPE_AURA; 1233 aq->op = NPA_AQ_INSTOP_INIT; 1234 1235 return 0; 1236 } 1237 1238 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1239 int stack_pages, int numptrs, int buf_size) 1240 { 1241 struct npa_aq_enq_req *aq; 1242 struct otx2_pool *pool; 1243 int err; 1244 1245 pool = &pfvf->qset.pool[pool_id]; 1246 /* Alloc memory for stack which is used to store buffer pointers */ 1247 err = qmem_alloc(pfvf->dev, &pool->stack, 1248 stack_pages, pfvf->hw.stack_pg_bytes); 1249 if (err) 1250 return err; 1251 1252 pool->rbsize = buf_size; 1253 1254 /* Initialize this pool's context via AF */ 1255 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1256 if (!aq) { 1257 /* Shared mbox memory buffer is full, flush it and retry */ 1258 err = otx2_sync_mbox_msg(&pfvf->mbox); 1259 if (err) { 1260 qmem_free(pfvf->dev, pool->stack); 1261 return err; 1262 } 1263 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1264 if (!aq) { 1265 qmem_free(pfvf->dev, pool->stack); 1266 return -ENOMEM; 1267 } 1268 } 1269 1270 aq->aura_id = pool_id; 1271 aq->pool.stack_base = pool->stack->iova; 1272 aq->pool.stack_caching = 1; 1273 aq->pool.ena = 1; 1274 aq->pool.buf_size = buf_size / 128; 1275 aq->pool.stack_max_pages = stack_pages; 1276 aq->pool.shift = ilog2(numptrs) - 8; 1277 aq->pool.ptr_start = 0; 1278 aq->pool.ptr_end = ~0ULL; 1279 1280 /* Fill AQ info */ 1281 aq->ctype = NPA_AQ_CTYPE_POOL; 1282 aq->op = NPA_AQ_INSTOP_INIT; 1283 1284 return 0; 1285 } 1286 1287 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1288 { 1289 int qidx, pool_id, stack_pages, num_sqbs; 1290 struct otx2_qset *qset = &pfvf->qset; 1291 struct otx2_hw *hw = &pfvf->hw; 1292 struct otx2_snd_queue *sq; 1293 struct otx2_pool *pool; 1294 dma_addr_t bufptr; 1295 int err, ptr; 1296 1297 /* Calculate number of SQBs needed. 1298 * 1299 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1300 * Last SQE is used for pointing to next SQB. 1301 */ 1302 num_sqbs = (hw->sqb_size / 128) - 1; 1303 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1304 1305 /* Get no of stack pages needed */ 1306 stack_pages = 1307 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1308 1309 for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) { 1310 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1311 /* Initialize aura context */ 1312 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1313 if (err) 1314 goto fail; 1315 1316 /* Initialize pool context */ 1317 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1318 num_sqbs, hw->sqb_size); 1319 if (err) 1320 goto fail; 1321 } 1322 1323 /* Flush accumulated messages */ 1324 err = otx2_sync_mbox_msg(&pfvf->mbox); 1325 if (err) 1326 goto fail; 1327 1328 /* Allocate pointers and free them to aura/pool */ 1329 for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) { 1330 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1331 pool = &pfvf->qset.pool[pool_id]; 1332 1333 sq = &qset->sq[qidx]; 1334 sq->sqb_count = 0; 1335 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1336 if (!sq->sqb_ptrs) 1337 return -ENOMEM; 1338 1339 for (ptr = 0; ptr < num_sqbs; ptr++) { 1340 if (otx2_alloc_rbuf(pfvf, pool, &bufptr)) 1341 return -ENOMEM; 1342 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1343 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1344 } 1345 } 1346 1347 return 0; 1348 fail: 1349 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1350 otx2_aura_pool_free(pfvf); 1351 return err; 1352 } 1353 1354 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1355 { 1356 struct otx2_hw *hw = &pfvf->hw; 1357 int stack_pages, pool_id, rq; 1358 struct otx2_pool *pool; 1359 int err, ptr, num_ptrs; 1360 dma_addr_t bufptr; 1361 1362 num_ptrs = pfvf->qset.rqe_cnt; 1363 1364 stack_pages = 1365 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1366 1367 for (rq = 0; rq < hw->rx_queues; rq++) { 1368 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1369 /* Initialize aura context */ 1370 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1371 if (err) 1372 goto fail; 1373 } 1374 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1375 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1376 num_ptrs, pfvf->rbsize); 1377 if (err) 1378 goto fail; 1379 } 1380 1381 /* Flush accumulated messages */ 1382 err = otx2_sync_mbox_msg(&pfvf->mbox); 1383 if (err) 1384 goto fail; 1385 1386 /* Allocate pointers and free them to aura/pool */ 1387 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1388 pool = &pfvf->qset.pool[pool_id]; 1389 for (ptr = 0; ptr < num_ptrs; ptr++) { 1390 if (otx2_alloc_rbuf(pfvf, pool, &bufptr)) 1391 return -ENOMEM; 1392 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1393 bufptr + OTX2_HEAD_ROOM); 1394 } 1395 } 1396 1397 return 0; 1398 fail: 1399 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1400 otx2_aura_pool_free(pfvf); 1401 return err; 1402 } 1403 1404 int otx2_config_npa(struct otx2_nic *pfvf) 1405 { 1406 struct otx2_qset *qset = &pfvf->qset; 1407 struct npa_lf_alloc_req *npalf; 1408 struct otx2_hw *hw = &pfvf->hw; 1409 int aura_cnt; 1410 1411 /* Pool - Stack of free buffer pointers 1412 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1413 */ 1414 1415 if (!hw->pool_cnt) 1416 return -EINVAL; 1417 1418 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1419 sizeof(struct otx2_pool), GFP_KERNEL); 1420 if (!qset->pool) 1421 return -ENOMEM; 1422 1423 /* Get memory to put this msg */ 1424 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1425 if (!npalf) 1426 return -ENOMEM; 1427 1428 /* Set aura and pool counts */ 1429 npalf->nr_pools = hw->pool_cnt; 1430 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1431 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1432 1433 return otx2_sync_mbox_msg(&pfvf->mbox); 1434 } 1435 1436 int otx2_detach_resources(struct mbox *mbox) 1437 { 1438 struct rsrc_detach *detach; 1439 1440 mutex_lock(&mbox->lock); 1441 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1442 if (!detach) { 1443 mutex_unlock(&mbox->lock); 1444 return -ENOMEM; 1445 } 1446 1447 /* detach all */ 1448 detach->partial = false; 1449 1450 /* Send detach request to AF */ 1451 otx2_mbox_msg_send(&mbox->mbox, 0); 1452 mutex_unlock(&mbox->lock); 1453 return 0; 1454 } 1455 EXPORT_SYMBOL(otx2_detach_resources); 1456 1457 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1458 { 1459 struct rsrc_attach *attach; 1460 struct msg_req *msix; 1461 int err; 1462 1463 mutex_lock(&pfvf->mbox.lock); 1464 /* Get memory to put this msg */ 1465 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1466 if (!attach) { 1467 mutex_unlock(&pfvf->mbox.lock); 1468 return -ENOMEM; 1469 } 1470 1471 attach->npalf = true; 1472 attach->nixlf = true; 1473 1474 /* Send attach request to AF */ 1475 err = otx2_sync_mbox_msg(&pfvf->mbox); 1476 if (err) { 1477 mutex_unlock(&pfvf->mbox.lock); 1478 return err; 1479 } 1480 1481 pfvf->nix_blkaddr = BLKADDR_NIX0; 1482 1483 /* If the platform has two NIX blocks then LF may be 1484 * allocated from NIX1. 1485 */ 1486 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1487 pfvf->nix_blkaddr = BLKADDR_NIX1; 1488 1489 /* Get NPA and NIX MSIX vector offsets */ 1490 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1491 if (!msix) { 1492 mutex_unlock(&pfvf->mbox.lock); 1493 return -ENOMEM; 1494 } 1495 1496 err = otx2_sync_mbox_msg(&pfvf->mbox); 1497 if (err) { 1498 mutex_unlock(&pfvf->mbox.lock); 1499 return err; 1500 } 1501 mutex_unlock(&pfvf->mbox.lock); 1502 1503 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1504 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1505 dev_err(pfvf->dev, 1506 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1507 return -EINVAL; 1508 } 1509 1510 return 0; 1511 } 1512 EXPORT_SYMBOL(otx2_attach_npa_nix); 1513 1514 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1515 { 1516 struct hwctx_disable_req *req; 1517 1518 mutex_lock(&mbox->lock); 1519 /* Request AQ to disable this context */ 1520 if (npa) 1521 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1522 else 1523 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1524 1525 if (!req) { 1526 mutex_unlock(&mbox->lock); 1527 return; 1528 } 1529 1530 req->ctype = type; 1531 1532 if (otx2_sync_mbox_msg(mbox)) 1533 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1534 __func__); 1535 1536 mutex_unlock(&mbox->lock); 1537 } 1538 1539 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1540 { 1541 struct nix_bp_cfg_req *req; 1542 1543 if (enable) 1544 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1545 else 1546 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1547 1548 if (!req) 1549 return -ENOMEM; 1550 1551 req->chan_base = 0; 1552 #ifdef CONFIG_DCB 1553 req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1; 1554 req->bpid_per_chan = pfvf->pfc_en ? 1 : 0; 1555 #else 1556 req->chan_cnt = 1; 1557 req->bpid_per_chan = 0; 1558 #endif 1559 1560 1561 return otx2_sync_mbox_msg(&pfvf->mbox); 1562 } 1563 EXPORT_SYMBOL(otx2_nix_config_bp); 1564 1565 /* Mbox message handlers */ 1566 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1567 struct cgx_stats_rsp *rsp) 1568 { 1569 int id; 1570 1571 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1572 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1573 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1574 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1575 } 1576 1577 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1578 struct cgx_fec_stats_rsp *rsp) 1579 { 1580 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1581 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1582 } 1583 1584 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1585 struct nix_txsch_alloc_rsp *rsp) 1586 { 1587 int lvl, schq; 1588 1589 /* Setup transmit scheduler list */ 1590 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 1591 for (schq = 0; schq < rsp->schq[lvl]; schq++) 1592 pf->hw.txschq_list[lvl][schq] = 1593 rsp->schq_list[lvl][schq]; 1594 } 1595 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc); 1596 1597 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1598 struct npa_lf_alloc_rsp *rsp) 1599 { 1600 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1601 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1602 } 1603 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1604 1605 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1606 struct nix_lf_alloc_rsp *rsp) 1607 { 1608 pfvf->hw.sqb_size = rsp->sqb_size; 1609 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1610 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1611 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1612 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1613 pfvf->hw.cgx_links = rsp->cgx_links; 1614 pfvf->hw.lbk_links = rsp->lbk_links; 1615 pfvf->hw.tx_link = rsp->tx_link; 1616 } 1617 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1618 1619 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1620 struct msix_offset_rsp *rsp) 1621 { 1622 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1623 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1624 } 1625 EXPORT_SYMBOL(mbox_handler_msix_offset); 1626 1627 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1628 struct nix_bp_cfg_rsp *rsp) 1629 { 1630 int chan, chan_id; 1631 1632 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1633 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1634 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1635 } 1636 } 1637 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1638 1639 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1640 { 1641 struct otx2_qset *qset = &pfvf->qset; 1642 struct otx2_hw *hw = &pfvf->hw; 1643 int irq, qidx; 1644 1645 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1646 qidx < n; 1647 qidx++, irq++) { 1648 int vector = pci_irq_vector(pfvf->pdev, irq); 1649 1650 irq_set_affinity_hint(vector, NULL); 1651 free_cpumask_var(hw->affinity_mask[irq]); 1652 free_irq(vector, &qset->napi[qidx]); 1653 } 1654 } 1655 1656 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1657 { 1658 struct otx2_hw *hw = &pfvf->hw; 1659 int vec, cpu, irq, cint; 1660 1661 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1662 cpu = cpumask_first(cpu_online_mask); 1663 1664 /* CQ interrupts */ 1665 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1666 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1667 return; 1668 1669 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1670 1671 irq = pci_irq_vector(pfvf->pdev, vec); 1672 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1673 1674 cpu = cpumask_next(cpu, cpu_online_mask); 1675 if (unlikely(cpu >= nr_cpu_ids)) 1676 cpu = 0; 1677 } 1678 } 1679 1680 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1681 { 1682 struct nix_hw_info *rsp; 1683 struct msg_req *req; 1684 u16 max_mtu; 1685 int rc; 1686 1687 mutex_lock(&pfvf->mbox.lock); 1688 1689 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1690 if (!req) { 1691 rc = -ENOMEM; 1692 goto out; 1693 } 1694 1695 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1696 if (!rc) { 1697 rsp = (struct nix_hw_info *) 1698 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1699 1700 /* HW counts VLAN insertion bytes (8 for double tag) 1701 * irrespective of whether SQE is requesting to insert VLAN 1702 * in the packet or not. Hence these 8 bytes have to be 1703 * discounted from max packet size otherwise HW will throw 1704 * SMQ errors 1705 */ 1706 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1707 1708 /* Also save DWRR MTU, needed for DWRR weight calculation */ 1709 pfvf->hw.dwrr_mtu = rsp->rpm_dwrr_mtu; 1710 if (!pfvf->hw.dwrr_mtu) 1711 pfvf->hw.dwrr_mtu = 1; 1712 } 1713 1714 out: 1715 mutex_unlock(&pfvf->mbox.lock); 1716 if (rc) { 1717 dev_warn(pfvf->dev, 1718 "Failed to get MTU from hardware setting default value(1500)\n"); 1719 max_mtu = 1500; 1720 } 1721 return max_mtu; 1722 } 1723 EXPORT_SYMBOL(otx2_get_max_mtu); 1724 1725 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features) 1726 { 1727 netdev_features_t changed = features ^ netdev->features; 1728 struct otx2_nic *pfvf = netdev_priv(netdev); 1729 bool ntuple = !!(features & NETIF_F_NTUPLE); 1730 bool tc = !!(features & NETIF_F_HW_TC); 1731 1732 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1733 otx2_destroy_ntuple_flows(pfvf); 1734 1735 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1736 if (!pfvf->flow_cfg->max_flows) { 1737 netdev_err(netdev, 1738 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1739 return -EINVAL; 1740 } 1741 } 1742 1743 if ((changed & NETIF_F_HW_TC) && tc) { 1744 if (!pfvf->flow_cfg->max_flows) { 1745 netdev_err(netdev, 1746 "Can't enable TC, MCAM entries not allocated\n"); 1747 return -EINVAL; 1748 } 1749 } 1750 1751 if ((changed & NETIF_F_HW_TC) && !tc && 1752 pfvf->flow_cfg && pfvf->flow_cfg->nr_flows) { 1753 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1754 return -EBUSY; 1755 } 1756 1757 if ((changed & NETIF_F_NTUPLE) && ntuple && 1758 (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) { 1759 netdev_err(netdev, 1760 "Can't enable NTUPLE when TC is active, disable TC and retry\n"); 1761 return -EINVAL; 1762 } 1763 1764 if ((changed & NETIF_F_HW_TC) && tc && 1765 (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) { 1766 netdev_err(netdev, 1767 "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n"); 1768 return -EINVAL; 1769 } 1770 1771 return 0; 1772 } 1773 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features); 1774 1775 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1776 int __weak \ 1777 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1778 struct _req_type *req, \ 1779 struct _rsp_type *rsp) \ 1780 { \ 1781 /* Nothing to do here */ \ 1782 return 0; \ 1783 } \ 1784 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1785 MBOX_UP_CGX_MESSAGES 1786 #undef M 1787