1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 #include <net/page_pool/helpers.h> 11 #include <net/tso.h> 12 #include <linux/bitfield.h> 13 14 #include "otx2_reg.h" 15 #include "otx2_common.h" 16 #include "otx2_struct.h" 17 #include "cn10k.h" 18 19 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 20 struct otx2_nic *pfvf, int qidx) 21 { 22 u64 incr = (u64)qidx << 32; 23 u64 *ptr; 24 25 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 26 stats->bytes = otx2_atomic64_add(incr, ptr); 27 28 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 29 stats->pkts = otx2_atomic64_add(incr, ptr); 30 } 31 32 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 33 struct otx2_nic *pfvf, int qidx) 34 { 35 u64 incr = (u64)qidx << 32; 36 u64 *ptr; 37 38 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 39 stats->bytes = otx2_atomic64_add(incr, ptr); 40 41 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 42 stats->pkts = otx2_atomic64_add(incr, ptr); 43 } 44 45 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 46 { 47 struct msg_req *req; 48 49 if (!netif_running(pfvf->netdev)) 50 return; 51 52 mutex_lock(&pfvf->mbox.lock); 53 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 54 if (!req) { 55 mutex_unlock(&pfvf->mbox.lock); 56 return; 57 } 58 59 otx2_sync_mbox_msg(&pfvf->mbox); 60 mutex_unlock(&pfvf->mbox.lock); 61 } 62 63 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 64 { 65 struct msg_req *req; 66 67 if (!netif_running(pfvf->netdev)) 68 return; 69 mutex_lock(&pfvf->mbox.lock); 70 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 71 if (req) 72 otx2_sync_mbox_msg(&pfvf->mbox); 73 mutex_unlock(&pfvf->mbox.lock); 74 } 75 76 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 77 { 78 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 79 80 if (!pfvf->qset.rq) 81 return 0; 82 83 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 84 return 1; 85 } 86 87 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 88 { 89 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 90 91 if (!pfvf->qset.sq) 92 return 0; 93 94 if (qidx >= pfvf->hw.non_qos_queues) { 95 if (!test_bit(qidx - pfvf->hw.non_qos_queues, pfvf->qos.qos_sq_bmap)) 96 return 0; 97 } 98 99 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 100 return 1; 101 } 102 103 void otx2_get_dev_stats(struct otx2_nic *pfvf) 104 { 105 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 106 107 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 108 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 109 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 110 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 111 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 112 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 113 dev_stats->rx_mcast_frames + 114 dev_stats->rx_ucast_frames; 115 116 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 117 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 118 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 119 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 120 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 121 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 122 dev_stats->tx_mcast_frames + 123 dev_stats->tx_ucast_frames; 124 } 125 126 void otx2_get_stats64(struct net_device *netdev, 127 struct rtnl_link_stats64 *stats) 128 { 129 struct otx2_nic *pfvf = netdev_priv(netdev); 130 struct otx2_dev_stats *dev_stats; 131 132 otx2_get_dev_stats(pfvf); 133 134 dev_stats = &pfvf->hw.dev_stats; 135 stats->rx_bytes = dev_stats->rx_bytes; 136 stats->rx_packets = dev_stats->rx_frames; 137 stats->rx_dropped = dev_stats->rx_drops; 138 stats->multicast = dev_stats->rx_mcast_frames; 139 140 stats->tx_bytes = dev_stats->tx_bytes; 141 stats->tx_packets = dev_stats->tx_frames; 142 stats->tx_dropped = dev_stats->tx_drops; 143 } 144 EXPORT_SYMBOL(otx2_get_stats64); 145 146 /* Sync MAC address with RVU AF */ 147 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 148 { 149 struct nix_set_mac_addr *req; 150 int err; 151 152 mutex_lock(&pfvf->mbox.lock); 153 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 154 if (!req) { 155 mutex_unlock(&pfvf->mbox.lock); 156 return -ENOMEM; 157 } 158 159 ether_addr_copy(req->mac_addr, mac); 160 161 err = otx2_sync_mbox_msg(&pfvf->mbox); 162 mutex_unlock(&pfvf->mbox.lock); 163 return err; 164 } 165 166 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 167 struct net_device *netdev) 168 { 169 struct nix_get_mac_addr_rsp *rsp; 170 struct mbox_msghdr *msghdr; 171 struct msg_req *req; 172 int err; 173 174 mutex_lock(&pfvf->mbox.lock); 175 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 176 if (!req) { 177 mutex_unlock(&pfvf->mbox.lock); 178 return -ENOMEM; 179 } 180 181 err = otx2_sync_mbox_msg(&pfvf->mbox); 182 if (err) { 183 mutex_unlock(&pfvf->mbox.lock); 184 return err; 185 } 186 187 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 188 if (IS_ERR(msghdr)) { 189 mutex_unlock(&pfvf->mbox.lock); 190 return PTR_ERR(msghdr); 191 } 192 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 193 eth_hw_addr_set(netdev, rsp->mac_addr); 194 mutex_unlock(&pfvf->mbox.lock); 195 196 return 0; 197 } 198 199 int otx2_set_mac_address(struct net_device *netdev, void *p) 200 { 201 struct otx2_nic *pfvf = netdev_priv(netdev); 202 struct sockaddr *addr = p; 203 204 if (!is_valid_ether_addr(addr->sa_data)) 205 return -EADDRNOTAVAIL; 206 207 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 208 eth_hw_addr_set(netdev, addr->sa_data); 209 /* update dmac field in vlan offload rule */ 210 if (netif_running(netdev) && 211 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 212 otx2_install_rxvlan_offload_flow(pfvf); 213 /* update dmac address in ntuple and DMAC filter list */ 214 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 215 otx2_dmacflt_update_pfmac_flow(pfvf); 216 } else { 217 return -EPERM; 218 } 219 220 return 0; 221 } 222 EXPORT_SYMBOL(otx2_set_mac_address); 223 224 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 225 { 226 struct nix_frs_cfg *req; 227 u16 maxlen; 228 int err; 229 230 maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 231 232 mutex_lock(&pfvf->mbox.lock); 233 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 234 if (!req) { 235 mutex_unlock(&pfvf->mbox.lock); 236 return -ENOMEM; 237 } 238 239 req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 240 241 /* Use max receive length supported by hardware for loopback devices */ 242 if (is_otx2_lbkvf(pfvf->pdev)) 243 req->maxlen = maxlen; 244 245 err = otx2_sync_mbox_msg(&pfvf->mbox); 246 mutex_unlock(&pfvf->mbox.lock); 247 return err; 248 } 249 250 int otx2_config_pause_frm(struct otx2_nic *pfvf) 251 { 252 struct cgx_pause_frm_cfg *req; 253 int err; 254 255 if (is_otx2_lbkvf(pfvf->pdev)) 256 return 0; 257 258 mutex_lock(&pfvf->mbox.lock); 259 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 260 if (!req) { 261 err = -ENOMEM; 262 goto unlock; 263 } 264 265 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 266 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 267 req->set = 1; 268 269 err = otx2_sync_mbox_msg(&pfvf->mbox); 270 unlock: 271 mutex_unlock(&pfvf->mbox.lock); 272 return err; 273 } 274 EXPORT_SYMBOL(otx2_config_pause_frm); 275 276 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 277 { 278 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 279 struct nix_rss_flowkey_cfg_rsp *rsp; 280 struct nix_rss_flowkey_cfg *req; 281 int err; 282 283 mutex_lock(&pfvf->mbox.lock); 284 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 285 if (!req) { 286 mutex_unlock(&pfvf->mbox.lock); 287 return -ENOMEM; 288 } 289 req->mcam_index = -1; /* Default or reserved index */ 290 req->flowkey_cfg = rss->flowkey_cfg; 291 req->group = DEFAULT_RSS_CONTEXT_GROUP; 292 293 err = otx2_sync_mbox_msg(&pfvf->mbox); 294 if (err) 295 goto fail; 296 297 rsp = (struct nix_rss_flowkey_cfg_rsp *) 298 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 299 if (IS_ERR(rsp)) { 300 err = PTR_ERR(rsp); 301 goto fail; 302 } 303 304 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 305 fail: 306 mutex_unlock(&pfvf->mbox.lock); 307 return err; 308 } 309 310 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 311 { 312 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 313 const int index = rss->rss_size * ctx_id; 314 struct mbox *mbox = &pfvf->mbox; 315 struct otx2_rss_ctx *rss_ctx; 316 struct nix_aq_enq_req *aq; 317 int idx, err; 318 319 mutex_lock(&mbox->lock); 320 rss_ctx = rss->rss_ctx[ctx_id]; 321 /* Get memory to put this msg */ 322 for (idx = 0; idx < rss->rss_size; idx++) { 323 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 324 if (!aq) { 325 /* The shared memory buffer can be full. 326 * Flush it and retry 327 */ 328 err = otx2_sync_mbox_msg(mbox); 329 if (err) { 330 mutex_unlock(&mbox->lock); 331 return err; 332 } 333 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 334 if (!aq) { 335 mutex_unlock(&mbox->lock); 336 return -ENOMEM; 337 } 338 } 339 340 aq->rss.rq = rss_ctx->ind_tbl[idx]; 341 342 /* Fill AQ info */ 343 aq->qidx = index + idx; 344 aq->ctype = NIX_AQ_CTYPE_RSS; 345 aq->op = NIX_AQ_INSTOP_INIT; 346 } 347 err = otx2_sync_mbox_msg(mbox); 348 mutex_unlock(&mbox->lock); 349 return err; 350 } 351 352 void otx2_set_rss_key(struct otx2_nic *pfvf) 353 { 354 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 355 u64 *key = (u64 *)&rss->key[4]; 356 int idx; 357 358 /* 352bit or 44byte key needs to be configured as below 359 * NIX_LF_RX_SECRETX0 = key<351:288> 360 * NIX_LF_RX_SECRETX1 = key<287:224> 361 * NIX_LF_RX_SECRETX2 = key<223:160> 362 * NIX_LF_RX_SECRETX3 = key<159:96> 363 * NIX_LF_RX_SECRETX4 = key<95:32> 364 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 365 */ 366 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 367 (u64)(*((u32 *)&rss->key)) << 32); 368 idx = sizeof(rss->key) / sizeof(u64); 369 while (idx > 0) { 370 idx--; 371 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 372 } 373 } 374 375 int otx2_rss_init(struct otx2_nic *pfvf) 376 { 377 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 378 struct otx2_rss_ctx *rss_ctx; 379 int idx, ret = 0; 380 381 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 382 383 /* Init RSS key if it is not setup already */ 384 if (!rss->enable) 385 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 386 otx2_set_rss_key(pfvf); 387 388 if (!netif_is_rxfh_configured(pfvf->netdev)) { 389 /* Set RSS group 0 as default indirection table */ 390 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 391 GFP_KERNEL); 392 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 393 return -ENOMEM; 394 395 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 396 for (idx = 0; idx < rss->rss_size; idx++) 397 rss_ctx->ind_tbl[idx] = 398 ethtool_rxfh_indir_default(idx, 399 pfvf->hw.rx_queues); 400 } 401 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 402 if (ret) 403 return ret; 404 405 /* Flowkey or hash config to be used for generating flow tag */ 406 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 407 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 408 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 409 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 410 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 411 412 ret = otx2_set_flowkey_cfg(pfvf); 413 if (ret) 414 return ret; 415 416 rss->enable = true; 417 return 0; 418 } 419 420 /* Setup UDP segmentation algorithm in HW */ 421 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 422 { 423 struct nix_lso_format *field; 424 425 field = (struct nix_lso_format *)&lso->fields[0]; 426 lso->field_mask = GENMASK(18, 0); 427 428 /* IP's Length field */ 429 field->layer = NIX_TXLAYER_OL3; 430 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 431 field->offset = v4 ? 2 : 4; 432 field->sizem1 = 1; /* i.e 2 bytes */ 433 field->alg = NIX_LSOALG_ADD_PAYLEN; 434 field++; 435 436 /* No ID field in IPv6 header */ 437 if (v4) { 438 /* Increment IPID */ 439 field->layer = NIX_TXLAYER_OL3; 440 field->offset = 4; 441 field->sizem1 = 1; /* i.e 2 bytes */ 442 field->alg = NIX_LSOALG_ADD_SEGNUM; 443 field++; 444 } 445 446 /* Update length in UDP header */ 447 field->layer = NIX_TXLAYER_OL4; 448 field->offset = 4; 449 field->sizem1 = 1; 450 field->alg = NIX_LSOALG_ADD_PAYLEN; 451 } 452 453 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 454 void otx2_setup_segmentation(struct otx2_nic *pfvf) 455 { 456 struct nix_lso_format_cfg_rsp *rsp; 457 struct nix_lso_format_cfg *lso; 458 struct otx2_hw *hw = &pfvf->hw; 459 int err; 460 461 mutex_lock(&pfvf->mbox.lock); 462 463 /* UDPv4 segmentation */ 464 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 465 if (!lso) 466 goto fail; 467 468 /* Setup UDP/IP header fields that HW should update per segment */ 469 otx2_setup_udp_segmentation(lso, true); 470 471 err = otx2_sync_mbox_msg(&pfvf->mbox); 472 if (err) 473 goto fail; 474 475 rsp = (struct nix_lso_format_cfg_rsp *) 476 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 477 if (IS_ERR(rsp)) 478 goto fail; 479 480 hw->lso_udpv4_idx = rsp->lso_format_idx; 481 482 /* UDPv6 segmentation */ 483 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 484 if (!lso) 485 goto fail; 486 487 /* Setup UDP/IP header fields that HW should update per segment */ 488 otx2_setup_udp_segmentation(lso, false); 489 490 err = otx2_sync_mbox_msg(&pfvf->mbox); 491 if (err) 492 goto fail; 493 494 rsp = (struct nix_lso_format_cfg_rsp *) 495 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 496 if (IS_ERR(rsp)) 497 goto fail; 498 499 hw->lso_udpv6_idx = rsp->lso_format_idx; 500 mutex_unlock(&pfvf->mbox.lock); 501 return; 502 fail: 503 mutex_unlock(&pfvf->mbox.lock); 504 netdev_info(pfvf->netdev, 505 "Failed to get LSO index for UDP GSO offload, disabling\n"); 506 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 507 } 508 509 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 510 { 511 /* Configure CQE interrupt coalescing parameters 512 * 513 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 514 * set 1 less than cq_ecount_wait. And cq_time_wait is in 515 * usecs, convert that to 100ns count. 516 */ 517 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 518 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 519 ((u64)pfvf->hw.cq_qcount_wait << 32) | 520 (pfvf->hw.cq_ecount_wait - 1)); 521 } 522 523 static int otx2_alloc_pool_buf(struct otx2_nic *pfvf, struct otx2_pool *pool, 524 dma_addr_t *dma) 525 { 526 unsigned int offset = 0; 527 struct page *page; 528 size_t sz; 529 530 sz = SKB_DATA_ALIGN(pool->rbsize); 531 sz = ALIGN(sz, OTX2_ALIGN); 532 533 page = page_pool_alloc_frag(pool->page_pool, &offset, sz, GFP_ATOMIC); 534 if (unlikely(!page)) 535 return -ENOMEM; 536 537 *dma = page_pool_get_dma_addr(page) + offset; 538 return 0; 539 } 540 541 static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 542 dma_addr_t *dma) 543 { 544 u8 *buf; 545 546 if (pool->page_pool) 547 return otx2_alloc_pool_buf(pfvf, pool, dma); 548 549 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 550 if (unlikely(!buf)) 551 return -ENOMEM; 552 553 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 554 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 555 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 556 page_frag_free(buf); 557 return -ENOMEM; 558 } 559 560 return 0; 561 } 562 563 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 564 dma_addr_t *dma) 565 { 566 int ret; 567 568 local_bh_disable(); 569 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 570 local_bh_enable(); 571 return ret; 572 } 573 574 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 575 dma_addr_t *dma) 576 { 577 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) { 578 struct refill_work *work; 579 struct delayed_work *dwork; 580 581 work = &pfvf->refill_wrk[cq->cq_idx]; 582 dwork = &work->pool_refill_work; 583 /* Schedule a task if no other task is running */ 584 if (!cq->refill_task_sched) { 585 cq->refill_task_sched = true; 586 schedule_delayed_work(dwork, 587 msecs_to_jiffies(100)); 588 } 589 return -ENOMEM; 590 } 591 return 0; 592 } 593 594 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 595 { 596 struct otx2_nic *pfvf = netdev_priv(netdev); 597 598 schedule_work(&pfvf->reset_task); 599 } 600 EXPORT_SYMBOL(otx2_tx_timeout); 601 602 void otx2_get_mac_from_af(struct net_device *netdev) 603 { 604 struct otx2_nic *pfvf = netdev_priv(netdev); 605 int err; 606 607 err = otx2_hw_get_mac_addr(pfvf, netdev); 608 if (err) 609 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 610 611 /* If AF doesn't provide a valid MAC, generate a random one */ 612 if (!is_valid_ether_addr(netdev->dev_addr)) 613 eth_hw_addr_random(netdev); 614 } 615 EXPORT_SYMBOL(otx2_get_mac_from_af); 616 617 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc) 618 { 619 u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC]; 620 struct otx2_hw *hw = &pfvf->hw; 621 struct nix_txschq_config *req; 622 u64 schq, parent; 623 u64 dwrr_val; 624 625 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 626 627 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 628 if (!req) 629 return -ENOMEM; 630 631 req->lvl = lvl; 632 req->num_regs = 1; 633 634 schq_list = hw->txschq_list; 635 #ifdef CONFIG_DCB 636 if (txschq_for_pfc) 637 schq_list = pfvf->pfc_schq_list; 638 #endif 639 640 schq = schq_list[lvl][prio]; 641 /* Set topology e.t.c configuration */ 642 if (lvl == NIX_TXSCH_LVL_SMQ) { 643 req->reg[0] = NIX_AF_SMQX_CFG(schq); 644 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU; 645 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 646 (0x2ULL << 36); 647 /* Set link type for DWRR MTU selection on CN10K silicons */ 648 if (!is_dev_otx2(pfvf->pdev)) 649 req->regval[0] |= FIELD_PREP(GENMASK_ULL(58, 57), 650 (u64)hw->smq_link_type); 651 req->num_regs++; 652 /* MDQ config */ 653 parent = schq_list[NIX_TXSCH_LVL_TL4][prio]; 654 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 655 req->regval[1] = parent << 16; 656 req->num_regs++; 657 /* Set DWRR quantum */ 658 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 659 req->regval[2] = dwrr_val; 660 } else if (lvl == NIX_TXSCH_LVL_TL4) { 661 parent = schq_list[NIX_TXSCH_LVL_TL3][prio]; 662 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 663 req->regval[0] = parent << 16; 664 req->num_regs++; 665 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 666 req->regval[1] = dwrr_val; 667 } else if (lvl == NIX_TXSCH_LVL_TL3) { 668 parent = schq_list[NIX_TXSCH_LVL_TL2][prio]; 669 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 670 req->regval[0] = parent << 16; 671 req->num_regs++; 672 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 673 req->regval[1] = dwrr_val; 674 if (lvl == hw->txschq_link_cfg_lvl) { 675 req->num_regs++; 676 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 677 /* Enable this queue and backpressure 678 * and set relative channel 679 */ 680 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 681 } 682 } else if (lvl == NIX_TXSCH_LVL_TL2) { 683 parent = schq_list[NIX_TXSCH_LVL_TL1][prio]; 684 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 685 req->regval[0] = parent << 16; 686 687 req->num_regs++; 688 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 689 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val; 690 691 if (lvl == hw->txschq_link_cfg_lvl) { 692 req->num_regs++; 693 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 694 /* Enable this queue and backpressure 695 * and set relative channel 696 */ 697 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 698 } 699 } else if (lvl == NIX_TXSCH_LVL_TL1) { 700 /* Default config for TL1. 701 * For VF this is always ignored. 702 */ 703 704 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 705 * clip it to 16384, so configuring a 24bit max value 706 * will work on both OTx2 and CN10K. 707 */ 708 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 709 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 710 711 req->num_regs++; 712 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 713 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 714 715 req->num_regs++; 716 req->reg[2] = NIX_AF_TL1X_CIR(schq); 717 req->regval[2] = 0; 718 } 719 720 return otx2_sync_mbox_msg(&pfvf->mbox); 721 } 722 EXPORT_SYMBOL(otx2_txschq_config); 723 724 int otx2_smq_flush(struct otx2_nic *pfvf, int smq) 725 { 726 struct nix_txschq_config *req; 727 int rc; 728 729 mutex_lock(&pfvf->mbox.lock); 730 731 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 732 if (!req) { 733 mutex_unlock(&pfvf->mbox.lock); 734 return -ENOMEM; 735 } 736 737 req->lvl = NIX_TXSCH_LVL_SMQ; 738 req->reg[0] = NIX_AF_SMQX_CFG(smq); 739 req->regval[0] |= BIT_ULL(49); 740 req->num_regs++; 741 742 rc = otx2_sync_mbox_msg(&pfvf->mbox); 743 mutex_unlock(&pfvf->mbox.lock); 744 return rc; 745 } 746 EXPORT_SYMBOL(otx2_smq_flush); 747 748 int otx2_txsch_alloc(struct otx2_nic *pfvf) 749 { 750 struct nix_txsch_alloc_req *req; 751 struct nix_txsch_alloc_rsp *rsp; 752 int lvl, schq, rc; 753 754 /* Get memory to put this msg */ 755 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 756 if (!req) 757 return -ENOMEM; 758 759 /* Request one schq per level */ 760 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 761 req->schq[lvl] = 1; 762 rc = otx2_sync_mbox_msg(&pfvf->mbox); 763 if (rc) 764 return rc; 765 766 rsp = (struct nix_txsch_alloc_rsp *) 767 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 768 if (IS_ERR(rsp)) 769 return PTR_ERR(rsp); 770 771 /* Setup transmit scheduler list */ 772 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 773 for (schq = 0; schq < rsp->schq[lvl]; schq++) 774 pfvf->hw.txschq_list[lvl][schq] = 775 rsp->schq_list[lvl][schq]; 776 777 pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl; 778 pfvf->hw.txschq_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio; 779 780 return 0; 781 } 782 783 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq) 784 { 785 struct nix_txsch_free_req *free_req; 786 int err; 787 788 mutex_lock(&pfvf->mbox.lock); 789 790 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 791 if (!free_req) { 792 mutex_unlock(&pfvf->mbox.lock); 793 netdev_err(pfvf->netdev, 794 "Failed alloc txschq free req\n"); 795 return; 796 } 797 798 free_req->schq_lvl = lvl; 799 free_req->schq = schq; 800 801 err = otx2_sync_mbox_msg(&pfvf->mbox); 802 if (err) { 803 netdev_err(pfvf->netdev, 804 "Failed stop txschq %d at level %d\n", schq, lvl); 805 } 806 807 mutex_unlock(&pfvf->mbox.lock); 808 } 809 EXPORT_SYMBOL(otx2_txschq_free_one); 810 811 void otx2_txschq_stop(struct otx2_nic *pfvf) 812 { 813 int lvl, schq; 814 815 /* free non QOS TLx nodes */ 816 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 817 otx2_txschq_free_one(pfvf, lvl, 818 pfvf->hw.txschq_list[lvl][0]); 819 820 /* Clear the txschq list */ 821 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 822 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 823 pfvf->hw.txschq_list[lvl][schq] = 0; 824 } 825 826 } 827 828 void otx2_sqb_flush(struct otx2_nic *pfvf) 829 { 830 int qidx, sqe_tail, sqe_head; 831 struct otx2_snd_queue *sq; 832 u64 incr, *ptr, val; 833 int timeout = 1000; 834 835 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 836 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 837 sq = &pfvf->qset.sq[qidx]; 838 if (!sq->sqb_ptrs) 839 continue; 840 841 incr = (u64)qidx << 32; 842 while (timeout) { 843 val = otx2_atomic64_add(incr, ptr); 844 sqe_head = (val >> 20) & 0x3F; 845 sqe_tail = (val >> 28) & 0x3F; 846 if (sqe_head == sqe_tail) 847 break; 848 usleep_range(1, 3); 849 timeout--; 850 } 851 } 852 } 853 854 /* RED and drop levels of CQ on packet reception. 855 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 856 */ 857 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 858 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 859 860 /* RED and drop levels of AURA for packet reception. 861 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 862 * Eg: For RQ length 1K, for pass/drop level 204/230. 863 * RED accepts pkts if free pointers > 102 & <= 205. 864 * Drops pkts if free pointers < 102. 865 */ 866 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 867 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 868 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 869 870 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 871 { 872 struct otx2_qset *qset = &pfvf->qset; 873 struct nix_aq_enq_req *aq; 874 875 /* Get memory to put this msg */ 876 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 877 if (!aq) 878 return -ENOMEM; 879 880 aq->rq.cq = qidx; 881 aq->rq.ena = 1; 882 aq->rq.pb_caching = 1; 883 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 884 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 885 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 886 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 887 aq->rq.qint_idx = 0; 888 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 889 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 890 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 891 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 892 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 893 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 894 895 /* Fill AQ info */ 896 aq->qidx = qidx; 897 aq->ctype = NIX_AQ_CTYPE_RQ; 898 aq->op = NIX_AQ_INSTOP_INIT; 899 900 return otx2_sync_mbox_msg(&pfvf->mbox); 901 } 902 903 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 904 { 905 struct otx2_nic *pfvf = dev; 906 struct otx2_snd_queue *sq; 907 struct nix_aq_enq_req *aq; 908 909 sq = &pfvf->qset.sq[qidx]; 910 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 911 /* Get memory to put this msg */ 912 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 913 if (!aq) 914 return -ENOMEM; 915 916 aq->sq.cq = pfvf->hw.rx_queues + qidx; 917 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 918 aq->sq.cq_ena = 1; 919 aq->sq.ena = 1; 920 aq->sq.smq = otx2_get_smq_idx(pfvf, qidx); 921 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 922 aq->sq.default_chan = pfvf->hw.tx_chan_base; 923 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 924 aq->sq.sqb_aura = sqb_aura; 925 aq->sq.sq_int_ena = NIX_SQINT_BITS; 926 aq->sq.qint_idx = 0; 927 /* Due pipelining impact minimum 2000 unused SQ CQE's 928 * need to maintain to avoid CQ overflow. 929 */ 930 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 931 932 /* Fill AQ info */ 933 aq->qidx = qidx; 934 aq->ctype = NIX_AQ_CTYPE_SQ; 935 aq->op = NIX_AQ_INSTOP_INIT; 936 937 return otx2_sync_mbox_msg(&pfvf->mbox); 938 } 939 940 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 941 { 942 struct otx2_qset *qset = &pfvf->qset; 943 struct otx2_snd_queue *sq; 944 struct otx2_pool *pool; 945 int err; 946 947 pool = &pfvf->qset.pool[sqb_aura]; 948 sq = &qset->sq[qidx]; 949 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 950 sq->sqe_cnt = qset->sqe_cnt; 951 952 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 953 if (err) 954 return err; 955 956 if (qidx < pfvf->hw.tx_queues) { 957 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 958 TSO_HEADER_SIZE); 959 if (err) 960 return err; 961 } 962 963 sq->sqe_base = sq->sqe->base; 964 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 965 if (!sq->sg) 966 return -ENOMEM; 967 968 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) { 969 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 970 sizeof(*sq->timestamps)); 971 if (err) 972 return err; 973 } 974 975 sq->head = 0; 976 sq->cons_head = 0; 977 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 978 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 979 /* Set SQE threshold to 10% of total SQEs */ 980 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 981 sq->aura_id = sqb_aura; 982 sq->aura_fc_addr = pool->fc_addr->base; 983 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 984 985 sq->stats.bytes = 0; 986 sq->stats.pkts = 0; 987 988 return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); 989 990 } 991 992 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 993 { 994 struct otx2_qset *qset = &pfvf->qset; 995 int err, pool_id, non_xdp_queues; 996 struct nix_aq_enq_req *aq; 997 struct otx2_cq_queue *cq; 998 999 cq = &qset->cq[qidx]; 1000 cq->cq_idx = qidx; 1001 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues; 1002 if (qidx < pfvf->hw.rx_queues) { 1003 cq->cq_type = CQ_RX; 1004 cq->cint_idx = qidx; 1005 cq->cqe_cnt = qset->rqe_cnt; 1006 if (pfvf->xdp_prog) 1007 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0); 1008 } else if (qidx < non_xdp_queues) { 1009 cq->cq_type = CQ_TX; 1010 cq->cint_idx = qidx - pfvf->hw.rx_queues; 1011 cq->cqe_cnt = qset->sqe_cnt; 1012 } else { 1013 if (pfvf->hw.xdp_queues && 1014 qidx < non_xdp_queues + pfvf->hw.xdp_queues) { 1015 cq->cq_type = CQ_XDP; 1016 cq->cint_idx = qidx - non_xdp_queues; 1017 cq->cqe_cnt = qset->sqe_cnt; 1018 } else { 1019 cq->cq_type = CQ_QOS; 1020 cq->cint_idx = qidx - non_xdp_queues - 1021 pfvf->hw.xdp_queues; 1022 cq->cqe_cnt = qset->sqe_cnt; 1023 } 1024 } 1025 cq->cqe_size = pfvf->qset.xqe_size; 1026 1027 /* Allocate memory for CQEs */ 1028 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 1029 if (err) 1030 return err; 1031 1032 /* Save CQE CPU base for faster reference */ 1033 cq->cqe_base = cq->cqe->base; 1034 /* In case where all RQs auras point to single pool, 1035 * all CQs receive buffer pool also point to same pool. 1036 */ 1037 pool_id = ((cq->cq_type == CQ_RX) && 1038 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 1039 cq->rbpool = &qset->pool[pool_id]; 1040 cq->refill_task_sched = false; 1041 1042 /* Get memory to put this msg */ 1043 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 1044 if (!aq) 1045 return -ENOMEM; 1046 1047 aq->cq.ena = 1; 1048 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 1049 aq->cq.caching = 1; 1050 aq->cq.base = cq->cqe->iova; 1051 aq->cq.cint_idx = cq->cint_idx; 1052 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 1053 aq->cq.qint_idx = 0; 1054 aq->cq.avg_level = 255; 1055 1056 if (qidx < pfvf->hw.rx_queues) { 1057 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 1058 aq->cq.drop_ena = 1; 1059 1060 if (!is_otx2_lbkvf(pfvf->pdev)) { 1061 /* Enable receive CQ backpressure */ 1062 aq->cq.bp_ena = 1; 1063 #ifdef CONFIG_DCB 1064 aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]]; 1065 #else 1066 aq->cq.bpid = pfvf->bpid[0]; 1067 #endif 1068 1069 /* Set backpressure level is same as cq pass level */ 1070 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 1071 } 1072 } 1073 1074 /* Fill AQ info */ 1075 aq->qidx = qidx; 1076 aq->ctype = NIX_AQ_CTYPE_CQ; 1077 aq->op = NIX_AQ_INSTOP_INIT; 1078 1079 return otx2_sync_mbox_msg(&pfvf->mbox); 1080 } 1081 1082 static void otx2_pool_refill_task(struct work_struct *work) 1083 { 1084 struct otx2_cq_queue *cq; 1085 struct otx2_pool *rbpool; 1086 struct refill_work *wrk; 1087 int qidx, free_ptrs = 0; 1088 struct otx2_nic *pfvf; 1089 dma_addr_t bufptr; 1090 1091 wrk = container_of(work, struct refill_work, pool_refill_work.work); 1092 pfvf = wrk->pf; 1093 qidx = wrk - pfvf->refill_wrk; 1094 cq = &pfvf->qset.cq[qidx]; 1095 rbpool = cq->rbpool; 1096 free_ptrs = cq->pool_ptrs; 1097 1098 while (cq->pool_ptrs) { 1099 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) { 1100 /* Schedule a WQ if we fails to free atleast half of the 1101 * pointers else enable napi for this RQ. 1102 */ 1103 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 1104 struct delayed_work *dwork; 1105 1106 dwork = &wrk->pool_refill_work; 1107 schedule_delayed_work(dwork, 1108 msecs_to_jiffies(100)); 1109 } else { 1110 cq->refill_task_sched = false; 1111 } 1112 return; 1113 } 1114 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 1115 cq->pool_ptrs--; 1116 } 1117 cq->refill_task_sched = false; 1118 } 1119 1120 int otx2_config_nix_queues(struct otx2_nic *pfvf) 1121 { 1122 int qidx, err; 1123 1124 /* Initialize RX queues */ 1125 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 1126 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 1127 1128 err = otx2_rq_init(pfvf, qidx, lpb_aura); 1129 if (err) 1130 return err; 1131 } 1132 1133 /* Initialize TX queues */ 1134 for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) { 1135 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1136 1137 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1138 if (err) 1139 return err; 1140 } 1141 1142 /* Initialize completion queues */ 1143 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1144 err = otx2_cq_init(pfvf, qidx); 1145 if (err) 1146 return err; 1147 } 1148 1149 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, 1150 NIX_LF_CQ_OP_STATUS); 1151 1152 /* Initialize work queue for receive buffer refill */ 1153 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1154 sizeof(struct refill_work), GFP_KERNEL); 1155 if (!pfvf->refill_wrk) 1156 return -ENOMEM; 1157 1158 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1159 pfvf->refill_wrk[qidx].pf = pfvf; 1160 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1161 otx2_pool_refill_task); 1162 } 1163 return 0; 1164 } 1165 1166 int otx2_config_nix(struct otx2_nic *pfvf) 1167 { 1168 struct nix_lf_alloc_req *nixlf; 1169 struct nix_lf_alloc_rsp *rsp; 1170 int err; 1171 1172 pfvf->qset.xqe_size = pfvf->hw.xqe_size; 1173 1174 /* Get memory to put this msg */ 1175 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1176 if (!nixlf) 1177 return -ENOMEM; 1178 1179 /* Set RQ/SQ/CQ counts */ 1180 nixlf->rq_cnt = pfvf->hw.rx_queues; 1181 nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf); 1182 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1183 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1184 nixlf->rss_grps = MAX_RSS_GROUPS; 1185 nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64; 1186 /* We don't know absolute NPA LF idx attached. 1187 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1188 * NPA LF attached to this RVU PF/VF. 1189 */ 1190 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1191 /* Disable alignment pad, enable L2 length check, 1192 * enable L4 TCP/UDP checksum verification. 1193 */ 1194 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1195 1196 err = otx2_sync_mbox_msg(&pfvf->mbox); 1197 if (err) 1198 return err; 1199 1200 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1201 &nixlf->hdr); 1202 if (IS_ERR(rsp)) 1203 return PTR_ERR(rsp); 1204 1205 if (rsp->qints < 1) 1206 return -ENXIO; 1207 1208 return rsp->hdr.rc; 1209 } 1210 1211 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1212 { 1213 struct otx2_qset *qset = &pfvf->qset; 1214 struct otx2_hw *hw = &pfvf->hw; 1215 struct otx2_snd_queue *sq; 1216 int sqb, qidx; 1217 u64 iova, pa; 1218 1219 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 1220 sq = &qset->sq[qidx]; 1221 if (!sq->sqb_ptrs) 1222 continue; 1223 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1224 if (!sq->sqb_ptrs[sqb]) 1225 continue; 1226 iova = sq->sqb_ptrs[sqb]; 1227 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1228 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1229 DMA_FROM_DEVICE, 1230 DMA_ATTR_SKIP_CPU_SYNC); 1231 put_page(virt_to_page(phys_to_virt(pa))); 1232 } 1233 sq->sqb_count = 0; 1234 } 1235 } 1236 1237 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1238 u64 iova, int size) 1239 { 1240 struct page *page; 1241 u64 pa; 1242 1243 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1244 page = virt_to_head_page(phys_to_virt(pa)); 1245 1246 if (pool->page_pool) { 1247 page_pool_put_full_page(pool->page_pool, page, true); 1248 } else { 1249 dma_unmap_page_attrs(pfvf->dev, iova, size, 1250 DMA_FROM_DEVICE, 1251 DMA_ATTR_SKIP_CPU_SYNC); 1252 1253 put_page(page); 1254 } 1255 } 1256 1257 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1258 { 1259 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1260 struct otx2_pool *pool; 1261 u64 iova; 1262 1263 if (type == AURA_NIX_SQ) { 1264 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1265 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1266 size = pfvf->hw.sqb_size; 1267 } 1268 if (type == AURA_NIX_RQ) { 1269 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1270 pool_end = pfvf->hw.rqpool_cnt; 1271 size = pfvf->rbsize; 1272 } 1273 1274 /* Free SQB and RQB pointers from the aura pool */ 1275 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1276 iova = otx2_aura_allocptr(pfvf, pool_id); 1277 pool = &pfvf->qset.pool[pool_id]; 1278 while (iova) { 1279 if (type == AURA_NIX_RQ) 1280 iova -= OTX2_HEAD_ROOM; 1281 1282 otx2_free_bufs(pfvf, pool, iova, size); 1283 1284 iova = otx2_aura_allocptr(pfvf, pool_id); 1285 } 1286 } 1287 } 1288 1289 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1290 { 1291 struct otx2_pool *pool; 1292 int pool_id; 1293 1294 if (!pfvf->qset.pool) 1295 return; 1296 1297 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1298 pool = &pfvf->qset.pool[pool_id]; 1299 qmem_free(pfvf->dev, pool->stack); 1300 qmem_free(pfvf->dev, pool->fc_addr); 1301 page_pool_destroy(pool->page_pool); 1302 pool->page_pool = NULL; 1303 } 1304 devm_kfree(pfvf->dev, pfvf->qset.pool); 1305 pfvf->qset.pool = NULL; 1306 } 1307 1308 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1309 int pool_id, int numptrs) 1310 { 1311 struct npa_aq_enq_req *aq; 1312 struct otx2_pool *pool; 1313 int err; 1314 1315 pool = &pfvf->qset.pool[pool_id]; 1316 1317 /* Allocate memory for HW to update Aura count. 1318 * Alloc one cache line, so that it fits all FC_STYPE modes. 1319 */ 1320 if (!pool->fc_addr) { 1321 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1322 if (err) 1323 return err; 1324 } 1325 1326 /* Initialize this aura's context via AF */ 1327 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1328 if (!aq) { 1329 /* Shared mbox memory buffer is full, flush it and retry */ 1330 err = otx2_sync_mbox_msg(&pfvf->mbox); 1331 if (err) 1332 return err; 1333 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1334 if (!aq) 1335 return -ENOMEM; 1336 } 1337 1338 aq->aura_id = aura_id; 1339 /* Will be filled by AF with correct pool context address */ 1340 aq->aura.pool_addr = pool_id; 1341 aq->aura.pool_caching = 1; 1342 aq->aura.shift = ilog2(numptrs) - 8; 1343 aq->aura.count = numptrs; 1344 aq->aura.limit = numptrs; 1345 aq->aura.avg_level = 255; 1346 aq->aura.ena = 1; 1347 aq->aura.fc_ena = 1; 1348 aq->aura.fc_addr = pool->fc_addr->iova; 1349 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1350 1351 /* Enable backpressure for RQ aura */ 1352 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1353 aq->aura.bp_ena = 0; 1354 /* If NIX1 LF is attached then specify NIX1_RX. 1355 * 1356 * Below NPA_AURA_S[BP_ENA] is set according to the 1357 * NPA_BPINTF_E enumeration given as: 1358 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1359 * NIX0_RX is 0x0 + 0*0x1 = 0 1360 * NIX1_RX is 0x0 + 1*0x1 = 1 1361 * But in HRM it is given that 1362 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1363 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1364 * enumerated by NPA_BPINTF_E." 1365 */ 1366 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1367 aq->aura.bp_ena = 1; 1368 #ifdef CONFIG_DCB 1369 aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]]; 1370 #else 1371 aq->aura.nix0_bpid = pfvf->bpid[0]; 1372 #endif 1373 1374 /* Set backpressure level for RQ's Aura */ 1375 aq->aura.bp = RQ_BP_LVL_AURA; 1376 } 1377 1378 /* Fill AQ info */ 1379 aq->ctype = NPA_AQ_CTYPE_AURA; 1380 aq->op = NPA_AQ_INSTOP_INIT; 1381 1382 return 0; 1383 } 1384 1385 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1386 int stack_pages, int numptrs, int buf_size, int type) 1387 { 1388 struct page_pool_params pp_params = { 0 }; 1389 struct npa_aq_enq_req *aq; 1390 struct otx2_pool *pool; 1391 int err; 1392 1393 pool = &pfvf->qset.pool[pool_id]; 1394 /* Alloc memory for stack which is used to store buffer pointers */ 1395 err = qmem_alloc(pfvf->dev, &pool->stack, 1396 stack_pages, pfvf->hw.stack_pg_bytes); 1397 if (err) 1398 return err; 1399 1400 pool->rbsize = buf_size; 1401 1402 /* Initialize this pool's context via AF */ 1403 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1404 if (!aq) { 1405 /* Shared mbox memory buffer is full, flush it and retry */ 1406 err = otx2_sync_mbox_msg(&pfvf->mbox); 1407 if (err) { 1408 qmem_free(pfvf->dev, pool->stack); 1409 return err; 1410 } 1411 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1412 if (!aq) { 1413 qmem_free(pfvf->dev, pool->stack); 1414 return -ENOMEM; 1415 } 1416 } 1417 1418 aq->aura_id = pool_id; 1419 aq->pool.stack_base = pool->stack->iova; 1420 aq->pool.stack_caching = 1; 1421 aq->pool.ena = 1; 1422 aq->pool.buf_size = buf_size / 128; 1423 aq->pool.stack_max_pages = stack_pages; 1424 aq->pool.shift = ilog2(numptrs) - 8; 1425 aq->pool.ptr_start = 0; 1426 aq->pool.ptr_end = ~0ULL; 1427 1428 /* Fill AQ info */ 1429 aq->ctype = NPA_AQ_CTYPE_POOL; 1430 aq->op = NPA_AQ_INSTOP_INIT; 1431 1432 if (type != AURA_NIX_RQ) { 1433 pool->page_pool = NULL; 1434 return 0; 1435 } 1436 1437 pp_params.flags = PP_FLAG_PAGE_FRAG | PP_FLAG_DMA_MAP; 1438 pp_params.pool_size = min(OTX2_PAGE_POOL_SZ, numptrs); 1439 pp_params.nid = NUMA_NO_NODE; 1440 pp_params.dev = pfvf->dev; 1441 pp_params.dma_dir = DMA_FROM_DEVICE; 1442 pool->page_pool = page_pool_create(&pp_params); 1443 if (IS_ERR(pool->page_pool)) { 1444 netdev_err(pfvf->netdev, "Creation of page pool failed\n"); 1445 return PTR_ERR(pool->page_pool); 1446 } 1447 1448 return 0; 1449 } 1450 1451 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1452 { 1453 int qidx, pool_id, stack_pages, num_sqbs; 1454 struct otx2_qset *qset = &pfvf->qset; 1455 struct otx2_hw *hw = &pfvf->hw; 1456 struct otx2_snd_queue *sq; 1457 struct otx2_pool *pool; 1458 dma_addr_t bufptr; 1459 int err, ptr; 1460 1461 /* Calculate number of SQBs needed. 1462 * 1463 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1464 * Last SQE is used for pointing to next SQB. 1465 */ 1466 num_sqbs = (hw->sqb_size / 128) - 1; 1467 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1468 1469 /* Get no of stack pages needed */ 1470 stack_pages = 1471 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1472 1473 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1474 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1475 /* Initialize aura context */ 1476 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1477 if (err) 1478 goto fail; 1479 1480 /* Initialize pool context */ 1481 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1482 num_sqbs, hw->sqb_size, AURA_NIX_SQ); 1483 if (err) 1484 goto fail; 1485 } 1486 1487 /* Flush accumulated messages */ 1488 err = otx2_sync_mbox_msg(&pfvf->mbox); 1489 if (err) 1490 goto fail; 1491 1492 /* Allocate pointers and free them to aura/pool */ 1493 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1494 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1495 pool = &pfvf->qset.pool[pool_id]; 1496 1497 sq = &qset->sq[qidx]; 1498 sq->sqb_count = 0; 1499 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1500 if (!sq->sqb_ptrs) { 1501 err = -ENOMEM; 1502 goto err_mem; 1503 } 1504 1505 for (ptr = 0; ptr < num_sqbs; ptr++) { 1506 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1507 if (err) 1508 goto err_mem; 1509 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1510 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1511 } 1512 } 1513 1514 err_mem: 1515 return err ? -ENOMEM : 0; 1516 1517 fail: 1518 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1519 otx2_aura_pool_free(pfvf); 1520 return err; 1521 } 1522 1523 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1524 { 1525 struct otx2_hw *hw = &pfvf->hw; 1526 int stack_pages, pool_id, rq; 1527 struct otx2_pool *pool; 1528 int err, ptr, num_ptrs; 1529 dma_addr_t bufptr; 1530 1531 num_ptrs = pfvf->qset.rqe_cnt; 1532 1533 stack_pages = 1534 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1535 1536 for (rq = 0; rq < hw->rx_queues; rq++) { 1537 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1538 /* Initialize aura context */ 1539 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1540 if (err) 1541 goto fail; 1542 } 1543 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1544 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1545 num_ptrs, pfvf->rbsize, AURA_NIX_RQ); 1546 if (err) 1547 goto fail; 1548 } 1549 1550 /* Flush accumulated messages */ 1551 err = otx2_sync_mbox_msg(&pfvf->mbox); 1552 if (err) 1553 goto fail; 1554 1555 /* Allocate pointers and free them to aura/pool */ 1556 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1557 pool = &pfvf->qset.pool[pool_id]; 1558 for (ptr = 0; ptr < num_ptrs; ptr++) { 1559 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1560 if (err) 1561 return -ENOMEM; 1562 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1563 bufptr + OTX2_HEAD_ROOM); 1564 } 1565 } 1566 return 0; 1567 fail: 1568 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1569 otx2_aura_pool_free(pfvf); 1570 return err; 1571 } 1572 1573 int otx2_config_npa(struct otx2_nic *pfvf) 1574 { 1575 struct otx2_qset *qset = &pfvf->qset; 1576 struct npa_lf_alloc_req *npalf; 1577 struct otx2_hw *hw = &pfvf->hw; 1578 int aura_cnt; 1579 1580 /* Pool - Stack of free buffer pointers 1581 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1582 */ 1583 1584 if (!hw->pool_cnt) 1585 return -EINVAL; 1586 1587 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1588 sizeof(struct otx2_pool), GFP_KERNEL); 1589 if (!qset->pool) 1590 return -ENOMEM; 1591 1592 /* Get memory to put this msg */ 1593 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1594 if (!npalf) 1595 return -ENOMEM; 1596 1597 /* Set aura and pool counts */ 1598 npalf->nr_pools = hw->pool_cnt; 1599 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1600 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1601 1602 return otx2_sync_mbox_msg(&pfvf->mbox); 1603 } 1604 1605 int otx2_detach_resources(struct mbox *mbox) 1606 { 1607 struct rsrc_detach *detach; 1608 1609 mutex_lock(&mbox->lock); 1610 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1611 if (!detach) { 1612 mutex_unlock(&mbox->lock); 1613 return -ENOMEM; 1614 } 1615 1616 /* detach all */ 1617 detach->partial = false; 1618 1619 /* Send detach request to AF */ 1620 otx2_mbox_msg_send(&mbox->mbox, 0); 1621 mutex_unlock(&mbox->lock); 1622 return 0; 1623 } 1624 EXPORT_SYMBOL(otx2_detach_resources); 1625 1626 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1627 { 1628 struct rsrc_attach *attach; 1629 struct msg_req *msix; 1630 int err; 1631 1632 mutex_lock(&pfvf->mbox.lock); 1633 /* Get memory to put this msg */ 1634 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1635 if (!attach) { 1636 mutex_unlock(&pfvf->mbox.lock); 1637 return -ENOMEM; 1638 } 1639 1640 attach->npalf = true; 1641 attach->nixlf = true; 1642 1643 /* Send attach request to AF */ 1644 err = otx2_sync_mbox_msg(&pfvf->mbox); 1645 if (err) { 1646 mutex_unlock(&pfvf->mbox.lock); 1647 return err; 1648 } 1649 1650 pfvf->nix_blkaddr = BLKADDR_NIX0; 1651 1652 /* If the platform has two NIX blocks then LF may be 1653 * allocated from NIX1. 1654 */ 1655 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1656 pfvf->nix_blkaddr = BLKADDR_NIX1; 1657 1658 /* Get NPA and NIX MSIX vector offsets */ 1659 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1660 if (!msix) { 1661 mutex_unlock(&pfvf->mbox.lock); 1662 return -ENOMEM; 1663 } 1664 1665 err = otx2_sync_mbox_msg(&pfvf->mbox); 1666 if (err) { 1667 mutex_unlock(&pfvf->mbox.lock); 1668 return err; 1669 } 1670 mutex_unlock(&pfvf->mbox.lock); 1671 1672 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1673 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1674 dev_err(pfvf->dev, 1675 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1676 return -EINVAL; 1677 } 1678 1679 return 0; 1680 } 1681 EXPORT_SYMBOL(otx2_attach_npa_nix); 1682 1683 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1684 { 1685 struct hwctx_disable_req *req; 1686 1687 mutex_lock(&mbox->lock); 1688 /* Request AQ to disable this context */ 1689 if (npa) 1690 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1691 else 1692 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1693 1694 if (!req) { 1695 mutex_unlock(&mbox->lock); 1696 return; 1697 } 1698 1699 req->ctype = type; 1700 1701 if (otx2_sync_mbox_msg(mbox)) 1702 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1703 __func__); 1704 1705 mutex_unlock(&mbox->lock); 1706 } 1707 1708 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1709 { 1710 struct nix_bp_cfg_req *req; 1711 1712 if (enable) 1713 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1714 else 1715 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1716 1717 if (!req) 1718 return -ENOMEM; 1719 1720 req->chan_base = 0; 1721 #ifdef CONFIG_DCB 1722 req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1; 1723 req->bpid_per_chan = pfvf->pfc_en ? 1 : 0; 1724 #else 1725 req->chan_cnt = 1; 1726 req->bpid_per_chan = 0; 1727 #endif 1728 1729 return otx2_sync_mbox_msg(&pfvf->mbox); 1730 } 1731 EXPORT_SYMBOL(otx2_nix_config_bp); 1732 1733 /* Mbox message handlers */ 1734 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1735 struct cgx_stats_rsp *rsp) 1736 { 1737 int id; 1738 1739 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1740 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1741 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1742 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1743 } 1744 1745 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1746 struct cgx_fec_stats_rsp *rsp) 1747 { 1748 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1749 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1750 } 1751 1752 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1753 struct npa_lf_alloc_rsp *rsp) 1754 { 1755 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1756 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1757 } 1758 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1759 1760 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1761 struct nix_lf_alloc_rsp *rsp) 1762 { 1763 pfvf->hw.sqb_size = rsp->sqb_size; 1764 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1765 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1766 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1767 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1768 pfvf->hw.cgx_links = rsp->cgx_links; 1769 pfvf->hw.lbk_links = rsp->lbk_links; 1770 pfvf->hw.tx_link = rsp->tx_link; 1771 } 1772 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1773 1774 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1775 struct msix_offset_rsp *rsp) 1776 { 1777 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1778 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1779 } 1780 EXPORT_SYMBOL(mbox_handler_msix_offset); 1781 1782 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1783 struct nix_bp_cfg_rsp *rsp) 1784 { 1785 int chan, chan_id; 1786 1787 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1788 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1789 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1790 } 1791 } 1792 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1793 1794 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1795 { 1796 struct otx2_qset *qset = &pfvf->qset; 1797 struct otx2_hw *hw = &pfvf->hw; 1798 int irq, qidx; 1799 1800 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1801 qidx < n; 1802 qidx++, irq++) { 1803 int vector = pci_irq_vector(pfvf->pdev, irq); 1804 1805 irq_set_affinity_hint(vector, NULL); 1806 free_cpumask_var(hw->affinity_mask[irq]); 1807 free_irq(vector, &qset->napi[qidx]); 1808 } 1809 } 1810 1811 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1812 { 1813 struct otx2_hw *hw = &pfvf->hw; 1814 int vec, cpu, irq, cint; 1815 1816 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1817 cpu = cpumask_first(cpu_online_mask); 1818 1819 /* CQ interrupts */ 1820 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1821 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1822 return; 1823 1824 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1825 1826 irq = pci_irq_vector(pfvf->pdev, vec); 1827 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1828 1829 cpu = cpumask_next(cpu, cpu_online_mask); 1830 if (unlikely(cpu >= nr_cpu_ids)) 1831 cpu = 0; 1832 } 1833 } 1834 1835 static u32 get_dwrr_mtu(struct otx2_nic *pfvf, struct nix_hw_info *hw) 1836 { 1837 if (is_otx2_lbkvf(pfvf->pdev)) { 1838 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_LBK; 1839 return hw->lbk_dwrr_mtu; 1840 } 1841 1842 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_RPM; 1843 return hw->rpm_dwrr_mtu; 1844 } 1845 1846 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1847 { 1848 struct nix_hw_info *rsp; 1849 struct msg_req *req; 1850 u16 max_mtu; 1851 int rc; 1852 1853 mutex_lock(&pfvf->mbox.lock); 1854 1855 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1856 if (!req) { 1857 rc = -ENOMEM; 1858 goto out; 1859 } 1860 1861 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1862 if (!rc) { 1863 rsp = (struct nix_hw_info *) 1864 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1865 1866 /* HW counts VLAN insertion bytes (8 for double tag) 1867 * irrespective of whether SQE is requesting to insert VLAN 1868 * in the packet or not. Hence these 8 bytes have to be 1869 * discounted from max packet size otherwise HW will throw 1870 * SMQ errors 1871 */ 1872 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1873 1874 /* Also save DWRR MTU, needed for DWRR weight calculation */ 1875 pfvf->hw.dwrr_mtu = get_dwrr_mtu(pfvf, rsp); 1876 if (!pfvf->hw.dwrr_mtu) 1877 pfvf->hw.dwrr_mtu = 1; 1878 } 1879 1880 out: 1881 mutex_unlock(&pfvf->mbox.lock); 1882 if (rc) { 1883 dev_warn(pfvf->dev, 1884 "Failed to get MTU from hardware setting default value(1500)\n"); 1885 max_mtu = 1500; 1886 } 1887 return max_mtu; 1888 } 1889 EXPORT_SYMBOL(otx2_get_max_mtu); 1890 1891 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features) 1892 { 1893 netdev_features_t changed = features ^ netdev->features; 1894 struct otx2_nic *pfvf = netdev_priv(netdev); 1895 bool ntuple = !!(features & NETIF_F_NTUPLE); 1896 bool tc = !!(features & NETIF_F_HW_TC); 1897 1898 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1899 otx2_destroy_ntuple_flows(pfvf); 1900 1901 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1902 if (!pfvf->flow_cfg->max_flows) { 1903 netdev_err(netdev, 1904 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1905 return -EINVAL; 1906 } 1907 } 1908 1909 if ((changed & NETIF_F_HW_TC) && !tc && 1910 otx2_tc_flower_rule_cnt(pfvf)) { 1911 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1912 return -EBUSY; 1913 } 1914 1915 if ((changed & NETIF_F_NTUPLE) && ntuple && 1916 otx2_tc_flower_rule_cnt(pfvf) && !(changed & NETIF_F_HW_TC)) { 1917 netdev_err(netdev, 1918 "Can't enable NTUPLE when TC flower offload is active, disable TC rules and retry\n"); 1919 return -EINVAL; 1920 } 1921 1922 return 0; 1923 } 1924 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features); 1925 1926 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1927 int __weak \ 1928 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1929 struct _req_type *req, \ 1930 struct _rsp_type *rsp) \ 1931 { \ 1932 /* Nothing to do here */ \ 1933 return 0; \ 1934 } \ 1935 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1936 MBOX_UP_CGX_MESSAGES 1937 MBOX_UP_MCS_MESSAGES 1938 #undef M 1939