1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <net/tso.h> 14 15 #include "otx2_reg.h" 16 #include "otx2_common.h" 17 #include "otx2_struct.h" 18 19 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 20 struct otx2_nic *pfvf, int qidx) 21 { 22 u64 incr = (u64)qidx << 32; 23 u64 *ptr; 24 25 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 26 stats->bytes = otx2_atomic64_add(incr, ptr); 27 28 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 29 stats->pkts = otx2_atomic64_add(incr, ptr); 30 } 31 32 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 33 struct otx2_nic *pfvf, int qidx) 34 { 35 u64 incr = (u64)qidx << 32; 36 u64 *ptr; 37 38 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 39 stats->bytes = otx2_atomic64_add(incr, ptr); 40 41 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 42 stats->pkts = otx2_atomic64_add(incr, ptr); 43 } 44 45 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 46 { 47 struct msg_req *req; 48 49 if (!netif_running(pfvf->netdev)) 50 return; 51 52 mutex_lock(&pfvf->mbox.lock); 53 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 54 if (!req) { 55 mutex_unlock(&pfvf->mbox.lock); 56 return; 57 } 58 59 otx2_sync_mbox_msg(&pfvf->mbox); 60 mutex_unlock(&pfvf->mbox.lock); 61 } 62 63 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 64 { 65 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 66 67 if (!pfvf->qset.rq) 68 return 0; 69 70 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 71 return 1; 72 } 73 74 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 75 { 76 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 77 78 if (!pfvf->qset.sq) 79 return 0; 80 81 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 82 return 1; 83 } 84 85 void otx2_get_dev_stats(struct otx2_nic *pfvf) 86 { 87 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 88 89 #define OTX2_GET_RX_STATS(reg) \ 90 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 91 #define OTX2_GET_TX_STATS(reg) \ 92 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 93 94 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 95 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 96 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 97 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 98 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 99 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 100 dev_stats->rx_mcast_frames + 101 dev_stats->rx_ucast_frames; 102 103 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 104 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 105 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 106 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 107 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 108 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 109 dev_stats->tx_mcast_frames + 110 dev_stats->tx_ucast_frames; 111 } 112 113 void otx2_get_stats64(struct net_device *netdev, 114 struct rtnl_link_stats64 *stats) 115 { 116 struct otx2_nic *pfvf = netdev_priv(netdev); 117 struct otx2_dev_stats *dev_stats; 118 119 otx2_get_dev_stats(pfvf); 120 121 dev_stats = &pfvf->hw.dev_stats; 122 stats->rx_bytes = dev_stats->rx_bytes; 123 stats->rx_packets = dev_stats->rx_frames; 124 stats->rx_dropped = dev_stats->rx_drops; 125 stats->multicast = dev_stats->rx_mcast_frames; 126 127 stats->tx_bytes = dev_stats->tx_bytes; 128 stats->tx_packets = dev_stats->tx_frames; 129 stats->tx_dropped = dev_stats->tx_drops; 130 } 131 EXPORT_SYMBOL(otx2_get_stats64); 132 133 /* Sync MAC address with RVU AF */ 134 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 135 { 136 struct nix_set_mac_addr *req; 137 int err; 138 139 mutex_lock(&pfvf->mbox.lock); 140 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 141 if (!req) { 142 mutex_unlock(&pfvf->mbox.lock); 143 return -ENOMEM; 144 } 145 146 ether_addr_copy(req->mac_addr, mac); 147 148 err = otx2_sync_mbox_msg(&pfvf->mbox); 149 mutex_unlock(&pfvf->mbox.lock); 150 return err; 151 } 152 153 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 154 struct net_device *netdev) 155 { 156 struct nix_get_mac_addr_rsp *rsp; 157 struct mbox_msghdr *msghdr; 158 struct msg_req *req; 159 int err; 160 161 mutex_lock(&pfvf->mbox.lock); 162 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 163 if (!req) { 164 mutex_unlock(&pfvf->mbox.lock); 165 return -ENOMEM; 166 } 167 168 err = otx2_sync_mbox_msg(&pfvf->mbox); 169 if (err) { 170 mutex_unlock(&pfvf->mbox.lock); 171 return err; 172 } 173 174 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 175 if (IS_ERR(msghdr)) { 176 mutex_unlock(&pfvf->mbox.lock); 177 return PTR_ERR(msghdr); 178 } 179 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 180 ether_addr_copy(netdev->dev_addr, rsp->mac_addr); 181 mutex_unlock(&pfvf->mbox.lock); 182 183 return 0; 184 } 185 186 int otx2_set_mac_address(struct net_device *netdev, void *p) 187 { 188 struct otx2_nic *pfvf = netdev_priv(netdev); 189 struct sockaddr *addr = p; 190 191 if (!is_valid_ether_addr(addr->sa_data)) 192 return -EADDRNOTAVAIL; 193 194 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 195 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 196 /* update dmac field in vlan offload rule */ 197 if (pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 198 otx2_install_rxvlan_offload_flow(pfvf); 199 } else { 200 return -EPERM; 201 } 202 203 return 0; 204 } 205 EXPORT_SYMBOL(otx2_set_mac_address); 206 207 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 208 { 209 struct nix_frs_cfg *req; 210 int err; 211 212 mutex_lock(&pfvf->mbox.lock); 213 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 214 if (!req) { 215 mutex_unlock(&pfvf->mbox.lock); 216 return -ENOMEM; 217 } 218 219 pfvf->max_frs = mtu + OTX2_ETH_HLEN; 220 req->maxlen = pfvf->max_frs; 221 222 err = otx2_sync_mbox_msg(&pfvf->mbox); 223 mutex_unlock(&pfvf->mbox.lock); 224 return err; 225 } 226 227 int otx2_config_pause_frm(struct otx2_nic *pfvf) 228 { 229 struct cgx_pause_frm_cfg *req; 230 int err; 231 232 if (is_otx2_lbkvf(pfvf->pdev)) 233 return 0; 234 235 mutex_lock(&pfvf->mbox.lock); 236 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 237 if (!req) { 238 err = -ENOMEM; 239 goto unlock; 240 } 241 242 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 243 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 244 req->set = 1; 245 246 err = otx2_sync_mbox_msg(&pfvf->mbox); 247 unlock: 248 mutex_unlock(&pfvf->mbox.lock); 249 return err; 250 } 251 252 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 253 { 254 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 255 struct nix_rss_flowkey_cfg *req; 256 int err; 257 258 mutex_lock(&pfvf->mbox.lock); 259 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 260 if (!req) { 261 mutex_unlock(&pfvf->mbox.lock); 262 return -ENOMEM; 263 } 264 req->mcam_index = -1; /* Default or reserved index */ 265 req->flowkey_cfg = rss->flowkey_cfg; 266 req->group = DEFAULT_RSS_CONTEXT_GROUP; 267 268 err = otx2_sync_mbox_msg(&pfvf->mbox); 269 mutex_unlock(&pfvf->mbox.lock); 270 return err; 271 } 272 273 int otx2_set_rss_table(struct otx2_nic *pfvf) 274 { 275 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 276 struct mbox *mbox = &pfvf->mbox; 277 struct nix_aq_enq_req *aq; 278 int idx, err; 279 280 mutex_lock(&mbox->lock); 281 /* Get memory to put this msg */ 282 for (idx = 0; idx < rss->rss_size; idx++) { 283 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 284 if (!aq) { 285 /* The shared memory buffer can be full. 286 * Flush it and retry 287 */ 288 err = otx2_sync_mbox_msg(mbox); 289 if (err) { 290 mutex_unlock(&mbox->lock); 291 return err; 292 } 293 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 294 if (!aq) { 295 mutex_unlock(&mbox->lock); 296 return -ENOMEM; 297 } 298 } 299 300 aq->rss.rq = rss->ind_tbl[idx]; 301 302 /* Fill AQ info */ 303 aq->qidx = idx; 304 aq->ctype = NIX_AQ_CTYPE_RSS; 305 aq->op = NIX_AQ_INSTOP_INIT; 306 } 307 err = otx2_sync_mbox_msg(mbox); 308 mutex_unlock(&mbox->lock); 309 return err; 310 } 311 312 void otx2_set_rss_key(struct otx2_nic *pfvf) 313 { 314 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 315 u64 *key = (u64 *)&rss->key[4]; 316 int idx; 317 318 /* 352bit or 44byte key needs to be configured as below 319 * NIX_LF_RX_SECRETX0 = key<351:288> 320 * NIX_LF_RX_SECRETX1 = key<287:224> 321 * NIX_LF_RX_SECRETX2 = key<223:160> 322 * NIX_LF_RX_SECRETX3 = key<159:96> 323 * NIX_LF_RX_SECRETX4 = key<95:32> 324 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 325 */ 326 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 327 (u64)(*((u32 *)&rss->key)) << 32); 328 idx = sizeof(rss->key) / sizeof(u64); 329 while (idx > 0) { 330 idx--; 331 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 332 } 333 } 334 335 int otx2_rss_init(struct otx2_nic *pfvf) 336 { 337 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 338 int idx, ret = 0; 339 340 rss->rss_size = sizeof(rss->ind_tbl); 341 342 /* Init RSS key if it is not setup already */ 343 if (!rss->enable) 344 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 345 otx2_set_rss_key(pfvf); 346 347 if (!netif_is_rxfh_configured(pfvf->netdev)) { 348 /* Default indirection table */ 349 for (idx = 0; idx < rss->rss_size; idx++) 350 rss->ind_tbl[idx] = 351 ethtool_rxfh_indir_default(idx, 352 pfvf->hw.rx_queues); 353 } 354 ret = otx2_set_rss_table(pfvf); 355 if (ret) 356 return ret; 357 358 /* Flowkey or hash config to be used for generating flow tag */ 359 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 360 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 361 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 362 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 363 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 364 365 ret = otx2_set_flowkey_cfg(pfvf); 366 if (ret) 367 return ret; 368 369 rss->enable = true; 370 return 0; 371 } 372 373 /* Setup UDP segmentation algorithm in HW */ 374 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 375 { 376 struct nix_lso_format *field; 377 378 field = (struct nix_lso_format *)&lso->fields[0]; 379 lso->field_mask = GENMASK(18, 0); 380 381 /* IP's Length field */ 382 field->layer = NIX_TXLAYER_OL3; 383 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 384 field->offset = v4 ? 2 : 4; 385 field->sizem1 = 1; /* i.e 2 bytes */ 386 field->alg = NIX_LSOALG_ADD_PAYLEN; 387 field++; 388 389 /* No ID field in IPv6 header */ 390 if (v4) { 391 /* Increment IPID */ 392 field->layer = NIX_TXLAYER_OL3; 393 field->offset = 4; 394 field->sizem1 = 1; /* i.e 2 bytes */ 395 field->alg = NIX_LSOALG_ADD_SEGNUM; 396 field++; 397 } 398 399 /* Update length in UDP header */ 400 field->layer = NIX_TXLAYER_OL4; 401 field->offset = 4; 402 field->sizem1 = 1; 403 field->alg = NIX_LSOALG_ADD_PAYLEN; 404 } 405 406 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 407 void otx2_setup_segmentation(struct otx2_nic *pfvf) 408 { 409 struct nix_lso_format_cfg_rsp *rsp; 410 struct nix_lso_format_cfg *lso; 411 struct otx2_hw *hw = &pfvf->hw; 412 int err; 413 414 mutex_lock(&pfvf->mbox.lock); 415 416 /* UDPv4 segmentation */ 417 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 418 if (!lso) 419 goto fail; 420 421 /* Setup UDP/IP header fields that HW should update per segment */ 422 otx2_setup_udp_segmentation(lso, true); 423 424 err = otx2_sync_mbox_msg(&pfvf->mbox); 425 if (err) 426 goto fail; 427 428 rsp = (struct nix_lso_format_cfg_rsp *) 429 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 430 if (IS_ERR(rsp)) 431 goto fail; 432 433 hw->lso_udpv4_idx = rsp->lso_format_idx; 434 435 /* UDPv6 segmentation */ 436 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 437 if (!lso) 438 goto fail; 439 440 /* Setup UDP/IP header fields that HW should update per segment */ 441 otx2_setup_udp_segmentation(lso, false); 442 443 err = otx2_sync_mbox_msg(&pfvf->mbox); 444 if (err) 445 goto fail; 446 447 rsp = (struct nix_lso_format_cfg_rsp *) 448 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 449 if (IS_ERR(rsp)) 450 goto fail; 451 452 hw->lso_udpv6_idx = rsp->lso_format_idx; 453 mutex_unlock(&pfvf->mbox.lock); 454 return; 455 fail: 456 mutex_unlock(&pfvf->mbox.lock); 457 netdev_info(pfvf->netdev, 458 "Failed to get LSO index for UDP GSO offload, disabling\n"); 459 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 460 } 461 462 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 463 { 464 /* Configure CQE interrupt coalescing parameters 465 * 466 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 467 * set 1 less than cq_ecount_wait. And cq_time_wait is in 468 * usecs, convert that to 100ns count. 469 */ 470 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 471 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 472 ((u64)pfvf->hw.cq_qcount_wait << 32) | 473 (pfvf->hw.cq_ecount_wait - 1)); 474 } 475 476 dma_addr_t __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool) 477 { 478 dma_addr_t iova; 479 u8 *buf; 480 481 buf = napi_alloc_frag(pool->rbsize + OTX2_ALIGN); 482 if (unlikely(!buf)) 483 return -ENOMEM; 484 485 buf = PTR_ALIGN(buf, OTX2_ALIGN); 486 iova = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 487 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 488 if (unlikely(dma_mapping_error(pfvf->dev, iova))) { 489 page_frag_free(buf); 490 return -ENOMEM; 491 } 492 493 return iova; 494 } 495 496 static dma_addr_t otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool) 497 { 498 dma_addr_t addr; 499 500 local_bh_disable(); 501 addr = __otx2_alloc_rbuf(pfvf, pool); 502 local_bh_enable(); 503 return addr; 504 } 505 506 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 507 { 508 struct otx2_nic *pfvf = netdev_priv(netdev); 509 510 schedule_work(&pfvf->reset_task); 511 } 512 EXPORT_SYMBOL(otx2_tx_timeout); 513 514 void otx2_get_mac_from_af(struct net_device *netdev) 515 { 516 struct otx2_nic *pfvf = netdev_priv(netdev); 517 int err; 518 519 err = otx2_hw_get_mac_addr(pfvf, netdev); 520 if (err) 521 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 522 523 /* If AF doesn't provide a valid MAC, generate a random one */ 524 if (!is_valid_ether_addr(netdev->dev_addr)) 525 eth_hw_addr_random(netdev); 526 } 527 EXPORT_SYMBOL(otx2_get_mac_from_af); 528 529 static int otx2_get_link(struct otx2_nic *pfvf) 530 { 531 int link = 0; 532 u16 map; 533 534 /* cgx lmac link */ 535 if (pfvf->hw.tx_chan_base >= CGX_CHAN_BASE) { 536 map = pfvf->hw.tx_chan_base & 0x7FF; 537 link = 4 * ((map >> 8) & 0xF) + ((map >> 4) & 0xF); 538 } 539 /* LBK channel */ 540 if (pfvf->hw.tx_chan_base < SDP_CHAN_BASE) { 541 map = pfvf->hw.tx_chan_base & 0x7FF; 542 link = pfvf->hw.cgx_links | ((map >> 8) & 0xF); 543 } 544 545 return link; 546 } 547 548 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl) 549 { 550 struct otx2_hw *hw = &pfvf->hw; 551 struct nix_txschq_config *req; 552 u64 schq, parent; 553 554 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 555 if (!req) 556 return -ENOMEM; 557 558 req->lvl = lvl; 559 req->num_regs = 1; 560 561 schq = hw->txschq_list[lvl][0]; 562 /* Set topology e.t.c configuration */ 563 if (lvl == NIX_TXSCH_LVL_SMQ) { 564 req->reg[0] = NIX_AF_SMQX_CFG(schq); 565 req->regval[0] = ((OTX2_MAX_MTU + OTX2_ETH_HLEN) << 8) | 566 OTX2_MIN_MTU; 567 568 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 569 (0x2ULL << 36); 570 req->num_regs++; 571 /* MDQ config */ 572 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0]; 573 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 574 req->regval[1] = parent << 16; 575 req->num_regs++; 576 /* Set DWRR quantum */ 577 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 578 req->regval[2] = DFLT_RR_QTM; 579 } else if (lvl == NIX_TXSCH_LVL_TL4) { 580 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0]; 581 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 582 req->regval[0] = parent << 16; 583 req->num_regs++; 584 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 585 req->regval[1] = DFLT_RR_QTM; 586 } else if (lvl == NIX_TXSCH_LVL_TL3) { 587 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0]; 588 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 589 req->regval[0] = parent << 16; 590 req->num_regs++; 591 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 592 req->regval[1] = DFLT_RR_QTM; 593 } else if (lvl == NIX_TXSCH_LVL_TL2) { 594 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0]; 595 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 596 req->regval[0] = parent << 16; 597 598 req->num_regs++; 599 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 600 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | DFLT_RR_QTM; 601 602 req->num_regs++; 603 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, 604 otx2_get_link(pfvf)); 605 /* Enable this queue and backpressure */ 606 req->regval[2] = BIT_ULL(13) | BIT_ULL(12); 607 608 } else if (lvl == NIX_TXSCH_LVL_TL1) { 609 /* Default config for TL1. 610 * For VF this is always ignored. 611 */ 612 613 /* Set DWRR quantum */ 614 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 615 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 616 617 req->num_regs++; 618 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 619 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 620 621 req->num_regs++; 622 req->reg[2] = NIX_AF_TL1X_CIR(schq); 623 req->regval[2] = 0; 624 } 625 626 return otx2_sync_mbox_msg(&pfvf->mbox); 627 } 628 629 int otx2_txsch_alloc(struct otx2_nic *pfvf) 630 { 631 struct nix_txsch_alloc_req *req; 632 int lvl; 633 634 /* Get memory to put this msg */ 635 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 636 if (!req) 637 return -ENOMEM; 638 639 /* Request one schq per level */ 640 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 641 req->schq[lvl] = 1; 642 643 return otx2_sync_mbox_msg(&pfvf->mbox); 644 } 645 646 int otx2_txschq_stop(struct otx2_nic *pfvf) 647 { 648 struct nix_txsch_free_req *free_req; 649 int lvl, schq, err; 650 651 mutex_lock(&pfvf->mbox.lock); 652 /* Free the transmit schedulers */ 653 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 654 if (!free_req) { 655 mutex_unlock(&pfvf->mbox.lock); 656 return -ENOMEM; 657 } 658 659 free_req->flags = TXSCHQ_FREE_ALL; 660 err = otx2_sync_mbox_msg(&pfvf->mbox); 661 mutex_unlock(&pfvf->mbox.lock); 662 663 /* Clear the txschq list */ 664 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 665 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 666 pfvf->hw.txschq_list[lvl][schq] = 0; 667 } 668 return err; 669 } 670 671 void otx2_sqb_flush(struct otx2_nic *pfvf) 672 { 673 int qidx, sqe_tail, sqe_head; 674 u64 incr, *ptr, val; 675 int timeout = 1000; 676 677 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 678 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 679 incr = (u64)qidx << 32; 680 while (timeout) { 681 val = otx2_atomic64_add(incr, ptr); 682 sqe_head = (val >> 20) & 0x3F; 683 sqe_tail = (val >> 28) & 0x3F; 684 if (sqe_head == sqe_tail) 685 break; 686 usleep_range(1, 3); 687 timeout--; 688 } 689 } 690 } 691 692 /* RED and drop levels of CQ on packet reception. 693 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 694 */ 695 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 696 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 697 698 /* RED and drop levels of AURA for packet reception. 699 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 700 * Eg: For RQ length 1K, for pass/drop level 204/230. 701 * RED accepts pkts if free pointers > 102 & <= 205. 702 * Drops pkts if free pointers < 102. 703 */ 704 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 705 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 706 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 707 708 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 709 #define SEND_CQ_SKID 2000 710 711 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 712 { 713 struct otx2_qset *qset = &pfvf->qset; 714 struct nix_aq_enq_req *aq; 715 716 /* Get memory to put this msg */ 717 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 718 if (!aq) 719 return -ENOMEM; 720 721 aq->rq.cq = qidx; 722 aq->rq.ena = 1; 723 aq->rq.pb_caching = 1; 724 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 725 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 726 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 727 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 728 aq->rq.qint_idx = 0; 729 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 730 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 731 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 732 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 733 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 734 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 735 736 /* Fill AQ info */ 737 aq->qidx = qidx; 738 aq->ctype = NIX_AQ_CTYPE_RQ; 739 aq->op = NIX_AQ_INSTOP_INIT; 740 741 return otx2_sync_mbox_msg(&pfvf->mbox); 742 } 743 744 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 745 { 746 struct otx2_qset *qset = &pfvf->qset; 747 struct otx2_snd_queue *sq; 748 struct nix_aq_enq_req *aq; 749 struct otx2_pool *pool; 750 int err; 751 752 pool = &pfvf->qset.pool[sqb_aura]; 753 sq = &qset->sq[qidx]; 754 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 755 sq->sqe_cnt = qset->sqe_cnt; 756 757 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 758 if (err) 759 return err; 760 761 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 762 TSO_HEADER_SIZE); 763 if (err) 764 return err; 765 766 sq->sqe_base = sq->sqe->base; 767 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 768 if (!sq->sg) 769 return -ENOMEM; 770 771 if (pfvf->ptp) { 772 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 773 sizeof(*sq->timestamps)); 774 if (err) 775 return err; 776 } 777 778 sq->head = 0; 779 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 780 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 781 /* Set SQE threshold to 10% of total SQEs */ 782 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 783 sq->aura_id = sqb_aura; 784 sq->aura_fc_addr = pool->fc_addr->base; 785 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 786 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 787 788 sq->stats.bytes = 0; 789 sq->stats.pkts = 0; 790 791 /* Get memory to put this msg */ 792 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 793 if (!aq) 794 return -ENOMEM; 795 796 aq->sq.cq = pfvf->hw.rx_queues + qidx; 797 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 798 aq->sq.cq_ena = 1; 799 aq->sq.ena = 1; 800 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 801 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 802 aq->sq.smq_rr_quantum = DFLT_RR_QTM; 803 aq->sq.default_chan = pfvf->hw.tx_chan_base; 804 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 805 aq->sq.sqb_aura = sqb_aura; 806 aq->sq.sq_int_ena = NIX_SQINT_BITS; 807 aq->sq.qint_idx = 0; 808 /* Due pipelining impact minimum 2000 unused SQ CQE's 809 * need to maintain to avoid CQ overflow. 810 */ 811 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (sq->sqe_cnt)); 812 813 /* Fill AQ info */ 814 aq->qidx = qidx; 815 aq->ctype = NIX_AQ_CTYPE_SQ; 816 aq->op = NIX_AQ_INSTOP_INIT; 817 818 return otx2_sync_mbox_msg(&pfvf->mbox); 819 } 820 821 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 822 { 823 struct otx2_qset *qset = &pfvf->qset; 824 struct nix_aq_enq_req *aq; 825 struct otx2_cq_queue *cq; 826 int err, pool_id; 827 828 cq = &qset->cq[qidx]; 829 cq->cq_idx = qidx; 830 if (qidx < pfvf->hw.rx_queues) { 831 cq->cq_type = CQ_RX; 832 cq->cint_idx = qidx; 833 cq->cqe_cnt = qset->rqe_cnt; 834 } else { 835 cq->cq_type = CQ_TX; 836 cq->cint_idx = qidx - pfvf->hw.rx_queues; 837 cq->cqe_cnt = qset->sqe_cnt; 838 } 839 cq->cqe_size = pfvf->qset.xqe_size; 840 841 /* Allocate memory for CQEs */ 842 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 843 if (err) 844 return err; 845 846 /* Save CQE CPU base for faster reference */ 847 cq->cqe_base = cq->cqe->base; 848 /* In case where all RQs auras point to single pool, 849 * all CQs receive buffer pool also point to same pool. 850 */ 851 pool_id = ((cq->cq_type == CQ_RX) && 852 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 853 cq->rbpool = &qset->pool[pool_id]; 854 cq->refill_task_sched = false; 855 856 /* Get memory to put this msg */ 857 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 858 if (!aq) 859 return -ENOMEM; 860 861 aq->cq.ena = 1; 862 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 863 aq->cq.caching = 1; 864 aq->cq.base = cq->cqe->iova; 865 aq->cq.cint_idx = cq->cint_idx; 866 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 867 aq->cq.qint_idx = 0; 868 aq->cq.avg_level = 255; 869 870 if (qidx < pfvf->hw.rx_queues) { 871 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 872 aq->cq.drop_ena = 1; 873 874 /* Enable receive CQ backpressure */ 875 aq->cq.bp_ena = 1; 876 aq->cq.bpid = pfvf->bpid[0]; 877 878 /* Set backpressure level is same as cq pass level */ 879 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 880 } 881 882 /* Fill AQ info */ 883 aq->qidx = qidx; 884 aq->ctype = NIX_AQ_CTYPE_CQ; 885 aq->op = NIX_AQ_INSTOP_INIT; 886 887 return otx2_sync_mbox_msg(&pfvf->mbox); 888 } 889 890 static void otx2_pool_refill_task(struct work_struct *work) 891 { 892 struct otx2_cq_queue *cq; 893 struct otx2_pool *rbpool; 894 struct refill_work *wrk; 895 int qidx, free_ptrs = 0; 896 struct otx2_nic *pfvf; 897 s64 bufptr; 898 899 wrk = container_of(work, struct refill_work, pool_refill_work.work); 900 pfvf = wrk->pf; 901 qidx = wrk - pfvf->refill_wrk; 902 cq = &pfvf->qset.cq[qidx]; 903 rbpool = cq->rbpool; 904 free_ptrs = cq->pool_ptrs; 905 906 while (cq->pool_ptrs) { 907 bufptr = otx2_alloc_rbuf(pfvf, rbpool); 908 if (bufptr <= 0) { 909 /* Schedule a WQ if we fails to free atleast half of the 910 * pointers else enable napi for this RQ. 911 */ 912 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 913 struct delayed_work *dwork; 914 915 dwork = &wrk->pool_refill_work; 916 schedule_delayed_work(dwork, 917 msecs_to_jiffies(100)); 918 } else { 919 cq->refill_task_sched = false; 920 } 921 return; 922 } 923 otx2_aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 924 cq->pool_ptrs--; 925 } 926 cq->refill_task_sched = false; 927 } 928 929 int otx2_config_nix_queues(struct otx2_nic *pfvf) 930 { 931 int qidx, err; 932 933 /* Initialize RX queues */ 934 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 935 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 936 937 err = otx2_rq_init(pfvf, qidx, lpb_aura); 938 if (err) 939 return err; 940 } 941 942 /* Initialize TX queues */ 943 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 944 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 945 946 err = otx2_sq_init(pfvf, qidx, sqb_aura); 947 if (err) 948 return err; 949 } 950 951 /* Initialize completion queues */ 952 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 953 err = otx2_cq_init(pfvf, qidx); 954 if (err) 955 return err; 956 } 957 958 /* Initialize work queue for receive buffer refill */ 959 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 960 sizeof(struct refill_work), GFP_KERNEL); 961 if (!pfvf->refill_wrk) 962 return -ENOMEM; 963 964 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 965 pfvf->refill_wrk[qidx].pf = pfvf; 966 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 967 otx2_pool_refill_task); 968 } 969 return 0; 970 } 971 972 int otx2_config_nix(struct otx2_nic *pfvf) 973 { 974 struct nix_lf_alloc_req *nixlf; 975 struct nix_lf_alloc_rsp *rsp; 976 int err; 977 978 pfvf->qset.xqe_size = NIX_XQESZ_W16 ? 128 : 512; 979 980 /* Get memory to put this msg */ 981 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 982 if (!nixlf) 983 return -ENOMEM; 984 985 /* Set RQ/SQ/CQ counts */ 986 nixlf->rq_cnt = pfvf->hw.rx_queues; 987 nixlf->sq_cnt = pfvf->hw.tx_queues; 988 nixlf->cq_cnt = pfvf->qset.cq_cnt; 989 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 990 nixlf->rss_grps = 1; /* Single RSS indir table supported, for now */ 991 nixlf->xqe_sz = NIX_XQESZ_W16; 992 /* We don't know absolute NPA LF idx attached. 993 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 994 * NPA LF attached to this RVU PF/VF. 995 */ 996 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 997 /* Disable alignment pad, enable L2 length check, 998 * enable L4 TCP/UDP checksum verification. 999 */ 1000 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1001 1002 err = otx2_sync_mbox_msg(&pfvf->mbox); 1003 if (err) 1004 return err; 1005 1006 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1007 &nixlf->hdr); 1008 if (IS_ERR(rsp)) 1009 return PTR_ERR(rsp); 1010 1011 if (rsp->qints < 1) 1012 return -ENXIO; 1013 1014 return rsp->hdr.rc; 1015 } 1016 1017 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1018 { 1019 struct otx2_qset *qset = &pfvf->qset; 1020 struct otx2_hw *hw = &pfvf->hw; 1021 struct otx2_snd_queue *sq; 1022 int sqb, qidx; 1023 u64 iova, pa; 1024 1025 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1026 sq = &qset->sq[qidx]; 1027 if (!sq->sqb_ptrs) 1028 continue; 1029 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1030 if (!sq->sqb_ptrs[sqb]) 1031 continue; 1032 iova = sq->sqb_ptrs[sqb]; 1033 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1034 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1035 DMA_FROM_DEVICE, 1036 DMA_ATTR_SKIP_CPU_SYNC); 1037 put_page(virt_to_page(phys_to_virt(pa))); 1038 } 1039 sq->sqb_count = 0; 1040 } 1041 } 1042 1043 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1044 { 1045 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1046 u64 iova, pa; 1047 1048 if (type == AURA_NIX_SQ) { 1049 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1050 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1051 size = pfvf->hw.sqb_size; 1052 } 1053 if (type == AURA_NIX_RQ) { 1054 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1055 pool_end = pfvf->hw.rqpool_cnt; 1056 size = pfvf->rbsize; 1057 } 1058 1059 /* Free SQB and RQB pointers from the aura pool */ 1060 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1061 iova = otx2_aura_allocptr(pfvf, pool_id); 1062 while (iova) { 1063 if (type == AURA_NIX_RQ) 1064 iova -= OTX2_HEAD_ROOM; 1065 1066 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1067 dma_unmap_page_attrs(pfvf->dev, iova, size, 1068 DMA_FROM_DEVICE, 1069 DMA_ATTR_SKIP_CPU_SYNC); 1070 put_page(virt_to_page(phys_to_virt(pa))); 1071 iova = otx2_aura_allocptr(pfvf, pool_id); 1072 } 1073 } 1074 } 1075 1076 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1077 { 1078 struct otx2_pool *pool; 1079 int pool_id; 1080 1081 if (!pfvf->qset.pool) 1082 return; 1083 1084 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1085 pool = &pfvf->qset.pool[pool_id]; 1086 qmem_free(pfvf->dev, pool->stack); 1087 qmem_free(pfvf->dev, pool->fc_addr); 1088 } 1089 devm_kfree(pfvf->dev, pfvf->qset.pool); 1090 pfvf->qset.pool = NULL; 1091 } 1092 1093 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1094 int pool_id, int numptrs) 1095 { 1096 struct npa_aq_enq_req *aq; 1097 struct otx2_pool *pool; 1098 int err; 1099 1100 pool = &pfvf->qset.pool[pool_id]; 1101 1102 /* Allocate memory for HW to update Aura count. 1103 * Alloc one cache line, so that it fits all FC_STYPE modes. 1104 */ 1105 if (!pool->fc_addr) { 1106 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1107 if (err) 1108 return err; 1109 } 1110 1111 /* Initialize this aura's context via AF */ 1112 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1113 if (!aq) { 1114 /* Shared mbox memory buffer is full, flush it and retry */ 1115 err = otx2_sync_mbox_msg(&pfvf->mbox); 1116 if (err) 1117 return err; 1118 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1119 if (!aq) 1120 return -ENOMEM; 1121 } 1122 1123 aq->aura_id = aura_id; 1124 /* Will be filled by AF with correct pool context address */ 1125 aq->aura.pool_addr = pool_id; 1126 aq->aura.pool_caching = 1; 1127 aq->aura.shift = ilog2(numptrs) - 8; 1128 aq->aura.count = numptrs; 1129 aq->aura.limit = numptrs; 1130 aq->aura.avg_level = 255; 1131 aq->aura.ena = 1; 1132 aq->aura.fc_ena = 1; 1133 aq->aura.fc_addr = pool->fc_addr->iova; 1134 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1135 1136 /* Enable backpressure for RQ aura */ 1137 if (aura_id < pfvf->hw.rqpool_cnt) { 1138 aq->aura.bp_ena = 0; 1139 aq->aura.nix0_bpid = pfvf->bpid[0]; 1140 /* Set backpressure level for RQ's Aura */ 1141 aq->aura.bp = RQ_BP_LVL_AURA; 1142 } 1143 1144 /* Fill AQ info */ 1145 aq->ctype = NPA_AQ_CTYPE_AURA; 1146 aq->op = NPA_AQ_INSTOP_INIT; 1147 1148 return 0; 1149 } 1150 1151 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1152 int stack_pages, int numptrs, int buf_size) 1153 { 1154 struct npa_aq_enq_req *aq; 1155 struct otx2_pool *pool; 1156 int err; 1157 1158 pool = &pfvf->qset.pool[pool_id]; 1159 /* Alloc memory for stack which is used to store buffer pointers */ 1160 err = qmem_alloc(pfvf->dev, &pool->stack, 1161 stack_pages, pfvf->hw.stack_pg_bytes); 1162 if (err) 1163 return err; 1164 1165 pool->rbsize = buf_size; 1166 1167 /* Initialize this pool's context via AF */ 1168 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1169 if (!aq) { 1170 /* Shared mbox memory buffer is full, flush it and retry */ 1171 err = otx2_sync_mbox_msg(&pfvf->mbox); 1172 if (err) { 1173 qmem_free(pfvf->dev, pool->stack); 1174 return err; 1175 } 1176 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1177 if (!aq) { 1178 qmem_free(pfvf->dev, pool->stack); 1179 return -ENOMEM; 1180 } 1181 } 1182 1183 aq->aura_id = pool_id; 1184 aq->pool.stack_base = pool->stack->iova; 1185 aq->pool.stack_caching = 1; 1186 aq->pool.ena = 1; 1187 aq->pool.buf_size = buf_size / 128; 1188 aq->pool.stack_max_pages = stack_pages; 1189 aq->pool.shift = ilog2(numptrs) - 8; 1190 aq->pool.ptr_start = 0; 1191 aq->pool.ptr_end = ~0ULL; 1192 1193 /* Fill AQ info */ 1194 aq->ctype = NPA_AQ_CTYPE_POOL; 1195 aq->op = NPA_AQ_INSTOP_INIT; 1196 1197 return 0; 1198 } 1199 1200 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1201 { 1202 int qidx, pool_id, stack_pages, num_sqbs; 1203 struct otx2_qset *qset = &pfvf->qset; 1204 struct otx2_hw *hw = &pfvf->hw; 1205 struct otx2_snd_queue *sq; 1206 struct otx2_pool *pool; 1207 int err, ptr; 1208 s64 bufptr; 1209 1210 /* Calculate number of SQBs needed. 1211 * 1212 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1213 * Last SQE is used for pointing to next SQB. 1214 */ 1215 num_sqbs = (hw->sqb_size / 128) - 1; 1216 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1217 1218 /* Get no of stack pages needed */ 1219 stack_pages = 1220 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1221 1222 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1223 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1224 /* Initialize aura context */ 1225 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1226 if (err) 1227 goto fail; 1228 1229 /* Initialize pool context */ 1230 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1231 num_sqbs, hw->sqb_size); 1232 if (err) 1233 goto fail; 1234 } 1235 1236 /* Flush accumulated messages */ 1237 err = otx2_sync_mbox_msg(&pfvf->mbox); 1238 if (err) 1239 goto fail; 1240 1241 /* Allocate pointers and free them to aura/pool */ 1242 for (qidx = 0; qidx < hw->tx_queues; qidx++) { 1243 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1244 pool = &pfvf->qset.pool[pool_id]; 1245 1246 sq = &qset->sq[qidx]; 1247 sq->sqb_count = 0; 1248 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1249 if (!sq->sqb_ptrs) 1250 return -ENOMEM; 1251 1252 for (ptr = 0; ptr < num_sqbs; ptr++) { 1253 bufptr = otx2_alloc_rbuf(pfvf, pool); 1254 if (bufptr <= 0) 1255 return bufptr; 1256 otx2_aura_freeptr(pfvf, pool_id, bufptr); 1257 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1258 } 1259 } 1260 1261 return 0; 1262 fail: 1263 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1264 otx2_aura_pool_free(pfvf); 1265 return err; 1266 } 1267 1268 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1269 { 1270 struct otx2_hw *hw = &pfvf->hw; 1271 int stack_pages, pool_id, rq; 1272 struct otx2_pool *pool; 1273 int err, ptr, num_ptrs; 1274 s64 bufptr; 1275 1276 num_ptrs = pfvf->qset.rqe_cnt; 1277 1278 stack_pages = 1279 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1280 1281 for (rq = 0; rq < hw->rx_queues; rq++) { 1282 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1283 /* Initialize aura context */ 1284 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1285 if (err) 1286 goto fail; 1287 } 1288 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1289 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1290 num_ptrs, pfvf->rbsize); 1291 if (err) 1292 goto fail; 1293 } 1294 1295 /* Flush accumulated messages */ 1296 err = otx2_sync_mbox_msg(&pfvf->mbox); 1297 if (err) 1298 goto fail; 1299 1300 /* Allocate pointers and free them to aura/pool */ 1301 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1302 pool = &pfvf->qset.pool[pool_id]; 1303 for (ptr = 0; ptr < num_ptrs; ptr++) { 1304 bufptr = otx2_alloc_rbuf(pfvf, pool); 1305 if (bufptr <= 0) 1306 return bufptr; 1307 otx2_aura_freeptr(pfvf, pool_id, 1308 bufptr + OTX2_HEAD_ROOM); 1309 } 1310 } 1311 1312 return 0; 1313 fail: 1314 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1315 otx2_aura_pool_free(pfvf); 1316 return err; 1317 } 1318 1319 int otx2_config_npa(struct otx2_nic *pfvf) 1320 { 1321 struct otx2_qset *qset = &pfvf->qset; 1322 struct npa_lf_alloc_req *npalf; 1323 struct otx2_hw *hw = &pfvf->hw; 1324 int aura_cnt; 1325 1326 /* Pool - Stack of free buffer pointers 1327 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1328 */ 1329 1330 if (!hw->pool_cnt) 1331 return -EINVAL; 1332 1333 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1334 sizeof(struct otx2_pool), GFP_KERNEL); 1335 if (!qset->pool) 1336 return -ENOMEM; 1337 1338 /* Get memory to put this msg */ 1339 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1340 if (!npalf) 1341 return -ENOMEM; 1342 1343 /* Set aura and pool counts */ 1344 npalf->nr_pools = hw->pool_cnt; 1345 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1346 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1347 1348 return otx2_sync_mbox_msg(&pfvf->mbox); 1349 } 1350 1351 int otx2_detach_resources(struct mbox *mbox) 1352 { 1353 struct rsrc_detach *detach; 1354 1355 mutex_lock(&mbox->lock); 1356 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1357 if (!detach) { 1358 mutex_unlock(&mbox->lock); 1359 return -ENOMEM; 1360 } 1361 1362 /* detach all */ 1363 detach->partial = false; 1364 1365 /* Send detach request to AF */ 1366 otx2_mbox_msg_send(&mbox->mbox, 0); 1367 mutex_unlock(&mbox->lock); 1368 return 0; 1369 } 1370 EXPORT_SYMBOL(otx2_detach_resources); 1371 1372 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1373 { 1374 struct rsrc_attach *attach; 1375 struct msg_req *msix; 1376 int err; 1377 1378 mutex_lock(&pfvf->mbox.lock); 1379 /* Get memory to put this msg */ 1380 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1381 if (!attach) { 1382 mutex_unlock(&pfvf->mbox.lock); 1383 return -ENOMEM; 1384 } 1385 1386 attach->npalf = true; 1387 attach->nixlf = true; 1388 1389 /* Send attach request to AF */ 1390 err = otx2_sync_mbox_msg(&pfvf->mbox); 1391 if (err) { 1392 mutex_unlock(&pfvf->mbox.lock); 1393 return err; 1394 } 1395 1396 pfvf->nix_blkaddr = BLKADDR_NIX0; 1397 1398 /* If the platform has two NIX blocks then LF may be 1399 * allocated from NIX1. 1400 */ 1401 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1402 pfvf->nix_blkaddr = BLKADDR_NIX1; 1403 1404 /* Get NPA and NIX MSIX vector offsets */ 1405 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1406 if (!msix) { 1407 mutex_unlock(&pfvf->mbox.lock); 1408 return -ENOMEM; 1409 } 1410 1411 err = otx2_sync_mbox_msg(&pfvf->mbox); 1412 if (err) { 1413 mutex_unlock(&pfvf->mbox.lock); 1414 return err; 1415 } 1416 mutex_unlock(&pfvf->mbox.lock); 1417 1418 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1419 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1420 dev_err(pfvf->dev, 1421 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1422 return -EINVAL; 1423 } 1424 1425 return 0; 1426 } 1427 EXPORT_SYMBOL(otx2_attach_npa_nix); 1428 1429 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1430 { 1431 struct hwctx_disable_req *req; 1432 1433 mutex_lock(&mbox->lock); 1434 /* Request AQ to disable this context */ 1435 if (npa) 1436 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1437 else 1438 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1439 1440 if (!req) { 1441 mutex_unlock(&mbox->lock); 1442 return; 1443 } 1444 1445 req->ctype = type; 1446 1447 if (otx2_sync_mbox_msg(mbox)) 1448 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1449 __func__); 1450 1451 mutex_unlock(&mbox->lock); 1452 } 1453 1454 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1455 { 1456 struct nix_bp_cfg_req *req; 1457 1458 if (enable) 1459 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1460 else 1461 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1462 1463 if (!req) 1464 return -ENOMEM; 1465 1466 req->chan_base = 0; 1467 req->chan_cnt = 1; 1468 req->bpid_per_chan = 0; 1469 1470 return otx2_sync_mbox_msg(&pfvf->mbox); 1471 } 1472 1473 /* Mbox message handlers */ 1474 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1475 struct cgx_stats_rsp *rsp) 1476 { 1477 int id; 1478 1479 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1480 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1481 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1482 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1483 } 1484 1485 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1486 struct nix_txsch_alloc_rsp *rsp) 1487 { 1488 int lvl, schq; 1489 1490 /* Setup transmit scheduler list */ 1491 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 1492 for (schq = 0; schq < rsp->schq[lvl]; schq++) 1493 pf->hw.txschq_list[lvl][schq] = 1494 rsp->schq_list[lvl][schq]; 1495 } 1496 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc); 1497 1498 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1499 struct npa_lf_alloc_rsp *rsp) 1500 { 1501 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1502 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1503 } 1504 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1505 1506 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1507 struct nix_lf_alloc_rsp *rsp) 1508 { 1509 pfvf->hw.sqb_size = rsp->sqb_size; 1510 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1511 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1512 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1513 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1514 pfvf->hw.cgx_links = rsp->cgx_links; 1515 pfvf->hw.lbk_links = rsp->lbk_links; 1516 } 1517 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1518 1519 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1520 struct msix_offset_rsp *rsp) 1521 { 1522 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1523 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1524 } 1525 EXPORT_SYMBOL(mbox_handler_msix_offset); 1526 1527 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1528 struct nix_bp_cfg_rsp *rsp) 1529 { 1530 int chan, chan_id; 1531 1532 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1533 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1534 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1535 } 1536 } 1537 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1538 1539 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1540 { 1541 struct otx2_qset *qset = &pfvf->qset; 1542 struct otx2_hw *hw = &pfvf->hw; 1543 int irq, qidx; 1544 1545 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1546 qidx < n; 1547 qidx++, irq++) { 1548 int vector = pci_irq_vector(pfvf->pdev, irq); 1549 1550 irq_set_affinity_hint(vector, NULL); 1551 free_cpumask_var(hw->affinity_mask[irq]); 1552 free_irq(vector, &qset->napi[qidx]); 1553 } 1554 } 1555 1556 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1557 { 1558 struct otx2_hw *hw = &pfvf->hw; 1559 int vec, cpu, irq, cint; 1560 1561 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1562 cpu = cpumask_first(cpu_online_mask); 1563 1564 /* CQ interrupts */ 1565 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1566 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1567 return; 1568 1569 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1570 1571 irq = pci_irq_vector(pfvf->pdev, vec); 1572 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1573 1574 cpu = cpumask_next(cpu, cpu_online_mask); 1575 if (unlikely(cpu >= nr_cpu_ids)) 1576 cpu = 0; 1577 } 1578 } 1579 1580 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1581 int __weak \ 1582 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1583 struct _req_type *req, \ 1584 struct _rsp_type *rsp) \ 1585 { \ 1586 /* Nothing to do here */ \ 1587 return 0; \ 1588 } \ 1589 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1590 MBOX_UP_CGX_MESSAGES 1591 #undef M 1592