1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 #include <net/tso.h> 11 #include <linux/bitfield.h> 12 13 #include "otx2_reg.h" 14 #include "otx2_common.h" 15 #include "otx2_struct.h" 16 #include "cn10k.h" 17 18 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 19 struct otx2_nic *pfvf, int qidx) 20 { 21 u64 incr = (u64)qidx << 32; 22 u64 *ptr; 23 24 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 25 stats->bytes = otx2_atomic64_add(incr, ptr); 26 27 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 28 stats->pkts = otx2_atomic64_add(incr, ptr); 29 } 30 31 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 32 struct otx2_nic *pfvf, int qidx) 33 { 34 u64 incr = (u64)qidx << 32; 35 u64 *ptr; 36 37 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 38 stats->bytes = otx2_atomic64_add(incr, ptr); 39 40 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 41 stats->pkts = otx2_atomic64_add(incr, ptr); 42 } 43 44 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 45 { 46 struct msg_req *req; 47 48 if (!netif_running(pfvf->netdev)) 49 return; 50 51 mutex_lock(&pfvf->mbox.lock); 52 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 53 if (!req) { 54 mutex_unlock(&pfvf->mbox.lock); 55 return; 56 } 57 58 otx2_sync_mbox_msg(&pfvf->mbox); 59 mutex_unlock(&pfvf->mbox.lock); 60 } 61 62 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 63 { 64 struct msg_req *req; 65 66 if (!netif_running(pfvf->netdev)) 67 return; 68 mutex_lock(&pfvf->mbox.lock); 69 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 70 if (req) 71 otx2_sync_mbox_msg(&pfvf->mbox); 72 mutex_unlock(&pfvf->mbox.lock); 73 } 74 75 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 76 { 77 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 78 79 if (!pfvf->qset.rq) 80 return 0; 81 82 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 83 return 1; 84 } 85 86 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 87 { 88 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 89 90 if (!pfvf->qset.sq) 91 return 0; 92 93 if (qidx >= pfvf->hw.non_qos_queues) { 94 if (!test_bit(qidx - pfvf->hw.non_qos_queues, pfvf->qos.qos_sq_bmap)) 95 return 0; 96 } 97 98 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 99 return 1; 100 } 101 102 void otx2_get_dev_stats(struct otx2_nic *pfvf) 103 { 104 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 105 106 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 107 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 108 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 109 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 110 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 111 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 112 dev_stats->rx_mcast_frames + 113 dev_stats->rx_ucast_frames; 114 115 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 116 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 117 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 118 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 119 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 120 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 121 dev_stats->tx_mcast_frames + 122 dev_stats->tx_ucast_frames; 123 } 124 125 void otx2_get_stats64(struct net_device *netdev, 126 struct rtnl_link_stats64 *stats) 127 { 128 struct otx2_nic *pfvf = netdev_priv(netdev); 129 struct otx2_dev_stats *dev_stats; 130 131 otx2_get_dev_stats(pfvf); 132 133 dev_stats = &pfvf->hw.dev_stats; 134 stats->rx_bytes = dev_stats->rx_bytes; 135 stats->rx_packets = dev_stats->rx_frames; 136 stats->rx_dropped = dev_stats->rx_drops; 137 stats->multicast = dev_stats->rx_mcast_frames; 138 139 stats->tx_bytes = dev_stats->tx_bytes; 140 stats->tx_packets = dev_stats->tx_frames; 141 stats->tx_dropped = dev_stats->tx_drops; 142 } 143 EXPORT_SYMBOL(otx2_get_stats64); 144 145 /* Sync MAC address with RVU AF */ 146 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 147 { 148 struct nix_set_mac_addr *req; 149 int err; 150 151 mutex_lock(&pfvf->mbox.lock); 152 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 153 if (!req) { 154 mutex_unlock(&pfvf->mbox.lock); 155 return -ENOMEM; 156 } 157 158 ether_addr_copy(req->mac_addr, mac); 159 160 err = otx2_sync_mbox_msg(&pfvf->mbox); 161 mutex_unlock(&pfvf->mbox.lock); 162 return err; 163 } 164 165 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 166 struct net_device *netdev) 167 { 168 struct nix_get_mac_addr_rsp *rsp; 169 struct mbox_msghdr *msghdr; 170 struct msg_req *req; 171 int err; 172 173 mutex_lock(&pfvf->mbox.lock); 174 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 175 if (!req) { 176 mutex_unlock(&pfvf->mbox.lock); 177 return -ENOMEM; 178 } 179 180 err = otx2_sync_mbox_msg(&pfvf->mbox); 181 if (err) { 182 mutex_unlock(&pfvf->mbox.lock); 183 return err; 184 } 185 186 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 187 if (IS_ERR(msghdr)) { 188 mutex_unlock(&pfvf->mbox.lock); 189 return PTR_ERR(msghdr); 190 } 191 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 192 eth_hw_addr_set(netdev, rsp->mac_addr); 193 mutex_unlock(&pfvf->mbox.lock); 194 195 return 0; 196 } 197 198 int otx2_set_mac_address(struct net_device *netdev, void *p) 199 { 200 struct otx2_nic *pfvf = netdev_priv(netdev); 201 struct sockaddr *addr = p; 202 203 if (!is_valid_ether_addr(addr->sa_data)) 204 return -EADDRNOTAVAIL; 205 206 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 207 eth_hw_addr_set(netdev, addr->sa_data); 208 /* update dmac field in vlan offload rule */ 209 if (netif_running(netdev) && 210 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 211 otx2_install_rxvlan_offload_flow(pfvf); 212 /* update dmac address in ntuple and DMAC filter list */ 213 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 214 otx2_dmacflt_update_pfmac_flow(pfvf); 215 } else { 216 return -EPERM; 217 } 218 219 return 0; 220 } 221 EXPORT_SYMBOL(otx2_set_mac_address); 222 223 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 224 { 225 struct nix_frs_cfg *req; 226 u16 maxlen; 227 int err; 228 229 maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 230 231 mutex_lock(&pfvf->mbox.lock); 232 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 233 if (!req) { 234 mutex_unlock(&pfvf->mbox.lock); 235 return -ENOMEM; 236 } 237 238 req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 239 240 /* Use max receive length supported by hardware for loopback devices */ 241 if (is_otx2_lbkvf(pfvf->pdev)) 242 req->maxlen = maxlen; 243 244 err = otx2_sync_mbox_msg(&pfvf->mbox); 245 mutex_unlock(&pfvf->mbox.lock); 246 return err; 247 } 248 249 int otx2_config_pause_frm(struct otx2_nic *pfvf) 250 { 251 struct cgx_pause_frm_cfg *req; 252 int err; 253 254 if (is_otx2_lbkvf(pfvf->pdev)) 255 return 0; 256 257 mutex_lock(&pfvf->mbox.lock); 258 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 259 if (!req) { 260 err = -ENOMEM; 261 goto unlock; 262 } 263 264 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 265 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 266 req->set = 1; 267 268 err = otx2_sync_mbox_msg(&pfvf->mbox); 269 unlock: 270 mutex_unlock(&pfvf->mbox.lock); 271 return err; 272 } 273 EXPORT_SYMBOL(otx2_config_pause_frm); 274 275 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 276 { 277 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 278 struct nix_rss_flowkey_cfg_rsp *rsp; 279 struct nix_rss_flowkey_cfg *req; 280 int err; 281 282 mutex_lock(&pfvf->mbox.lock); 283 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 284 if (!req) { 285 mutex_unlock(&pfvf->mbox.lock); 286 return -ENOMEM; 287 } 288 req->mcam_index = -1; /* Default or reserved index */ 289 req->flowkey_cfg = rss->flowkey_cfg; 290 req->group = DEFAULT_RSS_CONTEXT_GROUP; 291 292 err = otx2_sync_mbox_msg(&pfvf->mbox); 293 if (err) 294 goto fail; 295 296 rsp = (struct nix_rss_flowkey_cfg_rsp *) 297 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 298 if (IS_ERR(rsp)) { 299 err = PTR_ERR(rsp); 300 goto fail; 301 } 302 303 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 304 fail: 305 mutex_unlock(&pfvf->mbox.lock); 306 return err; 307 } 308 309 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 310 { 311 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 312 const int index = rss->rss_size * ctx_id; 313 struct mbox *mbox = &pfvf->mbox; 314 struct otx2_rss_ctx *rss_ctx; 315 struct nix_aq_enq_req *aq; 316 int idx, err; 317 318 mutex_lock(&mbox->lock); 319 rss_ctx = rss->rss_ctx[ctx_id]; 320 /* Get memory to put this msg */ 321 for (idx = 0; idx < rss->rss_size; idx++) { 322 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 323 if (!aq) { 324 /* The shared memory buffer can be full. 325 * Flush it and retry 326 */ 327 err = otx2_sync_mbox_msg(mbox); 328 if (err) { 329 mutex_unlock(&mbox->lock); 330 return err; 331 } 332 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 333 if (!aq) { 334 mutex_unlock(&mbox->lock); 335 return -ENOMEM; 336 } 337 } 338 339 aq->rss.rq = rss_ctx->ind_tbl[idx]; 340 341 /* Fill AQ info */ 342 aq->qidx = index + idx; 343 aq->ctype = NIX_AQ_CTYPE_RSS; 344 aq->op = NIX_AQ_INSTOP_INIT; 345 } 346 err = otx2_sync_mbox_msg(mbox); 347 mutex_unlock(&mbox->lock); 348 return err; 349 } 350 351 void otx2_set_rss_key(struct otx2_nic *pfvf) 352 { 353 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 354 u64 *key = (u64 *)&rss->key[4]; 355 int idx; 356 357 /* 352bit or 44byte key needs to be configured as below 358 * NIX_LF_RX_SECRETX0 = key<351:288> 359 * NIX_LF_RX_SECRETX1 = key<287:224> 360 * NIX_LF_RX_SECRETX2 = key<223:160> 361 * NIX_LF_RX_SECRETX3 = key<159:96> 362 * NIX_LF_RX_SECRETX4 = key<95:32> 363 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 364 */ 365 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 366 (u64)(*((u32 *)&rss->key)) << 32); 367 idx = sizeof(rss->key) / sizeof(u64); 368 while (idx > 0) { 369 idx--; 370 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 371 } 372 } 373 374 int otx2_rss_init(struct otx2_nic *pfvf) 375 { 376 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 377 struct otx2_rss_ctx *rss_ctx; 378 int idx, ret = 0; 379 380 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 381 382 /* Init RSS key if it is not setup already */ 383 if (!rss->enable) 384 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 385 otx2_set_rss_key(pfvf); 386 387 if (!netif_is_rxfh_configured(pfvf->netdev)) { 388 /* Set RSS group 0 as default indirection table */ 389 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 390 GFP_KERNEL); 391 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 392 return -ENOMEM; 393 394 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 395 for (idx = 0; idx < rss->rss_size; idx++) 396 rss_ctx->ind_tbl[idx] = 397 ethtool_rxfh_indir_default(idx, 398 pfvf->hw.rx_queues); 399 } 400 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 401 if (ret) 402 return ret; 403 404 /* Flowkey or hash config to be used for generating flow tag */ 405 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 406 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 407 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 408 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 409 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 410 411 ret = otx2_set_flowkey_cfg(pfvf); 412 if (ret) 413 return ret; 414 415 rss->enable = true; 416 return 0; 417 } 418 419 /* Setup UDP segmentation algorithm in HW */ 420 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 421 { 422 struct nix_lso_format *field; 423 424 field = (struct nix_lso_format *)&lso->fields[0]; 425 lso->field_mask = GENMASK(18, 0); 426 427 /* IP's Length field */ 428 field->layer = NIX_TXLAYER_OL3; 429 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 430 field->offset = v4 ? 2 : 4; 431 field->sizem1 = 1; /* i.e 2 bytes */ 432 field->alg = NIX_LSOALG_ADD_PAYLEN; 433 field++; 434 435 /* No ID field in IPv6 header */ 436 if (v4) { 437 /* Increment IPID */ 438 field->layer = NIX_TXLAYER_OL3; 439 field->offset = 4; 440 field->sizem1 = 1; /* i.e 2 bytes */ 441 field->alg = NIX_LSOALG_ADD_SEGNUM; 442 field++; 443 } 444 445 /* Update length in UDP header */ 446 field->layer = NIX_TXLAYER_OL4; 447 field->offset = 4; 448 field->sizem1 = 1; 449 field->alg = NIX_LSOALG_ADD_PAYLEN; 450 } 451 452 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 453 void otx2_setup_segmentation(struct otx2_nic *pfvf) 454 { 455 struct nix_lso_format_cfg_rsp *rsp; 456 struct nix_lso_format_cfg *lso; 457 struct otx2_hw *hw = &pfvf->hw; 458 int err; 459 460 mutex_lock(&pfvf->mbox.lock); 461 462 /* UDPv4 segmentation */ 463 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 464 if (!lso) 465 goto fail; 466 467 /* Setup UDP/IP header fields that HW should update per segment */ 468 otx2_setup_udp_segmentation(lso, true); 469 470 err = otx2_sync_mbox_msg(&pfvf->mbox); 471 if (err) 472 goto fail; 473 474 rsp = (struct nix_lso_format_cfg_rsp *) 475 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 476 if (IS_ERR(rsp)) 477 goto fail; 478 479 hw->lso_udpv4_idx = rsp->lso_format_idx; 480 481 /* UDPv6 segmentation */ 482 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 483 if (!lso) 484 goto fail; 485 486 /* Setup UDP/IP header fields that HW should update per segment */ 487 otx2_setup_udp_segmentation(lso, false); 488 489 err = otx2_sync_mbox_msg(&pfvf->mbox); 490 if (err) 491 goto fail; 492 493 rsp = (struct nix_lso_format_cfg_rsp *) 494 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 495 if (IS_ERR(rsp)) 496 goto fail; 497 498 hw->lso_udpv6_idx = rsp->lso_format_idx; 499 mutex_unlock(&pfvf->mbox.lock); 500 return; 501 fail: 502 mutex_unlock(&pfvf->mbox.lock); 503 netdev_info(pfvf->netdev, 504 "Failed to get LSO index for UDP GSO offload, disabling\n"); 505 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 506 } 507 508 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 509 { 510 /* Configure CQE interrupt coalescing parameters 511 * 512 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 513 * set 1 less than cq_ecount_wait. And cq_time_wait is in 514 * usecs, convert that to 100ns count. 515 */ 516 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 517 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 518 ((u64)pfvf->hw.cq_qcount_wait << 32) | 519 (pfvf->hw.cq_ecount_wait - 1)); 520 } 521 522 static int otx2_alloc_pool_buf(struct otx2_nic *pfvf, struct otx2_pool *pool, 523 dma_addr_t *dma) 524 { 525 unsigned int offset = 0; 526 struct page *page; 527 size_t sz; 528 529 sz = SKB_DATA_ALIGN(pool->rbsize); 530 sz = ALIGN(sz, OTX2_ALIGN); 531 532 page = page_pool_alloc_frag(pool->page_pool, &offset, sz, GFP_ATOMIC); 533 if (unlikely(!page)) 534 return -ENOMEM; 535 536 *dma = page_pool_get_dma_addr(page) + offset; 537 return 0; 538 } 539 540 static int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 541 dma_addr_t *dma) 542 { 543 u8 *buf; 544 545 if (pool->page_pool) 546 return otx2_alloc_pool_buf(pfvf, pool, dma); 547 548 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 549 if (unlikely(!buf)) 550 return -ENOMEM; 551 552 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 553 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 554 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 555 page_frag_free(buf); 556 return -ENOMEM; 557 } 558 559 return 0; 560 } 561 562 int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 563 dma_addr_t *dma) 564 { 565 int ret; 566 567 local_bh_disable(); 568 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 569 local_bh_enable(); 570 return ret; 571 } 572 573 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 574 dma_addr_t *dma) 575 { 576 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) { 577 struct refill_work *work; 578 struct delayed_work *dwork; 579 580 work = &pfvf->refill_wrk[cq->cq_idx]; 581 dwork = &work->pool_refill_work; 582 /* Schedule a task if no other task is running */ 583 if (!cq->refill_task_sched) { 584 cq->refill_task_sched = true; 585 schedule_delayed_work(dwork, 586 msecs_to_jiffies(100)); 587 } 588 return -ENOMEM; 589 } 590 return 0; 591 } 592 593 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 594 { 595 struct otx2_nic *pfvf = netdev_priv(netdev); 596 597 schedule_work(&pfvf->reset_task); 598 } 599 EXPORT_SYMBOL(otx2_tx_timeout); 600 601 void otx2_get_mac_from_af(struct net_device *netdev) 602 { 603 struct otx2_nic *pfvf = netdev_priv(netdev); 604 int err; 605 606 err = otx2_hw_get_mac_addr(pfvf, netdev); 607 if (err) 608 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 609 610 /* If AF doesn't provide a valid MAC, generate a random one */ 611 if (!is_valid_ether_addr(netdev->dev_addr)) 612 eth_hw_addr_random(netdev); 613 } 614 EXPORT_SYMBOL(otx2_get_mac_from_af); 615 616 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, int prio, bool txschq_for_pfc) 617 { 618 u16 (*schq_list)[MAX_TXSCHQ_PER_FUNC]; 619 struct otx2_hw *hw = &pfvf->hw; 620 struct nix_txschq_config *req; 621 u64 schq, parent; 622 u64 dwrr_val; 623 624 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 625 626 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 627 if (!req) 628 return -ENOMEM; 629 630 req->lvl = lvl; 631 req->num_regs = 1; 632 633 schq_list = hw->txschq_list; 634 #ifdef CONFIG_DCB 635 if (txschq_for_pfc) 636 schq_list = pfvf->pfc_schq_list; 637 #endif 638 639 schq = schq_list[lvl][prio]; 640 /* Set topology e.t.c configuration */ 641 if (lvl == NIX_TXSCH_LVL_SMQ) { 642 req->reg[0] = NIX_AF_SMQX_CFG(schq); 643 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU; 644 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 645 (0x2ULL << 36); 646 /* Set link type for DWRR MTU selection on CN10K silicons */ 647 if (!is_dev_otx2(pfvf->pdev)) 648 req->regval[0] |= FIELD_PREP(GENMASK_ULL(58, 57), 649 (u64)hw->smq_link_type); 650 req->num_regs++; 651 /* MDQ config */ 652 parent = schq_list[NIX_TXSCH_LVL_TL4][prio]; 653 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 654 req->regval[1] = parent << 16; 655 req->num_regs++; 656 /* Set DWRR quantum */ 657 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 658 req->regval[2] = dwrr_val; 659 } else if (lvl == NIX_TXSCH_LVL_TL4) { 660 parent = schq_list[NIX_TXSCH_LVL_TL3][prio]; 661 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 662 req->regval[0] = parent << 16; 663 req->num_regs++; 664 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 665 req->regval[1] = dwrr_val; 666 } else if (lvl == NIX_TXSCH_LVL_TL3) { 667 parent = schq_list[NIX_TXSCH_LVL_TL2][prio]; 668 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 669 req->regval[0] = parent << 16; 670 req->num_regs++; 671 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 672 req->regval[1] = dwrr_val; 673 if (lvl == hw->txschq_link_cfg_lvl) { 674 req->num_regs++; 675 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 676 /* Enable this queue and backpressure 677 * and set relative channel 678 */ 679 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 680 } 681 } else if (lvl == NIX_TXSCH_LVL_TL2) { 682 parent = schq_list[NIX_TXSCH_LVL_TL1][prio]; 683 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 684 req->regval[0] = parent << 16; 685 686 req->num_regs++; 687 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 688 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val; 689 690 if (lvl == hw->txschq_link_cfg_lvl) { 691 req->num_regs++; 692 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 693 /* Enable this queue and backpressure 694 * and set relative channel 695 */ 696 req->regval[2] = BIT_ULL(13) | BIT_ULL(12) | prio; 697 } 698 } else if (lvl == NIX_TXSCH_LVL_TL1) { 699 /* Default config for TL1. 700 * For VF this is always ignored. 701 */ 702 703 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 704 * clip it to 16384, so configuring a 24bit max value 705 * will work on both OTx2 and CN10K. 706 */ 707 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 708 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 709 710 req->num_regs++; 711 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 712 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 713 714 req->num_regs++; 715 req->reg[2] = NIX_AF_TL1X_CIR(schq); 716 req->regval[2] = 0; 717 } 718 719 return otx2_sync_mbox_msg(&pfvf->mbox); 720 } 721 EXPORT_SYMBOL(otx2_txschq_config); 722 723 int otx2_smq_flush(struct otx2_nic *pfvf, int smq) 724 { 725 struct nix_txschq_config *req; 726 int rc; 727 728 mutex_lock(&pfvf->mbox.lock); 729 730 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 731 if (!req) { 732 mutex_unlock(&pfvf->mbox.lock); 733 return -ENOMEM; 734 } 735 736 req->lvl = NIX_TXSCH_LVL_SMQ; 737 req->reg[0] = NIX_AF_SMQX_CFG(smq); 738 req->regval[0] |= BIT_ULL(49); 739 req->num_regs++; 740 741 rc = otx2_sync_mbox_msg(&pfvf->mbox); 742 mutex_unlock(&pfvf->mbox.lock); 743 return rc; 744 } 745 EXPORT_SYMBOL(otx2_smq_flush); 746 747 int otx2_txsch_alloc(struct otx2_nic *pfvf) 748 { 749 struct nix_txsch_alloc_req *req; 750 struct nix_txsch_alloc_rsp *rsp; 751 int lvl, schq, rc; 752 753 /* Get memory to put this msg */ 754 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 755 if (!req) 756 return -ENOMEM; 757 758 /* Request one schq per level */ 759 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 760 req->schq[lvl] = 1; 761 rc = otx2_sync_mbox_msg(&pfvf->mbox); 762 if (rc) 763 return rc; 764 765 rsp = (struct nix_txsch_alloc_rsp *) 766 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 767 if (IS_ERR(rsp)) 768 return PTR_ERR(rsp); 769 770 /* Setup transmit scheduler list */ 771 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 772 for (schq = 0; schq < rsp->schq[lvl]; schq++) 773 pfvf->hw.txschq_list[lvl][schq] = 774 rsp->schq_list[lvl][schq]; 775 776 pfvf->hw.txschq_link_cfg_lvl = rsp->link_cfg_lvl; 777 pfvf->hw.txschq_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio; 778 779 return 0; 780 } 781 782 void otx2_txschq_free_one(struct otx2_nic *pfvf, u16 lvl, u16 schq) 783 { 784 struct nix_txsch_free_req *free_req; 785 int err; 786 787 mutex_lock(&pfvf->mbox.lock); 788 789 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 790 if (!free_req) { 791 mutex_unlock(&pfvf->mbox.lock); 792 netdev_err(pfvf->netdev, 793 "Failed alloc txschq free req\n"); 794 return; 795 } 796 797 free_req->schq_lvl = lvl; 798 free_req->schq = schq; 799 800 err = otx2_sync_mbox_msg(&pfvf->mbox); 801 if (err) { 802 netdev_err(pfvf->netdev, 803 "Failed stop txschq %d at level %d\n", schq, lvl); 804 } 805 806 mutex_unlock(&pfvf->mbox.lock); 807 } 808 809 void otx2_txschq_stop(struct otx2_nic *pfvf) 810 { 811 int lvl, schq; 812 813 /* free non QOS TLx nodes */ 814 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 815 otx2_txschq_free_one(pfvf, lvl, 816 pfvf->hw.txschq_list[lvl][0]); 817 818 /* Clear the txschq list */ 819 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 820 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 821 pfvf->hw.txschq_list[lvl][schq] = 0; 822 } 823 824 } 825 826 void otx2_sqb_flush(struct otx2_nic *pfvf) 827 { 828 int qidx, sqe_tail, sqe_head; 829 struct otx2_snd_queue *sq; 830 u64 incr, *ptr, val; 831 int timeout = 1000; 832 833 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 834 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 835 sq = &pfvf->qset.sq[qidx]; 836 if (!sq->sqb_ptrs) 837 continue; 838 839 incr = (u64)qidx << 32; 840 while (timeout) { 841 val = otx2_atomic64_add(incr, ptr); 842 sqe_head = (val >> 20) & 0x3F; 843 sqe_tail = (val >> 28) & 0x3F; 844 if (sqe_head == sqe_tail) 845 break; 846 usleep_range(1, 3); 847 timeout--; 848 } 849 } 850 } 851 852 /* RED and drop levels of CQ on packet reception. 853 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 854 */ 855 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 856 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 857 858 /* RED and drop levels of AURA for packet reception. 859 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 860 * Eg: For RQ length 1K, for pass/drop level 204/230. 861 * RED accepts pkts if free pointers > 102 & <= 205. 862 * Drops pkts if free pointers < 102. 863 */ 864 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 865 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 866 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 867 868 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 869 { 870 struct otx2_qset *qset = &pfvf->qset; 871 struct nix_aq_enq_req *aq; 872 873 /* Get memory to put this msg */ 874 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 875 if (!aq) 876 return -ENOMEM; 877 878 aq->rq.cq = qidx; 879 aq->rq.ena = 1; 880 aq->rq.pb_caching = 1; 881 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 882 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 883 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 884 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 885 aq->rq.qint_idx = 0; 886 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 887 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 888 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 889 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 890 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 891 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 892 893 /* Fill AQ info */ 894 aq->qidx = qidx; 895 aq->ctype = NIX_AQ_CTYPE_RQ; 896 aq->op = NIX_AQ_INSTOP_INIT; 897 898 return otx2_sync_mbox_msg(&pfvf->mbox); 899 } 900 901 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 902 { 903 struct otx2_nic *pfvf = dev; 904 struct otx2_snd_queue *sq; 905 struct nix_aq_enq_req *aq; 906 907 sq = &pfvf->qset.sq[qidx]; 908 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 909 /* Get memory to put this msg */ 910 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 911 if (!aq) 912 return -ENOMEM; 913 914 aq->sq.cq = pfvf->hw.rx_queues + qidx; 915 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 916 aq->sq.cq_ena = 1; 917 aq->sq.ena = 1; 918 aq->sq.smq = otx2_get_smq_idx(pfvf, qidx); 919 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 920 aq->sq.default_chan = pfvf->hw.tx_chan_base; 921 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 922 aq->sq.sqb_aura = sqb_aura; 923 aq->sq.sq_int_ena = NIX_SQINT_BITS; 924 aq->sq.qint_idx = 0; 925 /* Due pipelining impact minimum 2000 unused SQ CQE's 926 * need to maintain to avoid CQ overflow. 927 */ 928 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 929 930 /* Fill AQ info */ 931 aq->qidx = qidx; 932 aq->ctype = NIX_AQ_CTYPE_SQ; 933 aq->op = NIX_AQ_INSTOP_INIT; 934 935 return otx2_sync_mbox_msg(&pfvf->mbox); 936 } 937 938 int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 939 { 940 struct otx2_qset *qset = &pfvf->qset; 941 struct otx2_snd_queue *sq; 942 struct otx2_pool *pool; 943 int err; 944 945 pool = &pfvf->qset.pool[sqb_aura]; 946 sq = &qset->sq[qidx]; 947 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 948 sq->sqe_cnt = qset->sqe_cnt; 949 950 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 951 if (err) 952 return err; 953 954 if (qidx < pfvf->hw.tx_queues) { 955 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 956 TSO_HEADER_SIZE); 957 if (err) 958 return err; 959 } 960 961 sq->sqe_base = sq->sqe->base; 962 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 963 if (!sq->sg) 964 return -ENOMEM; 965 966 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) { 967 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 968 sizeof(*sq->timestamps)); 969 if (err) 970 return err; 971 } 972 973 sq->head = 0; 974 sq->cons_head = 0; 975 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 976 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 977 /* Set SQE threshold to 10% of total SQEs */ 978 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 979 sq->aura_id = sqb_aura; 980 sq->aura_fc_addr = pool->fc_addr->base; 981 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 982 983 sq->stats.bytes = 0; 984 sq->stats.pkts = 0; 985 986 return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); 987 988 } 989 990 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 991 { 992 struct otx2_qset *qset = &pfvf->qset; 993 int err, pool_id, non_xdp_queues; 994 struct nix_aq_enq_req *aq; 995 struct otx2_cq_queue *cq; 996 997 cq = &qset->cq[qidx]; 998 cq->cq_idx = qidx; 999 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues; 1000 if (qidx < pfvf->hw.rx_queues) { 1001 cq->cq_type = CQ_RX; 1002 cq->cint_idx = qidx; 1003 cq->cqe_cnt = qset->rqe_cnt; 1004 if (pfvf->xdp_prog) 1005 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0); 1006 } else if (qidx < non_xdp_queues) { 1007 cq->cq_type = CQ_TX; 1008 cq->cint_idx = qidx - pfvf->hw.rx_queues; 1009 cq->cqe_cnt = qset->sqe_cnt; 1010 } else { 1011 if (pfvf->hw.xdp_queues && 1012 qidx < non_xdp_queues + pfvf->hw.xdp_queues) { 1013 cq->cq_type = CQ_XDP; 1014 cq->cint_idx = qidx - non_xdp_queues; 1015 cq->cqe_cnt = qset->sqe_cnt; 1016 } else { 1017 cq->cq_type = CQ_QOS; 1018 cq->cint_idx = qidx - non_xdp_queues - 1019 pfvf->hw.xdp_queues; 1020 cq->cqe_cnt = qset->sqe_cnt; 1021 } 1022 } 1023 cq->cqe_size = pfvf->qset.xqe_size; 1024 1025 /* Allocate memory for CQEs */ 1026 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 1027 if (err) 1028 return err; 1029 1030 /* Save CQE CPU base for faster reference */ 1031 cq->cqe_base = cq->cqe->base; 1032 /* In case where all RQs auras point to single pool, 1033 * all CQs receive buffer pool also point to same pool. 1034 */ 1035 pool_id = ((cq->cq_type == CQ_RX) && 1036 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 1037 cq->rbpool = &qset->pool[pool_id]; 1038 cq->refill_task_sched = false; 1039 1040 /* Get memory to put this msg */ 1041 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 1042 if (!aq) 1043 return -ENOMEM; 1044 1045 aq->cq.ena = 1; 1046 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 1047 aq->cq.caching = 1; 1048 aq->cq.base = cq->cqe->iova; 1049 aq->cq.cint_idx = cq->cint_idx; 1050 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 1051 aq->cq.qint_idx = 0; 1052 aq->cq.avg_level = 255; 1053 1054 if (qidx < pfvf->hw.rx_queues) { 1055 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 1056 aq->cq.drop_ena = 1; 1057 1058 if (!is_otx2_lbkvf(pfvf->pdev)) { 1059 /* Enable receive CQ backpressure */ 1060 aq->cq.bp_ena = 1; 1061 #ifdef CONFIG_DCB 1062 aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]]; 1063 #else 1064 aq->cq.bpid = pfvf->bpid[0]; 1065 #endif 1066 1067 /* Set backpressure level is same as cq pass level */ 1068 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 1069 } 1070 } 1071 1072 /* Fill AQ info */ 1073 aq->qidx = qidx; 1074 aq->ctype = NIX_AQ_CTYPE_CQ; 1075 aq->op = NIX_AQ_INSTOP_INIT; 1076 1077 return otx2_sync_mbox_msg(&pfvf->mbox); 1078 } 1079 1080 static void otx2_pool_refill_task(struct work_struct *work) 1081 { 1082 struct otx2_cq_queue *cq; 1083 struct otx2_pool *rbpool; 1084 struct refill_work *wrk; 1085 int qidx, free_ptrs = 0; 1086 struct otx2_nic *pfvf; 1087 dma_addr_t bufptr; 1088 1089 wrk = container_of(work, struct refill_work, pool_refill_work.work); 1090 pfvf = wrk->pf; 1091 qidx = wrk - pfvf->refill_wrk; 1092 cq = &pfvf->qset.cq[qidx]; 1093 rbpool = cq->rbpool; 1094 free_ptrs = cq->pool_ptrs; 1095 1096 while (cq->pool_ptrs) { 1097 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) { 1098 /* Schedule a WQ if we fails to free atleast half of the 1099 * pointers else enable napi for this RQ. 1100 */ 1101 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 1102 struct delayed_work *dwork; 1103 1104 dwork = &wrk->pool_refill_work; 1105 schedule_delayed_work(dwork, 1106 msecs_to_jiffies(100)); 1107 } else { 1108 cq->refill_task_sched = false; 1109 } 1110 return; 1111 } 1112 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 1113 cq->pool_ptrs--; 1114 } 1115 cq->refill_task_sched = false; 1116 } 1117 1118 int otx2_config_nix_queues(struct otx2_nic *pfvf) 1119 { 1120 int qidx, err; 1121 1122 /* Initialize RX queues */ 1123 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 1124 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 1125 1126 err = otx2_rq_init(pfvf, qidx, lpb_aura); 1127 if (err) 1128 return err; 1129 } 1130 1131 /* Initialize TX queues */ 1132 for (qidx = 0; qidx < pfvf->hw.non_qos_queues; qidx++) { 1133 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1134 1135 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1136 if (err) 1137 return err; 1138 } 1139 1140 /* Initialize completion queues */ 1141 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1142 err = otx2_cq_init(pfvf, qidx); 1143 if (err) 1144 return err; 1145 } 1146 1147 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, 1148 NIX_LF_CQ_OP_STATUS); 1149 1150 /* Initialize work queue for receive buffer refill */ 1151 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1152 sizeof(struct refill_work), GFP_KERNEL); 1153 if (!pfvf->refill_wrk) 1154 return -ENOMEM; 1155 1156 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1157 pfvf->refill_wrk[qidx].pf = pfvf; 1158 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1159 otx2_pool_refill_task); 1160 } 1161 return 0; 1162 } 1163 1164 int otx2_config_nix(struct otx2_nic *pfvf) 1165 { 1166 struct nix_lf_alloc_req *nixlf; 1167 struct nix_lf_alloc_rsp *rsp; 1168 int err; 1169 1170 pfvf->qset.xqe_size = pfvf->hw.xqe_size; 1171 1172 /* Get memory to put this msg */ 1173 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1174 if (!nixlf) 1175 return -ENOMEM; 1176 1177 /* Set RQ/SQ/CQ counts */ 1178 nixlf->rq_cnt = pfvf->hw.rx_queues; 1179 nixlf->sq_cnt = otx2_get_total_tx_queues(pfvf); 1180 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1181 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1182 nixlf->rss_grps = MAX_RSS_GROUPS; 1183 nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64; 1184 /* We don't know absolute NPA LF idx attached. 1185 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1186 * NPA LF attached to this RVU PF/VF. 1187 */ 1188 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1189 /* Disable alignment pad, enable L2 length check, 1190 * enable L4 TCP/UDP checksum verification. 1191 */ 1192 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1193 1194 err = otx2_sync_mbox_msg(&pfvf->mbox); 1195 if (err) 1196 return err; 1197 1198 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1199 &nixlf->hdr); 1200 if (IS_ERR(rsp)) 1201 return PTR_ERR(rsp); 1202 1203 if (rsp->qints < 1) 1204 return -ENXIO; 1205 1206 return rsp->hdr.rc; 1207 } 1208 1209 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1210 { 1211 struct otx2_qset *qset = &pfvf->qset; 1212 struct otx2_hw *hw = &pfvf->hw; 1213 struct otx2_snd_queue *sq; 1214 int sqb, qidx; 1215 u64 iova, pa; 1216 1217 for (qidx = 0; qidx < otx2_get_total_tx_queues(pfvf); qidx++) { 1218 sq = &qset->sq[qidx]; 1219 if (!sq->sqb_ptrs) 1220 continue; 1221 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1222 if (!sq->sqb_ptrs[sqb]) 1223 continue; 1224 iova = sq->sqb_ptrs[sqb]; 1225 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1226 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1227 DMA_FROM_DEVICE, 1228 DMA_ATTR_SKIP_CPU_SYNC); 1229 put_page(virt_to_page(phys_to_virt(pa))); 1230 } 1231 sq->sqb_count = 0; 1232 } 1233 } 1234 1235 void otx2_free_bufs(struct otx2_nic *pfvf, struct otx2_pool *pool, 1236 u64 iova, int size) 1237 { 1238 struct page *page; 1239 u64 pa; 1240 1241 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1242 page = virt_to_head_page(phys_to_virt(pa)); 1243 1244 if (pool->page_pool) { 1245 page_pool_put_full_page(pool->page_pool, page, true); 1246 } else { 1247 dma_unmap_page_attrs(pfvf->dev, iova, size, 1248 DMA_FROM_DEVICE, 1249 DMA_ATTR_SKIP_CPU_SYNC); 1250 1251 put_page(page); 1252 } 1253 } 1254 1255 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1256 { 1257 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1258 struct otx2_pool *pool; 1259 u64 iova; 1260 1261 if (type == AURA_NIX_SQ) { 1262 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1263 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1264 size = pfvf->hw.sqb_size; 1265 } 1266 if (type == AURA_NIX_RQ) { 1267 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1268 pool_end = pfvf->hw.rqpool_cnt; 1269 size = pfvf->rbsize; 1270 } 1271 1272 /* Free SQB and RQB pointers from the aura pool */ 1273 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1274 iova = otx2_aura_allocptr(pfvf, pool_id); 1275 pool = &pfvf->qset.pool[pool_id]; 1276 while (iova) { 1277 if (type == AURA_NIX_RQ) 1278 iova -= OTX2_HEAD_ROOM; 1279 1280 otx2_free_bufs(pfvf, pool, iova, size); 1281 1282 iova = otx2_aura_allocptr(pfvf, pool_id); 1283 } 1284 } 1285 } 1286 1287 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1288 { 1289 struct otx2_pool *pool; 1290 int pool_id; 1291 1292 if (!pfvf->qset.pool) 1293 return; 1294 1295 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1296 pool = &pfvf->qset.pool[pool_id]; 1297 qmem_free(pfvf->dev, pool->stack); 1298 qmem_free(pfvf->dev, pool->fc_addr); 1299 page_pool_destroy(pool->page_pool); 1300 pool->page_pool = NULL; 1301 } 1302 devm_kfree(pfvf->dev, pfvf->qset.pool); 1303 pfvf->qset.pool = NULL; 1304 } 1305 1306 int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1307 int pool_id, int numptrs) 1308 { 1309 struct npa_aq_enq_req *aq; 1310 struct otx2_pool *pool; 1311 int err; 1312 1313 pool = &pfvf->qset.pool[pool_id]; 1314 1315 /* Allocate memory for HW to update Aura count. 1316 * Alloc one cache line, so that it fits all FC_STYPE modes. 1317 */ 1318 if (!pool->fc_addr) { 1319 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1320 if (err) 1321 return err; 1322 } 1323 1324 /* Initialize this aura's context via AF */ 1325 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1326 if (!aq) { 1327 /* Shared mbox memory buffer is full, flush it and retry */ 1328 err = otx2_sync_mbox_msg(&pfvf->mbox); 1329 if (err) 1330 return err; 1331 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1332 if (!aq) 1333 return -ENOMEM; 1334 } 1335 1336 aq->aura_id = aura_id; 1337 /* Will be filled by AF with correct pool context address */ 1338 aq->aura.pool_addr = pool_id; 1339 aq->aura.pool_caching = 1; 1340 aq->aura.shift = ilog2(numptrs) - 8; 1341 aq->aura.count = numptrs; 1342 aq->aura.limit = numptrs; 1343 aq->aura.avg_level = 255; 1344 aq->aura.ena = 1; 1345 aq->aura.fc_ena = 1; 1346 aq->aura.fc_addr = pool->fc_addr->iova; 1347 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1348 1349 /* Enable backpressure for RQ aura */ 1350 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1351 aq->aura.bp_ena = 0; 1352 /* If NIX1 LF is attached then specify NIX1_RX. 1353 * 1354 * Below NPA_AURA_S[BP_ENA] is set according to the 1355 * NPA_BPINTF_E enumeration given as: 1356 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1357 * NIX0_RX is 0x0 + 0*0x1 = 0 1358 * NIX1_RX is 0x0 + 1*0x1 = 1 1359 * But in HRM it is given that 1360 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1361 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1362 * enumerated by NPA_BPINTF_E." 1363 */ 1364 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1365 aq->aura.bp_ena = 1; 1366 #ifdef CONFIG_DCB 1367 aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]]; 1368 #else 1369 aq->aura.nix0_bpid = pfvf->bpid[0]; 1370 #endif 1371 1372 /* Set backpressure level for RQ's Aura */ 1373 aq->aura.bp = RQ_BP_LVL_AURA; 1374 } 1375 1376 /* Fill AQ info */ 1377 aq->ctype = NPA_AQ_CTYPE_AURA; 1378 aq->op = NPA_AQ_INSTOP_INIT; 1379 1380 return 0; 1381 } 1382 1383 int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1384 int stack_pages, int numptrs, int buf_size, int type) 1385 { 1386 struct page_pool_params pp_params = { 0 }; 1387 struct npa_aq_enq_req *aq; 1388 struct otx2_pool *pool; 1389 int err; 1390 1391 pool = &pfvf->qset.pool[pool_id]; 1392 /* Alloc memory for stack which is used to store buffer pointers */ 1393 err = qmem_alloc(pfvf->dev, &pool->stack, 1394 stack_pages, pfvf->hw.stack_pg_bytes); 1395 if (err) 1396 return err; 1397 1398 pool->rbsize = buf_size; 1399 1400 /* Initialize this pool's context via AF */ 1401 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1402 if (!aq) { 1403 /* Shared mbox memory buffer is full, flush it and retry */ 1404 err = otx2_sync_mbox_msg(&pfvf->mbox); 1405 if (err) { 1406 qmem_free(pfvf->dev, pool->stack); 1407 return err; 1408 } 1409 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1410 if (!aq) { 1411 qmem_free(pfvf->dev, pool->stack); 1412 return -ENOMEM; 1413 } 1414 } 1415 1416 aq->aura_id = pool_id; 1417 aq->pool.stack_base = pool->stack->iova; 1418 aq->pool.stack_caching = 1; 1419 aq->pool.ena = 1; 1420 aq->pool.buf_size = buf_size / 128; 1421 aq->pool.stack_max_pages = stack_pages; 1422 aq->pool.shift = ilog2(numptrs) - 8; 1423 aq->pool.ptr_start = 0; 1424 aq->pool.ptr_end = ~0ULL; 1425 1426 /* Fill AQ info */ 1427 aq->ctype = NPA_AQ_CTYPE_POOL; 1428 aq->op = NPA_AQ_INSTOP_INIT; 1429 1430 if (type != AURA_NIX_RQ) { 1431 pool->page_pool = NULL; 1432 return 0; 1433 } 1434 1435 pp_params.flags = PP_FLAG_PAGE_FRAG | PP_FLAG_DMA_MAP; 1436 pp_params.pool_size = numptrs; 1437 pp_params.nid = NUMA_NO_NODE; 1438 pp_params.dev = pfvf->dev; 1439 pp_params.dma_dir = DMA_FROM_DEVICE; 1440 pool->page_pool = page_pool_create(&pp_params); 1441 if (IS_ERR(pool->page_pool)) { 1442 netdev_err(pfvf->netdev, "Creation of page pool failed\n"); 1443 return PTR_ERR(pool->page_pool); 1444 } 1445 1446 return 0; 1447 } 1448 1449 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1450 { 1451 int qidx, pool_id, stack_pages, num_sqbs; 1452 struct otx2_qset *qset = &pfvf->qset; 1453 struct otx2_hw *hw = &pfvf->hw; 1454 struct otx2_snd_queue *sq; 1455 struct otx2_pool *pool; 1456 dma_addr_t bufptr; 1457 int err, ptr; 1458 1459 /* Calculate number of SQBs needed. 1460 * 1461 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1462 * Last SQE is used for pointing to next SQB. 1463 */ 1464 num_sqbs = (hw->sqb_size / 128) - 1; 1465 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1466 1467 /* Get no of stack pages needed */ 1468 stack_pages = 1469 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1470 1471 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1472 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1473 /* Initialize aura context */ 1474 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1475 if (err) 1476 goto fail; 1477 1478 /* Initialize pool context */ 1479 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1480 num_sqbs, hw->sqb_size, AURA_NIX_SQ); 1481 if (err) 1482 goto fail; 1483 } 1484 1485 /* Flush accumulated messages */ 1486 err = otx2_sync_mbox_msg(&pfvf->mbox); 1487 if (err) 1488 goto fail; 1489 1490 /* Allocate pointers and free them to aura/pool */ 1491 for (qidx = 0; qidx < hw->non_qos_queues; qidx++) { 1492 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1493 pool = &pfvf->qset.pool[pool_id]; 1494 1495 sq = &qset->sq[qidx]; 1496 sq->sqb_count = 0; 1497 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1498 if (!sq->sqb_ptrs) { 1499 err = -ENOMEM; 1500 goto err_mem; 1501 } 1502 1503 for (ptr = 0; ptr < num_sqbs; ptr++) { 1504 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1505 if (err) 1506 goto err_mem; 1507 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1508 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1509 } 1510 } 1511 1512 err_mem: 1513 return err ? -ENOMEM : 0; 1514 1515 fail: 1516 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1517 otx2_aura_pool_free(pfvf); 1518 return err; 1519 } 1520 1521 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1522 { 1523 struct otx2_hw *hw = &pfvf->hw; 1524 int stack_pages, pool_id, rq; 1525 struct otx2_pool *pool; 1526 int err, ptr, num_ptrs; 1527 dma_addr_t bufptr; 1528 1529 num_ptrs = pfvf->qset.rqe_cnt; 1530 1531 stack_pages = 1532 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1533 1534 for (rq = 0; rq < hw->rx_queues; rq++) { 1535 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1536 /* Initialize aura context */ 1537 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1538 if (err) 1539 goto fail; 1540 } 1541 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1542 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1543 num_ptrs, pfvf->rbsize, AURA_NIX_RQ); 1544 if (err) 1545 goto fail; 1546 } 1547 1548 /* Flush accumulated messages */ 1549 err = otx2_sync_mbox_msg(&pfvf->mbox); 1550 if (err) 1551 goto fail; 1552 1553 /* Allocate pointers and free them to aura/pool */ 1554 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1555 pool = &pfvf->qset.pool[pool_id]; 1556 for (ptr = 0; ptr < num_ptrs; ptr++) { 1557 err = otx2_alloc_rbuf(pfvf, pool, &bufptr); 1558 if (err) 1559 return -ENOMEM; 1560 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1561 bufptr + OTX2_HEAD_ROOM); 1562 } 1563 } 1564 return 0; 1565 fail: 1566 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1567 otx2_aura_pool_free(pfvf); 1568 return err; 1569 } 1570 1571 int otx2_config_npa(struct otx2_nic *pfvf) 1572 { 1573 struct otx2_qset *qset = &pfvf->qset; 1574 struct npa_lf_alloc_req *npalf; 1575 struct otx2_hw *hw = &pfvf->hw; 1576 int aura_cnt; 1577 1578 /* Pool - Stack of free buffer pointers 1579 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1580 */ 1581 1582 if (!hw->pool_cnt) 1583 return -EINVAL; 1584 1585 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1586 sizeof(struct otx2_pool), GFP_KERNEL); 1587 if (!qset->pool) 1588 return -ENOMEM; 1589 1590 /* Get memory to put this msg */ 1591 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1592 if (!npalf) 1593 return -ENOMEM; 1594 1595 /* Set aura and pool counts */ 1596 npalf->nr_pools = hw->pool_cnt; 1597 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1598 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1599 1600 return otx2_sync_mbox_msg(&pfvf->mbox); 1601 } 1602 1603 int otx2_detach_resources(struct mbox *mbox) 1604 { 1605 struct rsrc_detach *detach; 1606 1607 mutex_lock(&mbox->lock); 1608 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1609 if (!detach) { 1610 mutex_unlock(&mbox->lock); 1611 return -ENOMEM; 1612 } 1613 1614 /* detach all */ 1615 detach->partial = false; 1616 1617 /* Send detach request to AF */ 1618 otx2_mbox_msg_send(&mbox->mbox, 0); 1619 mutex_unlock(&mbox->lock); 1620 return 0; 1621 } 1622 EXPORT_SYMBOL(otx2_detach_resources); 1623 1624 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1625 { 1626 struct rsrc_attach *attach; 1627 struct msg_req *msix; 1628 int err; 1629 1630 mutex_lock(&pfvf->mbox.lock); 1631 /* Get memory to put this msg */ 1632 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1633 if (!attach) { 1634 mutex_unlock(&pfvf->mbox.lock); 1635 return -ENOMEM; 1636 } 1637 1638 attach->npalf = true; 1639 attach->nixlf = true; 1640 1641 /* Send attach request to AF */ 1642 err = otx2_sync_mbox_msg(&pfvf->mbox); 1643 if (err) { 1644 mutex_unlock(&pfvf->mbox.lock); 1645 return err; 1646 } 1647 1648 pfvf->nix_blkaddr = BLKADDR_NIX0; 1649 1650 /* If the platform has two NIX blocks then LF may be 1651 * allocated from NIX1. 1652 */ 1653 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1654 pfvf->nix_blkaddr = BLKADDR_NIX1; 1655 1656 /* Get NPA and NIX MSIX vector offsets */ 1657 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1658 if (!msix) { 1659 mutex_unlock(&pfvf->mbox.lock); 1660 return -ENOMEM; 1661 } 1662 1663 err = otx2_sync_mbox_msg(&pfvf->mbox); 1664 if (err) { 1665 mutex_unlock(&pfvf->mbox.lock); 1666 return err; 1667 } 1668 mutex_unlock(&pfvf->mbox.lock); 1669 1670 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1671 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1672 dev_err(pfvf->dev, 1673 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1674 return -EINVAL; 1675 } 1676 1677 return 0; 1678 } 1679 EXPORT_SYMBOL(otx2_attach_npa_nix); 1680 1681 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1682 { 1683 struct hwctx_disable_req *req; 1684 1685 mutex_lock(&mbox->lock); 1686 /* Request AQ to disable this context */ 1687 if (npa) 1688 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1689 else 1690 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1691 1692 if (!req) { 1693 mutex_unlock(&mbox->lock); 1694 return; 1695 } 1696 1697 req->ctype = type; 1698 1699 if (otx2_sync_mbox_msg(mbox)) 1700 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1701 __func__); 1702 1703 mutex_unlock(&mbox->lock); 1704 } 1705 1706 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1707 { 1708 struct nix_bp_cfg_req *req; 1709 1710 if (enable) 1711 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1712 else 1713 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1714 1715 if (!req) 1716 return -ENOMEM; 1717 1718 req->chan_base = 0; 1719 #ifdef CONFIG_DCB 1720 req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1; 1721 req->bpid_per_chan = pfvf->pfc_en ? 1 : 0; 1722 #else 1723 req->chan_cnt = 1; 1724 req->bpid_per_chan = 0; 1725 #endif 1726 1727 return otx2_sync_mbox_msg(&pfvf->mbox); 1728 } 1729 EXPORT_SYMBOL(otx2_nix_config_bp); 1730 1731 /* Mbox message handlers */ 1732 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1733 struct cgx_stats_rsp *rsp) 1734 { 1735 int id; 1736 1737 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1738 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1739 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1740 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1741 } 1742 1743 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1744 struct cgx_fec_stats_rsp *rsp) 1745 { 1746 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1747 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1748 } 1749 1750 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1751 struct npa_lf_alloc_rsp *rsp) 1752 { 1753 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1754 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1755 } 1756 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1757 1758 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1759 struct nix_lf_alloc_rsp *rsp) 1760 { 1761 pfvf->hw.sqb_size = rsp->sqb_size; 1762 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1763 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1764 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1765 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1766 pfvf->hw.cgx_links = rsp->cgx_links; 1767 pfvf->hw.lbk_links = rsp->lbk_links; 1768 pfvf->hw.tx_link = rsp->tx_link; 1769 } 1770 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1771 1772 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1773 struct msix_offset_rsp *rsp) 1774 { 1775 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1776 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1777 } 1778 EXPORT_SYMBOL(mbox_handler_msix_offset); 1779 1780 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1781 struct nix_bp_cfg_rsp *rsp) 1782 { 1783 int chan, chan_id; 1784 1785 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1786 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1787 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1788 } 1789 } 1790 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1791 1792 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1793 { 1794 struct otx2_qset *qset = &pfvf->qset; 1795 struct otx2_hw *hw = &pfvf->hw; 1796 int irq, qidx; 1797 1798 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1799 qidx < n; 1800 qidx++, irq++) { 1801 int vector = pci_irq_vector(pfvf->pdev, irq); 1802 1803 irq_set_affinity_hint(vector, NULL); 1804 free_cpumask_var(hw->affinity_mask[irq]); 1805 free_irq(vector, &qset->napi[qidx]); 1806 } 1807 } 1808 1809 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1810 { 1811 struct otx2_hw *hw = &pfvf->hw; 1812 int vec, cpu, irq, cint; 1813 1814 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1815 cpu = cpumask_first(cpu_online_mask); 1816 1817 /* CQ interrupts */ 1818 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1819 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1820 return; 1821 1822 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1823 1824 irq = pci_irq_vector(pfvf->pdev, vec); 1825 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1826 1827 cpu = cpumask_next(cpu, cpu_online_mask); 1828 if (unlikely(cpu >= nr_cpu_ids)) 1829 cpu = 0; 1830 } 1831 } 1832 1833 static u32 get_dwrr_mtu(struct otx2_nic *pfvf, struct nix_hw_info *hw) 1834 { 1835 if (is_otx2_lbkvf(pfvf->pdev)) { 1836 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_LBK; 1837 return hw->lbk_dwrr_mtu; 1838 } 1839 1840 pfvf->hw.smq_link_type = SMQ_LINK_TYPE_RPM; 1841 return hw->rpm_dwrr_mtu; 1842 } 1843 1844 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1845 { 1846 struct nix_hw_info *rsp; 1847 struct msg_req *req; 1848 u16 max_mtu; 1849 int rc; 1850 1851 mutex_lock(&pfvf->mbox.lock); 1852 1853 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1854 if (!req) { 1855 rc = -ENOMEM; 1856 goto out; 1857 } 1858 1859 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1860 if (!rc) { 1861 rsp = (struct nix_hw_info *) 1862 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1863 1864 /* HW counts VLAN insertion bytes (8 for double tag) 1865 * irrespective of whether SQE is requesting to insert VLAN 1866 * in the packet or not. Hence these 8 bytes have to be 1867 * discounted from max packet size otherwise HW will throw 1868 * SMQ errors 1869 */ 1870 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1871 1872 /* Also save DWRR MTU, needed for DWRR weight calculation */ 1873 pfvf->hw.dwrr_mtu = get_dwrr_mtu(pfvf, rsp); 1874 if (!pfvf->hw.dwrr_mtu) 1875 pfvf->hw.dwrr_mtu = 1; 1876 } 1877 1878 out: 1879 mutex_unlock(&pfvf->mbox.lock); 1880 if (rc) { 1881 dev_warn(pfvf->dev, 1882 "Failed to get MTU from hardware setting default value(1500)\n"); 1883 max_mtu = 1500; 1884 } 1885 return max_mtu; 1886 } 1887 EXPORT_SYMBOL(otx2_get_max_mtu); 1888 1889 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features) 1890 { 1891 netdev_features_t changed = features ^ netdev->features; 1892 struct otx2_nic *pfvf = netdev_priv(netdev); 1893 bool ntuple = !!(features & NETIF_F_NTUPLE); 1894 bool tc = !!(features & NETIF_F_HW_TC); 1895 1896 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1897 otx2_destroy_ntuple_flows(pfvf); 1898 1899 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1900 if (!pfvf->flow_cfg->max_flows) { 1901 netdev_err(netdev, 1902 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1903 return -EINVAL; 1904 } 1905 } 1906 1907 if ((changed & NETIF_F_HW_TC) && tc) { 1908 if (!pfvf->flow_cfg->max_flows) { 1909 netdev_err(netdev, 1910 "Can't enable TC, MCAM entries not allocated\n"); 1911 return -EINVAL; 1912 } 1913 } 1914 1915 if ((changed & NETIF_F_HW_TC) && !tc && 1916 pfvf->flow_cfg && pfvf->flow_cfg->nr_flows) { 1917 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1918 return -EBUSY; 1919 } 1920 1921 if ((changed & NETIF_F_NTUPLE) && ntuple && 1922 (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) { 1923 netdev_err(netdev, 1924 "Can't enable NTUPLE when TC is active, disable TC and retry\n"); 1925 return -EINVAL; 1926 } 1927 1928 if ((changed & NETIF_F_HW_TC) && tc && 1929 (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) { 1930 netdev_err(netdev, 1931 "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n"); 1932 return -EINVAL; 1933 } 1934 1935 return 0; 1936 } 1937 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features); 1938 1939 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1940 int __weak \ 1941 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1942 struct _req_type *req, \ 1943 struct _rsp_type *rsp) \ 1944 { \ 1945 /* Nothing to do here */ \ 1946 return 0; \ 1947 } \ 1948 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1949 MBOX_UP_CGX_MESSAGES 1950 MBOX_UP_MCS_MESSAGES 1951 #undef M 1952