1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 #include <net/tso.h> 11 12 #include "otx2_reg.h" 13 #include "otx2_common.h" 14 #include "otx2_struct.h" 15 #include "cn10k.h" 16 17 static void otx2_nix_rq_op_stats(struct queue_stats *stats, 18 struct otx2_nic *pfvf, int qidx) 19 { 20 u64 incr = (u64)qidx << 32; 21 u64 *ptr; 22 23 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_OCTS); 24 stats->bytes = otx2_atomic64_add(incr, ptr); 25 26 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_RQ_OP_PKTS); 27 stats->pkts = otx2_atomic64_add(incr, ptr); 28 } 29 30 static void otx2_nix_sq_op_stats(struct queue_stats *stats, 31 struct otx2_nic *pfvf, int qidx) 32 { 33 u64 incr = (u64)qidx << 32; 34 u64 *ptr; 35 36 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_OCTS); 37 stats->bytes = otx2_atomic64_add(incr, ptr); 38 39 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_PKTS); 40 stats->pkts = otx2_atomic64_add(incr, ptr); 41 } 42 43 void otx2_update_lmac_stats(struct otx2_nic *pfvf) 44 { 45 struct msg_req *req; 46 47 if (!netif_running(pfvf->netdev)) 48 return; 49 50 mutex_lock(&pfvf->mbox.lock); 51 req = otx2_mbox_alloc_msg_cgx_stats(&pfvf->mbox); 52 if (!req) { 53 mutex_unlock(&pfvf->mbox.lock); 54 return; 55 } 56 57 otx2_sync_mbox_msg(&pfvf->mbox); 58 mutex_unlock(&pfvf->mbox.lock); 59 } 60 61 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) 62 { 63 struct msg_req *req; 64 65 if (!netif_running(pfvf->netdev)) 66 return; 67 mutex_lock(&pfvf->mbox.lock); 68 req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); 69 if (req) 70 otx2_sync_mbox_msg(&pfvf->mbox); 71 mutex_unlock(&pfvf->mbox.lock); 72 } 73 74 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) 75 { 76 struct otx2_rcv_queue *rq = &pfvf->qset.rq[qidx]; 77 78 if (!pfvf->qset.rq) 79 return 0; 80 81 otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); 82 return 1; 83 } 84 85 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) 86 { 87 struct otx2_snd_queue *sq = &pfvf->qset.sq[qidx]; 88 89 if (!pfvf->qset.sq) 90 return 0; 91 92 otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); 93 return 1; 94 } 95 96 void otx2_get_dev_stats(struct otx2_nic *pfvf) 97 { 98 struct otx2_dev_stats *dev_stats = &pfvf->hw.dev_stats; 99 100 #define OTX2_GET_RX_STATS(reg) \ 101 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 102 #define OTX2_GET_TX_STATS(reg) \ 103 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 104 105 dev_stats->rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 106 dev_stats->rx_drops = OTX2_GET_RX_STATS(RX_DROP); 107 dev_stats->rx_bcast_frames = OTX2_GET_RX_STATS(RX_BCAST); 108 dev_stats->rx_mcast_frames = OTX2_GET_RX_STATS(RX_MCAST); 109 dev_stats->rx_ucast_frames = OTX2_GET_RX_STATS(RX_UCAST); 110 dev_stats->rx_frames = dev_stats->rx_bcast_frames + 111 dev_stats->rx_mcast_frames + 112 dev_stats->rx_ucast_frames; 113 114 dev_stats->tx_bytes = OTX2_GET_TX_STATS(TX_OCTS); 115 dev_stats->tx_drops = OTX2_GET_TX_STATS(TX_DROP); 116 dev_stats->tx_bcast_frames = OTX2_GET_TX_STATS(TX_BCAST); 117 dev_stats->tx_mcast_frames = OTX2_GET_TX_STATS(TX_MCAST); 118 dev_stats->tx_ucast_frames = OTX2_GET_TX_STATS(TX_UCAST); 119 dev_stats->tx_frames = dev_stats->tx_bcast_frames + 120 dev_stats->tx_mcast_frames + 121 dev_stats->tx_ucast_frames; 122 } 123 124 void otx2_get_stats64(struct net_device *netdev, 125 struct rtnl_link_stats64 *stats) 126 { 127 struct otx2_nic *pfvf = netdev_priv(netdev); 128 struct otx2_dev_stats *dev_stats; 129 130 otx2_get_dev_stats(pfvf); 131 132 dev_stats = &pfvf->hw.dev_stats; 133 stats->rx_bytes = dev_stats->rx_bytes; 134 stats->rx_packets = dev_stats->rx_frames; 135 stats->rx_dropped = dev_stats->rx_drops; 136 stats->multicast = dev_stats->rx_mcast_frames; 137 138 stats->tx_bytes = dev_stats->tx_bytes; 139 stats->tx_packets = dev_stats->tx_frames; 140 stats->tx_dropped = dev_stats->tx_drops; 141 } 142 EXPORT_SYMBOL(otx2_get_stats64); 143 144 /* Sync MAC address with RVU AF */ 145 static int otx2_hw_set_mac_addr(struct otx2_nic *pfvf, u8 *mac) 146 { 147 struct nix_set_mac_addr *req; 148 int err; 149 150 mutex_lock(&pfvf->mbox.lock); 151 req = otx2_mbox_alloc_msg_nix_set_mac_addr(&pfvf->mbox); 152 if (!req) { 153 mutex_unlock(&pfvf->mbox.lock); 154 return -ENOMEM; 155 } 156 157 ether_addr_copy(req->mac_addr, mac); 158 159 err = otx2_sync_mbox_msg(&pfvf->mbox); 160 mutex_unlock(&pfvf->mbox.lock); 161 return err; 162 } 163 164 static int otx2_hw_get_mac_addr(struct otx2_nic *pfvf, 165 struct net_device *netdev) 166 { 167 struct nix_get_mac_addr_rsp *rsp; 168 struct mbox_msghdr *msghdr; 169 struct msg_req *req; 170 int err; 171 172 mutex_lock(&pfvf->mbox.lock); 173 req = otx2_mbox_alloc_msg_nix_get_mac_addr(&pfvf->mbox); 174 if (!req) { 175 mutex_unlock(&pfvf->mbox.lock); 176 return -ENOMEM; 177 } 178 179 err = otx2_sync_mbox_msg(&pfvf->mbox); 180 if (err) { 181 mutex_unlock(&pfvf->mbox.lock); 182 return err; 183 } 184 185 msghdr = otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 186 if (IS_ERR(msghdr)) { 187 mutex_unlock(&pfvf->mbox.lock); 188 return PTR_ERR(msghdr); 189 } 190 rsp = (struct nix_get_mac_addr_rsp *)msghdr; 191 eth_hw_addr_set(netdev, rsp->mac_addr); 192 mutex_unlock(&pfvf->mbox.lock); 193 194 return 0; 195 } 196 197 int otx2_set_mac_address(struct net_device *netdev, void *p) 198 { 199 struct otx2_nic *pfvf = netdev_priv(netdev); 200 struct sockaddr *addr = p; 201 202 if (!is_valid_ether_addr(addr->sa_data)) 203 return -EADDRNOTAVAIL; 204 205 if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { 206 eth_hw_addr_set(netdev, addr->sa_data); 207 /* update dmac field in vlan offload rule */ 208 if (netif_running(netdev) && 209 pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 210 otx2_install_rxvlan_offload_flow(pfvf); 211 /* update dmac address in ntuple and DMAC filter list */ 212 if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 213 otx2_dmacflt_update_pfmac_flow(pfvf); 214 } else { 215 return -EPERM; 216 } 217 218 return 0; 219 } 220 EXPORT_SYMBOL(otx2_set_mac_address); 221 222 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) 223 { 224 struct nix_frs_cfg *req; 225 u16 maxlen; 226 int err; 227 228 maxlen = otx2_get_max_mtu(pfvf) + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 229 230 mutex_lock(&pfvf->mbox.lock); 231 req = otx2_mbox_alloc_msg_nix_set_hw_frs(&pfvf->mbox); 232 if (!req) { 233 mutex_unlock(&pfvf->mbox.lock); 234 return -ENOMEM; 235 } 236 237 req->maxlen = pfvf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 238 239 /* Use max receive length supported by hardware for loopback devices */ 240 if (is_otx2_lbkvf(pfvf->pdev)) 241 req->maxlen = maxlen; 242 243 err = otx2_sync_mbox_msg(&pfvf->mbox); 244 mutex_unlock(&pfvf->mbox.lock); 245 return err; 246 } 247 248 int otx2_config_pause_frm(struct otx2_nic *pfvf) 249 { 250 struct cgx_pause_frm_cfg *req; 251 int err; 252 253 if (is_otx2_lbkvf(pfvf->pdev)) 254 return 0; 255 256 mutex_lock(&pfvf->mbox.lock); 257 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 258 if (!req) { 259 err = -ENOMEM; 260 goto unlock; 261 } 262 263 req->rx_pause = !!(pfvf->flags & OTX2_FLAG_RX_PAUSE_ENABLED); 264 req->tx_pause = !!(pfvf->flags & OTX2_FLAG_TX_PAUSE_ENABLED); 265 req->set = 1; 266 267 err = otx2_sync_mbox_msg(&pfvf->mbox); 268 unlock: 269 mutex_unlock(&pfvf->mbox.lock); 270 return err; 271 } 272 EXPORT_SYMBOL(otx2_config_pause_frm); 273 274 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) 275 { 276 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 277 struct nix_rss_flowkey_cfg_rsp *rsp; 278 struct nix_rss_flowkey_cfg *req; 279 int err; 280 281 mutex_lock(&pfvf->mbox.lock); 282 req = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(&pfvf->mbox); 283 if (!req) { 284 mutex_unlock(&pfvf->mbox.lock); 285 return -ENOMEM; 286 } 287 req->mcam_index = -1; /* Default or reserved index */ 288 req->flowkey_cfg = rss->flowkey_cfg; 289 req->group = DEFAULT_RSS_CONTEXT_GROUP; 290 291 err = otx2_sync_mbox_msg(&pfvf->mbox); 292 if (err) 293 goto fail; 294 295 rsp = (struct nix_rss_flowkey_cfg_rsp *) 296 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 297 if (IS_ERR(rsp)) { 298 err = PTR_ERR(rsp); 299 goto fail; 300 } 301 302 pfvf->hw.flowkey_alg_idx = rsp->alg_idx; 303 fail: 304 mutex_unlock(&pfvf->mbox.lock); 305 return err; 306 } 307 308 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) 309 { 310 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 311 const int index = rss->rss_size * ctx_id; 312 struct mbox *mbox = &pfvf->mbox; 313 struct otx2_rss_ctx *rss_ctx; 314 struct nix_aq_enq_req *aq; 315 int idx, err; 316 317 mutex_lock(&mbox->lock); 318 rss_ctx = rss->rss_ctx[ctx_id]; 319 /* Get memory to put this msg */ 320 for (idx = 0; idx < rss->rss_size; idx++) { 321 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 322 if (!aq) { 323 /* The shared memory buffer can be full. 324 * Flush it and retry 325 */ 326 err = otx2_sync_mbox_msg(mbox); 327 if (err) { 328 mutex_unlock(&mbox->lock); 329 return err; 330 } 331 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox); 332 if (!aq) { 333 mutex_unlock(&mbox->lock); 334 return -ENOMEM; 335 } 336 } 337 338 aq->rss.rq = rss_ctx->ind_tbl[idx]; 339 340 /* Fill AQ info */ 341 aq->qidx = index + idx; 342 aq->ctype = NIX_AQ_CTYPE_RSS; 343 aq->op = NIX_AQ_INSTOP_INIT; 344 } 345 err = otx2_sync_mbox_msg(mbox); 346 mutex_unlock(&mbox->lock); 347 return err; 348 } 349 350 void otx2_set_rss_key(struct otx2_nic *pfvf) 351 { 352 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 353 u64 *key = (u64 *)&rss->key[4]; 354 int idx; 355 356 /* 352bit or 44byte key needs to be configured as below 357 * NIX_LF_RX_SECRETX0 = key<351:288> 358 * NIX_LF_RX_SECRETX1 = key<287:224> 359 * NIX_LF_RX_SECRETX2 = key<223:160> 360 * NIX_LF_RX_SECRETX3 = key<159:96> 361 * NIX_LF_RX_SECRETX4 = key<95:32> 362 * NIX_LF_RX_SECRETX5<63:32> = key<31:0> 363 */ 364 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), 365 (u64)(*((u32 *)&rss->key)) << 32); 366 idx = sizeof(rss->key) / sizeof(u64); 367 while (idx > 0) { 368 idx--; 369 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); 370 } 371 } 372 373 int otx2_rss_init(struct otx2_nic *pfvf) 374 { 375 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 376 struct otx2_rss_ctx *rss_ctx; 377 int idx, ret = 0; 378 379 rss->rss_size = sizeof(*rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 380 381 /* Init RSS key if it is not setup already */ 382 if (!rss->enable) 383 netdev_rss_key_fill(rss->key, sizeof(rss->key)); 384 otx2_set_rss_key(pfvf); 385 386 if (!netif_is_rxfh_configured(pfvf->netdev)) { 387 /* Set RSS group 0 as default indirection table */ 388 rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP] = kzalloc(rss->rss_size, 389 GFP_KERNEL); 390 if (!rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]) 391 return -ENOMEM; 392 393 rss_ctx = rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]; 394 for (idx = 0; idx < rss->rss_size; idx++) 395 rss_ctx->ind_tbl[idx] = 396 ethtool_rxfh_indir_default(idx, 397 pfvf->hw.rx_queues); 398 } 399 ret = otx2_set_rss_table(pfvf, DEFAULT_RSS_CONTEXT_GROUP); 400 if (ret) 401 return ret; 402 403 /* Flowkey or hash config to be used for generating flow tag */ 404 rss->flowkey_cfg = rss->enable ? rss->flowkey_cfg : 405 NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6 | 406 NIX_FLOW_KEY_TYPE_TCP | NIX_FLOW_KEY_TYPE_UDP | 407 NIX_FLOW_KEY_TYPE_SCTP | NIX_FLOW_KEY_TYPE_VLAN | 408 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 409 410 ret = otx2_set_flowkey_cfg(pfvf); 411 if (ret) 412 return ret; 413 414 rss->enable = true; 415 return 0; 416 } 417 418 /* Setup UDP segmentation algorithm in HW */ 419 static void otx2_setup_udp_segmentation(struct nix_lso_format_cfg *lso, bool v4) 420 { 421 struct nix_lso_format *field; 422 423 field = (struct nix_lso_format *)&lso->fields[0]; 424 lso->field_mask = GENMASK(18, 0); 425 426 /* IP's Length field */ 427 field->layer = NIX_TXLAYER_OL3; 428 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 429 field->offset = v4 ? 2 : 4; 430 field->sizem1 = 1; /* i.e 2 bytes */ 431 field->alg = NIX_LSOALG_ADD_PAYLEN; 432 field++; 433 434 /* No ID field in IPv6 header */ 435 if (v4) { 436 /* Increment IPID */ 437 field->layer = NIX_TXLAYER_OL3; 438 field->offset = 4; 439 field->sizem1 = 1; /* i.e 2 bytes */ 440 field->alg = NIX_LSOALG_ADD_SEGNUM; 441 field++; 442 } 443 444 /* Update length in UDP header */ 445 field->layer = NIX_TXLAYER_OL4; 446 field->offset = 4; 447 field->sizem1 = 1; 448 field->alg = NIX_LSOALG_ADD_PAYLEN; 449 } 450 451 /* Setup segmentation algorithms in HW and retrieve algorithm index */ 452 void otx2_setup_segmentation(struct otx2_nic *pfvf) 453 { 454 struct nix_lso_format_cfg_rsp *rsp; 455 struct nix_lso_format_cfg *lso; 456 struct otx2_hw *hw = &pfvf->hw; 457 int err; 458 459 mutex_lock(&pfvf->mbox.lock); 460 461 /* UDPv4 segmentation */ 462 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 463 if (!lso) 464 goto fail; 465 466 /* Setup UDP/IP header fields that HW should update per segment */ 467 otx2_setup_udp_segmentation(lso, true); 468 469 err = otx2_sync_mbox_msg(&pfvf->mbox); 470 if (err) 471 goto fail; 472 473 rsp = (struct nix_lso_format_cfg_rsp *) 474 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 475 if (IS_ERR(rsp)) 476 goto fail; 477 478 hw->lso_udpv4_idx = rsp->lso_format_idx; 479 480 /* UDPv6 segmentation */ 481 lso = otx2_mbox_alloc_msg_nix_lso_format_cfg(&pfvf->mbox); 482 if (!lso) 483 goto fail; 484 485 /* Setup UDP/IP header fields that HW should update per segment */ 486 otx2_setup_udp_segmentation(lso, false); 487 488 err = otx2_sync_mbox_msg(&pfvf->mbox); 489 if (err) 490 goto fail; 491 492 rsp = (struct nix_lso_format_cfg_rsp *) 493 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &lso->hdr); 494 if (IS_ERR(rsp)) 495 goto fail; 496 497 hw->lso_udpv6_idx = rsp->lso_format_idx; 498 mutex_unlock(&pfvf->mbox.lock); 499 return; 500 fail: 501 mutex_unlock(&pfvf->mbox.lock); 502 netdev_info(pfvf->netdev, 503 "Failed to get LSO index for UDP GSO offload, disabling\n"); 504 pfvf->netdev->hw_features &= ~NETIF_F_GSO_UDP_L4; 505 } 506 507 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx) 508 { 509 /* Configure CQE interrupt coalescing parameters 510 * 511 * HW triggers an irq when ECOUNT > cq_ecount_wait, hence 512 * set 1 less than cq_ecount_wait. And cq_time_wait is in 513 * usecs, convert that to 100ns count. 514 */ 515 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), 516 ((u64)(pfvf->hw.cq_time_wait * 10) << 48) | 517 ((u64)pfvf->hw.cq_qcount_wait << 32) | 518 (pfvf->hw.cq_ecount_wait - 1)); 519 } 520 521 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 522 dma_addr_t *dma) 523 { 524 u8 *buf; 525 526 buf = napi_alloc_frag_align(pool->rbsize, OTX2_ALIGN); 527 if (unlikely(!buf)) 528 return -ENOMEM; 529 530 *dma = dma_map_single_attrs(pfvf->dev, buf, pool->rbsize, 531 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); 532 if (unlikely(dma_mapping_error(pfvf->dev, *dma))) { 533 page_frag_free(buf); 534 return -ENOMEM; 535 } 536 537 return 0; 538 } 539 540 static int otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 541 dma_addr_t *dma) 542 { 543 int ret; 544 545 local_bh_disable(); 546 ret = __otx2_alloc_rbuf(pfvf, pool, dma); 547 local_bh_enable(); 548 return ret; 549 } 550 551 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 552 dma_addr_t *dma) 553 { 554 if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) { 555 struct refill_work *work; 556 struct delayed_work *dwork; 557 558 work = &pfvf->refill_wrk[cq->cq_idx]; 559 dwork = &work->pool_refill_work; 560 /* Schedule a task if no other task is running */ 561 if (!cq->refill_task_sched) { 562 cq->refill_task_sched = true; 563 schedule_delayed_work(dwork, 564 msecs_to_jiffies(100)); 565 } 566 return -ENOMEM; 567 } 568 return 0; 569 } 570 571 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq) 572 { 573 struct otx2_nic *pfvf = netdev_priv(netdev); 574 575 schedule_work(&pfvf->reset_task); 576 } 577 EXPORT_SYMBOL(otx2_tx_timeout); 578 579 void otx2_get_mac_from_af(struct net_device *netdev) 580 { 581 struct otx2_nic *pfvf = netdev_priv(netdev); 582 int err; 583 584 err = otx2_hw_get_mac_addr(pfvf, netdev); 585 if (err) 586 dev_warn(pfvf->dev, "Failed to read mac from hardware\n"); 587 588 /* If AF doesn't provide a valid MAC, generate a random one */ 589 if (!is_valid_ether_addr(netdev->dev_addr)) 590 eth_hw_addr_random(netdev); 591 } 592 EXPORT_SYMBOL(otx2_get_mac_from_af); 593 594 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl) 595 { 596 struct otx2_hw *hw = &pfvf->hw; 597 struct nix_txschq_config *req; 598 u64 schq, parent; 599 u64 dwrr_val; 600 601 dwrr_val = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 602 603 req = otx2_mbox_alloc_msg_nix_txschq_cfg(&pfvf->mbox); 604 if (!req) 605 return -ENOMEM; 606 607 req->lvl = lvl; 608 req->num_regs = 1; 609 610 schq = hw->txschq_list[lvl][0]; 611 /* Set topology e.t.c configuration */ 612 if (lvl == NIX_TXSCH_LVL_SMQ) { 613 req->reg[0] = NIX_AF_SMQX_CFG(schq); 614 req->regval[0] = ((u64)pfvf->tx_max_pktlen << 8) | OTX2_MIN_MTU; 615 req->regval[0] |= (0x20ULL << 51) | (0x80ULL << 39) | 616 (0x2ULL << 36); 617 req->num_regs++; 618 /* MDQ config */ 619 parent = hw->txschq_list[NIX_TXSCH_LVL_TL4][0]; 620 req->reg[1] = NIX_AF_MDQX_PARENT(schq); 621 req->regval[1] = parent << 16; 622 req->num_regs++; 623 /* Set DWRR quantum */ 624 req->reg[2] = NIX_AF_MDQX_SCHEDULE(schq); 625 req->regval[2] = dwrr_val; 626 } else if (lvl == NIX_TXSCH_LVL_TL4) { 627 parent = hw->txschq_list[NIX_TXSCH_LVL_TL3][0]; 628 req->reg[0] = NIX_AF_TL4X_PARENT(schq); 629 req->regval[0] = parent << 16; 630 req->num_regs++; 631 req->reg[1] = NIX_AF_TL4X_SCHEDULE(schq); 632 req->regval[1] = dwrr_val; 633 } else if (lvl == NIX_TXSCH_LVL_TL3) { 634 parent = hw->txschq_list[NIX_TXSCH_LVL_TL2][0]; 635 req->reg[0] = NIX_AF_TL3X_PARENT(schq); 636 req->regval[0] = parent << 16; 637 req->num_regs++; 638 req->reg[1] = NIX_AF_TL3X_SCHEDULE(schq); 639 req->regval[1] = dwrr_val; 640 } else if (lvl == NIX_TXSCH_LVL_TL2) { 641 parent = hw->txschq_list[NIX_TXSCH_LVL_TL1][0]; 642 req->reg[0] = NIX_AF_TL2X_PARENT(schq); 643 req->regval[0] = parent << 16; 644 645 req->num_regs++; 646 req->reg[1] = NIX_AF_TL2X_SCHEDULE(schq); 647 req->regval[1] = TXSCH_TL1_DFLT_RR_PRIO << 24 | dwrr_val; 648 649 req->num_regs++; 650 req->reg[2] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); 651 /* Enable this queue and backpressure */ 652 req->regval[2] = BIT_ULL(13) | BIT_ULL(12); 653 654 } else if (lvl == NIX_TXSCH_LVL_TL1) { 655 /* Default config for TL1. 656 * For VF this is always ignored. 657 */ 658 659 /* On CN10K, if RR_WEIGHT is greater than 16384, HW will 660 * clip it to 16384, so configuring a 24bit max value 661 * will work on both OTx2 and CN10K. 662 */ 663 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq); 664 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM; 665 666 req->num_regs++; 667 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq); 668 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1); 669 670 req->num_regs++; 671 req->reg[2] = NIX_AF_TL1X_CIR(schq); 672 req->regval[2] = 0; 673 } 674 675 return otx2_sync_mbox_msg(&pfvf->mbox); 676 } 677 678 int otx2_txsch_alloc(struct otx2_nic *pfvf) 679 { 680 struct nix_txsch_alloc_req *req; 681 int lvl; 682 683 /* Get memory to put this msg */ 684 req = otx2_mbox_alloc_msg_nix_txsch_alloc(&pfvf->mbox); 685 if (!req) 686 return -ENOMEM; 687 688 /* Request one schq per level */ 689 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 690 req->schq[lvl] = 1; 691 692 return otx2_sync_mbox_msg(&pfvf->mbox); 693 } 694 695 int otx2_txschq_stop(struct otx2_nic *pfvf) 696 { 697 struct nix_txsch_free_req *free_req; 698 int lvl, schq, err; 699 700 mutex_lock(&pfvf->mbox.lock); 701 /* Free the transmit schedulers */ 702 free_req = otx2_mbox_alloc_msg_nix_txsch_free(&pfvf->mbox); 703 if (!free_req) { 704 mutex_unlock(&pfvf->mbox.lock); 705 return -ENOMEM; 706 } 707 708 free_req->flags = TXSCHQ_FREE_ALL; 709 err = otx2_sync_mbox_msg(&pfvf->mbox); 710 mutex_unlock(&pfvf->mbox.lock); 711 712 /* Clear the txschq list */ 713 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 714 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) 715 pfvf->hw.txschq_list[lvl][schq] = 0; 716 } 717 return err; 718 } 719 720 void otx2_sqb_flush(struct otx2_nic *pfvf) 721 { 722 int qidx, sqe_tail, sqe_head; 723 u64 incr, *ptr, val; 724 int timeout = 1000; 725 726 ptr = (u64 *)otx2_get_regaddr(pfvf, NIX_LF_SQ_OP_STATUS); 727 for (qidx = 0; qidx < pfvf->hw.tot_tx_queues; qidx++) { 728 incr = (u64)qidx << 32; 729 while (timeout) { 730 val = otx2_atomic64_add(incr, ptr); 731 sqe_head = (val >> 20) & 0x3F; 732 sqe_tail = (val >> 28) & 0x3F; 733 if (sqe_head == sqe_tail) 734 break; 735 usleep_range(1, 3); 736 timeout--; 737 } 738 } 739 } 740 741 /* RED and drop levels of CQ on packet reception. 742 * For CQ level is measure of emptiness ( 0x0 = full, 255 = empty). 743 */ 744 #define RQ_PASS_LVL_CQ(skid, qsize) ((((skid) + 16) * 256) / (qsize)) 745 #define RQ_DROP_LVL_CQ(skid, qsize) (((skid) * 256) / (qsize)) 746 747 /* RED and drop levels of AURA for packet reception. 748 * For AURA level is measure of fullness (0x0 = empty, 255 = full). 749 * Eg: For RQ length 1K, for pass/drop level 204/230. 750 * RED accepts pkts if free pointers > 102 & <= 205. 751 * Drops pkts if free pointers < 102. 752 */ 753 #define RQ_BP_LVL_AURA (255 - ((85 * 256) / 100)) /* BP when 85% is full */ 754 #define RQ_PASS_LVL_AURA (255 - ((95 * 256) / 100)) /* RED when 95% is full */ 755 #define RQ_DROP_LVL_AURA (255 - ((99 * 256) / 100)) /* Drop when 99% is full */ 756 757 static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura) 758 { 759 struct otx2_qset *qset = &pfvf->qset; 760 struct nix_aq_enq_req *aq; 761 762 /* Get memory to put this msg */ 763 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 764 if (!aq) 765 return -ENOMEM; 766 767 aq->rq.cq = qidx; 768 aq->rq.ena = 1; 769 aq->rq.pb_caching = 1; 770 aq->rq.lpb_aura = lpb_aura; /* Use large packet buffer aura */ 771 aq->rq.lpb_sizem1 = (DMA_BUFFER_LEN(pfvf->rbsize) / 8) - 1; 772 aq->rq.xqe_imm_size = 0; /* Copying of packet to CQE not needed */ 773 aq->rq.flow_tagw = 32; /* Copy full 32bit flow_tag to CQE header */ 774 aq->rq.qint_idx = 0; 775 aq->rq.lpb_drop_ena = 1; /* Enable RED dropping for AURA */ 776 aq->rq.xqe_drop_ena = 1; /* Enable RED dropping for CQ/SSO */ 777 aq->rq.xqe_pass = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 778 aq->rq.xqe_drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 779 aq->rq.lpb_aura_pass = RQ_PASS_LVL_AURA; 780 aq->rq.lpb_aura_drop = RQ_DROP_LVL_AURA; 781 782 /* Fill AQ info */ 783 aq->qidx = qidx; 784 aq->ctype = NIX_AQ_CTYPE_RQ; 785 aq->op = NIX_AQ_INSTOP_INIT; 786 787 return otx2_sync_mbox_msg(&pfvf->mbox); 788 } 789 790 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 791 { 792 struct otx2_nic *pfvf = dev; 793 struct otx2_snd_queue *sq; 794 struct nix_aq_enq_req *aq; 795 796 sq = &pfvf->qset.sq[qidx]; 797 sq->lmt_addr = (__force u64 *)(pfvf->reg_base + LMT_LF_LMTLINEX(qidx)); 798 /* Get memory to put this msg */ 799 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 800 if (!aq) 801 return -ENOMEM; 802 803 aq->sq.cq = pfvf->hw.rx_queues + qidx; 804 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 805 aq->sq.cq_ena = 1; 806 aq->sq.ena = 1; 807 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 808 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 809 aq->sq.smq_rr_quantum = mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); 810 aq->sq.default_chan = pfvf->hw.tx_chan_base; 811 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 812 aq->sq.sqb_aura = sqb_aura; 813 aq->sq.sq_int_ena = NIX_SQINT_BITS; 814 aq->sq.qint_idx = 0; 815 /* Due pipelining impact minimum 2000 unused SQ CQE's 816 * need to maintain to avoid CQ overflow. 817 */ 818 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 819 820 /* Fill AQ info */ 821 aq->qidx = qidx; 822 aq->ctype = NIX_AQ_CTYPE_SQ; 823 aq->op = NIX_AQ_INSTOP_INIT; 824 825 return otx2_sync_mbox_msg(&pfvf->mbox); 826 } 827 828 static int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) 829 { 830 struct otx2_qset *qset = &pfvf->qset; 831 struct otx2_snd_queue *sq; 832 struct otx2_pool *pool; 833 int err; 834 835 pool = &pfvf->qset.pool[sqb_aura]; 836 sq = &qset->sq[qidx]; 837 sq->sqe_size = NIX_SQESZ_W16 ? 64 : 128; 838 sq->sqe_cnt = qset->sqe_cnt; 839 840 err = qmem_alloc(pfvf->dev, &sq->sqe, 1, sq->sqe_size); 841 if (err) 842 return err; 843 844 if (qidx < pfvf->hw.tx_queues) { 845 err = qmem_alloc(pfvf->dev, &sq->tso_hdrs, qset->sqe_cnt, 846 TSO_HEADER_SIZE); 847 if (err) 848 return err; 849 } 850 851 sq->sqe_base = sq->sqe->base; 852 sq->sg = kcalloc(qset->sqe_cnt, sizeof(struct sg_list), GFP_KERNEL); 853 if (!sq->sg) 854 return -ENOMEM; 855 856 if (pfvf->ptp && qidx < pfvf->hw.tx_queues) { 857 err = qmem_alloc(pfvf->dev, &sq->timestamps, qset->sqe_cnt, 858 sizeof(*sq->timestamps)); 859 if (err) 860 return err; 861 } 862 863 sq->head = 0; 864 sq->sqe_per_sqb = (pfvf->hw.sqb_size / sq->sqe_size) - 1; 865 sq->num_sqbs = (qset->sqe_cnt + sq->sqe_per_sqb) / sq->sqe_per_sqb; 866 /* Set SQE threshold to 10% of total SQEs */ 867 sq->sqe_thresh = ((sq->num_sqbs * sq->sqe_per_sqb) * 10) / 100; 868 sq->aura_id = sqb_aura; 869 sq->aura_fc_addr = pool->fc_addr->base; 870 sq->io_addr = (__force u64)otx2_get_regaddr(pfvf, NIX_LF_OP_SENDX(0)); 871 872 sq->stats.bytes = 0; 873 sq->stats.pkts = 0; 874 875 return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); 876 877 } 878 879 static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx) 880 { 881 struct otx2_qset *qset = &pfvf->qset; 882 int err, pool_id, non_xdp_queues; 883 struct nix_aq_enq_req *aq; 884 struct otx2_cq_queue *cq; 885 886 cq = &qset->cq[qidx]; 887 cq->cq_idx = qidx; 888 non_xdp_queues = pfvf->hw.rx_queues + pfvf->hw.tx_queues; 889 if (qidx < pfvf->hw.rx_queues) { 890 cq->cq_type = CQ_RX; 891 cq->cint_idx = qidx; 892 cq->cqe_cnt = qset->rqe_cnt; 893 if (pfvf->xdp_prog) 894 xdp_rxq_info_reg(&cq->xdp_rxq, pfvf->netdev, qidx, 0); 895 } else if (qidx < non_xdp_queues) { 896 cq->cq_type = CQ_TX; 897 cq->cint_idx = qidx - pfvf->hw.rx_queues; 898 cq->cqe_cnt = qset->sqe_cnt; 899 } else { 900 cq->cq_type = CQ_XDP; 901 cq->cint_idx = qidx - non_xdp_queues; 902 cq->cqe_cnt = qset->sqe_cnt; 903 } 904 cq->cqe_size = pfvf->qset.xqe_size; 905 906 /* Allocate memory for CQEs */ 907 err = qmem_alloc(pfvf->dev, &cq->cqe, cq->cqe_cnt, cq->cqe_size); 908 if (err) 909 return err; 910 911 /* Save CQE CPU base for faster reference */ 912 cq->cqe_base = cq->cqe->base; 913 /* In case where all RQs auras point to single pool, 914 * all CQs receive buffer pool also point to same pool. 915 */ 916 pool_id = ((cq->cq_type == CQ_RX) && 917 (pfvf->hw.rqpool_cnt != pfvf->hw.rx_queues)) ? 0 : qidx; 918 cq->rbpool = &qset->pool[pool_id]; 919 cq->refill_task_sched = false; 920 921 /* Get memory to put this msg */ 922 aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); 923 if (!aq) 924 return -ENOMEM; 925 926 aq->cq.ena = 1; 927 aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4); 928 aq->cq.caching = 1; 929 aq->cq.base = cq->cqe->iova; 930 aq->cq.cint_idx = cq->cint_idx; 931 aq->cq.cq_err_int_ena = NIX_CQERRINT_BITS; 932 aq->cq.qint_idx = 0; 933 aq->cq.avg_level = 255; 934 935 if (qidx < pfvf->hw.rx_queues) { 936 aq->cq.drop = RQ_DROP_LVL_CQ(pfvf->hw.rq_skid, cq->cqe_cnt); 937 aq->cq.drop_ena = 1; 938 939 if (!is_otx2_lbkvf(pfvf->pdev)) { 940 /* Enable receive CQ backpressure */ 941 aq->cq.bp_ena = 1; 942 #ifdef CONFIG_DCB 943 aq->cq.bpid = pfvf->bpid[pfvf->queue_to_pfc_map[qidx]]; 944 #else 945 aq->cq.bpid = pfvf->bpid[0]; 946 #endif 947 948 /* Set backpressure level is same as cq pass level */ 949 aq->cq.bp = RQ_PASS_LVL_CQ(pfvf->hw.rq_skid, qset->rqe_cnt); 950 } 951 } 952 953 /* Fill AQ info */ 954 aq->qidx = qidx; 955 aq->ctype = NIX_AQ_CTYPE_CQ; 956 aq->op = NIX_AQ_INSTOP_INIT; 957 958 return otx2_sync_mbox_msg(&pfvf->mbox); 959 } 960 961 static void otx2_pool_refill_task(struct work_struct *work) 962 { 963 struct otx2_cq_queue *cq; 964 struct otx2_pool *rbpool; 965 struct refill_work *wrk; 966 int qidx, free_ptrs = 0; 967 struct otx2_nic *pfvf; 968 dma_addr_t bufptr; 969 970 wrk = container_of(work, struct refill_work, pool_refill_work.work); 971 pfvf = wrk->pf; 972 qidx = wrk - pfvf->refill_wrk; 973 cq = &pfvf->qset.cq[qidx]; 974 rbpool = cq->rbpool; 975 free_ptrs = cq->pool_ptrs; 976 977 while (cq->pool_ptrs) { 978 if (otx2_alloc_rbuf(pfvf, rbpool, &bufptr)) { 979 /* Schedule a WQ if we fails to free atleast half of the 980 * pointers else enable napi for this RQ. 981 */ 982 if (!((free_ptrs - cq->pool_ptrs) > free_ptrs / 2)) { 983 struct delayed_work *dwork; 984 985 dwork = &wrk->pool_refill_work; 986 schedule_delayed_work(dwork, 987 msecs_to_jiffies(100)); 988 } else { 989 cq->refill_task_sched = false; 990 } 991 return; 992 } 993 pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + OTX2_HEAD_ROOM); 994 cq->pool_ptrs--; 995 } 996 cq->refill_task_sched = false; 997 } 998 999 int otx2_config_nix_queues(struct otx2_nic *pfvf) 1000 { 1001 int qidx, err; 1002 1003 /* Initialize RX queues */ 1004 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 1005 u16 lpb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 1006 1007 err = otx2_rq_init(pfvf, qidx, lpb_aura); 1008 if (err) 1009 return err; 1010 } 1011 1012 /* Initialize TX queues */ 1013 for (qidx = 0; qidx < pfvf->hw.tot_tx_queues; qidx++) { 1014 u16 sqb_aura = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1015 1016 err = otx2_sq_init(pfvf, qidx, sqb_aura); 1017 if (err) 1018 return err; 1019 } 1020 1021 /* Initialize completion queues */ 1022 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1023 err = otx2_cq_init(pfvf, qidx); 1024 if (err) 1025 return err; 1026 } 1027 1028 pfvf->cq_op_addr = (__force u64 *)otx2_get_regaddr(pfvf, 1029 NIX_LF_CQ_OP_STATUS); 1030 1031 /* Initialize work queue for receive buffer refill */ 1032 pfvf->refill_wrk = devm_kcalloc(pfvf->dev, pfvf->qset.cq_cnt, 1033 sizeof(struct refill_work), GFP_KERNEL); 1034 if (!pfvf->refill_wrk) 1035 return -ENOMEM; 1036 1037 for (qidx = 0; qidx < pfvf->qset.cq_cnt; qidx++) { 1038 pfvf->refill_wrk[qidx].pf = pfvf; 1039 INIT_DELAYED_WORK(&pfvf->refill_wrk[qidx].pool_refill_work, 1040 otx2_pool_refill_task); 1041 } 1042 return 0; 1043 } 1044 1045 int otx2_config_nix(struct otx2_nic *pfvf) 1046 { 1047 struct nix_lf_alloc_req *nixlf; 1048 struct nix_lf_alloc_rsp *rsp; 1049 int err; 1050 1051 pfvf->qset.xqe_size = pfvf->hw.xqe_size; 1052 1053 /* Get memory to put this msg */ 1054 nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox); 1055 if (!nixlf) 1056 return -ENOMEM; 1057 1058 /* Set RQ/SQ/CQ counts */ 1059 nixlf->rq_cnt = pfvf->hw.rx_queues; 1060 nixlf->sq_cnt = pfvf->hw.tot_tx_queues; 1061 nixlf->cq_cnt = pfvf->qset.cq_cnt; 1062 nixlf->rss_sz = MAX_RSS_INDIR_TBL_SIZE; 1063 nixlf->rss_grps = MAX_RSS_GROUPS; 1064 nixlf->xqe_sz = pfvf->hw.xqe_size == 128 ? NIX_XQESZ_W16 : NIX_XQESZ_W64; 1065 /* We don't know absolute NPA LF idx attached. 1066 * AF will replace 'RVU_DEFAULT_PF_FUNC' with 1067 * NPA LF attached to this RVU PF/VF. 1068 */ 1069 nixlf->npa_func = RVU_DEFAULT_PF_FUNC; 1070 /* Disable alignment pad, enable L2 length check, 1071 * enable L4 TCP/UDP checksum verification. 1072 */ 1073 nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37); 1074 1075 err = otx2_sync_mbox_msg(&pfvf->mbox); 1076 if (err) 1077 return err; 1078 1079 rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, 1080 &nixlf->hdr); 1081 if (IS_ERR(rsp)) 1082 return PTR_ERR(rsp); 1083 1084 if (rsp->qints < 1) 1085 return -ENXIO; 1086 1087 return rsp->hdr.rc; 1088 } 1089 1090 void otx2_sq_free_sqbs(struct otx2_nic *pfvf) 1091 { 1092 struct otx2_qset *qset = &pfvf->qset; 1093 struct otx2_hw *hw = &pfvf->hw; 1094 struct otx2_snd_queue *sq; 1095 int sqb, qidx; 1096 u64 iova, pa; 1097 1098 for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) { 1099 sq = &qset->sq[qidx]; 1100 if (!sq->sqb_ptrs) 1101 continue; 1102 for (sqb = 0; sqb < sq->sqb_count; sqb++) { 1103 if (!sq->sqb_ptrs[sqb]) 1104 continue; 1105 iova = sq->sqb_ptrs[sqb]; 1106 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1107 dma_unmap_page_attrs(pfvf->dev, iova, hw->sqb_size, 1108 DMA_FROM_DEVICE, 1109 DMA_ATTR_SKIP_CPU_SYNC); 1110 put_page(virt_to_page(phys_to_virt(pa))); 1111 } 1112 sq->sqb_count = 0; 1113 } 1114 } 1115 1116 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type) 1117 { 1118 int pool_id, pool_start = 0, pool_end = 0, size = 0; 1119 u64 iova, pa; 1120 1121 if (type == AURA_NIX_SQ) { 1122 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1123 pool_end = pool_start + pfvf->hw.sqpool_cnt; 1124 size = pfvf->hw.sqb_size; 1125 } 1126 if (type == AURA_NIX_RQ) { 1127 pool_start = otx2_get_pool_idx(pfvf, type, 0); 1128 pool_end = pfvf->hw.rqpool_cnt; 1129 size = pfvf->rbsize; 1130 } 1131 1132 /* Free SQB and RQB pointers from the aura pool */ 1133 for (pool_id = pool_start; pool_id < pool_end; pool_id++) { 1134 iova = otx2_aura_allocptr(pfvf, pool_id); 1135 while (iova) { 1136 if (type == AURA_NIX_RQ) 1137 iova -= OTX2_HEAD_ROOM; 1138 1139 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1140 dma_unmap_page_attrs(pfvf->dev, iova, size, 1141 DMA_FROM_DEVICE, 1142 DMA_ATTR_SKIP_CPU_SYNC); 1143 put_page(virt_to_page(phys_to_virt(pa))); 1144 iova = otx2_aura_allocptr(pfvf, pool_id); 1145 } 1146 } 1147 } 1148 1149 void otx2_aura_pool_free(struct otx2_nic *pfvf) 1150 { 1151 struct otx2_pool *pool; 1152 int pool_id; 1153 1154 if (!pfvf->qset.pool) 1155 return; 1156 1157 for (pool_id = 0; pool_id < pfvf->hw.pool_cnt; pool_id++) { 1158 pool = &pfvf->qset.pool[pool_id]; 1159 qmem_free(pfvf->dev, pool->stack); 1160 qmem_free(pfvf->dev, pool->fc_addr); 1161 } 1162 devm_kfree(pfvf->dev, pfvf->qset.pool); 1163 pfvf->qset.pool = NULL; 1164 } 1165 1166 static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, 1167 int pool_id, int numptrs) 1168 { 1169 struct npa_aq_enq_req *aq; 1170 struct otx2_pool *pool; 1171 int err; 1172 1173 pool = &pfvf->qset.pool[pool_id]; 1174 1175 /* Allocate memory for HW to update Aura count. 1176 * Alloc one cache line, so that it fits all FC_STYPE modes. 1177 */ 1178 if (!pool->fc_addr) { 1179 err = qmem_alloc(pfvf->dev, &pool->fc_addr, 1, OTX2_ALIGN); 1180 if (err) 1181 return err; 1182 } 1183 1184 /* Initialize this aura's context via AF */ 1185 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1186 if (!aq) { 1187 /* Shared mbox memory buffer is full, flush it and retry */ 1188 err = otx2_sync_mbox_msg(&pfvf->mbox); 1189 if (err) 1190 return err; 1191 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1192 if (!aq) 1193 return -ENOMEM; 1194 } 1195 1196 aq->aura_id = aura_id; 1197 /* Will be filled by AF with correct pool context address */ 1198 aq->aura.pool_addr = pool_id; 1199 aq->aura.pool_caching = 1; 1200 aq->aura.shift = ilog2(numptrs) - 8; 1201 aq->aura.count = numptrs; 1202 aq->aura.limit = numptrs; 1203 aq->aura.avg_level = 255; 1204 aq->aura.ena = 1; 1205 aq->aura.fc_ena = 1; 1206 aq->aura.fc_addr = pool->fc_addr->iova; 1207 aq->aura.fc_hyst_bits = 0; /* Store count on all updates */ 1208 1209 /* Enable backpressure for RQ aura */ 1210 if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { 1211 aq->aura.bp_ena = 0; 1212 /* If NIX1 LF is attached then specify NIX1_RX. 1213 * 1214 * Below NPA_AURA_S[BP_ENA] is set according to the 1215 * NPA_BPINTF_E enumeration given as: 1216 * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so 1217 * NIX0_RX is 0x0 + 0*0x1 = 0 1218 * NIX1_RX is 0x0 + 1*0x1 = 1 1219 * But in HRM it is given that 1220 * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to 1221 * NIX-RX based on [BP] level. One bit per NIX-RX; index 1222 * enumerated by NPA_BPINTF_E." 1223 */ 1224 if (pfvf->nix_blkaddr == BLKADDR_NIX1) 1225 aq->aura.bp_ena = 1; 1226 #ifdef CONFIG_DCB 1227 aq->aura.nix0_bpid = pfvf->bpid[pfvf->queue_to_pfc_map[aura_id]]; 1228 #else 1229 aq->aura.nix0_bpid = pfvf->bpid[0]; 1230 #endif 1231 1232 /* Set backpressure level for RQ's Aura */ 1233 aq->aura.bp = RQ_BP_LVL_AURA; 1234 } 1235 1236 /* Fill AQ info */ 1237 aq->ctype = NPA_AQ_CTYPE_AURA; 1238 aq->op = NPA_AQ_INSTOP_INIT; 1239 1240 return 0; 1241 } 1242 1243 static int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, 1244 int stack_pages, int numptrs, int buf_size) 1245 { 1246 struct npa_aq_enq_req *aq; 1247 struct otx2_pool *pool; 1248 int err; 1249 1250 pool = &pfvf->qset.pool[pool_id]; 1251 /* Alloc memory for stack which is used to store buffer pointers */ 1252 err = qmem_alloc(pfvf->dev, &pool->stack, 1253 stack_pages, pfvf->hw.stack_pg_bytes); 1254 if (err) 1255 return err; 1256 1257 pool->rbsize = buf_size; 1258 1259 /* Initialize this pool's context via AF */ 1260 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1261 if (!aq) { 1262 /* Shared mbox memory buffer is full, flush it and retry */ 1263 err = otx2_sync_mbox_msg(&pfvf->mbox); 1264 if (err) { 1265 qmem_free(pfvf->dev, pool->stack); 1266 return err; 1267 } 1268 aq = otx2_mbox_alloc_msg_npa_aq_enq(&pfvf->mbox); 1269 if (!aq) { 1270 qmem_free(pfvf->dev, pool->stack); 1271 return -ENOMEM; 1272 } 1273 } 1274 1275 aq->aura_id = pool_id; 1276 aq->pool.stack_base = pool->stack->iova; 1277 aq->pool.stack_caching = 1; 1278 aq->pool.ena = 1; 1279 aq->pool.buf_size = buf_size / 128; 1280 aq->pool.stack_max_pages = stack_pages; 1281 aq->pool.shift = ilog2(numptrs) - 8; 1282 aq->pool.ptr_start = 0; 1283 aq->pool.ptr_end = ~0ULL; 1284 1285 /* Fill AQ info */ 1286 aq->ctype = NPA_AQ_CTYPE_POOL; 1287 aq->op = NPA_AQ_INSTOP_INIT; 1288 1289 return 0; 1290 } 1291 1292 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf) 1293 { 1294 int qidx, pool_id, stack_pages, num_sqbs; 1295 struct otx2_qset *qset = &pfvf->qset; 1296 struct otx2_hw *hw = &pfvf->hw; 1297 struct otx2_snd_queue *sq; 1298 struct otx2_pool *pool; 1299 dma_addr_t bufptr; 1300 int err, ptr; 1301 1302 /* Calculate number of SQBs needed. 1303 * 1304 * For a 128byte SQE, and 4K size SQB, 31 SQEs will fit in one SQB. 1305 * Last SQE is used for pointing to next SQB. 1306 */ 1307 num_sqbs = (hw->sqb_size / 128) - 1; 1308 num_sqbs = (qset->sqe_cnt + num_sqbs) / num_sqbs; 1309 1310 /* Get no of stack pages needed */ 1311 stack_pages = 1312 (num_sqbs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1313 1314 for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) { 1315 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1316 /* Initialize aura context */ 1317 err = otx2_aura_init(pfvf, pool_id, pool_id, num_sqbs); 1318 if (err) 1319 goto fail; 1320 1321 /* Initialize pool context */ 1322 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1323 num_sqbs, hw->sqb_size); 1324 if (err) 1325 goto fail; 1326 } 1327 1328 /* Flush accumulated messages */ 1329 err = otx2_sync_mbox_msg(&pfvf->mbox); 1330 if (err) 1331 goto fail; 1332 1333 /* Allocate pointers and free them to aura/pool */ 1334 for (qidx = 0; qidx < hw->tot_tx_queues; qidx++) { 1335 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_SQ, qidx); 1336 pool = &pfvf->qset.pool[pool_id]; 1337 1338 sq = &qset->sq[qidx]; 1339 sq->sqb_count = 0; 1340 sq->sqb_ptrs = kcalloc(num_sqbs, sizeof(*sq->sqb_ptrs), GFP_KERNEL); 1341 if (!sq->sqb_ptrs) 1342 return -ENOMEM; 1343 1344 for (ptr = 0; ptr < num_sqbs; ptr++) { 1345 if (otx2_alloc_rbuf(pfvf, pool, &bufptr)) 1346 return -ENOMEM; 1347 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); 1348 sq->sqb_ptrs[sq->sqb_count++] = (u64)bufptr; 1349 } 1350 } 1351 1352 return 0; 1353 fail: 1354 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1355 otx2_aura_pool_free(pfvf); 1356 return err; 1357 } 1358 1359 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf) 1360 { 1361 struct otx2_hw *hw = &pfvf->hw; 1362 int stack_pages, pool_id, rq; 1363 struct otx2_pool *pool; 1364 int err, ptr, num_ptrs; 1365 dma_addr_t bufptr; 1366 1367 num_ptrs = pfvf->qset.rqe_cnt; 1368 1369 stack_pages = 1370 (num_ptrs + hw->stack_pg_ptrs - 1) / hw->stack_pg_ptrs; 1371 1372 for (rq = 0; rq < hw->rx_queues; rq++) { 1373 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, rq); 1374 /* Initialize aura context */ 1375 err = otx2_aura_init(pfvf, pool_id, pool_id, num_ptrs); 1376 if (err) 1377 goto fail; 1378 } 1379 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1380 err = otx2_pool_init(pfvf, pool_id, stack_pages, 1381 num_ptrs, pfvf->rbsize); 1382 if (err) 1383 goto fail; 1384 } 1385 1386 /* Flush accumulated messages */ 1387 err = otx2_sync_mbox_msg(&pfvf->mbox); 1388 if (err) 1389 goto fail; 1390 1391 /* Allocate pointers and free them to aura/pool */ 1392 for (pool_id = 0; pool_id < hw->rqpool_cnt; pool_id++) { 1393 pool = &pfvf->qset.pool[pool_id]; 1394 for (ptr = 0; ptr < num_ptrs; ptr++) { 1395 if (otx2_alloc_rbuf(pfvf, pool, &bufptr)) 1396 return -ENOMEM; 1397 pfvf->hw_ops->aura_freeptr(pfvf, pool_id, 1398 bufptr + OTX2_HEAD_ROOM); 1399 } 1400 } 1401 1402 return 0; 1403 fail: 1404 otx2_mbox_reset(&pfvf->mbox.mbox, 0); 1405 otx2_aura_pool_free(pfvf); 1406 return err; 1407 } 1408 1409 int otx2_config_npa(struct otx2_nic *pfvf) 1410 { 1411 struct otx2_qset *qset = &pfvf->qset; 1412 struct npa_lf_alloc_req *npalf; 1413 struct otx2_hw *hw = &pfvf->hw; 1414 int aura_cnt; 1415 1416 /* Pool - Stack of free buffer pointers 1417 * Aura - Alloc/frees pointers from/to pool for NIX DMA. 1418 */ 1419 1420 if (!hw->pool_cnt) 1421 return -EINVAL; 1422 1423 qset->pool = devm_kcalloc(pfvf->dev, hw->pool_cnt, 1424 sizeof(struct otx2_pool), GFP_KERNEL); 1425 if (!qset->pool) 1426 return -ENOMEM; 1427 1428 /* Get memory to put this msg */ 1429 npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox); 1430 if (!npalf) 1431 return -ENOMEM; 1432 1433 /* Set aura and pool counts */ 1434 npalf->nr_pools = hw->pool_cnt; 1435 aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt)); 1436 npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1; 1437 1438 return otx2_sync_mbox_msg(&pfvf->mbox); 1439 } 1440 1441 int otx2_detach_resources(struct mbox *mbox) 1442 { 1443 struct rsrc_detach *detach; 1444 1445 mutex_lock(&mbox->lock); 1446 detach = otx2_mbox_alloc_msg_detach_resources(mbox); 1447 if (!detach) { 1448 mutex_unlock(&mbox->lock); 1449 return -ENOMEM; 1450 } 1451 1452 /* detach all */ 1453 detach->partial = false; 1454 1455 /* Send detach request to AF */ 1456 otx2_mbox_msg_send(&mbox->mbox, 0); 1457 mutex_unlock(&mbox->lock); 1458 return 0; 1459 } 1460 EXPORT_SYMBOL(otx2_detach_resources); 1461 1462 int otx2_attach_npa_nix(struct otx2_nic *pfvf) 1463 { 1464 struct rsrc_attach *attach; 1465 struct msg_req *msix; 1466 int err; 1467 1468 mutex_lock(&pfvf->mbox.lock); 1469 /* Get memory to put this msg */ 1470 attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox); 1471 if (!attach) { 1472 mutex_unlock(&pfvf->mbox.lock); 1473 return -ENOMEM; 1474 } 1475 1476 attach->npalf = true; 1477 attach->nixlf = true; 1478 1479 /* Send attach request to AF */ 1480 err = otx2_sync_mbox_msg(&pfvf->mbox); 1481 if (err) { 1482 mutex_unlock(&pfvf->mbox.lock); 1483 return err; 1484 } 1485 1486 pfvf->nix_blkaddr = BLKADDR_NIX0; 1487 1488 /* If the platform has two NIX blocks then LF may be 1489 * allocated from NIX1. 1490 */ 1491 if (otx2_read64(pfvf, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_NIX1)) & 0x1FFULL) 1492 pfvf->nix_blkaddr = BLKADDR_NIX1; 1493 1494 /* Get NPA and NIX MSIX vector offsets */ 1495 msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox); 1496 if (!msix) { 1497 mutex_unlock(&pfvf->mbox.lock); 1498 return -ENOMEM; 1499 } 1500 1501 err = otx2_sync_mbox_msg(&pfvf->mbox); 1502 if (err) { 1503 mutex_unlock(&pfvf->mbox.lock); 1504 return err; 1505 } 1506 mutex_unlock(&pfvf->mbox.lock); 1507 1508 if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID || 1509 pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) { 1510 dev_err(pfvf->dev, 1511 "RVUPF: Invalid MSIX vector offset for NPA/NIX\n"); 1512 return -EINVAL; 1513 } 1514 1515 return 0; 1516 } 1517 EXPORT_SYMBOL(otx2_attach_npa_nix); 1518 1519 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa) 1520 { 1521 struct hwctx_disable_req *req; 1522 1523 mutex_lock(&mbox->lock); 1524 /* Request AQ to disable this context */ 1525 if (npa) 1526 req = otx2_mbox_alloc_msg_npa_hwctx_disable(mbox); 1527 else 1528 req = otx2_mbox_alloc_msg_nix_hwctx_disable(mbox); 1529 1530 if (!req) { 1531 mutex_unlock(&mbox->lock); 1532 return; 1533 } 1534 1535 req->ctype = type; 1536 1537 if (otx2_sync_mbox_msg(mbox)) 1538 dev_err(mbox->pfvf->dev, "%s failed to disable context\n", 1539 __func__); 1540 1541 mutex_unlock(&mbox->lock); 1542 } 1543 1544 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable) 1545 { 1546 struct nix_bp_cfg_req *req; 1547 1548 if (enable) 1549 req = otx2_mbox_alloc_msg_nix_bp_enable(&pfvf->mbox); 1550 else 1551 req = otx2_mbox_alloc_msg_nix_bp_disable(&pfvf->mbox); 1552 1553 if (!req) 1554 return -ENOMEM; 1555 1556 req->chan_base = 0; 1557 #ifdef CONFIG_DCB 1558 req->chan_cnt = pfvf->pfc_en ? IEEE_8021QAZ_MAX_TCS : 1; 1559 req->bpid_per_chan = pfvf->pfc_en ? 1 : 0; 1560 #else 1561 req->chan_cnt = 1; 1562 req->bpid_per_chan = 0; 1563 #endif 1564 1565 1566 return otx2_sync_mbox_msg(&pfvf->mbox); 1567 } 1568 EXPORT_SYMBOL(otx2_nix_config_bp); 1569 1570 /* Mbox message handlers */ 1571 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 1572 struct cgx_stats_rsp *rsp) 1573 { 1574 int id; 1575 1576 for (id = 0; id < CGX_RX_STATS_COUNT; id++) 1577 pfvf->hw.cgx_rx_stats[id] = rsp->rx_stats[id]; 1578 for (id = 0; id < CGX_TX_STATS_COUNT; id++) 1579 pfvf->hw.cgx_tx_stats[id] = rsp->tx_stats[id]; 1580 } 1581 1582 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 1583 struct cgx_fec_stats_rsp *rsp) 1584 { 1585 pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; 1586 pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; 1587 } 1588 1589 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 1590 struct nix_txsch_alloc_rsp *rsp) 1591 { 1592 int lvl, schq; 1593 1594 /* Setup transmit scheduler list */ 1595 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) 1596 for (schq = 0; schq < rsp->schq[lvl]; schq++) 1597 pf->hw.txschq_list[lvl][schq] = 1598 rsp->schq_list[lvl][schq]; 1599 } 1600 EXPORT_SYMBOL(mbox_handler_nix_txsch_alloc); 1601 1602 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 1603 struct npa_lf_alloc_rsp *rsp) 1604 { 1605 pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs; 1606 pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes; 1607 } 1608 EXPORT_SYMBOL(mbox_handler_npa_lf_alloc); 1609 1610 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 1611 struct nix_lf_alloc_rsp *rsp) 1612 { 1613 pfvf->hw.sqb_size = rsp->sqb_size; 1614 pfvf->hw.rx_chan_base = rsp->rx_chan_base; 1615 pfvf->hw.tx_chan_base = rsp->tx_chan_base; 1616 pfvf->hw.lso_tsov4_idx = rsp->lso_tsov4_idx; 1617 pfvf->hw.lso_tsov6_idx = rsp->lso_tsov6_idx; 1618 pfvf->hw.cgx_links = rsp->cgx_links; 1619 pfvf->hw.lbk_links = rsp->lbk_links; 1620 pfvf->hw.tx_link = rsp->tx_link; 1621 } 1622 EXPORT_SYMBOL(mbox_handler_nix_lf_alloc); 1623 1624 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 1625 struct msix_offset_rsp *rsp) 1626 { 1627 pfvf->hw.npa_msixoff = rsp->npa_msixoff; 1628 pfvf->hw.nix_msixoff = rsp->nix_msixoff; 1629 } 1630 EXPORT_SYMBOL(mbox_handler_msix_offset); 1631 1632 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 1633 struct nix_bp_cfg_rsp *rsp) 1634 { 1635 int chan, chan_id; 1636 1637 for (chan = 0; chan < rsp->chan_cnt; chan++) { 1638 chan_id = ((rsp->chan_bpid[chan] >> 10) & 0x7F); 1639 pfvf->bpid[chan_id] = rsp->chan_bpid[chan] & 0x3FF; 1640 } 1641 } 1642 EXPORT_SYMBOL(mbox_handler_nix_bp_enable); 1643 1644 void otx2_free_cints(struct otx2_nic *pfvf, int n) 1645 { 1646 struct otx2_qset *qset = &pfvf->qset; 1647 struct otx2_hw *hw = &pfvf->hw; 1648 int irq, qidx; 1649 1650 for (qidx = 0, irq = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1651 qidx < n; 1652 qidx++, irq++) { 1653 int vector = pci_irq_vector(pfvf->pdev, irq); 1654 1655 irq_set_affinity_hint(vector, NULL); 1656 free_cpumask_var(hw->affinity_mask[irq]); 1657 free_irq(vector, &qset->napi[qidx]); 1658 } 1659 } 1660 1661 void otx2_set_cints_affinity(struct otx2_nic *pfvf) 1662 { 1663 struct otx2_hw *hw = &pfvf->hw; 1664 int vec, cpu, irq, cint; 1665 1666 vec = hw->nix_msixoff + NIX_LF_CINT_VEC_START; 1667 cpu = cpumask_first(cpu_online_mask); 1668 1669 /* CQ interrupts */ 1670 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++, vec++) { 1671 if (!alloc_cpumask_var(&hw->affinity_mask[vec], GFP_KERNEL)) 1672 return; 1673 1674 cpumask_set_cpu(cpu, hw->affinity_mask[vec]); 1675 1676 irq = pci_irq_vector(pfvf->pdev, vec); 1677 irq_set_affinity_hint(irq, hw->affinity_mask[vec]); 1678 1679 cpu = cpumask_next(cpu, cpu_online_mask); 1680 if (unlikely(cpu >= nr_cpu_ids)) 1681 cpu = 0; 1682 } 1683 } 1684 1685 u16 otx2_get_max_mtu(struct otx2_nic *pfvf) 1686 { 1687 struct nix_hw_info *rsp; 1688 struct msg_req *req; 1689 u16 max_mtu; 1690 int rc; 1691 1692 mutex_lock(&pfvf->mbox.lock); 1693 1694 req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); 1695 if (!req) { 1696 rc = -ENOMEM; 1697 goto out; 1698 } 1699 1700 rc = otx2_sync_mbox_msg(&pfvf->mbox); 1701 if (!rc) { 1702 rsp = (struct nix_hw_info *) 1703 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 1704 1705 /* HW counts VLAN insertion bytes (8 for double tag) 1706 * irrespective of whether SQE is requesting to insert VLAN 1707 * in the packet or not. Hence these 8 bytes have to be 1708 * discounted from max packet size otherwise HW will throw 1709 * SMQ errors 1710 */ 1711 max_mtu = rsp->max_mtu - 8 - OTX2_ETH_HLEN; 1712 1713 /* Also save DWRR MTU, needed for DWRR weight calculation */ 1714 pfvf->hw.dwrr_mtu = rsp->rpm_dwrr_mtu; 1715 if (!pfvf->hw.dwrr_mtu) 1716 pfvf->hw.dwrr_mtu = 1; 1717 } 1718 1719 out: 1720 mutex_unlock(&pfvf->mbox.lock); 1721 if (rc) { 1722 dev_warn(pfvf->dev, 1723 "Failed to get MTU from hardware setting default value(1500)\n"); 1724 max_mtu = 1500; 1725 } 1726 return max_mtu; 1727 } 1728 EXPORT_SYMBOL(otx2_get_max_mtu); 1729 1730 int otx2_handle_ntuple_tc_features(struct net_device *netdev, netdev_features_t features) 1731 { 1732 netdev_features_t changed = features ^ netdev->features; 1733 struct otx2_nic *pfvf = netdev_priv(netdev); 1734 bool ntuple = !!(features & NETIF_F_NTUPLE); 1735 bool tc = !!(features & NETIF_F_HW_TC); 1736 1737 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1738 otx2_destroy_ntuple_flows(pfvf); 1739 1740 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1741 if (!pfvf->flow_cfg->max_flows) { 1742 netdev_err(netdev, 1743 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1744 return -EINVAL; 1745 } 1746 } 1747 1748 if ((changed & NETIF_F_HW_TC) && tc) { 1749 if (!pfvf->flow_cfg->max_flows) { 1750 netdev_err(netdev, 1751 "Can't enable TC, MCAM entries not allocated\n"); 1752 return -EINVAL; 1753 } 1754 } 1755 1756 if ((changed & NETIF_F_HW_TC) && !tc && 1757 pfvf->flow_cfg && pfvf->flow_cfg->nr_flows) { 1758 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1759 return -EBUSY; 1760 } 1761 1762 if ((changed & NETIF_F_NTUPLE) && ntuple && 1763 (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) { 1764 netdev_err(netdev, 1765 "Can't enable NTUPLE when TC is active, disable TC and retry\n"); 1766 return -EINVAL; 1767 } 1768 1769 if ((changed & NETIF_F_HW_TC) && tc && 1770 (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) { 1771 netdev_err(netdev, 1772 "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n"); 1773 return -EINVAL; 1774 } 1775 1776 return 0; 1777 } 1778 EXPORT_SYMBOL(otx2_handle_ntuple_tc_features); 1779 1780 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1781 int __weak \ 1782 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 1783 struct _req_type *req, \ 1784 struct _rsp_type *rsp) \ 1785 { \ 1786 /* Nothing to do here */ \ 1787 return 0; \ 1788 } \ 1789 EXPORT_SYMBOL(otx2_mbox_up_handler_ ## _fn_name); 1790 MBOX_UP_CGX_MESSAGES 1791 #undef M 1792