1 /* SPDX-License-Identifier: GPL-2.0 2 * Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 */ 6 7 #ifndef CN10K_H 8 #define CN10K_H 9 10 #include "otx2_common.h" 11 12 static inline int mtu_to_dwrr_weight(struct otx2_nic *pfvf, int mtu) 13 { 14 u32 weight; 15 16 /* On OTx2, since AF returns DWRR_MTU as '1', this logic 17 * will work on those silicons as well. 18 */ 19 weight = mtu / pfvf->hw.dwrr_mtu; 20 if (mtu % pfvf->hw.dwrr_mtu) 21 weight += 1; 22 23 return weight; 24 } 25 26 void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq); 27 void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx); 28 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 29 int cn10k_lmtst_init(struct otx2_nic *pfvf); 30 int cn10k_free_all_ipolicers(struct otx2_nic *pfvf); 31 int cn10k_alloc_matchall_ipolicer(struct otx2_nic *pfvf); 32 int cn10k_free_matchall_ipolicer(struct otx2_nic *pfvf); 33 int cn10k_set_matchall_ipolicer_rate(struct otx2_nic *pfvf, 34 u32 burst, u64 rate); 35 int cn10k_map_unmap_rq_policer(struct otx2_nic *pfvf, int rq_idx, 36 u16 policer, bool map); 37 int cn10k_alloc_leaf_profile(struct otx2_nic *pfvf, u16 *leaf); 38 int cn10k_set_ipolicer_rate(struct otx2_nic *pfvf, u16 profile, 39 u32 burst, u64 rate, bool pps); 40 int cn10k_free_leaf_profile(struct otx2_nic *pfvf, u16 leaf); 41 #endif /* CN10K_H */ 42