1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Physcial Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 */ 6 7 #include "cn10k.h" 8 #include "otx2_reg.h" 9 #include "otx2_struct.h" 10 11 static struct dev_hw_ops otx2_hw_ops = { 12 .sq_aq_init = otx2_sq_aq_init, 13 .sqe_flush = otx2_sqe_flush, 14 .aura_freeptr = otx2_aura_freeptr, 15 .refill_pool_ptrs = otx2_refill_pool_ptrs, 16 }; 17 18 static struct dev_hw_ops cn10k_hw_ops = { 19 .sq_aq_init = cn10k_sq_aq_init, 20 .sqe_flush = cn10k_sqe_flush, 21 .aura_freeptr = cn10k_aura_freeptr, 22 .refill_pool_ptrs = cn10k_refill_pool_ptrs, 23 }; 24 25 int cn10k_lmtst_init(struct otx2_nic *pfvf) 26 { 27 28 struct lmtst_tbl_setup_req *req; 29 int qcount, err; 30 31 if (!test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) { 32 pfvf->hw_ops = &otx2_hw_ops; 33 return 0; 34 } 35 36 pfvf->hw_ops = &cn10k_hw_ops; 37 qcount = pfvf->hw.max_queues; 38 /* LMTST lines allocation 39 * qcount = num_online_cpus(); 40 * NPA = TX + RX + XDP. 41 * NIX = TX * 32 (For Burst SQE flush). 42 */ 43 pfvf->tot_lmt_lines = (qcount * 3) + (qcount * 32); 44 pfvf->npa_lmt_lines = qcount * 3; 45 pfvf->nix_lmt_size = LMT_BURST_SIZE * LMT_LINE_SIZE; 46 47 mutex_lock(&pfvf->mbox.lock); 48 req = otx2_mbox_alloc_msg_lmtst_tbl_setup(&pfvf->mbox); 49 if (!req) { 50 mutex_unlock(&pfvf->mbox.lock); 51 return -ENOMEM; 52 } 53 54 req->use_local_lmt_region = true; 55 56 err = qmem_alloc(pfvf->dev, &pfvf->dync_lmt, pfvf->tot_lmt_lines, 57 LMT_LINE_SIZE); 58 if (err) { 59 mutex_unlock(&pfvf->mbox.lock); 60 return err; 61 } 62 pfvf->hw.lmt_base = (u64 *)pfvf->dync_lmt->base; 63 req->lmt_iova = (u64)pfvf->dync_lmt->iova; 64 65 err = otx2_sync_mbox_msg(&pfvf->mbox); 66 mutex_unlock(&pfvf->mbox.lock); 67 68 return 0; 69 } 70 EXPORT_SYMBOL(cn10k_lmtst_init); 71 72 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 73 { 74 struct nix_cn10k_aq_enq_req *aq; 75 struct otx2_nic *pfvf = dev; 76 struct otx2_snd_queue *sq; 77 78 sq = &pfvf->qset.sq[qidx]; 79 sq->lmt_addr = (u64 *)((u64)pfvf->hw.nix_lmt_base + 80 (qidx * pfvf->nix_lmt_size)); 81 82 sq->lmt_id = pfvf->npa_lmt_lines + (qidx * LMT_BURST_SIZE); 83 84 /* Get memory to put this msg */ 85 aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox); 86 if (!aq) 87 return -ENOMEM; 88 89 aq->sq.cq = pfvf->hw.rx_queues + qidx; 90 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 91 aq->sq.cq_ena = 1; 92 aq->sq.ena = 1; 93 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 94 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 95 aq->sq.smq_rr_weight = mtu_to_dwrr_weight(pfvf, pfvf->max_frs); 96 aq->sq.default_chan = pfvf->hw.tx_chan_base; 97 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 98 aq->sq.sqb_aura = sqb_aura; 99 aq->sq.sq_int_ena = NIX_SQINT_BITS; 100 aq->sq.qint_idx = 0; 101 /* Due pipelining impact minimum 2000 unused SQ CQE's 102 * need to maintain to avoid CQ overflow. 103 */ 104 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 105 106 /* Fill AQ info */ 107 aq->qidx = qidx; 108 aq->ctype = NIX_AQ_CTYPE_SQ; 109 aq->op = NIX_AQ_INSTOP_INIT; 110 111 return otx2_sync_mbox_msg(&pfvf->mbox); 112 } 113 114 #define NPA_MAX_BURST 16 115 void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq) 116 { 117 struct otx2_nic *pfvf = dev; 118 u64 ptrs[NPA_MAX_BURST]; 119 int num_ptrs = 1; 120 dma_addr_t bufptr; 121 122 /* Refill pool with new buffers */ 123 while (cq->pool_ptrs) { 124 if (otx2_alloc_buffer(pfvf, cq, &bufptr)) { 125 if (num_ptrs--) 126 __cn10k_aura_freeptr(pfvf, cq->cq_idx, ptrs, 127 num_ptrs, 128 cq->rbpool->lmt_addr); 129 break; 130 } 131 cq->pool_ptrs--; 132 ptrs[num_ptrs] = (u64)bufptr + OTX2_HEAD_ROOM; 133 num_ptrs++; 134 if (num_ptrs == NPA_MAX_BURST || cq->pool_ptrs == 0) { 135 __cn10k_aura_freeptr(pfvf, cq->cq_idx, ptrs, 136 num_ptrs, 137 cq->rbpool->lmt_addr); 138 num_ptrs = 1; 139 } 140 } 141 } 142 143 void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx) 144 { 145 u64 val = 0, tar_addr = 0; 146 147 /* FIXME: val[0:10] LMT_ID. 148 * [12:15] no of LMTST - 1 in the burst. 149 * [19:63] data size of each LMTST in the burst except first. 150 */ 151 val = (sq->lmt_id & 0x7FF); 152 /* Target address for LMTST flush tells HW how many 128bit 153 * words are present. 154 * tar_addr[6:4] size of first LMTST - 1 in units of 128b. 155 */ 156 tar_addr |= sq->io_addr | (((size / 16) - 1) & 0x7) << 4; 157 dma_wmb(); 158 memcpy(sq->lmt_addr, sq->sqe_base, size); 159 cn10k_lmt_flush(val, tar_addr); 160 161 sq->head++; 162 sq->head &= (sq->sqe_cnt - 1); 163 } 164 165 int cn10k_free_all_ipolicers(struct otx2_nic *pfvf) 166 { 167 struct nix_bandprof_free_req *req; 168 int rc; 169 170 if (is_dev_otx2(pfvf->pdev)) 171 return 0; 172 173 mutex_lock(&pfvf->mbox.lock); 174 175 req = otx2_mbox_alloc_msg_nix_bandprof_free(&pfvf->mbox); 176 if (!req) { 177 rc = -ENOMEM; 178 goto out; 179 } 180 181 /* Free all bandwidth profiles allocated */ 182 req->free_all = true; 183 184 rc = otx2_sync_mbox_msg(&pfvf->mbox); 185 out: 186 mutex_unlock(&pfvf->mbox.lock); 187 return rc; 188 } 189 190 int cn10k_alloc_leaf_profile(struct otx2_nic *pfvf, u16 *leaf) 191 { 192 struct nix_bandprof_alloc_req *req; 193 struct nix_bandprof_alloc_rsp *rsp; 194 int rc; 195 196 req = otx2_mbox_alloc_msg_nix_bandprof_alloc(&pfvf->mbox); 197 if (!req) 198 return -ENOMEM; 199 200 req->prof_count[BAND_PROF_LEAF_LAYER] = 1; 201 202 rc = otx2_sync_mbox_msg(&pfvf->mbox); 203 if (rc) 204 goto out; 205 206 rsp = (struct nix_bandprof_alloc_rsp *) 207 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 208 if (!rsp->prof_count[BAND_PROF_LEAF_LAYER]) { 209 rc = -EIO; 210 goto out; 211 } 212 213 *leaf = rsp->prof_idx[BAND_PROF_LEAF_LAYER][0]; 214 out: 215 if (rc) { 216 dev_warn(pfvf->dev, 217 "Failed to allocate ingress bandwidth policer\n"); 218 } 219 220 return rc; 221 } 222 223 int cn10k_alloc_matchall_ipolicer(struct otx2_nic *pfvf) 224 { 225 struct otx2_hw *hw = &pfvf->hw; 226 int ret; 227 228 mutex_lock(&pfvf->mbox.lock); 229 230 ret = cn10k_alloc_leaf_profile(pfvf, &hw->matchall_ipolicer); 231 232 mutex_unlock(&pfvf->mbox.lock); 233 234 return ret; 235 } 236 237 #define POLICER_TIMESTAMP 1 /* 1 second */ 238 #define MAX_RATE_EXP 22 /* Valid rate exponent range: 0 - 22 */ 239 240 static void cn10k_get_ingress_burst_cfg(u32 burst, u32 *burst_exp, 241 u32 *burst_mantissa) 242 { 243 int tmp; 244 245 /* Burst is calculated as 246 * (1+[BURST_MANTISSA]/256)*2^[BURST_EXPONENT] 247 * This is the upper limit on number tokens (bytes) that 248 * can be accumulated in the bucket. 249 */ 250 *burst_exp = ilog2(burst); 251 if (burst < 256) { 252 /* No float: can't express mantissa in this case */ 253 *burst_mantissa = 0; 254 return; 255 } 256 257 if (*burst_exp > MAX_RATE_EXP) 258 *burst_exp = MAX_RATE_EXP; 259 260 /* Calculate mantissa 261 * Find remaining bytes 'burst - 2^burst_exp' 262 * mantissa = (remaining bytes) / 2^ (burst_exp - 8) 263 */ 264 tmp = burst - rounddown_pow_of_two(burst); 265 *burst_mantissa = tmp / (1UL << (*burst_exp - 8)); 266 } 267 268 static void cn10k_get_ingress_rate_cfg(u64 rate, u32 *rate_exp, 269 u32 *rate_mantissa, u32 *rdiv) 270 { 271 u32 div = 0; 272 u32 exp = 0; 273 u64 tmp; 274 275 /* Figure out mantissa, exponent and divider from given max pkt rate 276 * 277 * To achieve desired rate HW adds 278 * (1+[RATE_MANTISSA]/256)*2^[RATE_EXPONENT] tokens (bytes) at every 279 * policer timeunit * 2^rdiv ie 2 * 2^rdiv usecs, to the token bucket. 280 * Here policer timeunit is 2 usecs and rate is in bits per sec. 281 * Since floating point cannot be used below algorithm uses 1000000 282 * scale factor to support rates upto 100Gbps. 283 */ 284 tmp = rate * 32 * 2; 285 if (tmp < 256000000) { 286 while (tmp < 256000000) { 287 tmp = tmp * 2; 288 div++; 289 } 290 } else { 291 for (exp = 0; tmp >= 512000000 && exp <= MAX_RATE_EXP; exp++) 292 tmp = tmp / 2; 293 294 if (exp > MAX_RATE_EXP) 295 exp = MAX_RATE_EXP; 296 } 297 298 *rate_mantissa = (tmp - 256000000) / 1000000; 299 *rate_exp = exp; 300 *rdiv = div; 301 } 302 303 int cn10k_map_unmap_rq_policer(struct otx2_nic *pfvf, int rq_idx, 304 u16 policer, bool map) 305 { 306 struct nix_cn10k_aq_enq_req *aq; 307 308 aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox); 309 if (!aq) 310 return -ENOMEM; 311 312 /* Enable policing and set the bandwidth profile (policer) index */ 313 if (map) 314 aq->rq.policer_ena = 1; 315 else 316 aq->rq.policer_ena = 0; 317 aq->rq_mask.policer_ena = 1; 318 319 aq->rq.band_prof_id = policer; 320 aq->rq_mask.band_prof_id = GENMASK(9, 0); 321 322 /* Fill AQ info */ 323 aq->qidx = rq_idx; 324 aq->ctype = NIX_AQ_CTYPE_RQ; 325 aq->op = NIX_AQ_INSTOP_WRITE; 326 327 return otx2_sync_mbox_msg(&pfvf->mbox); 328 } 329 330 int cn10k_free_leaf_profile(struct otx2_nic *pfvf, u16 leaf) 331 { 332 struct nix_bandprof_free_req *req; 333 334 req = otx2_mbox_alloc_msg_nix_bandprof_free(&pfvf->mbox); 335 if (!req) 336 return -ENOMEM; 337 338 req->prof_count[BAND_PROF_LEAF_LAYER] = 1; 339 req->prof_idx[BAND_PROF_LEAF_LAYER][0] = leaf; 340 341 return otx2_sync_mbox_msg(&pfvf->mbox); 342 } 343 344 int cn10k_free_matchall_ipolicer(struct otx2_nic *pfvf) 345 { 346 struct otx2_hw *hw = &pfvf->hw; 347 int qidx, rc; 348 349 mutex_lock(&pfvf->mbox.lock); 350 351 /* Remove RQ's policer mapping */ 352 for (qidx = 0; qidx < hw->rx_queues; qidx++) 353 cn10k_map_unmap_rq_policer(pfvf, qidx, 354 hw->matchall_ipolicer, false); 355 356 rc = cn10k_free_leaf_profile(pfvf, hw->matchall_ipolicer); 357 358 mutex_unlock(&pfvf->mbox.lock); 359 return rc; 360 } 361 362 int cn10k_set_ipolicer_rate(struct otx2_nic *pfvf, u16 profile, 363 u32 burst, u64 rate, bool pps) 364 { 365 struct nix_cn10k_aq_enq_req *aq; 366 u32 burst_exp, burst_mantissa; 367 u32 rate_exp, rate_mantissa; 368 u32 rdiv; 369 370 /* Get exponent and mantissa values for the desired rate */ 371 cn10k_get_ingress_burst_cfg(burst, &burst_exp, &burst_mantissa); 372 cn10k_get_ingress_rate_cfg(rate, &rate_exp, &rate_mantissa, &rdiv); 373 374 /* Init bandwidth profile */ 375 aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox); 376 if (!aq) 377 return -ENOMEM; 378 379 /* Set initial color mode to blind */ 380 aq->prof.icolor = 0x03; 381 aq->prof_mask.icolor = 0x03; 382 383 /* Set rate and burst values */ 384 aq->prof.cir_exponent = rate_exp; 385 aq->prof_mask.cir_exponent = 0x1F; 386 387 aq->prof.cir_mantissa = rate_mantissa; 388 aq->prof_mask.cir_mantissa = 0xFF; 389 390 aq->prof.cbs_exponent = burst_exp; 391 aq->prof_mask.cbs_exponent = 0x1F; 392 393 aq->prof.cbs_mantissa = burst_mantissa; 394 aq->prof_mask.cbs_mantissa = 0xFF; 395 396 aq->prof.rdiv = rdiv; 397 aq->prof_mask.rdiv = 0xF; 398 399 if (pps) { 400 /* The amount of decremented tokens is calculated according to 401 * the following equation: 402 * max([ LMODE ? 0 : (packet_length - LXPTR)] + 403 * ([ADJUST_MANTISSA]/256 - 1) * 2^[ADJUST_EXPONENT], 404 * 1/256) 405 * if LMODE is 1 then rate limiting will be based on 406 * PPS otherwise bps. 407 * The aim of the ADJUST value is to specify a token cost per 408 * packet in contrary to the packet length that specifies a 409 * cost per byte. To rate limit based on PPS adjust mantissa 410 * is set as 384 and exponent as 1 so that number of tokens 411 * decremented becomes 1 i.e, 1 token per packeet. 412 */ 413 aq->prof.adjust_exponent = 1; 414 aq->prof_mask.adjust_exponent = 0x1F; 415 416 aq->prof.adjust_mantissa = 384; 417 aq->prof_mask.adjust_mantissa = 0x1FF; 418 419 aq->prof.lmode = 0x1; 420 aq->prof_mask.lmode = 0x1; 421 } 422 423 /* Two rate three color marker 424 * With PEIR/EIR set to zero, color will be either green or red 425 */ 426 aq->prof.meter_algo = 2; 427 aq->prof_mask.meter_algo = 0x3; 428 429 aq->prof.rc_action = NIX_RX_BAND_PROF_ACTIONRESULT_DROP; 430 aq->prof_mask.rc_action = 0x3; 431 432 aq->prof.yc_action = NIX_RX_BAND_PROF_ACTIONRESULT_PASS; 433 aq->prof_mask.yc_action = 0x3; 434 435 aq->prof.gc_action = NIX_RX_BAND_PROF_ACTIONRESULT_PASS; 436 aq->prof_mask.gc_action = 0x3; 437 438 /* Setting exponent value as 24 and mantissa as 0 configures 439 * the bucket with zero values making bucket unused. Peak 440 * information rate and Excess information rate buckets are 441 * unused here. 442 */ 443 aq->prof.peir_exponent = 24; 444 aq->prof_mask.peir_exponent = 0x1F; 445 446 aq->prof.peir_mantissa = 0; 447 aq->prof_mask.peir_mantissa = 0xFF; 448 449 aq->prof.pebs_exponent = 24; 450 aq->prof_mask.pebs_exponent = 0x1F; 451 452 aq->prof.pebs_mantissa = 0; 453 aq->prof_mask.pebs_mantissa = 0xFF; 454 455 /* Fill AQ info */ 456 aq->qidx = profile; 457 aq->ctype = NIX_AQ_CTYPE_BANDPROF; 458 aq->op = NIX_AQ_INSTOP_WRITE; 459 460 return otx2_sync_mbox_msg(&pfvf->mbox); 461 } 462 463 int cn10k_set_matchall_ipolicer_rate(struct otx2_nic *pfvf, 464 u32 burst, u64 rate) 465 { 466 struct otx2_hw *hw = &pfvf->hw; 467 int qidx, rc; 468 469 mutex_lock(&pfvf->mbox.lock); 470 471 rc = cn10k_set_ipolicer_rate(pfvf, hw->matchall_ipolicer, burst, 472 rate, false); 473 if (rc) 474 goto out; 475 476 for (qidx = 0; qidx < hw->rx_queues; qidx++) { 477 rc = cn10k_map_unmap_rq_policer(pfvf, qidx, 478 hw->matchall_ipolicer, true); 479 if (rc) 480 break; 481 } 482 483 out: 484 mutex_unlock(&pfvf->mbox.lock); 485 return rc; 486 } 487