1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Physcial Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 */ 6 7 #include "cn10k.h" 8 #include "otx2_reg.h" 9 #include "otx2_struct.h" 10 11 static struct dev_hw_ops otx2_hw_ops = { 12 .sq_aq_init = otx2_sq_aq_init, 13 .sqe_flush = otx2_sqe_flush, 14 .aura_freeptr = otx2_aura_freeptr, 15 .refill_pool_ptrs = otx2_refill_pool_ptrs, 16 }; 17 18 static struct dev_hw_ops cn10k_hw_ops = { 19 .sq_aq_init = cn10k_sq_aq_init, 20 .sqe_flush = cn10k_sqe_flush, 21 .aura_freeptr = cn10k_aura_freeptr, 22 .refill_pool_ptrs = cn10k_refill_pool_ptrs, 23 }; 24 25 int cn10k_pf_lmtst_init(struct otx2_nic *pf) 26 { 27 int size, num_lines; 28 u64 base; 29 30 if (!test_bit(CN10K_LMTST, &pf->hw.cap_flag)) { 31 pf->hw_ops = &otx2_hw_ops; 32 return 0; 33 } 34 35 pf->hw_ops = &cn10k_hw_ops; 36 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 37 (MBOX_SIZE * (pf->total_vfs + 1)); 38 39 size = pci_resource_len(pf->pdev, PCI_MBOX_BAR_NUM) - 40 (MBOX_SIZE * (pf->total_vfs + 1)); 41 42 pf->hw.lmt_base = ioremap(base, size); 43 44 if (!pf->hw.lmt_base) { 45 dev_err(pf->dev, "Unable to map PF LMTST region\n"); 46 return -ENOMEM; 47 } 48 49 /* FIXME: Get the num of LMTST lines from LMT table */ 50 pf->tot_lmt_lines = size / LMT_LINE_SIZE; 51 num_lines = (pf->tot_lmt_lines - NIX_LMTID_BASE) / 52 pf->hw.tx_queues; 53 /* Number of LMT lines per SQ queues */ 54 pf->nix_lmt_lines = num_lines > 32 ? 32 : num_lines; 55 56 pf->nix_lmt_size = pf->nix_lmt_lines * LMT_LINE_SIZE; 57 return 0; 58 } 59 60 int cn10k_vf_lmtst_init(struct otx2_nic *vf) 61 { 62 int size, num_lines; 63 64 if (!test_bit(CN10K_LMTST, &vf->hw.cap_flag)) { 65 vf->hw_ops = &otx2_hw_ops; 66 return 0; 67 } 68 69 vf->hw_ops = &cn10k_hw_ops; 70 size = pci_resource_len(vf->pdev, PCI_MBOX_BAR_NUM); 71 vf->hw.lmt_base = ioremap_wc(pci_resource_start(vf->pdev, 72 PCI_MBOX_BAR_NUM), 73 size); 74 if (!vf->hw.lmt_base) { 75 dev_err(vf->dev, "Unable to map VF LMTST region\n"); 76 return -ENOMEM; 77 } 78 79 vf->tot_lmt_lines = size / LMT_LINE_SIZE; 80 /* LMTST lines per SQ */ 81 num_lines = (vf->tot_lmt_lines - NIX_LMTID_BASE) / 82 vf->hw.tx_queues; 83 vf->nix_lmt_lines = num_lines > 32 ? 32 : num_lines; 84 vf->nix_lmt_size = vf->nix_lmt_lines * LMT_LINE_SIZE; 85 return 0; 86 } 87 EXPORT_SYMBOL(cn10k_vf_lmtst_init); 88 89 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) 90 { 91 struct nix_cn10k_aq_enq_req *aq; 92 struct otx2_nic *pfvf = dev; 93 struct otx2_snd_queue *sq; 94 95 sq = &pfvf->qset.sq[qidx]; 96 sq->lmt_addr = (__force u64 *)((u64)pfvf->hw.nix_lmt_base + 97 (qidx * pfvf->nix_lmt_size)); 98 99 /* Get memory to put this msg */ 100 aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox); 101 if (!aq) 102 return -ENOMEM; 103 104 aq->sq.cq = pfvf->hw.rx_queues + qidx; 105 aq->sq.max_sqe_size = NIX_MAXSQESZ_W16; /* 128 byte */ 106 aq->sq.cq_ena = 1; 107 aq->sq.ena = 1; 108 /* Only one SMQ is allocated, map all SQ's to that SMQ */ 109 aq->sq.smq = pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; 110 /* FIXME: set based on NIX_AF_DWRR_RPM_MTU*/ 111 aq->sq.smq_rr_weight = pfvf->netdev->mtu; 112 aq->sq.default_chan = pfvf->hw.tx_chan_base; 113 aq->sq.sqe_stype = NIX_STYPE_STF; /* Cache SQB */ 114 aq->sq.sqb_aura = sqb_aura; 115 aq->sq.sq_int_ena = NIX_SQINT_BITS; 116 aq->sq.qint_idx = 0; 117 /* Due pipelining impact minimum 2000 unused SQ CQE's 118 * need to maintain to avoid CQ overflow. 119 */ 120 aq->sq.cq_limit = ((SEND_CQ_SKID * 256) / (pfvf->qset.sqe_cnt)); 121 122 /* Fill AQ info */ 123 aq->qidx = qidx; 124 aq->ctype = NIX_AQ_CTYPE_SQ; 125 aq->op = NIX_AQ_INSTOP_INIT; 126 127 return otx2_sync_mbox_msg(&pfvf->mbox); 128 } 129 130 #define NPA_MAX_BURST 16 131 void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq) 132 { 133 struct otx2_nic *pfvf = dev; 134 u64 ptrs[NPA_MAX_BURST]; 135 int num_ptrs = 1; 136 dma_addr_t bufptr; 137 138 /* Refill pool with new buffers */ 139 while (cq->pool_ptrs) { 140 if (otx2_alloc_buffer(pfvf, cq, &bufptr)) { 141 if (num_ptrs--) 142 __cn10k_aura_freeptr(pfvf, cq->cq_idx, ptrs, 143 num_ptrs, 144 cq->rbpool->lmt_addr); 145 break; 146 } 147 cq->pool_ptrs--; 148 ptrs[num_ptrs] = (u64)bufptr + OTX2_HEAD_ROOM; 149 num_ptrs++; 150 if (num_ptrs == NPA_MAX_BURST || cq->pool_ptrs == 0) { 151 __cn10k_aura_freeptr(pfvf, cq->cq_idx, ptrs, 152 num_ptrs, 153 cq->rbpool->lmt_addr); 154 num_ptrs = 1; 155 } 156 } 157 } 158 159 void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx) 160 { 161 struct otx2_nic *pfvf = dev; 162 int lmt_id = NIX_LMTID_BASE + (qidx * pfvf->nix_lmt_lines); 163 u64 val = 0, tar_addr = 0; 164 165 /* FIXME: val[0:10] LMT_ID. 166 * [12:15] no of LMTST - 1 in the burst. 167 * [19:63] data size of each LMTST in the burst except first. 168 */ 169 val = (lmt_id & 0x7FF); 170 /* Target address for LMTST flush tells HW how many 128bit 171 * words are present. 172 * tar_addr[6:4] size of first LMTST - 1 in units of 128b. 173 */ 174 tar_addr |= sq->io_addr | (((size / 16) - 1) & 0x7) << 4; 175 dma_wmb(); 176 memcpy(sq->lmt_addr, sq->sqe_base, size); 177 cn10k_lmt_flush(val, tar_addr); 178 179 sq->head++; 180 sq->head &= (sq->sqe_cnt - 1); 181 } 182