1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2020 Marvell. 5 */ 6 7 #include <linux/bitfield.h> 8 9 #include "rvu_struct.h" 10 #include "rvu_reg.h" 11 #include "rvu.h" 12 #include "npc.h" 13 #include "rvu_npc_fs.h" 14 #include "rvu_npc_hash.h" 15 16 static const char * const npc_flow_names[] = { 17 [NPC_DMAC] = "dmac", 18 [NPC_SMAC] = "smac", 19 [NPC_ETYPE] = "ether type", 20 [NPC_VLAN_ETYPE_CTAG] = "vlan ether type ctag", 21 [NPC_VLAN_ETYPE_STAG] = "vlan ether type stag", 22 [NPC_OUTER_VID] = "outer vlan id", 23 [NPC_TOS] = "tos", 24 [NPC_IPFRAG_IPV4] = "fragmented IPv4 header ", 25 [NPC_SIP_IPV4] = "ipv4 source ip", 26 [NPC_DIP_IPV4] = "ipv4 destination ip", 27 [NPC_IPFRAG_IPV6] = "fragmented IPv6 header ", 28 [NPC_SIP_IPV6] = "ipv6 source ip", 29 [NPC_DIP_IPV6] = "ipv6 destination ip", 30 [NPC_IPPROTO_TCP] = "ip proto tcp", 31 [NPC_IPPROTO_UDP] = "ip proto udp", 32 [NPC_IPPROTO_SCTP] = "ip proto sctp", 33 [NPC_IPPROTO_ICMP] = "ip proto icmp", 34 [NPC_IPPROTO_ICMP6] = "ip proto icmp6", 35 [NPC_IPPROTO_AH] = "ip proto AH", 36 [NPC_IPPROTO_ESP] = "ip proto ESP", 37 [NPC_SPORT_TCP] = "tcp source port", 38 [NPC_DPORT_TCP] = "tcp destination port", 39 [NPC_SPORT_UDP] = "udp source port", 40 [NPC_DPORT_UDP] = "udp destination port", 41 [NPC_SPORT_SCTP] = "sctp source port", 42 [NPC_DPORT_SCTP] = "sctp destination port", 43 [NPC_LXMB] = "Mcast/Bcast header ", 44 [NPC_IPSEC_SPI] = "SPI ", 45 [NPC_UNKNOWN] = "unknown", 46 }; 47 48 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf) 49 { 50 struct npc_mcam *mcam = &rvu->hw->mcam; 51 u64 mcam_features; 52 u64 unsupported; 53 54 mcam_features = is_npc_intf_tx(intf) ? mcam->tx_features : mcam->rx_features; 55 unsupported = (mcam_features ^ features) & ~mcam_features; 56 57 /* Return false if at least one of the input flows is not extracted */ 58 return !unsupported; 59 } 60 61 const char *npc_get_field_name(u8 hdr) 62 { 63 if (hdr >= ARRAY_SIZE(npc_flow_names)) 64 return npc_flow_names[NPC_UNKNOWN]; 65 66 return npc_flow_names[hdr]; 67 } 68 69 /* Compute keyword masks and figure out the number of keywords a field 70 * spans in the key. 71 */ 72 static void npc_set_kw_masks(struct npc_mcam *mcam, u8 type, 73 u8 nr_bits, int start_kwi, int offset, u8 intf) 74 { 75 struct npc_key_field *field = &mcam->rx_key_fields[type]; 76 u8 bits_in_kw; 77 int max_kwi; 78 79 if (mcam->banks_per_entry == 1) 80 max_kwi = 1; /* NPC_MCAM_KEY_X1 */ 81 else if (mcam->banks_per_entry == 2) 82 max_kwi = 3; /* NPC_MCAM_KEY_X2 */ 83 else 84 max_kwi = 6; /* NPC_MCAM_KEY_X4 */ 85 86 if (is_npc_intf_tx(intf)) 87 field = &mcam->tx_key_fields[type]; 88 89 if (offset + nr_bits <= 64) { 90 /* one KW only */ 91 if (start_kwi > max_kwi) 92 return; 93 field->kw_mask[start_kwi] |= GENMASK_ULL(nr_bits - 1, 0) 94 << offset; 95 field->nr_kws = 1; 96 } else if (offset + nr_bits > 64 && 97 offset + nr_bits <= 128) { 98 /* two KWs */ 99 if (start_kwi + 1 > max_kwi) 100 return; 101 /* first KW mask */ 102 bits_in_kw = 64 - offset; 103 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0) 104 << offset; 105 /* second KW mask i.e. mask for rest of bits */ 106 bits_in_kw = nr_bits + offset - 64; 107 field->kw_mask[start_kwi + 1] |= GENMASK_ULL(bits_in_kw - 1, 0); 108 field->nr_kws = 2; 109 } else { 110 /* three KWs */ 111 if (start_kwi + 2 > max_kwi) 112 return; 113 /* first KW mask */ 114 bits_in_kw = 64 - offset; 115 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0) 116 << offset; 117 /* second KW mask */ 118 field->kw_mask[start_kwi + 1] = ~0ULL; 119 /* third KW mask i.e. mask for rest of bits */ 120 bits_in_kw = nr_bits + offset - 128; 121 field->kw_mask[start_kwi + 2] |= GENMASK_ULL(bits_in_kw - 1, 0); 122 field->nr_kws = 3; 123 } 124 } 125 126 /* Helper function to figure out whether field exists in the key */ 127 static bool npc_is_field_present(struct rvu *rvu, enum key_fields type, u8 intf) 128 { 129 struct npc_mcam *mcam = &rvu->hw->mcam; 130 struct npc_key_field *input; 131 132 input = &mcam->rx_key_fields[type]; 133 if (is_npc_intf_tx(intf)) 134 input = &mcam->tx_key_fields[type]; 135 136 return input->nr_kws > 0; 137 } 138 139 static bool npc_is_same(struct npc_key_field *input, 140 struct npc_key_field *field) 141 { 142 return memcmp(&input->layer_mdata, &field->layer_mdata, 143 sizeof(struct npc_layer_mdata)) == 0; 144 } 145 146 static void npc_set_layer_mdata(struct npc_mcam *mcam, enum key_fields type, 147 u64 cfg, u8 lid, u8 lt, u8 intf) 148 { 149 struct npc_key_field *input = &mcam->rx_key_fields[type]; 150 151 if (is_npc_intf_tx(intf)) 152 input = &mcam->tx_key_fields[type]; 153 154 input->layer_mdata.hdr = FIELD_GET(NPC_HDR_OFFSET, cfg); 155 input->layer_mdata.key = FIELD_GET(NPC_KEY_OFFSET, cfg); 156 input->layer_mdata.len = FIELD_GET(NPC_BYTESM, cfg) + 1; 157 input->layer_mdata.ltype = lt; 158 input->layer_mdata.lid = lid; 159 } 160 161 static bool npc_check_overlap_fields(struct npc_key_field *input1, 162 struct npc_key_field *input2) 163 { 164 int kwi; 165 166 /* Fields with same layer id and different ltypes are mutually 167 * exclusive hence they can be overlapped 168 */ 169 if (input1->layer_mdata.lid == input2->layer_mdata.lid && 170 input1->layer_mdata.ltype != input2->layer_mdata.ltype) 171 return false; 172 173 for (kwi = 0; kwi < NPC_MAX_KWS_IN_KEY; kwi++) { 174 if (input1->kw_mask[kwi] & input2->kw_mask[kwi]) 175 return true; 176 } 177 178 return false; 179 } 180 181 /* Helper function to check whether given field overlaps with any other fields 182 * in the key. Due to limitations on key size and the key extraction profile in 183 * use higher layers can overwrite lower layer's header fields. Hence overlap 184 * needs to be checked. 185 */ 186 static bool npc_check_overlap(struct rvu *rvu, int blkaddr, 187 enum key_fields type, u8 start_lid, u8 intf) 188 { 189 struct npc_mcam *mcam = &rvu->hw->mcam; 190 struct npc_key_field *dummy, *input; 191 int start_kwi, offset; 192 u8 nr_bits, lid, lt, ld; 193 u64 cfg; 194 195 dummy = &mcam->rx_key_fields[NPC_UNKNOWN]; 196 input = &mcam->rx_key_fields[type]; 197 198 if (is_npc_intf_tx(intf)) { 199 dummy = &mcam->tx_key_fields[NPC_UNKNOWN]; 200 input = &mcam->tx_key_fields[type]; 201 } 202 203 for (lid = start_lid; lid < NPC_MAX_LID; lid++) { 204 for (lt = 0; lt < NPC_MAX_LT; lt++) { 205 for (ld = 0; ld < NPC_MAX_LD; ld++) { 206 cfg = rvu_read64(rvu, blkaddr, 207 NPC_AF_INTFX_LIDX_LTX_LDX_CFG 208 (intf, lid, lt, ld)); 209 if (!FIELD_GET(NPC_LDATA_EN, cfg)) 210 continue; 211 memset(dummy, 0, sizeof(struct npc_key_field)); 212 npc_set_layer_mdata(mcam, NPC_UNKNOWN, cfg, 213 lid, lt, intf); 214 /* exclude input */ 215 if (npc_is_same(input, dummy)) 216 continue; 217 start_kwi = dummy->layer_mdata.key / 8; 218 offset = (dummy->layer_mdata.key * 8) % 64; 219 nr_bits = dummy->layer_mdata.len * 8; 220 /* form KW masks */ 221 npc_set_kw_masks(mcam, NPC_UNKNOWN, nr_bits, 222 start_kwi, offset, intf); 223 /* check any input field bits falls in any 224 * other field bits. 225 */ 226 if (npc_check_overlap_fields(dummy, input)) 227 return true; 228 } 229 } 230 } 231 232 return false; 233 } 234 235 static bool npc_check_field(struct rvu *rvu, int blkaddr, enum key_fields type, 236 u8 intf) 237 { 238 if (!npc_is_field_present(rvu, type, intf) || 239 npc_check_overlap(rvu, blkaddr, type, 0, intf)) 240 return false; 241 return true; 242 } 243 244 static void npc_scan_exact_result(struct npc_mcam *mcam, u8 bit_number, 245 u8 key_nibble, u8 intf) 246 { 247 u8 offset = (key_nibble * 4) % 64; /* offset within key word */ 248 u8 kwi = (key_nibble * 4) / 64; /* which word in key */ 249 u8 nr_bits = 4; /* bits in a nibble */ 250 u8 type; 251 252 switch (bit_number) { 253 case 40 ... 43: 254 type = NPC_EXACT_RESULT; 255 break; 256 257 default: 258 return; 259 } 260 npc_set_kw_masks(mcam, type, nr_bits, kwi, offset, intf); 261 } 262 263 static void npc_scan_parse_result(struct npc_mcam *mcam, u8 bit_number, 264 u8 key_nibble, u8 intf) 265 { 266 u8 offset = (key_nibble * 4) % 64; /* offset within key word */ 267 u8 kwi = (key_nibble * 4) / 64; /* which word in key */ 268 u8 nr_bits = 4; /* bits in a nibble */ 269 u8 type; 270 271 switch (bit_number) { 272 case 0 ... 2: 273 type = NPC_CHAN; 274 break; 275 case 3: 276 type = NPC_ERRLEV; 277 break; 278 case 4 ... 5: 279 type = NPC_ERRCODE; 280 break; 281 case 6: 282 type = NPC_LXMB; 283 break; 284 /* check for LTYPE only as of now */ 285 case 9: 286 type = NPC_LA; 287 break; 288 case 12: 289 type = NPC_LB; 290 break; 291 case 15: 292 type = NPC_LC; 293 break; 294 case 18: 295 type = NPC_LD; 296 break; 297 case 21: 298 type = NPC_LE; 299 break; 300 case 24: 301 type = NPC_LF; 302 break; 303 case 27: 304 type = NPC_LG; 305 break; 306 case 30: 307 type = NPC_LH; 308 break; 309 default: 310 return; 311 } 312 313 npc_set_kw_masks(mcam, type, nr_bits, kwi, offset, intf); 314 } 315 316 static void npc_handle_multi_layer_fields(struct rvu *rvu, int blkaddr, u8 intf) 317 { 318 struct npc_mcam *mcam = &rvu->hw->mcam; 319 struct npc_key_field *key_fields; 320 /* Ether type can come from three layers 321 * (ethernet, single tagged, double tagged) 322 */ 323 struct npc_key_field *etype_ether; 324 struct npc_key_field *etype_tag1; 325 struct npc_key_field *etype_tag2; 326 /* Outer VLAN TCI can come from two layers 327 * (single tagged, double tagged) 328 */ 329 struct npc_key_field *vlan_tag1; 330 struct npc_key_field *vlan_tag2; 331 u64 *features; 332 u8 start_lid; 333 int i; 334 335 key_fields = mcam->rx_key_fields; 336 features = &mcam->rx_features; 337 338 if (is_npc_intf_tx(intf)) { 339 key_fields = mcam->tx_key_fields; 340 features = &mcam->tx_features; 341 } 342 343 /* Handle header fields which can come from multiple layers like 344 * etype, outer vlan tci. These fields should have same position in 345 * the key otherwise to install a mcam rule more than one entry is 346 * needed which complicates mcam space management. 347 */ 348 etype_ether = &key_fields[NPC_ETYPE_ETHER]; 349 etype_tag1 = &key_fields[NPC_ETYPE_TAG1]; 350 etype_tag2 = &key_fields[NPC_ETYPE_TAG2]; 351 vlan_tag1 = &key_fields[NPC_VLAN_TAG1]; 352 vlan_tag2 = &key_fields[NPC_VLAN_TAG2]; 353 354 /* if key profile programmed does not extract Ethertype at all */ 355 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws) { 356 dev_err(rvu->dev, "mkex: Ethertype is not extracted.\n"); 357 goto vlan_tci; 358 } 359 360 /* if key profile programmed extracts Ethertype from one layer */ 361 if (etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws) 362 key_fields[NPC_ETYPE] = *etype_ether; 363 if (!etype_ether->nr_kws && etype_tag1->nr_kws && !etype_tag2->nr_kws) 364 key_fields[NPC_ETYPE] = *etype_tag1; 365 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && etype_tag2->nr_kws) 366 key_fields[NPC_ETYPE] = *etype_tag2; 367 368 /* if key profile programmed extracts Ethertype from multiple layers */ 369 if (etype_ether->nr_kws && etype_tag1->nr_kws) { 370 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 371 if (etype_ether->kw_mask[i] != etype_tag1->kw_mask[i]) { 372 dev_err(rvu->dev, "mkex: Etype pos is different for untagged and tagged pkts.\n"); 373 goto vlan_tci; 374 } 375 } 376 key_fields[NPC_ETYPE] = *etype_tag1; 377 } 378 if (etype_ether->nr_kws && etype_tag2->nr_kws) { 379 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 380 if (etype_ether->kw_mask[i] != etype_tag2->kw_mask[i]) { 381 dev_err(rvu->dev, "mkex: Etype pos is different for untagged and double tagged pkts.\n"); 382 goto vlan_tci; 383 } 384 } 385 key_fields[NPC_ETYPE] = *etype_tag2; 386 } 387 if (etype_tag1->nr_kws && etype_tag2->nr_kws) { 388 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 389 if (etype_tag1->kw_mask[i] != etype_tag2->kw_mask[i]) { 390 dev_err(rvu->dev, "mkex: Etype pos is different for tagged and double tagged pkts.\n"); 391 goto vlan_tci; 392 } 393 } 394 key_fields[NPC_ETYPE] = *etype_tag2; 395 } 396 397 /* check none of higher layers overwrite Ethertype */ 398 start_lid = key_fields[NPC_ETYPE].layer_mdata.lid + 1; 399 if (npc_check_overlap(rvu, blkaddr, NPC_ETYPE, start_lid, intf)) { 400 dev_err(rvu->dev, "mkex: Ethertype is overwritten by higher layers.\n"); 401 goto vlan_tci; 402 } 403 *features |= BIT_ULL(NPC_ETYPE); 404 vlan_tci: 405 /* if key profile does not extract outer vlan tci at all */ 406 if (!vlan_tag1->nr_kws && !vlan_tag2->nr_kws) { 407 dev_err(rvu->dev, "mkex: Outer vlan tci is not extracted.\n"); 408 goto done; 409 } 410 411 /* if key profile extracts outer vlan tci from one layer */ 412 if (vlan_tag1->nr_kws && !vlan_tag2->nr_kws) 413 key_fields[NPC_OUTER_VID] = *vlan_tag1; 414 if (!vlan_tag1->nr_kws && vlan_tag2->nr_kws) 415 key_fields[NPC_OUTER_VID] = *vlan_tag2; 416 417 /* if key profile extracts outer vlan tci from multiple layers */ 418 if (vlan_tag1->nr_kws && vlan_tag2->nr_kws) { 419 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 420 if (vlan_tag1->kw_mask[i] != vlan_tag2->kw_mask[i]) { 421 dev_err(rvu->dev, "mkex: Out vlan tci pos is different for tagged and double tagged pkts.\n"); 422 goto done; 423 } 424 } 425 key_fields[NPC_OUTER_VID] = *vlan_tag2; 426 } 427 /* check none of higher layers overwrite outer vlan tci */ 428 start_lid = key_fields[NPC_OUTER_VID].layer_mdata.lid + 1; 429 if (npc_check_overlap(rvu, blkaddr, NPC_OUTER_VID, start_lid, intf)) { 430 dev_err(rvu->dev, "mkex: Outer vlan tci is overwritten by higher layers.\n"); 431 goto done; 432 } 433 *features |= BIT_ULL(NPC_OUTER_VID); 434 done: 435 return; 436 } 437 438 static void npc_scan_ldata(struct rvu *rvu, int blkaddr, u8 lid, 439 u8 lt, u64 cfg, u8 intf) 440 { 441 struct npc_mcam_kex_hash *mkex_hash = rvu->kpu.mkex_hash; 442 struct npc_mcam *mcam = &rvu->hw->mcam; 443 u8 hdr, key, nr_bytes, bit_offset; 444 u8 la_ltype, la_start; 445 /* starting KW index and starting bit position */ 446 int start_kwi, offset; 447 448 nr_bytes = FIELD_GET(NPC_BYTESM, cfg) + 1; 449 hdr = FIELD_GET(NPC_HDR_OFFSET, cfg); 450 key = FIELD_GET(NPC_KEY_OFFSET, cfg); 451 452 /* For Tx, Layer A has NIX_INST_HDR_S(64 bytes) preceding 453 * ethernet header. 454 */ 455 if (is_npc_intf_tx(intf)) { 456 la_ltype = NPC_LT_LA_IH_NIX_ETHER; 457 la_start = 8; 458 } else { 459 la_ltype = NPC_LT_LA_ETHER; 460 la_start = 0; 461 } 462 463 #define NPC_SCAN_HDR(name, hlid, hlt, hstart, hlen) \ 464 do { \ 465 start_kwi = key / 8; \ 466 offset = (key * 8) % 64; \ 467 if (lid == (hlid) && lt == (hlt)) { \ 468 if ((hstart) >= hdr && \ 469 ((hstart) + (hlen)) <= (hdr + nr_bytes)) { \ 470 bit_offset = (hdr + nr_bytes - (hstart) - (hlen)) * 8; \ 471 npc_set_layer_mdata(mcam, (name), cfg, lid, lt, intf); \ 472 offset += bit_offset; \ 473 start_kwi += offset / 64; \ 474 offset %= 64; \ 475 npc_set_kw_masks(mcam, (name), (hlen) * 8, \ 476 start_kwi, offset, intf); \ 477 } \ 478 } \ 479 } while (0) 480 481 /* List LID, LTYPE, start offset from layer and length(in bytes) of 482 * packet header fields below. 483 * Example: Source IP is 4 bytes and starts at 12th byte of IP header 484 */ 485 NPC_SCAN_HDR(NPC_TOS, NPC_LID_LC, NPC_LT_LC_IP, 1, 1); 486 NPC_SCAN_HDR(NPC_IPFRAG_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 6, 1); 487 NPC_SCAN_HDR(NPC_SIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 12, 4); 488 NPC_SCAN_HDR(NPC_DIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 16, 4); 489 NPC_SCAN_HDR(NPC_IPFRAG_IPV6, NPC_LID_LC, NPC_LT_LC_IP6_EXT, 6, 1); 490 if (rvu->hw->cap.npc_hash_extract) { 491 if (mkex_hash->lid_lt_ld_hash_en[intf][lid][lt][0]) 492 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 4); 493 else 494 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16); 495 496 if (mkex_hash->lid_lt_ld_hash_en[intf][lid][lt][1]) 497 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 4); 498 else 499 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16); 500 } else { 501 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16); 502 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16); 503 } 504 505 NPC_SCAN_HDR(NPC_SPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 0, 2); 506 NPC_SCAN_HDR(NPC_DPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 2, 2); 507 NPC_SCAN_HDR(NPC_SPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 0, 2); 508 NPC_SCAN_HDR(NPC_DPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 2, 2); 509 NPC_SCAN_HDR(NPC_SPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 0, 2); 510 NPC_SCAN_HDR(NPC_DPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 2, 2); 511 NPC_SCAN_HDR(NPC_ETYPE_ETHER, NPC_LID_LA, NPC_LT_LA_ETHER, 12, 2); 512 NPC_SCAN_HDR(NPC_ETYPE_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 4, 2); 513 NPC_SCAN_HDR(NPC_ETYPE_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 8, 2); 514 NPC_SCAN_HDR(NPC_VLAN_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 2, 2); 515 NPC_SCAN_HDR(NPC_VLAN_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 2, 2); 516 NPC_SCAN_HDR(NPC_DMAC, NPC_LID_LA, la_ltype, la_start, 6); 517 518 NPC_SCAN_HDR(NPC_IPSEC_SPI, NPC_LID_LD, NPC_LT_LD_AH, 4, 4); 519 NPC_SCAN_HDR(NPC_IPSEC_SPI, NPC_LID_LE, NPC_LT_LE_ESP, 0, 4); 520 521 /* SMAC follows the DMAC(which is 6 bytes) */ 522 NPC_SCAN_HDR(NPC_SMAC, NPC_LID_LA, la_ltype, la_start + 6, 6); 523 /* PF_FUNC is 2 bytes at 0th byte of NPC_LT_LA_IH_NIX_ETHER */ 524 NPC_SCAN_HDR(NPC_PF_FUNC, NPC_LID_LA, NPC_LT_LA_IH_NIX_ETHER, 0, 2); 525 } 526 527 static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf) 528 { 529 struct npc_mcam *mcam = &rvu->hw->mcam; 530 u64 *features = &mcam->rx_features; 531 u64 tcp_udp_sctp; 532 int hdr; 533 534 if (is_npc_intf_tx(intf)) 535 features = &mcam->tx_features; 536 537 for (hdr = NPC_DMAC; hdr < NPC_HEADER_FIELDS_MAX; hdr++) { 538 if (npc_check_field(rvu, blkaddr, hdr, intf)) 539 *features |= BIT_ULL(hdr); 540 } 541 542 tcp_udp_sctp = BIT_ULL(NPC_SPORT_TCP) | BIT_ULL(NPC_SPORT_UDP) | 543 BIT_ULL(NPC_DPORT_TCP) | BIT_ULL(NPC_DPORT_UDP) | 544 BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP); 545 546 /* for tcp/udp/sctp corresponding layer type should be in the key */ 547 if (*features & tcp_udp_sctp) { 548 if (!npc_check_field(rvu, blkaddr, NPC_LD, intf)) 549 *features &= ~tcp_udp_sctp; 550 else 551 *features |= BIT_ULL(NPC_IPPROTO_TCP) | 552 BIT_ULL(NPC_IPPROTO_UDP) | 553 BIT_ULL(NPC_IPPROTO_SCTP); 554 } 555 556 /* for AH/ICMP/ICMPv6/, check if corresponding layer type is present in the key */ 557 if (npc_check_field(rvu, blkaddr, NPC_LD, intf)) { 558 *features |= BIT_ULL(NPC_IPPROTO_AH); 559 *features |= BIT_ULL(NPC_IPPROTO_ICMP); 560 *features |= BIT_ULL(NPC_IPPROTO_ICMP6); 561 } 562 563 /* for ESP, check if corresponding layer type is present in the key */ 564 if (npc_check_field(rvu, blkaddr, NPC_LE, intf)) 565 *features |= BIT_ULL(NPC_IPPROTO_ESP); 566 567 /* for vlan corresponding layer type should be in the key */ 568 if (*features & BIT_ULL(NPC_OUTER_VID)) 569 if (!npc_check_field(rvu, blkaddr, NPC_LB, intf)) 570 *features &= ~BIT_ULL(NPC_OUTER_VID); 571 572 if (*features & (BIT_ULL(NPC_IPPROTO_AH) | BIT_ULL(NPC_IPPROTO_ESP))) 573 *features |= BIT_ULL(NPC_IPSEC_SPI); 574 575 /* for vlan ethertypes corresponding layer type should be in the key */ 576 if (npc_check_field(rvu, blkaddr, NPC_LB, intf)) 577 *features |= BIT_ULL(NPC_VLAN_ETYPE_CTAG) | 578 BIT_ULL(NPC_VLAN_ETYPE_STAG); 579 580 /* for L2M/L2B/L3M/L3B, check if the type is present in the key */ 581 if (npc_check_field(rvu, blkaddr, NPC_LXMB, intf)) 582 *features |= BIT_ULL(NPC_LXMB); 583 } 584 585 /* Scan key extraction profile and record how fields of our interest 586 * fill the key structure. Also verify Channel and DMAC exists in 587 * key and not overwritten by other header fields. 588 */ 589 static int npc_scan_kex(struct rvu *rvu, int blkaddr, u8 intf) 590 { 591 struct npc_mcam *mcam = &rvu->hw->mcam; 592 u8 lid, lt, ld, bitnr; 593 u64 cfg, masked_cfg; 594 u8 key_nibble = 0; 595 596 /* Scan and note how parse result is going to be in key. 597 * A bit set in PARSE_NIBBLE_ENA corresponds to a nibble from 598 * parse result in the key. The enabled nibbles from parse result 599 * will be concatenated in key. 600 */ 601 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf)); 602 masked_cfg = cfg & NPC_PARSE_NIBBLE; 603 for_each_set_bit(bitnr, (unsigned long *)&masked_cfg, 31) { 604 npc_scan_parse_result(mcam, bitnr, key_nibble, intf); 605 key_nibble++; 606 } 607 608 /* Ignore exact match bits for mcam entries except the first rule 609 * which is drop on hit. This first rule is configured explitcitly by 610 * exact match code. 611 */ 612 masked_cfg = cfg & NPC_EXACT_NIBBLE; 613 bitnr = NPC_EXACT_NIBBLE_START; 614 for_each_set_bit_from(bitnr, (unsigned long *)&masked_cfg, NPC_EXACT_NIBBLE_END + 1) { 615 npc_scan_exact_result(mcam, bitnr, key_nibble, intf); 616 key_nibble++; 617 } 618 619 /* Scan and note how layer data is going to be in key */ 620 for (lid = 0; lid < NPC_MAX_LID; lid++) { 621 for (lt = 0; lt < NPC_MAX_LT; lt++) { 622 for (ld = 0; ld < NPC_MAX_LD; ld++) { 623 cfg = rvu_read64(rvu, blkaddr, 624 NPC_AF_INTFX_LIDX_LTX_LDX_CFG 625 (intf, lid, lt, ld)); 626 if (!FIELD_GET(NPC_LDATA_EN, cfg)) 627 continue; 628 npc_scan_ldata(rvu, blkaddr, lid, lt, cfg, 629 intf); 630 } 631 } 632 } 633 634 return 0; 635 } 636 637 static int npc_scan_verify_kex(struct rvu *rvu, int blkaddr) 638 { 639 int err; 640 641 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_RX); 642 if (err) 643 return err; 644 645 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_TX); 646 if (err) 647 return err; 648 649 /* Channel is mandatory */ 650 if (!npc_is_field_present(rvu, NPC_CHAN, NIX_INTF_RX)) { 651 dev_err(rvu->dev, "Channel not present in Key\n"); 652 return -EINVAL; 653 } 654 /* check that none of the fields overwrite channel */ 655 if (npc_check_overlap(rvu, blkaddr, NPC_CHAN, 0, NIX_INTF_RX)) { 656 dev_err(rvu->dev, "Channel cannot be overwritten\n"); 657 return -EINVAL; 658 } 659 660 npc_set_features(rvu, blkaddr, NIX_INTF_TX); 661 npc_set_features(rvu, blkaddr, NIX_INTF_RX); 662 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_TX); 663 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_RX); 664 665 return 0; 666 } 667 668 int npc_flow_steering_init(struct rvu *rvu, int blkaddr) 669 { 670 struct npc_mcam *mcam = &rvu->hw->mcam; 671 672 INIT_LIST_HEAD(&mcam->mcam_rules); 673 674 return npc_scan_verify_kex(rvu, blkaddr); 675 } 676 677 static int npc_check_unsupported_flows(struct rvu *rvu, u64 features, u8 intf) 678 { 679 struct npc_mcam *mcam = &rvu->hw->mcam; 680 u64 *mcam_features = &mcam->rx_features; 681 u64 unsupported; 682 u8 bit; 683 684 if (is_npc_intf_tx(intf)) 685 mcam_features = &mcam->tx_features; 686 687 unsupported = (*mcam_features ^ features) & ~(*mcam_features); 688 if (unsupported) { 689 dev_warn(rvu->dev, "Unsupported flow(s):\n"); 690 for_each_set_bit(bit, (unsigned long *)&unsupported, 64) 691 dev_warn(rvu->dev, "%s ", npc_get_field_name(bit)); 692 return -EOPNOTSUPP; 693 } 694 695 return 0; 696 } 697 698 /* npc_update_entry - Based on the masks generated during 699 * the key scanning, updates the given entry with value and 700 * masks for the field of interest. Maximum 16 bytes of a packet 701 * header can be extracted by HW hence lo and hi are sufficient. 702 * When field bytes are less than or equal to 8 then hi should be 703 * 0 for value and mask. 704 * 705 * If exact match of value is required then mask should be all 1's. 706 * If any bits in mask are 0 then corresponding bits in value are 707 * dont care. 708 */ 709 void npc_update_entry(struct rvu *rvu, enum key_fields type, 710 struct mcam_entry *entry, u64 val_lo, 711 u64 val_hi, u64 mask_lo, u64 mask_hi, u8 intf) 712 { 713 struct npc_mcam *mcam = &rvu->hw->mcam; 714 struct mcam_entry dummy = { {0} }; 715 struct npc_key_field *field; 716 u64 kw1, kw2, kw3; 717 u8 shift; 718 int i; 719 720 field = &mcam->rx_key_fields[type]; 721 if (is_npc_intf_tx(intf)) 722 field = &mcam->tx_key_fields[type]; 723 724 if (!field->nr_kws) 725 return; 726 727 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 728 if (!field->kw_mask[i]) 729 continue; 730 /* place key value in kw[x] */ 731 shift = __ffs64(field->kw_mask[i]); 732 /* update entry value */ 733 kw1 = (val_lo << shift) & field->kw_mask[i]; 734 dummy.kw[i] = kw1; 735 /* update entry mask */ 736 kw1 = (mask_lo << shift) & field->kw_mask[i]; 737 dummy.kw_mask[i] = kw1; 738 739 if (field->nr_kws == 1) 740 break; 741 /* place remaining bits of key value in kw[x + 1] */ 742 if (field->nr_kws == 2) { 743 /* update entry value */ 744 kw2 = shift ? val_lo >> (64 - shift) : 0; 745 kw2 |= (val_hi << shift); 746 kw2 &= field->kw_mask[i + 1]; 747 dummy.kw[i + 1] = kw2; 748 /* update entry mask */ 749 kw2 = shift ? mask_lo >> (64 - shift) : 0; 750 kw2 |= (mask_hi << shift); 751 kw2 &= field->kw_mask[i + 1]; 752 dummy.kw_mask[i + 1] = kw2; 753 break; 754 } 755 /* place remaining bits of key value in kw[x + 1], kw[x + 2] */ 756 if (field->nr_kws == 3) { 757 /* update entry value */ 758 kw2 = shift ? val_lo >> (64 - shift) : 0; 759 kw2 |= (val_hi << shift); 760 kw2 &= field->kw_mask[i + 1]; 761 kw3 = shift ? val_hi >> (64 - shift) : 0; 762 kw3 &= field->kw_mask[i + 2]; 763 dummy.kw[i + 1] = kw2; 764 dummy.kw[i + 2] = kw3; 765 /* update entry mask */ 766 kw2 = shift ? mask_lo >> (64 - shift) : 0; 767 kw2 |= (mask_hi << shift); 768 kw2 &= field->kw_mask[i + 1]; 769 kw3 = shift ? mask_hi >> (64 - shift) : 0; 770 kw3 &= field->kw_mask[i + 2]; 771 dummy.kw_mask[i + 1] = kw2; 772 dummy.kw_mask[i + 2] = kw3; 773 break; 774 } 775 } 776 /* dummy is ready with values and masks for given key 777 * field now clear and update input entry with those 778 */ 779 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 780 if (!field->kw_mask[i]) 781 continue; 782 entry->kw[i] &= ~field->kw_mask[i]; 783 entry->kw_mask[i] &= ~field->kw_mask[i]; 784 785 entry->kw[i] |= dummy.kw[i]; 786 entry->kw_mask[i] |= dummy.kw_mask[i]; 787 } 788 } 789 790 static void npc_update_ipv6_flow(struct rvu *rvu, struct mcam_entry *entry, 791 u64 features, struct flow_msg *pkt, 792 struct flow_msg *mask, 793 struct rvu_npc_mcam_rule *output, u8 intf) 794 { 795 u32 src_ip[IPV6_WORDS], src_ip_mask[IPV6_WORDS]; 796 u32 dst_ip[IPV6_WORDS], dst_ip_mask[IPV6_WORDS]; 797 struct flow_msg *opkt = &output->packet; 798 struct flow_msg *omask = &output->mask; 799 u64 mask_lo, mask_hi; 800 u64 val_lo, val_hi; 801 802 /* For an ipv6 address fe80::2c68:63ff:fe5e:2d0a the packet 803 * values to be programmed in MCAM should as below: 804 * val_high: 0xfe80000000000000 805 * val_low: 0x2c6863fffe5e2d0a 806 */ 807 if (features & BIT_ULL(NPC_SIP_IPV6)) { 808 be32_to_cpu_array(src_ip_mask, mask->ip6src, IPV6_WORDS); 809 be32_to_cpu_array(src_ip, pkt->ip6src, IPV6_WORDS); 810 811 mask_hi = (u64)src_ip_mask[0] << 32 | src_ip_mask[1]; 812 mask_lo = (u64)src_ip_mask[2] << 32 | src_ip_mask[3]; 813 val_hi = (u64)src_ip[0] << 32 | src_ip[1]; 814 val_lo = (u64)src_ip[2] << 32 | src_ip[3]; 815 816 npc_update_entry(rvu, NPC_SIP_IPV6, entry, val_lo, val_hi, 817 mask_lo, mask_hi, intf); 818 memcpy(opkt->ip6src, pkt->ip6src, sizeof(opkt->ip6src)); 819 memcpy(omask->ip6src, mask->ip6src, sizeof(omask->ip6src)); 820 } 821 if (features & BIT_ULL(NPC_DIP_IPV6)) { 822 be32_to_cpu_array(dst_ip_mask, mask->ip6dst, IPV6_WORDS); 823 be32_to_cpu_array(dst_ip, pkt->ip6dst, IPV6_WORDS); 824 825 mask_hi = (u64)dst_ip_mask[0] << 32 | dst_ip_mask[1]; 826 mask_lo = (u64)dst_ip_mask[2] << 32 | dst_ip_mask[3]; 827 val_hi = (u64)dst_ip[0] << 32 | dst_ip[1]; 828 val_lo = (u64)dst_ip[2] << 32 | dst_ip[3]; 829 830 npc_update_entry(rvu, NPC_DIP_IPV6, entry, val_lo, val_hi, 831 mask_lo, mask_hi, intf); 832 memcpy(opkt->ip6dst, pkt->ip6dst, sizeof(opkt->ip6dst)); 833 memcpy(omask->ip6dst, mask->ip6dst, sizeof(omask->ip6dst)); 834 } 835 } 836 837 static void npc_update_vlan_features(struct rvu *rvu, struct mcam_entry *entry, 838 u64 features, u8 intf) 839 { 840 bool ctag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_CTAG)); 841 bool stag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_STAG)); 842 bool vid = !!(features & BIT_ULL(NPC_OUTER_VID)); 843 844 /* If only VLAN id is given then always match outer VLAN id */ 845 if (vid && !ctag && !stag) { 846 npc_update_entry(rvu, NPC_LB, entry, 847 NPC_LT_LB_STAG_QINQ | NPC_LT_LB_CTAG, 0, 848 NPC_LT_LB_STAG_QINQ & NPC_LT_LB_CTAG, 0, intf); 849 return; 850 } 851 if (ctag) 852 npc_update_entry(rvu, NPC_LB, entry, NPC_LT_LB_CTAG, 0, 853 ~0ULL, 0, intf); 854 if (stag) 855 npc_update_entry(rvu, NPC_LB, entry, NPC_LT_LB_STAG_QINQ, 0, 856 ~0ULL, 0, intf); 857 } 858 859 static void npc_update_flow(struct rvu *rvu, struct mcam_entry *entry, 860 u64 features, struct flow_msg *pkt, 861 struct flow_msg *mask, 862 struct rvu_npc_mcam_rule *output, u8 intf, 863 int blkaddr) 864 { 865 u64 dmac_mask = ether_addr_to_u64(mask->dmac); 866 u64 smac_mask = ether_addr_to_u64(mask->smac); 867 u64 dmac_val = ether_addr_to_u64(pkt->dmac); 868 u64 smac_val = ether_addr_to_u64(pkt->smac); 869 struct flow_msg *opkt = &output->packet; 870 struct flow_msg *omask = &output->mask; 871 872 if (!features) 873 return; 874 875 /* For tcp/udp/sctp LTYPE should be present in entry */ 876 if (features & BIT_ULL(NPC_IPPROTO_TCP)) 877 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_TCP, 878 0, ~0ULL, 0, intf); 879 if (features & BIT_ULL(NPC_IPPROTO_UDP)) 880 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_UDP, 881 0, ~0ULL, 0, intf); 882 if (features & BIT_ULL(NPC_IPPROTO_SCTP)) 883 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_SCTP, 884 0, ~0ULL, 0, intf); 885 if (features & BIT_ULL(NPC_IPPROTO_ICMP)) 886 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_ICMP, 887 0, ~0ULL, 0, intf); 888 if (features & BIT_ULL(NPC_IPPROTO_ICMP6)) 889 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_ICMP6, 890 0, ~0ULL, 0, intf); 891 892 /* For AH, LTYPE should be present in entry */ 893 if (features & BIT_ULL(NPC_IPPROTO_AH)) 894 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_AH, 895 0, ~0ULL, 0, intf); 896 /* For ESP, LTYPE should be present in entry */ 897 if (features & BIT_ULL(NPC_IPPROTO_ESP)) 898 npc_update_entry(rvu, NPC_LE, entry, NPC_LT_LE_ESP, 899 0, ~0ULL, 0, intf); 900 901 if (features & BIT_ULL(NPC_LXMB)) { 902 output->lxmb = is_broadcast_ether_addr(pkt->dmac) ? 2 : 1; 903 npc_update_entry(rvu, NPC_LXMB, entry, output->lxmb, 0, 904 output->lxmb, 0, intf); 905 } 906 #define NPC_WRITE_FLOW(field, member, val_lo, val_hi, mask_lo, mask_hi) \ 907 do { \ 908 if (features & BIT_ULL((field))) { \ 909 npc_update_entry(rvu, (field), entry, (val_lo), (val_hi), \ 910 (mask_lo), (mask_hi), intf); \ 911 memcpy(&opkt->member, &pkt->member, sizeof(pkt->member)); \ 912 memcpy(&omask->member, &mask->member, sizeof(mask->member)); \ 913 } \ 914 } while (0) 915 916 NPC_WRITE_FLOW(NPC_DMAC, dmac, dmac_val, 0, dmac_mask, 0); 917 918 NPC_WRITE_FLOW(NPC_SMAC, smac, smac_val, 0, smac_mask, 0); 919 NPC_WRITE_FLOW(NPC_ETYPE, etype, ntohs(pkt->etype), 0, 920 ntohs(mask->etype), 0); 921 NPC_WRITE_FLOW(NPC_TOS, tos, pkt->tos, 0, mask->tos, 0); 922 NPC_WRITE_FLOW(NPC_IPFRAG_IPV4, ip_flag, pkt->ip_flag, 0, 923 mask->ip_flag, 0); 924 NPC_WRITE_FLOW(NPC_SIP_IPV4, ip4src, ntohl(pkt->ip4src), 0, 925 ntohl(mask->ip4src), 0); 926 NPC_WRITE_FLOW(NPC_DIP_IPV4, ip4dst, ntohl(pkt->ip4dst), 0, 927 ntohl(mask->ip4dst), 0); 928 NPC_WRITE_FLOW(NPC_SPORT_TCP, sport, ntohs(pkt->sport), 0, 929 ntohs(mask->sport), 0); 930 NPC_WRITE_FLOW(NPC_SPORT_UDP, sport, ntohs(pkt->sport), 0, 931 ntohs(mask->sport), 0); 932 NPC_WRITE_FLOW(NPC_DPORT_TCP, dport, ntohs(pkt->dport), 0, 933 ntohs(mask->dport), 0); 934 NPC_WRITE_FLOW(NPC_DPORT_UDP, dport, ntohs(pkt->dport), 0, 935 ntohs(mask->dport), 0); 936 NPC_WRITE_FLOW(NPC_SPORT_SCTP, sport, ntohs(pkt->sport), 0, 937 ntohs(mask->sport), 0); 938 NPC_WRITE_FLOW(NPC_DPORT_SCTP, dport, ntohs(pkt->dport), 0, 939 ntohs(mask->dport), 0); 940 941 NPC_WRITE_FLOW(NPC_IPSEC_SPI, spi, ntohl(pkt->spi), 0, 942 ntohl(mask->spi), 0); 943 944 NPC_WRITE_FLOW(NPC_OUTER_VID, vlan_tci, ntohs(pkt->vlan_tci), 0, 945 ntohs(mask->vlan_tci), 0); 946 947 NPC_WRITE_FLOW(NPC_IPFRAG_IPV6, next_header, pkt->next_header, 0, 948 mask->next_header, 0); 949 npc_update_ipv6_flow(rvu, entry, features, pkt, mask, output, intf); 950 npc_update_vlan_features(rvu, entry, features, intf); 951 952 npc_update_field_hash(rvu, intf, entry, blkaddr, features, 953 pkt, mask, opkt, omask); 954 } 955 956 static struct rvu_npc_mcam_rule *rvu_mcam_find_rule(struct npc_mcam *mcam, u16 entry) 957 { 958 struct rvu_npc_mcam_rule *iter; 959 960 mutex_lock(&mcam->lock); 961 list_for_each_entry(iter, &mcam->mcam_rules, list) { 962 if (iter->entry == entry) { 963 mutex_unlock(&mcam->lock); 964 return iter; 965 } 966 } 967 mutex_unlock(&mcam->lock); 968 969 return NULL; 970 } 971 972 static void rvu_mcam_add_rule(struct npc_mcam *mcam, 973 struct rvu_npc_mcam_rule *rule) 974 { 975 struct list_head *head = &mcam->mcam_rules; 976 struct rvu_npc_mcam_rule *iter; 977 978 mutex_lock(&mcam->lock); 979 list_for_each_entry(iter, &mcam->mcam_rules, list) { 980 if (iter->entry > rule->entry) 981 break; 982 head = &iter->list; 983 } 984 985 list_add(&rule->list, head); 986 mutex_unlock(&mcam->lock); 987 } 988 989 static void rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, 990 struct rvu_npc_mcam_rule *rule) 991 { 992 struct npc_mcam_oper_counter_req free_req = { 0 }; 993 struct msg_rsp free_rsp; 994 995 if (!rule->has_cntr) 996 return; 997 998 free_req.hdr.pcifunc = pcifunc; 999 free_req.cntr = rule->cntr; 1000 1001 rvu_mbox_handler_npc_mcam_free_counter(rvu, &free_req, &free_rsp); 1002 rule->has_cntr = false; 1003 } 1004 1005 static void rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, 1006 struct rvu_npc_mcam_rule *rule, 1007 struct npc_install_flow_rsp *rsp) 1008 { 1009 struct npc_mcam_alloc_counter_req cntr_req = { 0 }; 1010 struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 }; 1011 int err; 1012 1013 cntr_req.hdr.pcifunc = pcifunc; 1014 cntr_req.contig = true; 1015 cntr_req.count = 1; 1016 1017 /* we try to allocate a counter to track the stats of this 1018 * rule. If counter could not be allocated then proceed 1019 * without counter because counters are limited than entries. 1020 */ 1021 err = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, 1022 &cntr_rsp); 1023 if (!err && cntr_rsp.count) { 1024 rule->cntr = cntr_rsp.cntr; 1025 rule->has_cntr = true; 1026 rsp->counter = rule->cntr; 1027 } else { 1028 rsp->counter = err; 1029 } 1030 } 1031 1032 static void npc_update_rx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf, 1033 struct mcam_entry *entry, 1034 struct npc_install_flow_req *req, 1035 u16 target, bool pf_set_vfs_mac) 1036 { 1037 struct rvu_switch *rswitch = &rvu->rswitch; 1038 struct nix_rx_action action; 1039 1040 if (rswitch->mode == DEVLINK_ESWITCH_MODE_SWITCHDEV && pf_set_vfs_mac) 1041 req->chan_mask = 0x0; /* Do not care channel */ 1042 1043 npc_update_entry(rvu, NPC_CHAN, entry, req->channel, 0, req->chan_mask, 1044 0, NIX_INTF_RX); 1045 1046 *(u64 *)&action = 0x00; 1047 action.pf_func = target; 1048 action.op = req->op; 1049 action.index = req->index; 1050 action.match_id = req->match_id; 1051 action.flow_key_alg = req->flow_key_alg; 1052 1053 if (req->op == NIX_RX_ACTION_DEFAULT) { 1054 if (pfvf->def_ucast_rule) { 1055 action = pfvf->def_ucast_rule->rx_action; 1056 } else { 1057 /* For profiles which do not extract DMAC, the default 1058 * unicast entry is unused. Hence modify action for the 1059 * requests which use same action as default unicast 1060 * entry 1061 */ 1062 *(u64 *)&action = 0; 1063 action.pf_func = target; 1064 action.op = NIX_RX_ACTIONOP_UCAST; 1065 } 1066 } 1067 1068 entry->action = *(u64 *)&action; 1069 1070 /* VTAG0 starts at 0th byte of LID_B. 1071 * VTAG1 starts at 4th byte of LID_B. 1072 */ 1073 entry->vtag_action = FIELD_PREP(RX_VTAG0_VALID_BIT, req->vtag0_valid) | 1074 FIELD_PREP(RX_VTAG0_TYPE_MASK, req->vtag0_type) | 1075 FIELD_PREP(RX_VTAG0_LID_MASK, NPC_LID_LB) | 1076 FIELD_PREP(RX_VTAG0_RELPTR_MASK, 0) | 1077 FIELD_PREP(RX_VTAG1_VALID_BIT, req->vtag1_valid) | 1078 FIELD_PREP(RX_VTAG1_TYPE_MASK, req->vtag1_type) | 1079 FIELD_PREP(RX_VTAG1_LID_MASK, NPC_LID_LB) | 1080 FIELD_PREP(RX_VTAG1_RELPTR_MASK, 4); 1081 } 1082 1083 static void npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf, 1084 struct mcam_entry *entry, 1085 struct npc_install_flow_req *req, u16 target) 1086 { 1087 struct nix_tx_action action; 1088 u64 mask = ~0ULL; 1089 1090 /* If AF is installing then do not care about 1091 * PF_FUNC in Send Descriptor 1092 */ 1093 if (is_pffunc_af(req->hdr.pcifunc)) 1094 mask = 0; 1095 1096 npc_update_entry(rvu, NPC_PF_FUNC, entry, (__force u16)htons(target), 1097 0, mask, 0, NIX_INTF_TX); 1098 1099 *(u64 *)&action = 0x00; 1100 action.op = req->op; 1101 action.index = req->index; 1102 action.match_id = req->match_id; 1103 1104 entry->action = *(u64 *)&action; 1105 1106 /* VTAG0 starts at 0th byte of LID_B. 1107 * VTAG1 starts at 4th byte of LID_B. 1108 */ 1109 entry->vtag_action = FIELD_PREP(TX_VTAG0_DEF_MASK, req->vtag0_def) | 1110 FIELD_PREP(TX_VTAG0_OP_MASK, req->vtag0_op) | 1111 FIELD_PREP(TX_VTAG0_LID_MASK, NPC_LID_LA) | 1112 FIELD_PREP(TX_VTAG0_RELPTR_MASK, 20) | 1113 FIELD_PREP(TX_VTAG1_DEF_MASK, req->vtag1_def) | 1114 FIELD_PREP(TX_VTAG1_OP_MASK, req->vtag1_op) | 1115 FIELD_PREP(TX_VTAG1_LID_MASK, NPC_LID_LA) | 1116 FIELD_PREP(TX_VTAG1_RELPTR_MASK, 24); 1117 } 1118 1119 static int npc_install_flow(struct rvu *rvu, int blkaddr, u16 target, 1120 int nixlf, struct rvu_pfvf *pfvf, 1121 struct npc_install_flow_req *req, 1122 struct npc_install_flow_rsp *rsp, bool enable, 1123 bool pf_set_vfs_mac) 1124 { 1125 struct rvu_npc_mcam_rule *def_ucast_rule = pfvf->def_ucast_rule; 1126 u64 features, installed_features, missing_features = 0; 1127 struct npc_mcam_write_entry_req write_req = { 0 }; 1128 struct npc_mcam *mcam = &rvu->hw->mcam; 1129 struct rvu_npc_mcam_rule dummy = { 0 }; 1130 struct rvu_npc_mcam_rule *rule; 1131 u16 owner = req->hdr.pcifunc; 1132 struct msg_rsp write_rsp; 1133 struct mcam_entry *entry; 1134 bool new = false; 1135 u16 entry_index; 1136 int err; 1137 1138 installed_features = req->features; 1139 features = req->features; 1140 entry = &write_req.entry_data; 1141 entry_index = req->entry; 1142 1143 npc_update_flow(rvu, entry, features, &req->packet, &req->mask, &dummy, 1144 req->intf, blkaddr); 1145 1146 if (is_npc_intf_rx(req->intf)) 1147 npc_update_rx_entry(rvu, pfvf, entry, req, target, pf_set_vfs_mac); 1148 else 1149 npc_update_tx_entry(rvu, pfvf, entry, req, target); 1150 1151 /* Default unicast rules do not exist for TX */ 1152 if (is_npc_intf_tx(req->intf)) 1153 goto find_rule; 1154 1155 if (req->default_rule) { 1156 entry_index = npc_get_nixlf_mcam_index(mcam, target, nixlf, 1157 NIXLF_UCAST_ENTRY); 1158 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, entry_index); 1159 } 1160 1161 /* update mcam entry with default unicast rule attributes */ 1162 if (def_ucast_rule && (req->default_rule && req->append)) { 1163 missing_features = (def_ucast_rule->features ^ features) & 1164 def_ucast_rule->features; 1165 if (missing_features) 1166 npc_update_flow(rvu, entry, missing_features, 1167 &def_ucast_rule->packet, 1168 &def_ucast_rule->mask, 1169 &dummy, req->intf, 1170 blkaddr); 1171 installed_features = req->features | missing_features; 1172 } 1173 1174 find_rule: 1175 rule = rvu_mcam_find_rule(mcam, entry_index); 1176 if (!rule) { 1177 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 1178 if (!rule) 1179 return -ENOMEM; 1180 new = true; 1181 } 1182 1183 /* allocate new counter if rule has no counter */ 1184 if (!req->default_rule && req->set_cntr && !rule->has_cntr) 1185 rvu_mcam_add_counter_to_rule(rvu, owner, rule, rsp); 1186 1187 /* if user wants to delete an existing counter for a rule then 1188 * free the counter 1189 */ 1190 if (!req->set_cntr && rule->has_cntr) 1191 rvu_mcam_remove_counter_from_rule(rvu, owner, rule); 1192 1193 write_req.hdr.pcifunc = owner; 1194 1195 /* AF owns the default rules so change the owner just to relax 1196 * the checks in rvu_mbox_handler_npc_mcam_write_entry 1197 */ 1198 if (req->default_rule) 1199 write_req.hdr.pcifunc = 0; 1200 1201 write_req.entry = entry_index; 1202 write_req.intf = req->intf; 1203 write_req.enable_entry = (u8)enable; 1204 /* if counter is available then clear and use it */ 1205 if (req->set_cntr && rule->has_cntr) { 1206 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(rule->cntr), req->cntr_val); 1207 write_req.set_cntr = 1; 1208 write_req.cntr = rule->cntr; 1209 } 1210 1211 /* update rule */ 1212 memcpy(&rule->packet, &dummy.packet, sizeof(rule->packet)); 1213 memcpy(&rule->mask, &dummy.mask, sizeof(rule->mask)); 1214 rule->entry = entry_index; 1215 memcpy(&rule->rx_action, &entry->action, sizeof(struct nix_rx_action)); 1216 if (is_npc_intf_tx(req->intf)) 1217 memcpy(&rule->tx_action, &entry->action, 1218 sizeof(struct nix_tx_action)); 1219 rule->vtag_action = entry->vtag_action; 1220 rule->features = installed_features; 1221 rule->default_rule = req->default_rule; 1222 rule->owner = owner; 1223 rule->enable = enable; 1224 rule->chan_mask = write_req.entry_data.kw_mask[0] & NPC_KEX_CHAN_MASK; 1225 rule->chan = write_req.entry_data.kw[0] & NPC_KEX_CHAN_MASK; 1226 rule->chan &= rule->chan_mask; 1227 rule->lxmb = dummy.lxmb; 1228 if (is_npc_intf_tx(req->intf)) 1229 rule->intf = pfvf->nix_tx_intf; 1230 else 1231 rule->intf = pfvf->nix_rx_intf; 1232 1233 if (new) 1234 rvu_mcam_add_rule(mcam, rule); 1235 if (req->default_rule) 1236 pfvf->def_ucast_rule = rule; 1237 1238 /* write to mcam entry registers */ 1239 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, 1240 &write_rsp); 1241 if (err) { 1242 rvu_mcam_remove_counter_from_rule(rvu, owner, rule); 1243 if (new) { 1244 list_del(&rule->list); 1245 kfree(rule); 1246 } 1247 return err; 1248 } 1249 1250 /* VF's MAC address is being changed via PF */ 1251 if (pf_set_vfs_mac) { 1252 ether_addr_copy(pfvf->default_mac, req->packet.dmac); 1253 ether_addr_copy(pfvf->mac_addr, req->packet.dmac); 1254 set_bit(PF_SET_VF_MAC, &pfvf->flags); 1255 } 1256 1257 if (test_bit(PF_SET_VF_CFG, &pfvf->flags) && 1258 req->vtag0_type == NIX_AF_LFX_RX_VTAG_TYPE7) 1259 rule->vfvlan_cfg = true; 1260 1261 if (is_npc_intf_rx(req->intf) && req->match_id && 1262 (req->op == NIX_RX_ACTIONOP_UCAST || req->op == NIX_RX_ACTIONOP_RSS)) 1263 return rvu_nix_setup_ratelimit_aggr(rvu, req->hdr.pcifunc, 1264 req->index, req->match_id); 1265 1266 return 0; 1267 } 1268 1269 int rvu_mbox_handler_npc_install_flow(struct rvu *rvu, 1270 struct npc_install_flow_req *req, 1271 struct npc_install_flow_rsp *rsp) 1272 { 1273 bool from_vf = !!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK); 1274 struct rvu_switch *rswitch = &rvu->rswitch; 1275 int blkaddr, nixlf, err; 1276 struct rvu_pfvf *pfvf; 1277 bool pf_set_vfs_mac = false; 1278 bool enable = true; 1279 u16 target; 1280 1281 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1282 if (blkaddr < 0) { 1283 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 1284 return NPC_MCAM_INVALID_REQ; 1285 } 1286 1287 if (!is_npc_interface_valid(rvu, req->intf)) 1288 return NPC_FLOW_INTF_INVALID; 1289 1290 /* If DMAC is not extracted in MKEX, rules installed by AF 1291 * can rely on L2MB bit set by hardware protocol checker for 1292 * broadcast and multicast addresses. 1293 */ 1294 if (npc_check_field(rvu, blkaddr, NPC_DMAC, req->intf)) 1295 goto process_flow; 1296 1297 if (is_pffunc_af(req->hdr.pcifunc) && 1298 req->features & BIT_ULL(NPC_DMAC)) { 1299 if (is_unicast_ether_addr(req->packet.dmac)) { 1300 dev_warn(rvu->dev, 1301 "%s: mkex profile does not support ucast flow\n", 1302 __func__); 1303 return NPC_FLOW_NOT_SUPPORTED; 1304 } 1305 1306 if (!npc_is_field_present(rvu, NPC_LXMB, req->intf)) { 1307 dev_warn(rvu->dev, 1308 "%s: mkex profile does not support bcast/mcast flow", 1309 __func__); 1310 return NPC_FLOW_NOT_SUPPORTED; 1311 } 1312 1313 /* Modify feature to use LXMB instead of DMAC */ 1314 req->features &= ~BIT_ULL(NPC_DMAC); 1315 req->features |= BIT_ULL(NPC_LXMB); 1316 } 1317 1318 process_flow: 1319 if (from_vf && req->default_rule) 1320 return NPC_FLOW_VF_PERM_DENIED; 1321 1322 /* Each PF/VF info is maintained in struct rvu_pfvf. 1323 * rvu_pfvf for the target PF/VF needs to be retrieved 1324 * hence modify pcifunc accordingly. 1325 */ 1326 1327 /* AF installing for a PF/VF */ 1328 if (!req->hdr.pcifunc) 1329 target = req->vf; 1330 /* PF installing for its VF */ 1331 else if (!from_vf && req->vf) { 1332 target = (req->hdr.pcifunc & ~RVU_PFVF_FUNC_MASK) | req->vf; 1333 pf_set_vfs_mac = req->default_rule && 1334 (req->features & BIT_ULL(NPC_DMAC)); 1335 } 1336 /* msg received from PF/VF */ 1337 else 1338 target = req->hdr.pcifunc; 1339 1340 /* ignore chan_mask in case pf func is not AF, revisit later */ 1341 if (!is_pffunc_af(req->hdr.pcifunc)) 1342 req->chan_mask = 0xFFF; 1343 1344 err = npc_check_unsupported_flows(rvu, req->features, req->intf); 1345 if (err) 1346 return NPC_FLOW_NOT_SUPPORTED; 1347 1348 pfvf = rvu_get_pfvf(rvu, target); 1349 1350 /* PF installing for its VF */ 1351 if (req->hdr.pcifunc && !from_vf && req->vf) 1352 set_bit(PF_SET_VF_CFG, &pfvf->flags); 1353 1354 /* update req destination mac addr */ 1355 if ((req->features & BIT_ULL(NPC_DMAC)) && is_npc_intf_rx(req->intf) && 1356 is_zero_ether_addr(req->packet.dmac)) { 1357 ether_addr_copy(req->packet.dmac, pfvf->mac_addr); 1358 eth_broadcast_addr((u8 *)&req->mask.dmac); 1359 } 1360 1361 /* Proceed if NIXLF is attached or not for TX rules */ 1362 err = nix_get_nixlf(rvu, target, &nixlf, NULL); 1363 if (err && is_npc_intf_rx(req->intf) && !pf_set_vfs_mac) 1364 return NPC_FLOW_NO_NIXLF; 1365 1366 /* don't enable rule when nixlf not attached or initialized */ 1367 if (!(is_nixlf_attached(rvu, target) && 1368 test_bit(NIXLF_INITIALIZED, &pfvf->flags))) 1369 enable = false; 1370 1371 /* Packets reaching NPC in Tx path implies that a 1372 * NIXLF is properly setup and transmitting. 1373 * Hence rules can be enabled for Tx. 1374 */ 1375 if (is_npc_intf_tx(req->intf)) 1376 enable = true; 1377 1378 /* Do not allow requests from uninitialized VFs */ 1379 if (from_vf && !enable) 1380 return NPC_FLOW_VF_NOT_INIT; 1381 1382 /* PF sets VF mac & VF NIXLF is not attached, update the mac addr */ 1383 if (pf_set_vfs_mac && !enable) { 1384 ether_addr_copy(pfvf->default_mac, req->packet.dmac); 1385 ether_addr_copy(pfvf->mac_addr, req->packet.dmac); 1386 set_bit(PF_SET_VF_MAC, &pfvf->flags); 1387 return 0; 1388 } 1389 1390 mutex_lock(&rswitch->switch_lock); 1391 err = npc_install_flow(rvu, blkaddr, target, nixlf, pfvf, 1392 req, rsp, enable, pf_set_vfs_mac); 1393 mutex_unlock(&rswitch->switch_lock); 1394 1395 return err; 1396 } 1397 1398 static int npc_delete_flow(struct rvu *rvu, struct rvu_npc_mcam_rule *rule, 1399 u16 pcifunc) 1400 { 1401 struct npc_mcam_ena_dis_entry_req dis_req = { 0 }; 1402 struct msg_rsp dis_rsp; 1403 1404 if (rule->default_rule) 1405 return 0; 1406 1407 if (rule->has_cntr) 1408 rvu_mcam_remove_counter_from_rule(rvu, pcifunc, rule); 1409 1410 dis_req.hdr.pcifunc = pcifunc; 1411 dis_req.entry = rule->entry; 1412 1413 list_del(&rule->list); 1414 kfree(rule); 1415 1416 return rvu_mbox_handler_npc_mcam_dis_entry(rvu, &dis_req, &dis_rsp); 1417 } 1418 1419 int rvu_mbox_handler_npc_delete_flow(struct rvu *rvu, 1420 struct npc_delete_flow_req *req, 1421 struct npc_delete_flow_rsp *rsp) 1422 { 1423 struct npc_mcam *mcam = &rvu->hw->mcam; 1424 struct rvu_npc_mcam_rule *iter, *tmp; 1425 u16 pcifunc = req->hdr.pcifunc; 1426 struct list_head del_list; 1427 int blkaddr; 1428 1429 INIT_LIST_HEAD(&del_list); 1430 1431 mutex_lock(&mcam->lock); 1432 list_for_each_entry_safe(iter, tmp, &mcam->mcam_rules, list) { 1433 if (iter->owner == pcifunc) { 1434 /* All rules */ 1435 if (req->all) { 1436 list_move_tail(&iter->list, &del_list); 1437 /* Range of rules */ 1438 } else if (req->end && iter->entry >= req->start && 1439 iter->entry <= req->end) { 1440 list_move_tail(&iter->list, &del_list); 1441 /* single rule */ 1442 } else if (req->entry == iter->entry) { 1443 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1444 if (blkaddr) 1445 rsp->cntr_val = rvu_read64(rvu, blkaddr, 1446 NPC_AF_MATCH_STATX(iter->cntr)); 1447 list_move_tail(&iter->list, &del_list); 1448 break; 1449 } 1450 } 1451 } 1452 mutex_unlock(&mcam->lock); 1453 1454 list_for_each_entry_safe(iter, tmp, &del_list, list) { 1455 u16 entry = iter->entry; 1456 1457 /* clear the mcam entry target pcifunc */ 1458 mcam->entry2target_pffunc[entry] = 0x0; 1459 if (npc_delete_flow(rvu, iter, pcifunc)) 1460 dev_err(rvu->dev, "rule deletion failed for entry:%u", 1461 entry); 1462 } 1463 1464 return 0; 1465 } 1466 1467 static int npc_update_dmac_value(struct rvu *rvu, int npcblkaddr, 1468 struct rvu_npc_mcam_rule *rule, 1469 struct rvu_pfvf *pfvf) 1470 { 1471 struct npc_mcam_write_entry_req write_req = { 0 }; 1472 struct mcam_entry *entry = &write_req.entry_data; 1473 struct npc_mcam *mcam = &rvu->hw->mcam; 1474 struct msg_rsp rsp; 1475 u8 intf, enable; 1476 int err; 1477 1478 ether_addr_copy(rule->packet.dmac, pfvf->mac_addr); 1479 1480 npc_read_mcam_entry(rvu, mcam, npcblkaddr, rule->entry, 1481 entry, &intf, &enable); 1482 1483 npc_update_entry(rvu, NPC_DMAC, entry, 1484 ether_addr_to_u64(pfvf->mac_addr), 0, 1485 0xffffffffffffull, 0, intf); 1486 1487 write_req.hdr.pcifunc = rule->owner; 1488 write_req.entry = rule->entry; 1489 write_req.intf = pfvf->nix_rx_intf; 1490 1491 mutex_unlock(&mcam->lock); 1492 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, &rsp); 1493 mutex_lock(&mcam->lock); 1494 1495 return err; 1496 } 1497 1498 void npc_mcam_enable_flows(struct rvu *rvu, u16 target) 1499 { 1500 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, target); 1501 struct rvu_npc_mcam_rule *def_ucast_rule; 1502 struct npc_mcam *mcam = &rvu->hw->mcam; 1503 struct rvu_npc_mcam_rule *rule; 1504 int blkaddr, bank, index; 1505 u64 def_action; 1506 1507 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1508 if (blkaddr < 0) 1509 return; 1510 1511 def_ucast_rule = pfvf->def_ucast_rule; 1512 1513 mutex_lock(&mcam->lock); 1514 list_for_each_entry(rule, &mcam->mcam_rules, list) { 1515 if (is_npc_intf_rx(rule->intf) && 1516 rule->rx_action.pf_func == target && !rule->enable) { 1517 if (rule->default_rule) { 1518 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1519 rule->entry, true); 1520 rule->enable = true; 1521 continue; 1522 } 1523 1524 if (rule->vfvlan_cfg) 1525 npc_update_dmac_value(rvu, blkaddr, rule, pfvf); 1526 1527 if (rule->rx_action.op == NIX_RX_ACTION_DEFAULT) { 1528 if (!def_ucast_rule) 1529 continue; 1530 /* Use default unicast entry action */ 1531 rule->rx_action = def_ucast_rule->rx_action; 1532 def_action = *(u64 *)&def_ucast_rule->rx_action; 1533 bank = npc_get_bank(mcam, rule->entry); 1534 rvu_write64(rvu, blkaddr, 1535 NPC_AF_MCAMEX_BANKX_ACTION 1536 (rule->entry, bank), def_action); 1537 } 1538 1539 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1540 rule->entry, true); 1541 rule->enable = true; 1542 } 1543 } 1544 1545 /* Enable MCAM entries installed by PF with target as VF pcifunc */ 1546 for (index = 0; index < mcam->bmap_entries; index++) { 1547 if (mcam->entry2target_pffunc[index] == target) 1548 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1549 index, true); 1550 } 1551 mutex_unlock(&mcam->lock); 1552 } 1553 1554 void npc_mcam_disable_flows(struct rvu *rvu, u16 target) 1555 { 1556 struct npc_mcam *mcam = &rvu->hw->mcam; 1557 int blkaddr, index; 1558 1559 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1560 if (blkaddr < 0) 1561 return; 1562 1563 mutex_lock(&mcam->lock); 1564 /* Disable MCAM entries installed by PF with target as VF pcifunc */ 1565 for (index = 0; index < mcam->bmap_entries; index++) { 1566 if (mcam->entry2target_pffunc[index] == target) 1567 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1568 index, false); 1569 } 1570 mutex_unlock(&mcam->lock); 1571 } 1572 1573 /* single drop on non hit rule starting from 0th index. This an extension 1574 * to RPM mac filter to support more rules. 1575 */ 1576 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 1577 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 1578 u64 bcast_mcast_val, u64 bcast_mcast_mask) 1579 { 1580 struct npc_mcam_alloc_counter_req cntr_req = { 0 }; 1581 struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 }; 1582 struct npc_mcam_write_entry_req req = { 0 }; 1583 struct npc_mcam *mcam = &rvu->hw->mcam; 1584 struct rvu_npc_mcam_rule *rule; 1585 struct msg_rsp rsp; 1586 bool enabled; 1587 int blkaddr; 1588 int err; 1589 1590 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1591 if (blkaddr < 0) { 1592 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 1593 return -ENODEV; 1594 } 1595 1596 /* Bail out if no exact match support */ 1597 if (!rvu_npc_exact_has_match_table(rvu)) { 1598 dev_info(rvu->dev, "%s: No support for exact match feature\n", __func__); 1599 return -EINVAL; 1600 } 1601 1602 /* If 0th entry is already used, return err */ 1603 enabled = is_mcam_entry_enabled(rvu, mcam, blkaddr, mcam_idx); 1604 if (enabled) { 1605 dev_err(rvu->dev, "%s: failed to add single drop on non hit rule at %d th index\n", 1606 __func__, mcam_idx); 1607 return -EINVAL; 1608 } 1609 1610 /* Add this entry to mcam rules list */ 1611 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 1612 if (!rule) 1613 return -ENOMEM; 1614 1615 /* Disable rule by default. Enable rule when first dmac filter is 1616 * installed 1617 */ 1618 rule->enable = false; 1619 rule->chan = chan_val; 1620 rule->chan_mask = chan_mask; 1621 rule->entry = mcam_idx; 1622 rvu_mcam_add_rule(mcam, rule); 1623 1624 /* Reserve slot 0 */ 1625 npc_mcam_rsrcs_reserve(rvu, blkaddr, mcam_idx); 1626 1627 /* Allocate counter for this single drop on non hit rule */ 1628 cntr_req.hdr.pcifunc = 0; /* AF request */ 1629 cntr_req.contig = true; 1630 cntr_req.count = 1; 1631 err = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp); 1632 if (err) { 1633 dev_err(rvu->dev, "%s: Err to allocate cntr for drop rule (err=%d)\n", 1634 __func__, err); 1635 return -EFAULT; 1636 } 1637 *counter_idx = cntr_rsp.cntr; 1638 1639 /* Fill in fields for this mcam entry */ 1640 npc_update_entry(rvu, NPC_EXACT_RESULT, &req.entry_data, exact_val, 0, 1641 exact_mask, 0, NIX_INTF_RX); 1642 npc_update_entry(rvu, NPC_CHAN, &req.entry_data, chan_val, 0, 1643 chan_mask, 0, NIX_INTF_RX); 1644 npc_update_entry(rvu, NPC_LXMB, &req.entry_data, bcast_mcast_val, 0, 1645 bcast_mcast_mask, 0, NIX_INTF_RX); 1646 1647 req.intf = NIX_INTF_RX; 1648 req.set_cntr = true; 1649 req.cntr = cntr_rsp.cntr; 1650 req.entry = mcam_idx; 1651 1652 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &req, &rsp); 1653 if (err) { 1654 dev_err(rvu->dev, "%s: Installation of single drop on non hit rule at %d failed\n", 1655 __func__, mcam_idx); 1656 return err; 1657 } 1658 1659 dev_err(rvu->dev, "%s: Installed single drop on non hit rule at %d, cntr=%d\n", 1660 __func__, mcam_idx, req.cntr); 1661 1662 /* disable entry at Bank 0, index 0 */ 1663 npc_enable_mcam_entry(rvu, mcam, blkaddr, mcam_idx, false); 1664 1665 return 0; 1666 } 1667 1668 int rvu_mbox_handler_npc_get_field_status(struct rvu *rvu, 1669 struct npc_get_field_status_req *req, 1670 struct npc_get_field_status_rsp *rsp) 1671 { 1672 int blkaddr; 1673 1674 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1675 if (blkaddr < 0) 1676 return NPC_MCAM_INVALID_REQ; 1677 1678 if (!is_npc_interface_valid(rvu, req->intf)) 1679 return NPC_FLOW_INTF_INVALID; 1680 1681 if (npc_check_field(rvu, blkaddr, req->field, req->intf)) 1682 rsp->enable = 1; 1683 1684 return 0; 1685 } 1686