1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2020 Marvell. 5 */ 6 7 #include <linux/bitfield.h> 8 9 #include "rvu_struct.h" 10 #include "rvu_reg.h" 11 #include "rvu.h" 12 #include "npc.h" 13 #include "rvu_npc_fs.h" 14 #include "rvu_npc_hash.h" 15 16 static const char * const npc_flow_names[] = { 17 [NPC_DMAC] = "dmac", 18 [NPC_SMAC] = "smac", 19 [NPC_ETYPE] = "ether type", 20 [NPC_VLAN_ETYPE_CTAG] = "vlan ether type ctag", 21 [NPC_VLAN_ETYPE_STAG] = "vlan ether type stag", 22 [NPC_OUTER_VID] = "outer vlan id", 23 [NPC_TOS] = "tos", 24 [NPC_IPFRAG_IPV4] = "fragmented IPv4 header ", 25 [NPC_SIP_IPV4] = "ipv4 source ip", 26 [NPC_DIP_IPV4] = "ipv4 destination ip", 27 [NPC_IPFRAG_IPV6] = "fragmented IPv6 header ", 28 [NPC_SIP_IPV6] = "ipv6 source ip", 29 [NPC_DIP_IPV6] = "ipv6 destination ip", 30 [NPC_IPPROTO_TCP] = "ip proto tcp", 31 [NPC_IPPROTO_UDP] = "ip proto udp", 32 [NPC_IPPROTO_SCTP] = "ip proto sctp", 33 [NPC_IPPROTO_ICMP] = "ip proto icmp", 34 [NPC_IPPROTO_ICMP6] = "ip proto icmp6", 35 [NPC_IPPROTO_AH] = "ip proto AH", 36 [NPC_IPPROTO_ESP] = "ip proto ESP", 37 [NPC_SPORT_TCP] = "tcp source port", 38 [NPC_DPORT_TCP] = "tcp destination port", 39 [NPC_SPORT_UDP] = "udp source port", 40 [NPC_DPORT_UDP] = "udp destination port", 41 [NPC_SPORT_SCTP] = "sctp source port", 42 [NPC_DPORT_SCTP] = "sctp destination port", 43 [NPC_LXMB] = "Mcast/Bcast header ", 44 [NPC_UNKNOWN] = "unknown", 45 }; 46 47 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf) 48 { 49 struct npc_mcam *mcam = &rvu->hw->mcam; 50 u64 mcam_features; 51 u64 unsupported; 52 53 mcam_features = is_npc_intf_tx(intf) ? mcam->tx_features : mcam->rx_features; 54 unsupported = (mcam_features ^ features) & ~mcam_features; 55 56 /* Return false if at least one of the input flows is not extracted */ 57 return !unsupported; 58 } 59 60 const char *npc_get_field_name(u8 hdr) 61 { 62 if (hdr >= ARRAY_SIZE(npc_flow_names)) 63 return npc_flow_names[NPC_UNKNOWN]; 64 65 return npc_flow_names[hdr]; 66 } 67 68 /* Compute keyword masks and figure out the number of keywords a field 69 * spans in the key. 70 */ 71 static void npc_set_kw_masks(struct npc_mcam *mcam, u8 type, 72 u8 nr_bits, int start_kwi, int offset, u8 intf) 73 { 74 struct npc_key_field *field = &mcam->rx_key_fields[type]; 75 u8 bits_in_kw; 76 int max_kwi; 77 78 if (mcam->banks_per_entry == 1) 79 max_kwi = 1; /* NPC_MCAM_KEY_X1 */ 80 else if (mcam->banks_per_entry == 2) 81 max_kwi = 3; /* NPC_MCAM_KEY_X2 */ 82 else 83 max_kwi = 6; /* NPC_MCAM_KEY_X4 */ 84 85 if (is_npc_intf_tx(intf)) 86 field = &mcam->tx_key_fields[type]; 87 88 if (offset + nr_bits <= 64) { 89 /* one KW only */ 90 if (start_kwi > max_kwi) 91 return; 92 field->kw_mask[start_kwi] |= GENMASK_ULL(nr_bits - 1, 0) 93 << offset; 94 field->nr_kws = 1; 95 } else if (offset + nr_bits > 64 && 96 offset + nr_bits <= 128) { 97 /* two KWs */ 98 if (start_kwi + 1 > max_kwi) 99 return; 100 /* first KW mask */ 101 bits_in_kw = 64 - offset; 102 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0) 103 << offset; 104 /* second KW mask i.e. mask for rest of bits */ 105 bits_in_kw = nr_bits + offset - 64; 106 field->kw_mask[start_kwi + 1] |= GENMASK_ULL(bits_in_kw - 1, 0); 107 field->nr_kws = 2; 108 } else { 109 /* three KWs */ 110 if (start_kwi + 2 > max_kwi) 111 return; 112 /* first KW mask */ 113 bits_in_kw = 64 - offset; 114 field->kw_mask[start_kwi] |= GENMASK_ULL(bits_in_kw - 1, 0) 115 << offset; 116 /* second KW mask */ 117 field->kw_mask[start_kwi + 1] = ~0ULL; 118 /* third KW mask i.e. mask for rest of bits */ 119 bits_in_kw = nr_bits + offset - 128; 120 field->kw_mask[start_kwi + 2] |= GENMASK_ULL(bits_in_kw - 1, 0); 121 field->nr_kws = 3; 122 } 123 } 124 125 /* Helper function to figure out whether field exists in the key */ 126 static bool npc_is_field_present(struct rvu *rvu, enum key_fields type, u8 intf) 127 { 128 struct npc_mcam *mcam = &rvu->hw->mcam; 129 struct npc_key_field *input; 130 131 input = &mcam->rx_key_fields[type]; 132 if (is_npc_intf_tx(intf)) 133 input = &mcam->tx_key_fields[type]; 134 135 return input->nr_kws > 0; 136 } 137 138 static bool npc_is_same(struct npc_key_field *input, 139 struct npc_key_field *field) 140 { 141 return memcmp(&input->layer_mdata, &field->layer_mdata, 142 sizeof(struct npc_layer_mdata)) == 0; 143 } 144 145 static void npc_set_layer_mdata(struct npc_mcam *mcam, enum key_fields type, 146 u64 cfg, u8 lid, u8 lt, u8 intf) 147 { 148 struct npc_key_field *input = &mcam->rx_key_fields[type]; 149 150 if (is_npc_intf_tx(intf)) 151 input = &mcam->tx_key_fields[type]; 152 153 input->layer_mdata.hdr = FIELD_GET(NPC_HDR_OFFSET, cfg); 154 input->layer_mdata.key = FIELD_GET(NPC_KEY_OFFSET, cfg); 155 input->layer_mdata.len = FIELD_GET(NPC_BYTESM, cfg) + 1; 156 input->layer_mdata.ltype = lt; 157 input->layer_mdata.lid = lid; 158 } 159 160 static bool npc_check_overlap_fields(struct npc_key_field *input1, 161 struct npc_key_field *input2) 162 { 163 int kwi; 164 165 /* Fields with same layer id and different ltypes are mutually 166 * exclusive hence they can be overlapped 167 */ 168 if (input1->layer_mdata.lid == input2->layer_mdata.lid && 169 input1->layer_mdata.ltype != input2->layer_mdata.ltype) 170 return false; 171 172 for (kwi = 0; kwi < NPC_MAX_KWS_IN_KEY; kwi++) { 173 if (input1->kw_mask[kwi] & input2->kw_mask[kwi]) 174 return true; 175 } 176 177 return false; 178 } 179 180 /* Helper function to check whether given field overlaps with any other fields 181 * in the key. Due to limitations on key size and the key extraction profile in 182 * use higher layers can overwrite lower layer's header fields. Hence overlap 183 * needs to be checked. 184 */ 185 static bool npc_check_overlap(struct rvu *rvu, int blkaddr, 186 enum key_fields type, u8 start_lid, u8 intf) 187 { 188 struct npc_mcam *mcam = &rvu->hw->mcam; 189 struct npc_key_field *dummy, *input; 190 int start_kwi, offset; 191 u8 nr_bits, lid, lt, ld; 192 u64 cfg; 193 194 dummy = &mcam->rx_key_fields[NPC_UNKNOWN]; 195 input = &mcam->rx_key_fields[type]; 196 197 if (is_npc_intf_tx(intf)) { 198 dummy = &mcam->tx_key_fields[NPC_UNKNOWN]; 199 input = &mcam->tx_key_fields[type]; 200 } 201 202 for (lid = start_lid; lid < NPC_MAX_LID; lid++) { 203 for (lt = 0; lt < NPC_MAX_LT; lt++) { 204 for (ld = 0; ld < NPC_MAX_LD; ld++) { 205 cfg = rvu_read64(rvu, blkaddr, 206 NPC_AF_INTFX_LIDX_LTX_LDX_CFG 207 (intf, lid, lt, ld)); 208 if (!FIELD_GET(NPC_LDATA_EN, cfg)) 209 continue; 210 memset(dummy, 0, sizeof(struct npc_key_field)); 211 npc_set_layer_mdata(mcam, NPC_UNKNOWN, cfg, 212 lid, lt, intf); 213 /* exclude input */ 214 if (npc_is_same(input, dummy)) 215 continue; 216 start_kwi = dummy->layer_mdata.key / 8; 217 offset = (dummy->layer_mdata.key * 8) % 64; 218 nr_bits = dummy->layer_mdata.len * 8; 219 /* form KW masks */ 220 npc_set_kw_masks(mcam, NPC_UNKNOWN, nr_bits, 221 start_kwi, offset, intf); 222 /* check any input field bits falls in any 223 * other field bits. 224 */ 225 if (npc_check_overlap_fields(dummy, input)) 226 return true; 227 } 228 } 229 } 230 231 return false; 232 } 233 234 static bool npc_check_field(struct rvu *rvu, int blkaddr, enum key_fields type, 235 u8 intf) 236 { 237 if (!npc_is_field_present(rvu, type, intf) || 238 npc_check_overlap(rvu, blkaddr, type, 0, intf)) 239 return false; 240 return true; 241 } 242 243 static void npc_scan_exact_result(struct npc_mcam *mcam, u8 bit_number, 244 u8 key_nibble, u8 intf) 245 { 246 u8 offset = (key_nibble * 4) % 64; /* offset within key word */ 247 u8 kwi = (key_nibble * 4) / 64; /* which word in key */ 248 u8 nr_bits = 4; /* bits in a nibble */ 249 u8 type; 250 251 switch (bit_number) { 252 case 40 ... 43: 253 type = NPC_EXACT_RESULT; 254 break; 255 256 default: 257 return; 258 } 259 npc_set_kw_masks(mcam, type, nr_bits, kwi, offset, intf); 260 } 261 262 static void npc_scan_parse_result(struct npc_mcam *mcam, u8 bit_number, 263 u8 key_nibble, u8 intf) 264 { 265 u8 offset = (key_nibble * 4) % 64; /* offset within key word */ 266 u8 kwi = (key_nibble * 4) / 64; /* which word in key */ 267 u8 nr_bits = 4; /* bits in a nibble */ 268 u8 type; 269 270 switch (bit_number) { 271 case 0 ... 2: 272 type = NPC_CHAN; 273 break; 274 case 3: 275 type = NPC_ERRLEV; 276 break; 277 case 4 ... 5: 278 type = NPC_ERRCODE; 279 break; 280 case 6: 281 type = NPC_LXMB; 282 break; 283 /* check for LTYPE only as of now */ 284 case 9: 285 type = NPC_LA; 286 break; 287 case 12: 288 type = NPC_LB; 289 break; 290 case 15: 291 type = NPC_LC; 292 break; 293 case 18: 294 type = NPC_LD; 295 break; 296 case 21: 297 type = NPC_LE; 298 break; 299 case 24: 300 type = NPC_LF; 301 break; 302 case 27: 303 type = NPC_LG; 304 break; 305 case 30: 306 type = NPC_LH; 307 break; 308 default: 309 return; 310 } 311 312 npc_set_kw_masks(mcam, type, nr_bits, kwi, offset, intf); 313 } 314 315 static void npc_handle_multi_layer_fields(struct rvu *rvu, int blkaddr, u8 intf) 316 { 317 struct npc_mcam *mcam = &rvu->hw->mcam; 318 struct npc_key_field *key_fields; 319 /* Ether type can come from three layers 320 * (ethernet, single tagged, double tagged) 321 */ 322 struct npc_key_field *etype_ether; 323 struct npc_key_field *etype_tag1; 324 struct npc_key_field *etype_tag2; 325 /* Outer VLAN TCI can come from two layers 326 * (single tagged, double tagged) 327 */ 328 struct npc_key_field *vlan_tag1; 329 struct npc_key_field *vlan_tag2; 330 u64 *features; 331 u8 start_lid; 332 int i; 333 334 key_fields = mcam->rx_key_fields; 335 features = &mcam->rx_features; 336 337 if (is_npc_intf_tx(intf)) { 338 key_fields = mcam->tx_key_fields; 339 features = &mcam->tx_features; 340 } 341 342 /* Handle header fields which can come from multiple layers like 343 * etype, outer vlan tci. These fields should have same position in 344 * the key otherwise to install a mcam rule more than one entry is 345 * needed which complicates mcam space management. 346 */ 347 etype_ether = &key_fields[NPC_ETYPE_ETHER]; 348 etype_tag1 = &key_fields[NPC_ETYPE_TAG1]; 349 etype_tag2 = &key_fields[NPC_ETYPE_TAG2]; 350 vlan_tag1 = &key_fields[NPC_VLAN_TAG1]; 351 vlan_tag2 = &key_fields[NPC_VLAN_TAG2]; 352 353 /* if key profile programmed does not extract Ethertype at all */ 354 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws) { 355 dev_err(rvu->dev, "mkex: Ethertype is not extracted.\n"); 356 goto vlan_tci; 357 } 358 359 /* if key profile programmed extracts Ethertype from one layer */ 360 if (etype_ether->nr_kws && !etype_tag1->nr_kws && !etype_tag2->nr_kws) 361 key_fields[NPC_ETYPE] = *etype_ether; 362 if (!etype_ether->nr_kws && etype_tag1->nr_kws && !etype_tag2->nr_kws) 363 key_fields[NPC_ETYPE] = *etype_tag1; 364 if (!etype_ether->nr_kws && !etype_tag1->nr_kws && etype_tag2->nr_kws) 365 key_fields[NPC_ETYPE] = *etype_tag2; 366 367 /* if key profile programmed extracts Ethertype from multiple layers */ 368 if (etype_ether->nr_kws && etype_tag1->nr_kws) { 369 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 370 if (etype_ether->kw_mask[i] != etype_tag1->kw_mask[i]) { 371 dev_err(rvu->dev, "mkex: Etype pos is different for untagged and tagged pkts.\n"); 372 goto vlan_tci; 373 } 374 } 375 key_fields[NPC_ETYPE] = *etype_tag1; 376 } 377 if (etype_ether->nr_kws && etype_tag2->nr_kws) { 378 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 379 if (etype_ether->kw_mask[i] != etype_tag2->kw_mask[i]) { 380 dev_err(rvu->dev, "mkex: Etype pos is different for untagged and double tagged pkts.\n"); 381 goto vlan_tci; 382 } 383 } 384 key_fields[NPC_ETYPE] = *etype_tag2; 385 } 386 if (etype_tag1->nr_kws && etype_tag2->nr_kws) { 387 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 388 if (etype_tag1->kw_mask[i] != etype_tag2->kw_mask[i]) { 389 dev_err(rvu->dev, "mkex: Etype pos is different for tagged and double tagged pkts.\n"); 390 goto vlan_tci; 391 } 392 } 393 key_fields[NPC_ETYPE] = *etype_tag2; 394 } 395 396 /* check none of higher layers overwrite Ethertype */ 397 start_lid = key_fields[NPC_ETYPE].layer_mdata.lid + 1; 398 if (npc_check_overlap(rvu, blkaddr, NPC_ETYPE, start_lid, intf)) { 399 dev_err(rvu->dev, "mkex: Ethertype is overwritten by higher layers.\n"); 400 goto vlan_tci; 401 } 402 *features |= BIT_ULL(NPC_ETYPE); 403 vlan_tci: 404 /* if key profile does not extract outer vlan tci at all */ 405 if (!vlan_tag1->nr_kws && !vlan_tag2->nr_kws) { 406 dev_err(rvu->dev, "mkex: Outer vlan tci is not extracted.\n"); 407 goto done; 408 } 409 410 /* if key profile extracts outer vlan tci from one layer */ 411 if (vlan_tag1->nr_kws && !vlan_tag2->nr_kws) 412 key_fields[NPC_OUTER_VID] = *vlan_tag1; 413 if (!vlan_tag1->nr_kws && vlan_tag2->nr_kws) 414 key_fields[NPC_OUTER_VID] = *vlan_tag2; 415 416 /* if key profile extracts outer vlan tci from multiple layers */ 417 if (vlan_tag1->nr_kws && vlan_tag2->nr_kws) { 418 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 419 if (vlan_tag1->kw_mask[i] != vlan_tag2->kw_mask[i]) { 420 dev_err(rvu->dev, "mkex: Out vlan tci pos is different for tagged and double tagged pkts.\n"); 421 goto done; 422 } 423 } 424 key_fields[NPC_OUTER_VID] = *vlan_tag2; 425 } 426 /* check none of higher layers overwrite outer vlan tci */ 427 start_lid = key_fields[NPC_OUTER_VID].layer_mdata.lid + 1; 428 if (npc_check_overlap(rvu, blkaddr, NPC_OUTER_VID, start_lid, intf)) { 429 dev_err(rvu->dev, "mkex: Outer vlan tci is overwritten by higher layers.\n"); 430 goto done; 431 } 432 *features |= BIT_ULL(NPC_OUTER_VID); 433 done: 434 return; 435 } 436 437 static void npc_scan_ldata(struct rvu *rvu, int blkaddr, u8 lid, 438 u8 lt, u64 cfg, u8 intf) 439 { 440 struct npc_mcam_kex_hash *mkex_hash = rvu->kpu.mkex_hash; 441 struct npc_mcam *mcam = &rvu->hw->mcam; 442 u8 hdr, key, nr_bytes, bit_offset; 443 u8 la_ltype, la_start; 444 /* starting KW index and starting bit position */ 445 int start_kwi, offset; 446 447 nr_bytes = FIELD_GET(NPC_BYTESM, cfg) + 1; 448 hdr = FIELD_GET(NPC_HDR_OFFSET, cfg); 449 key = FIELD_GET(NPC_KEY_OFFSET, cfg); 450 451 /* For Tx, Layer A has NIX_INST_HDR_S(64 bytes) preceding 452 * ethernet header. 453 */ 454 if (is_npc_intf_tx(intf)) { 455 la_ltype = NPC_LT_LA_IH_NIX_ETHER; 456 la_start = 8; 457 } else { 458 la_ltype = NPC_LT_LA_ETHER; 459 la_start = 0; 460 } 461 462 #define NPC_SCAN_HDR(name, hlid, hlt, hstart, hlen) \ 463 do { \ 464 start_kwi = key / 8; \ 465 offset = (key * 8) % 64; \ 466 if (lid == (hlid) && lt == (hlt)) { \ 467 if ((hstart) >= hdr && \ 468 ((hstart) + (hlen)) <= (hdr + nr_bytes)) { \ 469 bit_offset = (hdr + nr_bytes - (hstart) - (hlen)) * 8; \ 470 npc_set_layer_mdata(mcam, (name), cfg, lid, lt, intf); \ 471 offset += bit_offset; \ 472 start_kwi += offset / 64; \ 473 offset %= 64; \ 474 npc_set_kw_masks(mcam, (name), (hlen) * 8, \ 475 start_kwi, offset, intf); \ 476 } \ 477 } \ 478 } while (0) 479 480 /* List LID, LTYPE, start offset from layer and length(in bytes) of 481 * packet header fields below. 482 * Example: Source IP is 4 bytes and starts at 12th byte of IP header 483 */ 484 NPC_SCAN_HDR(NPC_TOS, NPC_LID_LC, NPC_LT_LC_IP, 1, 1); 485 NPC_SCAN_HDR(NPC_IPFRAG_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 6, 1); 486 NPC_SCAN_HDR(NPC_SIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 12, 4); 487 NPC_SCAN_HDR(NPC_DIP_IPV4, NPC_LID_LC, NPC_LT_LC_IP, 16, 4); 488 NPC_SCAN_HDR(NPC_IPFRAG_IPV6, NPC_LID_LC, NPC_LT_LC_IP6_EXT, 6, 1); 489 if (rvu->hw->cap.npc_hash_extract) { 490 if (mkex_hash->lid_lt_ld_hash_en[intf][lid][lt][0]) 491 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 4); 492 else 493 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16); 494 495 if (mkex_hash->lid_lt_ld_hash_en[intf][lid][lt][1]) 496 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 4); 497 else 498 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16); 499 } else { 500 NPC_SCAN_HDR(NPC_SIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 8, 16); 501 NPC_SCAN_HDR(NPC_DIP_IPV6, NPC_LID_LC, NPC_LT_LC_IP6, 24, 16); 502 } 503 504 NPC_SCAN_HDR(NPC_SPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 0, 2); 505 NPC_SCAN_HDR(NPC_DPORT_UDP, NPC_LID_LD, NPC_LT_LD_UDP, 2, 2); 506 NPC_SCAN_HDR(NPC_SPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 0, 2); 507 NPC_SCAN_HDR(NPC_DPORT_TCP, NPC_LID_LD, NPC_LT_LD_TCP, 2, 2); 508 NPC_SCAN_HDR(NPC_SPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 0, 2); 509 NPC_SCAN_HDR(NPC_DPORT_SCTP, NPC_LID_LD, NPC_LT_LD_SCTP, 2, 2); 510 NPC_SCAN_HDR(NPC_ETYPE_ETHER, NPC_LID_LA, NPC_LT_LA_ETHER, 12, 2); 511 NPC_SCAN_HDR(NPC_ETYPE_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 4, 2); 512 NPC_SCAN_HDR(NPC_ETYPE_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 8, 2); 513 NPC_SCAN_HDR(NPC_VLAN_TAG1, NPC_LID_LB, NPC_LT_LB_CTAG, 2, 2); 514 NPC_SCAN_HDR(NPC_VLAN_TAG2, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 2, 2); 515 NPC_SCAN_HDR(NPC_DMAC, NPC_LID_LA, la_ltype, la_start, 6); 516 /* SMAC follows the DMAC(which is 6 bytes) */ 517 NPC_SCAN_HDR(NPC_SMAC, NPC_LID_LA, la_ltype, la_start + 6, 6); 518 /* PF_FUNC is 2 bytes at 0th byte of NPC_LT_LA_IH_NIX_ETHER */ 519 NPC_SCAN_HDR(NPC_PF_FUNC, NPC_LID_LA, NPC_LT_LA_IH_NIX_ETHER, 0, 2); 520 } 521 522 static void npc_set_features(struct rvu *rvu, int blkaddr, u8 intf) 523 { 524 struct npc_mcam *mcam = &rvu->hw->mcam; 525 u64 *features = &mcam->rx_features; 526 u64 tcp_udp_sctp; 527 int hdr; 528 529 if (is_npc_intf_tx(intf)) 530 features = &mcam->tx_features; 531 532 for (hdr = NPC_DMAC; hdr < NPC_HEADER_FIELDS_MAX; hdr++) { 533 if (npc_check_field(rvu, blkaddr, hdr, intf)) 534 *features |= BIT_ULL(hdr); 535 } 536 537 tcp_udp_sctp = BIT_ULL(NPC_SPORT_TCP) | BIT_ULL(NPC_SPORT_UDP) | 538 BIT_ULL(NPC_DPORT_TCP) | BIT_ULL(NPC_DPORT_UDP) | 539 BIT_ULL(NPC_SPORT_SCTP) | BIT_ULL(NPC_DPORT_SCTP); 540 541 /* for tcp/udp/sctp corresponding layer type should be in the key */ 542 if (*features & tcp_udp_sctp) { 543 if (!npc_check_field(rvu, blkaddr, NPC_LD, intf)) 544 *features &= ~tcp_udp_sctp; 545 else 546 *features |= BIT_ULL(NPC_IPPROTO_TCP) | 547 BIT_ULL(NPC_IPPROTO_UDP) | 548 BIT_ULL(NPC_IPPROTO_SCTP); 549 } 550 551 /* for AH/ICMP/ICMPv6/, check if corresponding layer type is present in the key */ 552 if (npc_check_field(rvu, blkaddr, NPC_LD, intf)) { 553 *features |= BIT_ULL(NPC_IPPROTO_AH); 554 *features |= BIT_ULL(NPC_IPPROTO_ICMP); 555 *features |= BIT_ULL(NPC_IPPROTO_ICMP6); 556 } 557 558 /* for ESP, check if corresponding layer type is present in the key */ 559 if (npc_check_field(rvu, blkaddr, NPC_LE, intf)) 560 *features |= BIT_ULL(NPC_IPPROTO_ESP); 561 562 /* for vlan corresponding layer type should be in the key */ 563 if (*features & BIT_ULL(NPC_OUTER_VID)) 564 if (!npc_check_field(rvu, blkaddr, NPC_LB, intf)) 565 *features &= ~BIT_ULL(NPC_OUTER_VID); 566 567 /* for vlan ethertypes corresponding layer type should be in the key */ 568 if (npc_check_field(rvu, blkaddr, NPC_LB, intf)) 569 *features |= BIT_ULL(NPC_VLAN_ETYPE_CTAG) | 570 BIT_ULL(NPC_VLAN_ETYPE_STAG); 571 572 /* for L2M/L2B/L3M/L3B, check if the type is present in the key */ 573 if (npc_check_field(rvu, blkaddr, NPC_LXMB, intf)) 574 *features |= BIT_ULL(NPC_LXMB); 575 } 576 577 /* Scan key extraction profile and record how fields of our interest 578 * fill the key structure. Also verify Channel and DMAC exists in 579 * key and not overwritten by other header fields. 580 */ 581 static int npc_scan_kex(struct rvu *rvu, int blkaddr, u8 intf) 582 { 583 struct npc_mcam *mcam = &rvu->hw->mcam; 584 u8 lid, lt, ld, bitnr; 585 u64 cfg, masked_cfg; 586 u8 key_nibble = 0; 587 588 /* Scan and note how parse result is going to be in key. 589 * A bit set in PARSE_NIBBLE_ENA corresponds to a nibble from 590 * parse result in the key. The enabled nibbles from parse result 591 * will be concatenated in key. 592 */ 593 cfg = rvu_read64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf)); 594 masked_cfg = cfg & NPC_PARSE_NIBBLE; 595 for_each_set_bit(bitnr, (unsigned long *)&masked_cfg, 31) { 596 npc_scan_parse_result(mcam, bitnr, key_nibble, intf); 597 key_nibble++; 598 } 599 600 /* Ignore exact match bits for mcam entries except the first rule 601 * which is drop on hit. This first rule is configured explitcitly by 602 * exact match code. 603 */ 604 masked_cfg = cfg & NPC_EXACT_NIBBLE; 605 bitnr = NPC_EXACT_NIBBLE_START; 606 for_each_set_bit_from(bitnr, (unsigned long *)&masked_cfg, NPC_EXACT_NIBBLE_END + 1) { 607 npc_scan_exact_result(mcam, bitnr, key_nibble, intf); 608 key_nibble++; 609 } 610 611 /* Scan and note how layer data is going to be in key */ 612 for (lid = 0; lid < NPC_MAX_LID; lid++) { 613 for (lt = 0; lt < NPC_MAX_LT; lt++) { 614 for (ld = 0; ld < NPC_MAX_LD; ld++) { 615 cfg = rvu_read64(rvu, blkaddr, 616 NPC_AF_INTFX_LIDX_LTX_LDX_CFG 617 (intf, lid, lt, ld)); 618 if (!FIELD_GET(NPC_LDATA_EN, cfg)) 619 continue; 620 npc_scan_ldata(rvu, blkaddr, lid, lt, cfg, 621 intf); 622 } 623 } 624 } 625 626 return 0; 627 } 628 629 static int npc_scan_verify_kex(struct rvu *rvu, int blkaddr) 630 { 631 int err; 632 633 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_RX); 634 if (err) 635 return err; 636 637 err = npc_scan_kex(rvu, blkaddr, NIX_INTF_TX); 638 if (err) 639 return err; 640 641 /* Channel is mandatory */ 642 if (!npc_is_field_present(rvu, NPC_CHAN, NIX_INTF_RX)) { 643 dev_err(rvu->dev, "Channel not present in Key\n"); 644 return -EINVAL; 645 } 646 /* check that none of the fields overwrite channel */ 647 if (npc_check_overlap(rvu, blkaddr, NPC_CHAN, 0, NIX_INTF_RX)) { 648 dev_err(rvu->dev, "Channel cannot be overwritten\n"); 649 return -EINVAL; 650 } 651 652 npc_set_features(rvu, blkaddr, NIX_INTF_TX); 653 npc_set_features(rvu, blkaddr, NIX_INTF_RX); 654 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_TX); 655 npc_handle_multi_layer_fields(rvu, blkaddr, NIX_INTF_RX); 656 657 return 0; 658 } 659 660 int npc_flow_steering_init(struct rvu *rvu, int blkaddr) 661 { 662 struct npc_mcam *mcam = &rvu->hw->mcam; 663 664 INIT_LIST_HEAD(&mcam->mcam_rules); 665 666 return npc_scan_verify_kex(rvu, blkaddr); 667 } 668 669 static int npc_check_unsupported_flows(struct rvu *rvu, u64 features, u8 intf) 670 { 671 struct npc_mcam *mcam = &rvu->hw->mcam; 672 u64 *mcam_features = &mcam->rx_features; 673 u64 unsupported; 674 u8 bit; 675 676 if (is_npc_intf_tx(intf)) 677 mcam_features = &mcam->tx_features; 678 679 unsupported = (*mcam_features ^ features) & ~(*mcam_features); 680 if (unsupported) { 681 dev_warn(rvu->dev, "Unsupported flow(s):\n"); 682 for_each_set_bit(bit, (unsigned long *)&unsupported, 64) 683 dev_warn(rvu->dev, "%s ", npc_get_field_name(bit)); 684 return -EOPNOTSUPP; 685 } 686 687 return 0; 688 } 689 690 /* npc_update_entry - Based on the masks generated during 691 * the key scanning, updates the given entry with value and 692 * masks for the field of interest. Maximum 16 bytes of a packet 693 * header can be extracted by HW hence lo and hi are sufficient. 694 * When field bytes are less than or equal to 8 then hi should be 695 * 0 for value and mask. 696 * 697 * If exact match of value is required then mask should be all 1's. 698 * If any bits in mask are 0 then corresponding bits in value are 699 * dont care. 700 */ 701 void npc_update_entry(struct rvu *rvu, enum key_fields type, 702 struct mcam_entry *entry, u64 val_lo, 703 u64 val_hi, u64 mask_lo, u64 mask_hi, u8 intf) 704 { 705 struct npc_mcam *mcam = &rvu->hw->mcam; 706 struct mcam_entry dummy = { {0} }; 707 struct npc_key_field *field; 708 u64 kw1, kw2, kw3; 709 u8 shift; 710 int i; 711 712 field = &mcam->rx_key_fields[type]; 713 if (is_npc_intf_tx(intf)) 714 field = &mcam->tx_key_fields[type]; 715 716 if (!field->nr_kws) 717 return; 718 719 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 720 if (!field->kw_mask[i]) 721 continue; 722 /* place key value in kw[x] */ 723 shift = __ffs64(field->kw_mask[i]); 724 /* update entry value */ 725 kw1 = (val_lo << shift) & field->kw_mask[i]; 726 dummy.kw[i] = kw1; 727 /* update entry mask */ 728 kw1 = (mask_lo << shift) & field->kw_mask[i]; 729 dummy.kw_mask[i] = kw1; 730 731 if (field->nr_kws == 1) 732 break; 733 /* place remaining bits of key value in kw[x + 1] */ 734 if (field->nr_kws == 2) { 735 /* update entry value */ 736 kw2 = shift ? val_lo >> (64 - shift) : 0; 737 kw2 |= (val_hi << shift); 738 kw2 &= field->kw_mask[i + 1]; 739 dummy.kw[i + 1] = kw2; 740 /* update entry mask */ 741 kw2 = shift ? mask_lo >> (64 - shift) : 0; 742 kw2 |= (mask_hi << shift); 743 kw2 &= field->kw_mask[i + 1]; 744 dummy.kw_mask[i + 1] = kw2; 745 break; 746 } 747 /* place remaining bits of key value in kw[x + 1], kw[x + 2] */ 748 if (field->nr_kws == 3) { 749 /* update entry value */ 750 kw2 = shift ? val_lo >> (64 - shift) : 0; 751 kw2 |= (val_hi << shift); 752 kw2 &= field->kw_mask[i + 1]; 753 kw3 = shift ? val_hi >> (64 - shift) : 0; 754 kw3 &= field->kw_mask[i + 2]; 755 dummy.kw[i + 1] = kw2; 756 dummy.kw[i + 2] = kw3; 757 /* update entry mask */ 758 kw2 = shift ? mask_lo >> (64 - shift) : 0; 759 kw2 |= (mask_hi << shift); 760 kw2 &= field->kw_mask[i + 1]; 761 kw3 = shift ? mask_hi >> (64 - shift) : 0; 762 kw3 &= field->kw_mask[i + 2]; 763 dummy.kw_mask[i + 1] = kw2; 764 dummy.kw_mask[i + 2] = kw3; 765 break; 766 } 767 } 768 /* dummy is ready with values and masks for given key 769 * field now clear and update input entry with those 770 */ 771 for (i = 0; i < NPC_MAX_KWS_IN_KEY; i++) { 772 if (!field->kw_mask[i]) 773 continue; 774 entry->kw[i] &= ~field->kw_mask[i]; 775 entry->kw_mask[i] &= ~field->kw_mask[i]; 776 777 entry->kw[i] |= dummy.kw[i]; 778 entry->kw_mask[i] |= dummy.kw_mask[i]; 779 } 780 } 781 782 static void npc_update_ipv6_flow(struct rvu *rvu, struct mcam_entry *entry, 783 u64 features, struct flow_msg *pkt, 784 struct flow_msg *mask, 785 struct rvu_npc_mcam_rule *output, u8 intf) 786 { 787 u32 src_ip[IPV6_WORDS], src_ip_mask[IPV6_WORDS]; 788 u32 dst_ip[IPV6_WORDS], dst_ip_mask[IPV6_WORDS]; 789 struct flow_msg *opkt = &output->packet; 790 struct flow_msg *omask = &output->mask; 791 u64 mask_lo, mask_hi; 792 u64 val_lo, val_hi; 793 794 /* For an ipv6 address fe80::2c68:63ff:fe5e:2d0a the packet 795 * values to be programmed in MCAM should as below: 796 * val_high: 0xfe80000000000000 797 * val_low: 0x2c6863fffe5e2d0a 798 */ 799 if (features & BIT_ULL(NPC_SIP_IPV6)) { 800 be32_to_cpu_array(src_ip_mask, mask->ip6src, IPV6_WORDS); 801 be32_to_cpu_array(src_ip, pkt->ip6src, IPV6_WORDS); 802 803 mask_hi = (u64)src_ip_mask[0] << 32 | src_ip_mask[1]; 804 mask_lo = (u64)src_ip_mask[2] << 32 | src_ip_mask[3]; 805 val_hi = (u64)src_ip[0] << 32 | src_ip[1]; 806 val_lo = (u64)src_ip[2] << 32 | src_ip[3]; 807 808 npc_update_entry(rvu, NPC_SIP_IPV6, entry, val_lo, val_hi, 809 mask_lo, mask_hi, intf); 810 memcpy(opkt->ip6src, pkt->ip6src, sizeof(opkt->ip6src)); 811 memcpy(omask->ip6src, mask->ip6src, sizeof(omask->ip6src)); 812 } 813 if (features & BIT_ULL(NPC_DIP_IPV6)) { 814 be32_to_cpu_array(dst_ip_mask, mask->ip6dst, IPV6_WORDS); 815 be32_to_cpu_array(dst_ip, pkt->ip6dst, IPV6_WORDS); 816 817 mask_hi = (u64)dst_ip_mask[0] << 32 | dst_ip_mask[1]; 818 mask_lo = (u64)dst_ip_mask[2] << 32 | dst_ip_mask[3]; 819 val_hi = (u64)dst_ip[0] << 32 | dst_ip[1]; 820 val_lo = (u64)dst_ip[2] << 32 | dst_ip[3]; 821 822 npc_update_entry(rvu, NPC_DIP_IPV6, entry, val_lo, val_hi, 823 mask_lo, mask_hi, intf); 824 memcpy(opkt->ip6dst, pkt->ip6dst, sizeof(opkt->ip6dst)); 825 memcpy(omask->ip6dst, mask->ip6dst, sizeof(omask->ip6dst)); 826 } 827 } 828 829 static void npc_update_vlan_features(struct rvu *rvu, struct mcam_entry *entry, 830 u64 features, u8 intf) 831 { 832 bool ctag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_CTAG)); 833 bool stag = !!(features & BIT_ULL(NPC_VLAN_ETYPE_STAG)); 834 bool vid = !!(features & BIT_ULL(NPC_OUTER_VID)); 835 836 /* If only VLAN id is given then always match outer VLAN id */ 837 if (vid && !ctag && !stag) { 838 npc_update_entry(rvu, NPC_LB, entry, 839 NPC_LT_LB_STAG_QINQ | NPC_LT_LB_CTAG, 0, 840 NPC_LT_LB_STAG_QINQ & NPC_LT_LB_CTAG, 0, intf); 841 return; 842 } 843 if (ctag) 844 npc_update_entry(rvu, NPC_LB, entry, NPC_LT_LB_CTAG, 0, 845 ~0ULL, 0, intf); 846 if (stag) 847 npc_update_entry(rvu, NPC_LB, entry, NPC_LT_LB_STAG_QINQ, 0, 848 ~0ULL, 0, intf); 849 } 850 851 static void npc_update_flow(struct rvu *rvu, struct mcam_entry *entry, 852 u64 features, struct flow_msg *pkt, 853 struct flow_msg *mask, 854 struct rvu_npc_mcam_rule *output, u8 intf, 855 int blkaddr) 856 { 857 u64 dmac_mask = ether_addr_to_u64(mask->dmac); 858 u64 smac_mask = ether_addr_to_u64(mask->smac); 859 u64 dmac_val = ether_addr_to_u64(pkt->dmac); 860 u64 smac_val = ether_addr_to_u64(pkt->smac); 861 struct flow_msg *opkt = &output->packet; 862 struct flow_msg *omask = &output->mask; 863 864 if (!features) 865 return; 866 867 /* For tcp/udp/sctp LTYPE should be present in entry */ 868 if (features & BIT_ULL(NPC_IPPROTO_TCP)) 869 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_TCP, 870 0, ~0ULL, 0, intf); 871 if (features & BIT_ULL(NPC_IPPROTO_UDP)) 872 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_UDP, 873 0, ~0ULL, 0, intf); 874 if (features & BIT_ULL(NPC_IPPROTO_SCTP)) 875 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_SCTP, 876 0, ~0ULL, 0, intf); 877 if (features & BIT_ULL(NPC_IPPROTO_ICMP)) 878 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_ICMP, 879 0, ~0ULL, 0, intf); 880 if (features & BIT_ULL(NPC_IPPROTO_ICMP6)) 881 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_ICMP6, 882 0, ~0ULL, 0, intf); 883 884 /* For AH, LTYPE should be present in entry */ 885 if (features & BIT_ULL(NPC_IPPROTO_AH)) 886 npc_update_entry(rvu, NPC_LD, entry, NPC_LT_LD_AH, 887 0, ~0ULL, 0, intf); 888 /* For ESP, LTYPE should be present in entry */ 889 if (features & BIT_ULL(NPC_IPPROTO_ESP)) 890 npc_update_entry(rvu, NPC_LE, entry, NPC_LT_LE_ESP, 891 0, ~0ULL, 0, intf); 892 893 if (features & BIT_ULL(NPC_LXMB)) { 894 output->lxmb = is_broadcast_ether_addr(pkt->dmac) ? 2 : 1; 895 npc_update_entry(rvu, NPC_LXMB, entry, output->lxmb, 0, 896 output->lxmb, 0, intf); 897 } 898 #define NPC_WRITE_FLOW(field, member, val_lo, val_hi, mask_lo, mask_hi) \ 899 do { \ 900 if (features & BIT_ULL((field))) { \ 901 npc_update_entry(rvu, (field), entry, (val_lo), (val_hi), \ 902 (mask_lo), (mask_hi), intf); \ 903 memcpy(&opkt->member, &pkt->member, sizeof(pkt->member)); \ 904 memcpy(&omask->member, &mask->member, sizeof(mask->member)); \ 905 } \ 906 } while (0) 907 908 NPC_WRITE_FLOW(NPC_DMAC, dmac, dmac_val, 0, dmac_mask, 0); 909 910 NPC_WRITE_FLOW(NPC_SMAC, smac, smac_val, 0, smac_mask, 0); 911 NPC_WRITE_FLOW(NPC_ETYPE, etype, ntohs(pkt->etype), 0, 912 ntohs(mask->etype), 0); 913 NPC_WRITE_FLOW(NPC_TOS, tos, pkt->tos, 0, mask->tos, 0); 914 NPC_WRITE_FLOW(NPC_IPFRAG_IPV4, ip_flag, pkt->ip_flag, 0, 915 mask->ip_flag, 0); 916 NPC_WRITE_FLOW(NPC_SIP_IPV4, ip4src, ntohl(pkt->ip4src), 0, 917 ntohl(mask->ip4src), 0); 918 NPC_WRITE_FLOW(NPC_DIP_IPV4, ip4dst, ntohl(pkt->ip4dst), 0, 919 ntohl(mask->ip4dst), 0); 920 NPC_WRITE_FLOW(NPC_SPORT_TCP, sport, ntohs(pkt->sport), 0, 921 ntohs(mask->sport), 0); 922 NPC_WRITE_FLOW(NPC_SPORT_UDP, sport, ntohs(pkt->sport), 0, 923 ntohs(mask->sport), 0); 924 NPC_WRITE_FLOW(NPC_DPORT_TCP, dport, ntohs(pkt->dport), 0, 925 ntohs(mask->dport), 0); 926 NPC_WRITE_FLOW(NPC_DPORT_UDP, dport, ntohs(pkt->dport), 0, 927 ntohs(mask->dport), 0); 928 NPC_WRITE_FLOW(NPC_SPORT_SCTP, sport, ntohs(pkt->sport), 0, 929 ntohs(mask->sport), 0); 930 NPC_WRITE_FLOW(NPC_DPORT_SCTP, dport, ntohs(pkt->dport), 0, 931 ntohs(mask->dport), 0); 932 933 NPC_WRITE_FLOW(NPC_OUTER_VID, vlan_tci, ntohs(pkt->vlan_tci), 0, 934 ntohs(mask->vlan_tci), 0); 935 936 NPC_WRITE_FLOW(NPC_IPFRAG_IPV6, next_header, pkt->next_header, 0, 937 mask->next_header, 0); 938 npc_update_ipv6_flow(rvu, entry, features, pkt, mask, output, intf); 939 npc_update_vlan_features(rvu, entry, features, intf); 940 941 npc_update_field_hash(rvu, intf, entry, blkaddr, features, 942 pkt, mask, opkt, omask); 943 } 944 945 static struct rvu_npc_mcam_rule *rvu_mcam_find_rule(struct npc_mcam *mcam, u16 entry) 946 { 947 struct rvu_npc_mcam_rule *iter; 948 949 mutex_lock(&mcam->lock); 950 list_for_each_entry(iter, &mcam->mcam_rules, list) { 951 if (iter->entry == entry) { 952 mutex_unlock(&mcam->lock); 953 return iter; 954 } 955 } 956 mutex_unlock(&mcam->lock); 957 958 return NULL; 959 } 960 961 static void rvu_mcam_add_rule(struct npc_mcam *mcam, 962 struct rvu_npc_mcam_rule *rule) 963 { 964 struct list_head *head = &mcam->mcam_rules; 965 struct rvu_npc_mcam_rule *iter; 966 967 mutex_lock(&mcam->lock); 968 list_for_each_entry(iter, &mcam->mcam_rules, list) { 969 if (iter->entry > rule->entry) 970 break; 971 head = &iter->list; 972 } 973 974 list_add(&rule->list, head); 975 mutex_unlock(&mcam->lock); 976 } 977 978 static void rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, 979 struct rvu_npc_mcam_rule *rule) 980 { 981 struct npc_mcam_oper_counter_req free_req = { 0 }; 982 struct msg_rsp free_rsp; 983 984 if (!rule->has_cntr) 985 return; 986 987 free_req.hdr.pcifunc = pcifunc; 988 free_req.cntr = rule->cntr; 989 990 rvu_mbox_handler_npc_mcam_free_counter(rvu, &free_req, &free_rsp); 991 rule->has_cntr = false; 992 } 993 994 static void rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, 995 struct rvu_npc_mcam_rule *rule, 996 struct npc_install_flow_rsp *rsp) 997 { 998 struct npc_mcam_alloc_counter_req cntr_req = { 0 }; 999 struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 }; 1000 int err; 1001 1002 cntr_req.hdr.pcifunc = pcifunc; 1003 cntr_req.contig = true; 1004 cntr_req.count = 1; 1005 1006 /* we try to allocate a counter to track the stats of this 1007 * rule. If counter could not be allocated then proceed 1008 * without counter because counters are limited than entries. 1009 */ 1010 err = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, 1011 &cntr_rsp); 1012 if (!err && cntr_rsp.count) { 1013 rule->cntr = cntr_rsp.cntr; 1014 rule->has_cntr = true; 1015 rsp->counter = rule->cntr; 1016 } else { 1017 rsp->counter = err; 1018 } 1019 } 1020 1021 static void npc_update_rx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf, 1022 struct mcam_entry *entry, 1023 struct npc_install_flow_req *req, 1024 u16 target, bool pf_set_vfs_mac) 1025 { 1026 struct rvu_switch *rswitch = &rvu->rswitch; 1027 struct nix_rx_action action; 1028 1029 if (rswitch->mode == DEVLINK_ESWITCH_MODE_SWITCHDEV && pf_set_vfs_mac) 1030 req->chan_mask = 0x0; /* Do not care channel */ 1031 1032 npc_update_entry(rvu, NPC_CHAN, entry, req->channel, 0, req->chan_mask, 1033 0, NIX_INTF_RX); 1034 1035 *(u64 *)&action = 0x00; 1036 action.pf_func = target; 1037 action.op = req->op; 1038 action.index = req->index; 1039 action.match_id = req->match_id; 1040 action.flow_key_alg = req->flow_key_alg; 1041 1042 if (req->op == NIX_RX_ACTION_DEFAULT) { 1043 if (pfvf->def_ucast_rule) { 1044 action = pfvf->def_ucast_rule->rx_action; 1045 } else { 1046 /* For profiles which do not extract DMAC, the default 1047 * unicast entry is unused. Hence modify action for the 1048 * requests which use same action as default unicast 1049 * entry 1050 */ 1051 *(u64 *)&action = 0; 1052 action.pf_func = target; 1053 action.op = NIX_RX_ACTIONOP_UCAST; 1054 } 1055 } 1056 1057 entry->action = *(u64 *)&action; 1058 1059 /* VTAG0 starts at 0th byte of LID_B. 1060 * VTAG1 starts at 4th byte of LID_B. 1061 */ 1062 entry->vtag_action = FIELD_PREP(RX_VTAG0_VALID_BIT, req->vtag0_valid) | 1063 FIELD_PREP(RX_VTAG0_TYPE_MASK, req->vtag0_type) | 1064 FIELD_PREP(RX_VTAG0_LID_MASK, NPC_LID_LB) | 1065 FIELD_PREP(RX_VTAG0_RELPTR_MASK, 0) | 1066 FIELD_PREP(RX_VTAG1_VALID_BIT, req->vtag1_valid) | 1067 FIELD_PREP(RX_VTAG1_TYPE_MASK, req->vtag1_type) | 1068 FIELD_PREP(RX_VTAG1_LID_MASK, NPC_LID_LB) | 1069 FIELD_PREP(RX_VTAG1_RELPTR_MASK, 4); 1070 } 1071 1072 static void npc_update_tx_entry(struct rvu *rvu, struct rvu_pfvf *pfvf, 1073 struct mcam_entry *entry, 1074 struct npc_install_flow_req *req, u16 target) 1075 { 1076 struct nix_tx_action action; 1077 u64 mask = ~0ULL; 1078 1079 /* If AF is installing then do not care about 1080 * PF_FUNC in Send Descriptor 1081 */ 1082 if (is_pffunc_af(req->hdr.pcifunc)) 1083 mask = 0; 1084 1085 npc_update_entry(rvu, NPC_PF_FUNC, entry, (__force u16)htons(target), 1086 0, mask, 0, NIX_INTF_TX); 1087 1088 *(u64 *)&action = 0x00; 1089 action.op = req->op; 1090 action.index = req->index; 1091 action.match_id = req->match_id; 1092 1093 entry->action = *(u64 *)&action; 1094 1095 /* VTAG0 starts at 0th byte of LID_B. 1096 * VTAG1 starts at 4th byte of LID_B. 1097 */ 1098 entry->vtag_action = FIELD_PREP(TX_VTAG0_DEF_MASK, req->vtag0_def) | 1099 FIELD_PREP(TX_VTAG0_OP_MASK, req->vtag0_op) | 1100 FIELD_PREP(TX_VTAG0_LID_MASK, NPC_LID_LA) | 1101 FIELD_PREP(TX_VTAG0_RELPTR_MASK, 20) | 1102 FIELD_PREP(TX_VTAG1_DEF_MASK, req->vtag1_def) | 1103 FIELD_PREP(TX_VTAG1_OP_MASK, req->vtag1_op) | 1104 FIELD_PREP(TX_VTAG1_LID_MASK, NPC_LID_LA) | 1105 FIELD_PREP(TX_VTAG1_RELPTR_MASK, 24); 1106 } 1107 1108 static int npc_install_flow(struct rvu *rvu, int blkaddr, u16 target, 1109 int nixlf, struct rvu_pfvf *pfvf, 1110 struct npc_install_flow_req *req, 1111 struct npc_install_flow_rsp *rsp, bool enable, 1112 bool pf_set_vfs_mac) 1113 { 1114 struct rvu_npc_mcam_rule *def_ucast_rule = pfvf->def_ucast_rule; 1115 u64 features, installed_features, missing_features = 0; 1116 struct npc_mcam_write_entry_req write_req = { 0 }; 1117 struct npc_mcam *mcam = &rvu->hw->mcam; 1118 struct rvu_npc_mcam_rule dummy = { 0 }; 1119 struct rvu_npc_mcam_rule *rule; 1120 u16 owner = req->hdr.pcifunc; 1121 struct msg_rsp write_rsp; 1122 struct mcam_entry *entry; 1123 bool new = false; 1124 u16 entry_index; 1125 int err; 1126 1127 installed_features = req->features; 1128 features = req->features; 1129 entry = &write_req.entry_data; 1130 entry_index = req->entry; 1131 1132 npc_update_flow(rvu, entry, features, &req->packet, &req->mask, &dummy, 1133 req->intf, blkaddr); 1134 1135 if (is_npc_intf_rx(req->intf)) 1136 npc_update_rx_entry(rvu, pfvf, entry, req, target, pf_set_vfs_mac); 1137 else 1138 npc_update_tx_entry(rvu, pfvf, entry, req, target); 1139 1140 /* Default unicast rules do not exist for TX */ 1141 if (is_npc_intf_tx(req->intf)) 1142 goto find_rule; 1143 1144 if (req->default_rule) { 1145 entry_index = npc_get_nixlf_mcam_index(mcam, target, nixlf, 1146 NIXLF_UCAST_ENTRY); 1147 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, entry_index); 1148 } 1149 1150 /* update mcam entry with default unicast rule attributes */ 1151 if (def_ucast_rule && (req->default_rule && req->append)) { 1152 missing_features = (def_ucast_rule->features ^ features) & 1153 def_ucast_rule->features; 1154 if (missing_features) 1155 npc_update_flow(rvu, entry, missing_features, 1156 &def_ucast_rule->packet, 1157 &def_ucast_rule->mask, 1158 &dummy, req->intf, 1159 blkaddr); 1160 installed_features = req->features | missing_features; 1161 } 1162 1163 find_rule: 1164 rule = rvu_mcam_find_rule(mcam, entry_index); 1165 if (!rule) { 1166 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 1167 if (!rule) 1168 return -ENOMEM; 1169 new = true; 1170 } 1171 1172 /* allocate new counter if rule has no counter */ 1173 if (!req->default_rule && req->set_cntr && !rule->has_cntr) 1174 rvu_mcam_add_counter_to_rule(rvu, owner, rule, rsp); 1175 1176 /* if user wants to delete an existing counter for a rule then 1177 * free the counter 1178 */ 1179 if (!req->set_cntr && rule->has_cntr) 1180 rvu_mcam_remove_counter_from_rule(rvu, owner, rule); 1181 1182 write_req.hdr.pcifunc = owner; 1183 1184 /* AF owns the default rules so change the owner just to relax 1185 * the checks in rvu_mbox_handler_npc_mcam_write_entry 1186 */ 1187 if (req->default_rule) 1188 write_req.hdr.pcifunc = 0; 1189 1190 write_req.entry = entry_index; 1191 write_req.intf = req->intf; 1192 write_req.enable_entry = (u8)enable; 1193 /* if counter is available then clear and use it */ 1194 if (req->set_cntr && rule->has_cntr) { 1195 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(rule->cntr), 0x00); 1196 write_req.set_cntr = 1; 1197 write_req.cntr = rule->cntr; 1198 } 1199 1200 /* update rule */ 1201 memcpy(&rule->packet, &dummy.packet, sizeof(rule->packet)); 1202 memcpy(&rule->mask, &dummy.mask, sizeof(rule->mask)); 1203 rule->entry = entry_index; 1204 memcpy(&rule->rx_action, &entry->action, sizeof(struct nix_rx_action)); 1205 if (is_npc_intf_tx(req->intf)) 1206 memcpy(&rule->tx_action, &entry->action, 1207 sizeof(struct nix_tx_action)); 1208 rule->vtag_action = entry->vtag_action; 1209 rule->features = installed_features; 1210 rule->default_rule = req->default_rule; 1211 rule->owner = owner; 1212 rule->enable = enable; 1213 rule->chan_mask = write_req.entry_data.kw_mask[0] & NPC_KEX_CHAN_MASK; 1214 rule->chan = write_req.entry_data.kw[0] & NPC_KEX_CHAN_MASK; 1215 rule->chan &= rule->chan_mask; 1216 rule->lxmb = dummy.lxmb; 1217 if (is_npc_intf_tx(req->intf)) 1218 rule->intf = pfvf->nix_tx_intf; 1219 else 1220 rule->intf = pfvf->nix_rx_intf; 1221 1222 if (new) 1223 rvu_mcam_add_rule(mcam, rule); 1224 if (req->default_rule) 1225 pfvf->def_ucast_rule = rule; 1226 1227 /* write to mcam entry registers */ 1228 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, 1229 &write_rsp); 1230 if (err) { 1231 rvu_mcam_remove_counter_from_rule(rvu, owner, rule); 1232 if (new) { 1233 list_del(&rule->list); 1234 kfree(rule); 1235 } 1236 return err; 1237 } 1238 1239 /* VF's MAC address is being changed via PF */ 1240 if (pf_set_vfs_mac) { 1241 ether_addr_copy(pfvf->default_mac, req->packet.dmac); 1242 ether_addr_copy(pfvf->mac_addr, req->packet.dmac); 1243 set_bit(PF_SET_VF_MAC, &pfvf->flags); 1244 } 1245 1246 if (test_bit(PF_SET_VF_CFG, &pfvf->flags) && 1247 req->vtag0_type == NIX_AF_LFX_RX_VTAG_TYPE7) 1248 rule->vfvlan_cfg = true; 1249 1250 if (is_npc_intf_rx(req->intf) && req->match_id && 1251 (req->op == NIX_RX_ACTIONOP_UCAST || req->op == NIX_RX_ACTIONOP_RSS)) 1252 return rvu_nix_setup_ratelimit_aggr(rvu, req->hdr.pcifunc, 1253 req->index, req->match_id); 1254 1255 return 0; 1256 } 1257 1258 int rvu_mbox_handler_npc_install_flow(struct rvu *rvu, 1259 struct npc_install_flow_req *req, 1260 struct npc_install_flow_rsp *rsp) 1261 { 1262 bool from_vf = !!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK); 1263 struct rvu_switch *rswitch = &rvu->rswitch; 1264 int blkaddr, nixlf, err; 1265 struct rvu_pfvf *pfvf; 1266 bool pf_set_vfs_mac = false; 1267 bool enable = true; 1268 u16 target; 1269 1270 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1271 if (blkaddr < 0) { 1272 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 1273 return NPC_MCAM_INVALID_REQ; 1274 } 1275 1276 if (!is_npc_interface_valid(rvu, req->intf)) 1277 return NPC_FLOW_INTF_INVALID; 1278 1279 /* If DMAC is not extracted in MKEX, rules installed by AF 1280 * can rely on L2MB bit set by hardware protocol checker for 1281 * broadcast and multicast addresses. 1282 */ 1283 if (npc_check_field(rvu, blkaddr, NPC_DMAC, req->intf)) 1284 goto process_flow; 1285 1286 if (is_pffunc_af(req->hdr.pcifunc) && 1287 req->features & BIT_ULL(NPC_DMAC)) { 1288 if (is_unicast_ether_addr(req->packet.dmac)) { 1289 dev_warn(rvu->dev, 1290 "%s: mkex profile does not support ucast flow\n", 1291 __func__); 1292 return NPC_FLOW_NOT_SUPPORTED; 1293 } 1294 1295 if (!npc_is_field_present(rvu, NPC_LXMB, req->intf)) { 1296 dev_warn(rvu->dev, 1297 "%s: mkex profile does not support bcast/mcast flow", 1298 __func__); 1299 return NPC_FLOW_NOT_SUPPORTED; 1300 } 1301 1302 /* Modify feature to use LXMB instead of DMAC */ 1303 req->features &= ~BIT_ULL(NPC_DMAC); 1304 req->features |= BIT_ULL(NPC_LXMB); 1305 } 1306 1307 process_flow: 1308 if (from_vf && req->default_rule) 1309 return NPC_FLOW_VF_PERM_DENIED; 1310 1311 /* Each PF/VF info is maintained in struct rvu_pfvf. 1312 * rvu_pfvf for the target PF/VF needs to be retrieved 1313 * hence modify pcifunc accordingly. 1314 */ 1315 1316 /* AF installing for a PF/VF */ 1317 if (!req->hdr.pcifunc) 1318 target = req->vf; 1319 /* PF installing for its VF */ 1320 else if (!from_vf && req->vf) { 1321 target = (req->hdr.pcifunc & ~RVU_PFVF_FUNC_MASK) | req->vf; 1322 pf_set_vfs_mac = req->default_rule && 1323 (req->features & BIT_ULL(NPC_DMAC)); 1324 } 1325 /* msg received from PF/VF */ 1326 else 1327 target = req->hdr.pcifunc; 1328 1329 /* ignore chan_mask in case pf func is not AF, revisit later */ 1330 if (!is_pffunc_af(req->hdr.pcifunc)) 1331 req->chan_mask = 0xFFF; 1332 1333 err = npc_check_unsupported_flows(rvu, req->features, req->intf); 1334 if (err) 1335 return NPC_FLOW_NOT_SUPPORTED; 1336 1337 pfvf = rvu_get_pfvf(rvu, target); 1338 1339 /* PF installing for its VF */ 1340 if (req->hdr.pcifunc && !from_vf && req->vf) 1341 set_bit(PF_SET_VF_CFG, &pfvf->flags); 1342 1343 /* update req destination mac addr */ 1344 if ((req->features & BIT_ULL(NPC_DMAC)) && is_npc_intf_rx(req->intf) && 1345 is_zero_ether_addr(req->packet.dmac)) { 1346 ether_addr_copy(req->packet.dmac, pfvf->mac_addr); 1347 eth_broadcast_addr((u8 *)&req->mask.dmac); 1348 } 1349 1350 /* Proceed if NIXLF is attached or not for TX rules */ 1351 err = nix_get_nixlf(rvu, target, &nixlf, NULL); 1352 if (err && is_npc_intf_rx(req->intf) && !pf_set_vfs_mac) 1353 return NPC_FLOW_NO_NIXLF; 1354 1355 /* don't enable rule when nixlf not attached or initialized */ 1356 if (!(is_nixlf_attached(rvu, target) && 1357 test_bit(NIXLF_INITIALIZED, &pfvf->flags))) 1358 enable = false; 1359 1360 /* Packets reaching NPC in Tx path implies that a 1361 * NIXLF is properly setup and transmitting. 1362 * Hence rules can be enabled for Tx. 1363 */ 1364 if (is_npc_intf_tx(req->intf)) 1365 enable = true; 1366 1367 /* Do not allow requests from uninitialized VFs */ 1368 if (from_vf && !enable) 1369 return NPC_FLOW_VF_NOT_INIT; 1370 1371 /* PF sets VF mac & VF NIXLF is not attached, update the mac addr */ 1372 if (pf_set_vfs_mac && !enable) { 1373 ether_addr_copy(pfvf->default_mac, req->packet.dmac); 1374 ether_addr_copy(pfvf->mac_addr, req->packet.dmac); 1375 set_bit(PF_SET_VF_MAC, &pfvf->flags); 1376 return 0; 1377 } 1378 1379 mutex_lock(&rswitch->switch_lock); 1380 err = npc_install_flow(rvu, blkaddr, target, nixlf, pfvf, 1381 req, rsp, enable, pf_set_vfs_mac); 1382 mutex_unlock(&rswitch->switch_lock); 1383 1384 return err; 1385 } 1386 1387 static int npc_delete_flow(struct rvu *rvu, struct rvu_npc_mcam_rule *rule, 1388 u16 pcifunc) 1389 { 1390 struct npc_mcam_ena_dis_entry_req dis_req = { 0 }; 1391 struct msg_rsp dis_rsp; 1392 1393 if (rule->default_rule) 1394 return 0; 1395 1396 if (rule->has_cntr) 1397 rvu_mcam_remove_counter_from_rule(rvu, pcifunc, rule); 1398 1399 dis_req.hdr.pcifunc = pcifunc; 1400 dis_req.entry = rule->entry; 1401 1402 list_del(&rule->list); 1403 kfree(rule); 1404 1405 return rvu_mbox_handler_npc_mcam_dis_entry(rvu, &dis_req, &dis_rsp); 1406 } 1407 1408 int rvu_mbox_handler_npc_delete_flow(struct rvu *rvu, 1409 struct npc_delete_flow_req *req, 1410 struct msg_rsp *rsp) 1411 { 1412 struct npc_mcam *mcam = &rvu->hw->mcam; 1413 struct rvu_npc_mcam_rule *iter, *tmp; 1414 u16 pcifunc = req->hdr.pcifunc; 1415 struct list_head del_list; 1416 1417 INIT_LIST_HEAD(&del_list); 1418 1419 mutex_lock(&mcam->lock); 1420 list_for_each_entry_safe(iter, tmp, &mcam->mcam_rules, list) { 1421 if (iter->owner == pcifunc) { 1422 /* All rules */ 1423 if (req->all) { 1424 list_move_tail(&iter->list, &del_list); 1425 /* Range of rules */ 1426 } else if (req->end && iter->entry >= req->start && 1427 iter->entry <= req->end) { 1428 list_move_tail(&iter->list, &del_list); 1429 /* single rule */ 1430 } else if (req->entry == iter->entry) { 1431 list_move_tail(&iter->list, &del_list); 1432 break; 1433 } 1434 } 1435 } 1436 mutex_unlock(&mcam->lock); 1437 1438 list_for_each_entry_safe(iter, tmp, &del_list, list) { 1439 u16 entry = iter->entry; 1440 1441 /* clear the mcam entry target pcifunc */ 1442 mcam->entry2target_pffunc[entry] = 0x0; 1443 if (npc_delete_flow(rvu, iter, pcifunc)) 1444 dev_err(rvu->dev, "rule deletion failed for entry:%u", 1445 entry); 1446 } 1447 1448 return 0; 1449 } 1450 1451 static int npc_update_dmac_value(struct rvu *rvu, int npcblkaddr, 1452 struct rvu_npc_mcam_rule *rule, 1453 struct rvu_pfvf *pfvf) 1454 { 1455 struct npc_mcam_write_entry_req write_req = { 0 }; 1456 struct mcam_entry *entry = &write_req.entry_data; 1457 struct npc_mcam *mcam = &rvu->hw->mcam; 1458 struct msg_rsp rsp; 1459 u8 intf, enable; 1460 int err; 1461 1462 ether_addr_copy(rule->packet.dmac, pfvf->mac_addr); 1463 1464 npc_read_mcam_entry(rvu, mcam, npcblkaddr, rule->entry, 1465 entry, &intf, &enable); 1466 1467 npc_update_entry(rvu, NPC_DMAC, entry, 1468 ether_addr_to_u64(pfvf->mac_addr), 0, 1469 0xffffffffffffull, 0, intf); 1470 1471 write_req.hdr.pcifunc = rule->owner; 1472 write_req.entry = rule->entry; 1473 write_req.intf = pfvf->nix_rx_intf; 1474 1475 mutex_unlock(&mcam->lock); 1476 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &write_req, &rsp); 1477 mutex_lock(&mcam->lock); 1478 1479 return err; 1480 } 1481 1482 void npc_mcam_enable_flows(struct rvu *rvu, u16 target) 1483 { 1484 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, target); 1485 struct rvu_npc_mcam_rule *def_ucast_rule; 1486 struct npc_mcam *mcam = &rvu->hw->mcam; 1487 struct rvu_npc_mcam_rule *rule; 1488 int blkaddr, bank, index; 1489 u64 def_action; 1490 1491 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1492 if (blkaddr < 0) 1493 return; 1494 1495 def_ucast_rule = pfvf->def_ucast_rule; 1496 1497 mutex_lock(&mcam->lock); 1498 list_for_each_entry(rule, &mcam->mcam_rules, list) { 1499 if (is_npc_intf_rx(rule->intf) && 1500 rule->rx_action.pf_func == target && !rule->enable) { 1501 if (rule->default_rule) { 1502 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1503 rule->entry, true); 1504 rule->enable = true; 1505 continue; 1506 } 1507 1508 if (rule->vfvlan_cfg) 1509 npc_update_dmac_value(rvu, blkaddr, rule, pfvf); 1510 1511 if (rule->rx_action.op == NIX_RX_ACTION_DEFAULT) { 1512 if (!def_ucast_rule) 1513 continue; 1514 /* Use default unicast entry action */ 1515 rule->rx_action = def_ucast_rule->rx_action; 1516 def_action = *(u64 *)&def_ucast_rule->rx_action; 1517 bank = npc_get_bank(mcam, rule->entry); 1518 rvu_write64(rvu, blkaddr, 1519 NPC_AF_MCAMEX_BANKX_ACTION 1520 (rule->entry, bank), def_action); 1521 } 1522 1523 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1524 rule->entry, true); 1525 rule->enable = true; 1526 } 1527 } 1528 1529 /* Enable MCAM entries installed by PF with target as VF pcifunc */ 1530 for (index = 0; index < mcam->bmap_entries; index++) { 1531 if (mcam->entry2target_pffunc[index] == target) 1532 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1533 index, true); 1534 } 1535 mutex_unlock(&mcam->lock); 1536 } 1537 1538 void npc_mcam_disable_flows(struct rvu *rvu, u16 target) 1539 { 1540 struct npc_mcam *mcam = &rvu->hw->mcam; 1541 int blkaddr, index; 1542 1543 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1544 if (blkaddr < 0) 1545 return; 1546 1547 mutex_lock(&mcam->lock); 1548 /* Disable MCAM entries installed by PF with target as VF pcifunc */ 1549 for (index = 0; index < mcam->bmap_entries; index++) { 1550 if (mcam->entry2target_pffunc[index] == target) 1551 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1552 index, false); 1553 } 1554 mutex_unlock(&mcam->lock); 1555 } 1556 1557 /* single drop on non hit rule starting from 0th index. This an extension 1558 * to RPM mac filter to support more rules. 1559 */ 1560 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 1561 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 1562 u64 bcast_mcast_val, u64 bcast_mcast_mask) 1563 { 1564 struct npc_mcam_alloc_counter_req cntr_req = { 0 }; 1565 struct npc_mcam_alloc_counter_rsp cntr_rsp = { 0 }; 1566 struct npc_mcam_write_entry_req req = { 0 }; 1567 struct npc_mcam *mcam = &rvu->hw->mcam; 1568 struct rvu_npc_mcam_rule *rule; 1569 struct msg_rsp rsp; 1570 bool enabled; 1571 int blkaddr; 1572 int err; 1573 1574 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1575 if (blkaddr < 0) { 1576 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 1577 return -ENODEV; 1578 } 1579 1580 /* Bail out if no exact match support */ 1581 if (!rvu_npc_exact_has_match_table(rvu)) { 1582 dev_info(rvu->dev, "%s: No support for exact match feature\n", __func__); 1583 return -EINVAL; 1584 } 1585 1586 /* If 0th entry is already used, return err */ 1587 enabled = is_mcam_entry_enabled(rvu, mcam, blkaddr, mcam_idx); 1588 if (enabled) { 1589 dev_err(rvu->dev, "%s: failed to add single drop on non hit rule at %d th index\n", 1590 __func__, mcam_idx); 1591 return -EINVAL; 1592 } 1593 1594 /* Add this entry to mcam rules list */ 1595 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 1596 if (!rule) 1597 return -ENOMEM; 1598 1599 /* Disable rule by default. Enable rule when first dmac filter is 1600 * installed 1601 */ 1602 rule->enable = false; 1603 rule->chan = chan_val; 1604 rule->chan_mask = chan_mask; 1605 rule->entry = mcam_idx; 1606 rvu_mcam_add_rule(mcam, rule); 1607 1608 /* Reserve slot 0 */ 1609 npc_mcam_rsrcs_reserve(rvu, blkaddr, mcam_idx); 1610 1611 /* Allocate counter for this single drop on non hit rule */ 1612 cntr_req.hdr.pcifunc = 0; /* AF request */ 1613 cntr_req.contig = true; 1614 cntr_req.count = 1; 1615 err = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp); 1616 if (err) { 1617 dev_err(rvu->dev, "%s: Err to allocate cntr for drop rule (err=%d)\n", 1618 __func__, err); 1619 return -EFAULT; 1620 } 1621 *counter_idx = cntr_rsp.cntr; 1622 1623 /* Fill in fields for this mcam entry */ 1624 npc_update_entry(rvu, NPC_EXACT_RESULT, &req.entry_data, exact_val, 0, 1625 exact_mask, 0, NIX_INTF_RX); 1626 npc_update_entry(rvu, NPC_CHAN, &req.entry_data, chan_val, 0, 1627 chan_mask, 0, NIX_INTF_RX); 1628 npc_update_entry(rvu, NPC_LXMB, &req.entry_data, bcast_mcast_val, 0, 1629 bcast_mcast_mask, 0, NIX_INTF_RX); 1630 1631 req.intf = NIX_INTF_RX; 1632 req.set_cntr = true; 1633 req.cntr = cntr_rsp.cntr; 1634 req.entry = mcam_idx; 1635 1636 err = rvu_mbox_handler_npc_mcam_write_entry(rvu, &req, &rsp); 1637 if (err) { 1638 dev_err(rvu->dev, "%s: Installation of single drop on non hit rule at %d failed\n", 1639 __func__, mcam_idx); 1640 return err; 1641 } 1642 1643 dev_err(rvu->dev, "%s: Installed single drop on non hit rule at %d, cntr=%d\n", 1644 __func__, mcam_idx, req.cntr); 1645 1646 /* disable entry at Bank 0, index 0 */ 1647 npc_enable_mcam_entry(rvu, mcam, blkaddr, mcam_idx, false); 1648 1649 return 0; 1650 } 1651 1652 int rvu_mbox_handler_npc_get_field_status(struct rvu *rvu, 1653 struct npc_get_field_status_req *req, 1654 struct npc_get_field_status_rsp *rsp) 1655 { 1656 int blkaddr; 1657 1658 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1659 if (blkaddr < 0) 1660 return NPC_MCAM_INVALID_REQ; 1661 1662 if (!is_npc_interface_valid(rvu, req->intf)) 1663 return NPC_FLOW_INTF_INVALID; 1664 1665 if (npc_check_field(rvu, blkaddr, req->field, req->intf)) 1666 rsp->enable = 1; 1667 1668 return 0; 1669 } 1670