1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 12 #include "rvu_struct.h" 13 #include "rvu_reg.h" 14 #include "rvu.h" 15 #include "npc.h" 16 #include "cgx.h" 17 #include "npc_profile.h" 18 #include "rvu_npc_hash.h" 19 20 #define RSVD_MCAM_ENTRIES_PER_PF 3 /* Broadcast, Promisc and AllMulticast */ 21 #define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */ 22 23 #define NPC_PARSE_RESULT_DMAC_OFFSET 8 24 #define NPC_HW_TSTAMP_OFFSET 8ULL 25 #define NPC_KEX_CHAN_MASK 0xFFFULL 26 #define NPC_KEX_PF_FUNC_MASK 0xFFFFULL 27 28 #define ALIGN_8B_CEIL(__a) (((__a) + 7) & (-8)) 29 30 static const char def_pfl_name[] = "default"; 31 32 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, 33 int blkaddr, u16 pcifunc); 34 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, 35 u16 pcifunc); 36 37 bool is_npc_intf_tx(u8 intf) 38 { 39 return !!(intf & 0x1); 40 } 41 42 bool is_npc_intf_rx(u8 intf) 43 { 44 return !(intf & 0x1); 45 } 46 47 bool is_npc_interface_valid(struct rvu *rvu, u8 intf) 48 { 49 struct rvu_hwinfo *hw = rvu->hw; 50 51 return intf < hw->npc_intfs; 52 } 53 54 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena) 55 { 56 /* Due to a HW issue in these silicon versions, parse nibble enable 57 * configuration has to be identical for both Rx and Tx interfaces. 58 */ 59 if (is_rvu_96xx_B0(rvu)) 60 return nibble_ena; 61 return 0; 62 } 63 64 static int npc_mcam_verify_pf_func(struct rvu *rvu, 65 struct mcam_entry *entry_data, u8 intf, 66 u16 pcifunc) 67 { 68 u16 pf_func, pf_func_mask; 69 70 if (is_npc_intf_rx(intf)) 71 return 0; 72 73 pf_func_mask = (entry_data->kw_mask[0] >> 32) & 74 NPC_KEX_PF_FUNC_MASK; 75 pf_func = (entry_data->kw[0] >> 32) & NPC_KEX_PF_FUNC_MASK; 76 77 pf_func = be16_to_cpu((__force __be16)pf_func); 78 if (pf_func_mask != NPC_KEX_PF_FUNC_MASK || 79 ((pf_func & ~RVU_PFVF_FUNC_MASK) != 80 (pcifunc & ~RVU_PFVF_FUNC_MASK))) 81 return -EINVAL; 82 83 return 0; 84 } 85 86 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf) 87 { 88 int blkaddr; 89 u64 val = 0; 90 91 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 92 if (blkaddr < 0) 93 return; 94 95 /* Config CPI base for the PKIND */ 96 val = pkind | 1ULL << 62; 97 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); 98 } 99 100 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf) 101 { 102 struct npc_pkind *pkind = &rvu->hw->pkind; 103 u32 map; 104 int i; 105 106 for (i = 0; i < pkind->rsrc.max; i++) { 107 map = pkind->pfchan_map[i]; 108 if (((map >> 16) & 0x3F) == pf) 109 return i; 110 } 111 return -1; 112 } 113 114 #define NPC_AF_ACTION0_PTR_ADVANCE GENMASK_ULL(27, 20) 115 116 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable) 117 { 118 int pkind, blkaddr; 119 u64 val; 120 121 pkind = rvu_npc_get_pkind(rvu, pf); 122 if (pkind < 0) { 123 dev_err(rvu->dev, "%s: pkind not mapped\n", __func__); 124 return -EINVAL; 125 } 126 127 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc); 128 if (blkaddr < 0) { 129 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 130 return -EINVAL; 131 } 132 133 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind)); 134 val &= ~NPC_AF_ACTION0_PTR_ADVANCE; 135 /* If timestamp is enabled then configure NPC to shift 8 bytes */ 136 if (enable) 137 val |= FIELD_PREP(NPC_AF_ACTION0_PTR_ADVANCE, 138 NPC_HW_TSTAMP_OFFSET); 139 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val); 140 141 return 0; 142 } 143 144 static int npc_get_ucast_mcam_index(struct npc_mcam *mcam, u16 pcifunc, 145 int nixlf) 146 { 147 struct rvu_hwinfo *hw = container_of(mcam, struct rvu_hwinfo, mcam); 148 struct rvu *rvu = hw->rvu; 149 int blkaddr = 0, max = 0; 150 struct rvu_block *block; 151 struct rvu_pfvf *pfvf; 152 153 pfvf = rvu_get_pfvf(rvu, pcifunc); 154 /* Given a PF/VF and NIX LF number calculate the unicast mcam 155 * entry index based on the NIX block assigned to the PF/VF. 156 */ 157 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 158 while (blkaddr) { 159 if (pfvf->nix_blkaddr == blkaddr) 160 break; 161 block = &rvu->hw->block[blkaddr]; 162 max += block->lf.max; 163 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 164 } 165 166 return mcam->nixlf_offset + (max + nixlf) * RSVD_MCAM_ENTRIES_PER_NIXLF; 167 } 168 169 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, 170 u16 pcifunc, int nixlf, int type) 171 { 172 int pf = rvu_get_pf(pcifunc); 173 int index; 174 175 /* Check if this is for a PF */ 176 if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) { 177 /* Reserved entries exclude PF0 */ 178 pf--; 179 index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF); 180 /* Broadcast address matching entry should be first so 181 * that the packet can be replicated to all VFs. 182 */ 183 if (type == NIXLF_BCAST_ENTRY) 184 return index; 185 else if (type == NIXLF_ALLMULTI_ENTRY) 186 return index + 1; 187 else if (type == NIXLF_PROMISC_ENTRY) 188 return index + 2; 189 } 190 191 return npc_get_ucast_mcam_index(mcam, pcifunc, nixlf); 192 } 193 194 int npc_get_bank(struct npc_mcam *mcam, int index) 195 { 196 int bank = index / mcam->banksize; 197 198 /* 0,1 & 2,3 banks are combined for this keysize */ 199 if (mcam->keysize == NPC_MCAM_KEY_X2) 200 return bank ? 2 : 0; 201 202 return bank; 203 } 204 205 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, 206 int blkaddr, int index) 207 { 208 int bank = npc_get_bank(mcam, index); 209 u64 cfg; 210 211 index &= (mcam->banksize - 1); 212 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank)); 213 return (cfg & 1); 214 } 215 216 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 217 int blkaddr, int index, bool enable) 218 { 219 int bank = npc_get_bank(mcam, index); 220 int actbank = bank; 221 222 index &= (mcam->banksize - 1); 223 for (; bank < (actbank + mcam->banks_per_entry); bank++) { 224 rvu_write64(rvu, blkaddr, 225 NPC_AF_MCAMEX_BANKX_CFG(index, bank), 226 enable ? 1 : 0); 227 } 228 } 229 230 static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 231 int blkaddr, int index) 232 { 233 int bank = npc_get_bank(mcam, index); 234 int actbank = bank; 235 236 index &= (mcam->banksize - 1); 237 for (; bank < (actbank + mcam->banks_per_entry); bank++) { 238 rvu_write64(rvu, blkaddr, 239 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0); 240 rvu_write64(rvu, blkaddr, 241 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0); 242 243 rvu_write64(rvu, blkaddr, 244 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0); 245 rvu_write64(rvu, blkaddr, 246 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0); 247 248 rvu_write64(rvu, blkaddr, 249 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0); 250 rvu_write64(rvu, blkaddr, 251 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0); 252 } 253 } 254 255 static void npc_get_keyword(struct mcam_entry *entry, int idx, 256 u64 *cam0, u64 *cam1) 257 { 258 u64 kw_mask = 0x00; 259 260 #define CAM_MASK(n) (BIT_ULL(n) - 1) 261 262 /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and 263 * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1. 264 * 265 * Also, only 48 bits of BANKX_CAMX_W1 are valid. 266 */ 267 switch (idx) { 268 case 0: 269 /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */ 270 *cam1 = entry->kw[0]; 271 kw_mask = entry->kw_mask[0]; 272 break; 273 case 1: 274 /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */ 275 *cam1 = entry->kw[1] & CAM_MASK(48); 276 kw_mask = entry->kw_mask[1] & CAM_MASK(48); 277 break; 278 case 2: 279 /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48> 280 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0> 281 */ 282 *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16); 283 *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16); 284 kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16); 285 kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16); 286 break; 287 case 3: 288 /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48> 289 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0> 290 */ 291 *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16); 292 *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16); 293 kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16); 294 kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16); 295 break; 296 case 4: 297 /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32> 298 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0> 299 */ 300 *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32); 301 *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32); 302 kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32); 303 kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32); 304 break; 305 case 5: 306 /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32> 307 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0> 308 */ 309 *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32); 310 *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32); 311 kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32); 312 kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32); 313 break; 314 case 6: 315 /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16> 316 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0> 317 */ 318 *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48); 319 *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48); 320 kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48); 321 kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48); 322 break; 323 case 7: 324 /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */ 325 *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48); 326 kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48); 327 break; 328 } 329 330 *cam1 &= kw_mask; 331 *cam0 = ~*cam1 & kw_mask; 332 } 333 334 static void npc_fill_entryword(struct mcam_entry *entry, int idx, 335 u64 cam0, u64 cam1) 336 { 337 /* Similar to npc_get_keyword, but fills mcam_entry structure from 338 * CAM registers. 339 */ 340 switch (idx) { 341 case 0: 342 entry->kw[0] = cam1; 343 entry->kw_mask[0] = cam1 ^ cam0; 344 break; 345 case 1: 346 entry->kw[1] = cam1; 347 entry->kw_mask[1] = cam1 ^ cam0; 348 break; 349 case 2: 350 entry->kw[1] |= (cam1 & CAM_MASK(16)) << 48; 351 entry->kw[2] = (cam1 >> 16) & CAM_MASK(48); 352 entry->kw_mask[1] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48; 353 entry->kw_mask[2] = ((cam1 ^ cam0) >> 16) & CAM_MASK(48); 354 break; 355 case 3: 356 entry->kw[2] |= (cam1 & CAM_MASK(16)) << 48; 357 entry->kw[3] = (cam1 >> 16) & CAM_MASK(32); 358 entry->kw_mask[2] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48; 359 entry->kw_mask[3] = ((cam1 ^ cam0) >> 16) & CAM_MASK(32); 360 break; 361 case 4: 362 entry->kw[3] |= (cam1 & CAM_MASK(32)) << 32; 363 entry->kw[4] = (cam1 >> 32) & CAM_MASK(32); 364 entry->kw_mask[3] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32; 365 entry->kw_mask[4] = ((cam1 ^ cam0) >> 32) & CAM_MASK(32); 366 break; 367 case 5: 368 entry->kw[4] |= (cam1 & CAM_MASK(32)) << 32; 369 entry->kw[5] = (cam1 >> 32) & CAM_MASK(16); 370 entry->kw_mask[4] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32; 371 entry->kw_mask[5] = ((cam1 ^ cam0) >> 32) & CAM_MASK(16); 372 break; 373 case 6: 374 entry->kw[5] |= (cam1 & CAM_MASK(48)) << 16; 375 entry->kw[6] = (cam1 >> 48) & CAM_MASK(16); 376 entry->kw_mask[5] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16; 377 entry->kw_mask[6] = ((cam1 ^ cam0) >> 48) & CAM_MASK(16); 378 break; 379 case 7: 380 entry->kw[6] |= (cam1 & CAM_MASK(48)) << 16; 381 entry->kw_mask[6] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16; 382 break; 383 } 384 } 385 386 static u64 npc_get_default_entry_action(struct rvu *rvu, struct npc_mcam *mcam, 387 int blkaddr, u16 pf_func) 388 { 389 int bank, nixlf, index; 390 391 /* get ucast entry rule entry index */ 392 if (nix_get_nixlf(rvu, pf_func, &nixlf, NULL)) { 393 dev_err(rvu->dev, "%s: nixlf not attached to pcifunc:0x%x\n", 394 __func__, pf_func); 395 /* Action 0 is drop */ 396 return 0; 397 } 398 399 index = npc_get_nixlf_mcam_index(mcam, pf_func, nixlf, 400 NIXLF_UCAST_ENTRY); 401 bank = npc_get_bank(mcam, index); 402 index &= (mcam->banksize - 1); 403 404 return rvu_read64(rvu, blkaddr, 405 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 406 } 407 408 static void npc_fixup_vf_rule(struct rvu *rvu, struct npc_mcam *mcam, 409 int blkaddr, int index, struct mcam_entry *entry, 410 bool *enable) 411 { 412 struct rvu_npc_mcam_rule *rule; 413 u16 owner, target_func; 414 struct rvu_pfvf *pfvf; 415 u64 rx_action; 416 417 owner = mcam->entry2pfvf_map[index]; 418 target_func = (entry->action >> 4) & 0xffff; 419 /* do nothing when target is LBK/PF or owner is not PF */ 420 if (is_pffunc_af(owner) || is_afvf(target_func) || 421 (owner & RVU_PFVF_FUNC_MASK) || 422 !(target_func & RVU_PFVF_FUNC_MASK)) 423 return; 424 425 /* save entry2target_pffunc */ 426 pfvf = rvu_get_pfvf(rvu, target_func); 427 mcam->entry2target_pffunc[index] = target_func; 428 429 /* don't enable rule when nixlf not attached or initialized */ 430 if (!(is_nixlf_attached(rvu, target_func) && 431 test_bit(NIXLF_INITIALIZED, &pfvf->flags))) 432 *enable = false; 433 434 /* fix up not needed for the rules added by user(ntuple filters) */ 435 list_for_each_entry(rule, &mcam->mcam_rules, list) { 436 if (rule->entry == index) 437 return; 438 } 439 440 /* copy VF default entry action to the VF mcam entry */ 441 rx_action = npc_get_default_entry_action(rvu, mcam, blkaddr, 442 target_func); 443 if (rx_action) 444 entry->action = rx_action; 445 } 446 447 static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 448 int blkaddr, int index, u8 intf, 449 struct mcam_entry *entry, bool enable) 450 { 451 int bank = npc_get_bank(mcam, index); 452 int kw = 0, actbank, actindex; 453 u8 tx_intf_mask = ~intf & 0x3; 454 u8 tx_intf = intf; 455 u64 cam0, cam1; 456 457 actbank = bank; /* Save bank id, to set action later on */ 458 actindex = index; 459 index &= (mcam->banksize - 1); 460 461 /* Disable before mcam entry update */ 462 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false); 463 464 /* Clear mcam entry to avoid writes being suppressed by NPC */ 465 npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex); 466 467 /* CAM1 takes the comparison value and 468 * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'. 469 * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0 470 * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1 471 * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare. 472 */ 473 for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) { 474 /* Interface should be set in all banks */ 475 if (is_npc_intf_tx(intf)) { 476 /* Last bit must be set and rest don't care 477 * for TX interfaces 478 */ 479 tx_intf_mask = 0x1; 480 tx_intf = intf & tx_intf_mask; 481 tx_intf_mask = ~tx_intf & tx_intf_mask; 482 } 483 484 rvu_write64(rvu, blkaddr, 485 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 486 tx_intf); 487 rvu_write64(rvu, blkaddr, 488 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 489 tx_intf_mask); 490 491 /* Set the match key */ 492 npc_get_keyword(entry, kw, &cam0, &cam1); 493 rvu_write64(rvu, blkaddr, 494 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1); 495 rvu_write64(rvu, blkaddr, 496 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0); 497 498 npc_get_keyword(entry, kw + 1, &cam0, &cam1); 499 rvu_write64(rvu, blkaddr, 500 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1); 501 rvu_write64(rvu, blkaddr, 502 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0); 503 } 504 505 /* PF installing VF rule */ 506 if (is_npc_intf_rx(intf) && actindex < mcam->bmap_entries) 507 npc_fixup_vf_rule(rvu, mcam, blkaddr, actindex, entry, &enable); 508 509 /* Set 'action' */ 510 rvu_write64(rvu, blkaddr, 511 NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action); 512 513 /* Set TAG 'action' */ 514 rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank), 515 entry->vtag_action); 516 517 /* Enable the entry */ 518 if (enable) 519 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true); 520 } 521 522 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 523 int blkaddr, u16 src, 524 struct mcam_entry *entry, u8 *intf, u8 *ena) 525 { 526 int sbank = npc_get_bank(mcam, src); 527 int bank, kw = 0; 528 u64 cam0, cam1; 529 530 src &= (mcam->banksize - 1); 531 bank = sbank; 532 533 for (; bank < (sbank + mcam->banks_per_entry); bank++, kw = kw + 2) { 534 cam1 = rvu_read64(rvu, blkaddr, 535 NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1)); 536 cam0 = rvu_read64(rvu, blkaddr, 537 NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0)); 538 npc_fill_entryword(entry, kw, cam0, cam1); 539 540 cam1 = rvu_read64(rvu, blkaddr, 541 NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1)); 542 cam0 = rvu_read64(rvu, blkaddr, 543 NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0)); 544 npc_fill_entryword(entry, kw + 1, cam0, cam1); 545 } 546 547 entry->action = rvu_read64(rvu, blkaddr, 548 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank)); 549 entry->vtag_action = 550 rvu_read64(rvu, blkaddr, 551 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank)); 552 *intf = rvu_read64(rvu, blkaddr, 553 NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank, 1)) & 3; 554 *ena = rvu_read64(rvu, blkaddr, 555 NPC_AF_MCAMEX_BANKX_CFG(src, sbank)) & 1; 556 } 557 558 static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 559 int blkaddr, u16 src, u16 dest) 560 { 561 int dbank = npc_get_bank(mcam, dest); 562 int sbank = npc_get_bank(mcam, src); 563 u64 cfg, sreg, dreg; 564 int bank, i; 565 566 src &= (mcam->banksize - 1); 567 dest &= (mcam->banksize - 1); 568 569 /* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */ 570 for (bank = 0; bank < mcam->banks_per_entry; bank++) { 571 sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0); 572 dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0); 573 for (i = 0; i < 6; i++) { 574 cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8)); 575 rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg); 576 } 577 } 578 579 /* Copy action */ 580 cfg = rvu_read64(rvu, blkaddr, 581 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank)); 582 rvu_write64(rvu, blkaddr, 583 NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg); 584 585 /* Copy TAG action */ 586 cfg = rvu_read64(rvu, blkaddr, 587 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank)); 588 rvu_write64(rvu, blkaddr, 589 NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg); 590 591 /* Enable or disable */ 592 cfg = rvu_read64(rvu, blkaddr, 593 NPC_AF_MCAMEX_BANKX_CFG(src, sbank)); 594 rvu_write64(rvu, blkaddr, 595 NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg); 596 } 597 598 static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 599 int blkaddr, int index) 600 { 601 int bank = npc_get_bank(mcam, index); 602 603 index &= (mcam->banksize - 1); 604 return rvu_read64(rvu, blkaddr, 605 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 606 } 607 608 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 609 int nixlf, u64 chan, u8 *mac_addr) 610 { 611 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 612 struct npc_install_flow_req req = { 0 }; 613 struct npc_install_flow_rsp rsp = { 0 }; 614 struct npc_mcam *mcam = &rvu->hw->mcam; 615 struct nix_rx_action action = { 0 }; 616 int blkaddr, index; 617 618 /* AF's and SDP VFs work in promiscuous mode */ 619 if (is_afvf(pcifunc) || is_sdp_vf(pcifunc)) 620 return; 621 622 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 623 if (blkaddr < 0) 624 return; 625 626 /* Ucast rule should not be installed if DMAC 627 * extraction is not supported by the profile. 628 */ 629 if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf)) 630 return; 631 632 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 633 nixlf, NIXLF_UCAST_ENTRY); 634 635 /* Don't change the action if entry is already enabled 636 * Otherwise RSS action may get overwritten. 637 */ 638 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) { 639 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 640 blkaddr, index); 641 } else { 642 action.op = NIX_RX_ACTIONOP_UCAST; 643 action.pf_func = pcifunc; 644 } 645 646 req.default_rule = 1; 647 ether_addr_copy(req.packet.dmac, mac_addr); 648 eth_broadcast_addr((u8 *)&req.mask.dmac); 649 req.features = BIT_ULL(NPC_DMAC); 650 req.channel = chan; 651 req.chan_mask = 0xFFFU; 652 req.intf = pfvf->nix_rx_intf; 653 req.op = action.op; 654 req.hdr.pcifunc = 0; /* AF is requester */ 655 req.vf = action.pf_func; 656 req.index = action.index; 657 req.match_id = action.match_id; 658 req.flow_key_alg = action.flow_key_alg; 659 660 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 661 } 662 663 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 664 int nixlf, u64 chan, u8 chan_cnt) 665 { 666 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 667 struct npc_install_flow_req req = { 0 }; 668 struct npc_install_flow_rsp rsp = { 0 }; 669 struct npc_mcam *mcam = &rvu->hw->mcam; 670 struct rvu_hwinfo *hw = rvu->hw; 671 int blkaddr, ucast_idx, index; 672 struct nix_rx_action action = { 0 }; 673 u64 relaxed_mask; 674 u8 flow_key_alg; 675 676 if (!hw->cap.nix_rx_multicast && is_cgx_vf(rvu, pcifunc)) 677 return; 678 679 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 680 if (blkaddr < 0) 681 return; 682 683 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 684 nixlf, NIXLF_PROMISC_ENTRY); 685 686 if (is_cgx_vf(rvu, pcifunc)) 687 index = npc_get_nixlf_mcam_index(mcam, 688 pcifunc & ~RVU_PFVF_FUNC_MASK, 689 nixlf, NIXLF_PROMISC_ENTRY); 690 691 /* If the corresponding PF's ucast action is RSS, 692 * use the same action for promisc also 693 */ 694 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc, 695 nixlf, NIXLF_UCAST_ENTRY); 696 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx)) 697 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 698 blkaddr, ucast_idx); 699 700 if (action.op != NIX_RX_ACTIONOP_RSS) { 701 *(u64 *)&action = 0; 702 action.op = NIX_RX_ACTIONOP_UCAST; 703 } 704 705 flow_key_alg = action.flow_key_alg; 706 707 /* RX_ACTION set to MCAST for CGX PF's */ 708 if (hw->cap.nix_rx_multicast && pfvf->use_mce_list && 709 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 710 *(u64 *)&action = 0; 711 action.op = NIX_RX_ACTIONOP_MCAST; 712 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 713 action.index = pfvf->promisc_mce_idx; 714 } 715 716 /* For cn10k the upper two bits of the channel number are 717 * cpt channel number. with masking out these bits in the 718 * mcam entry, same entry used for NIX will allow packets 719 * received from cpt for parsing. 720 */ 721 if (!is_rvu_otx2(rvu)) { 722 req.chan_mask = NIX_CHAN_CPT_X2P_MASK; 723 } else { 724 req.chan_mask = 0xFFFU; 725 } 726 727 if (chan_cnt > 1) { 728 if (!is_power_of_2(chan_cnt)) { 729 dev_err(rvu->dev, 730 "%s: channel count more than 1, must be power of 2\n", __func__); 731 return; 732 } 733 relaxed_mask = GENMASK_ULL(BITS_PER_LONG_LONG - 1, 734 ilog2(chan_cnt)); 735 req.chan_mask &= relaxed_mask; 736 } 737 738 req.channel = chan; 739 req.intf = pfvf->nix_rx_intf; 740 req.entry = index; 741 req.op = action.op; 742 req.hdr.pcifunc = 0; /* AF is requester */ 743 req.vf = pcifunc; 744 req.index = action.index; 745 req.match_id = action.match_id; 746 req.flow_key_alg = flow_key_alg; 747 748 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 749 } 750 751 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, 752 int nixlf, bool enable) 753 { 754 struct npc_mcam *mcam = &rvu->hw->mcam; 755 int blkaddr, index; 756 757 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 758 if (blkaddr < 0) 759 return; 760 761 /* Get 'pcifunc' of PF device */ 762 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 763 764 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 765 nixlf, NIXLF_PROMISC_ENTRY); 766 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 767 } 768 769 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 770 int nixlf, u64 chan) 771 { 772 struct rvu_pfvf *pfvf; 773 struct npc_install_flow_req req = { 0 }; 774 struct npc_install_flow_rsp rsp = { 0 }; 775 struct npc_mcam *mcam = &rvu->hw->mcam; 776 struct rvu_hwinfo *hw = rvu->hw; 777 int blkaddr, index; 778 779 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 780 if (blkaddr < 0) 781 return; 782 783 /* Skip LBK VFs */ 784 if (is_afvf(pcifunc)) 785 return; 786 787 /* If pkt replication is not supported, 788 * then only PF is allowed to add a bcast match entry. 789 */ 790 if (!hw->cap.nix_rx_multicast && is_vf(pcifunc)) 791 return; 792 793 /* Get 'pcifunc' of PF device */ 794 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 795 pfvf = rvu_get_pfvf(rvu, pcifunc); 796 797 /* Bcast rule should not be installed if both DMAC 798 * and LXMB extraction is not supported by the profile. 799 */ 800 if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf) && 801 !npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), pfvf->nix_rx_intf)) 802 return; 803 804 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 805 nixlf, NIXLF_BCAST_ENTRY); 806 807 if (!hw->cap.nix_rx_multicast) { 808 /* Early silicon doesn't support pkt replication, 809 * so install entry with UCAST action, so that PF 810 * receives all broadcast packets. 811 */ 812 req.op = NIX_RX_ACTIONOP_UCAST; 813 } else { 814 req.op = NIX_RX_ACTIONOP_MCAST; 815 req.index = pfvf->bcast_mce_idx; 816 } 817 818 eth_broadcast_addr((u8 *)&req.packet.dmac); 819 eth_broadcast_addr((u8 *)&req.mask.dmac); 820 req.features = BIT_ULL(NPC_DMAC); 821 req.channel = chan; 822 req.chan_mask = 0xFFFU; 823 req.intf = pfvf->nix_rx_intf; 824 req.entry = index; 825 req.hdr.pcifunc = 0; /* AF is requester */ 826 req.vf = pcifunc; 827 828 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 829 } 830 831 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 832 bool enable) 833 { 834 struct npc_mcam *mcam = &rvu->hw->mcam; 835 int blkaddr, index; 836 837 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 838 if (blkaddr < 0) 839 return; 840 841 /* Get 'pcifunc' of PF device */ 842 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 843 844 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, 845 NIXLF_BCAST_ENTRY); 846 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 847 } 848 849 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 850 u64 chan) 851 { 852 struct npc_install_flow_req req = { 0 }; 853 struct npc_install_flow_rsp rsp = { 0 }; 854 struct npc_mcam *mcam = &rvu->hw->mcam; 855 struct rvu_hwinfo *hw = rvu->hw; 856 int blkaddr, ucast_idx, index; 857 u8 mac_addr[ETH_ALEN] = { 0 }; 858 struct nix_rx_action action = { 0 }; 859 struct rvu_pfvf *pfvf; 860 u8 flow_key_alg; 861 u16 vf_func; 862 863 /* Only CGX PF/VF can add allmulticast entry */ 864 if (is_afvf(pcifunc) && is_sdp_vf(pcifunc)) 865 return; 866 867 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 868 if (blkaddr < 0) 869 return; 870 871 /* Get 'pcifunc' of PF device */ 872 vf_func = pcifunc & RVU_PFVF_FUNC_MASK; 873 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 874 pfvf = rvu_get_pfvf(rvu, pcifunc); 875 876 /* Mcast rule should not be installed if both DMAC 877 * and LXMB extraction is not supported by the profile. 878 */ 879 if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf) && 880 !npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), pfvf->nix_rx_intf)) 881 return; 882 883 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 884 nixlf, NIXLF_ALLMULTI_ENTRY); 885 886 /* If the corresponding PF's ucast action is RSS, 887 * use the same action for multicast entry also 888 */ 889 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc, 890 nixlf, NIXLF_UCAST_ENTRY); 891 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx)) 892 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 893 blkaddr, ucast_idx); 894 895 flow_key_alg = action.flow_key_alg; 896 if (action.op != NIX_RX_ACTIONOP_RSS) { 897 *(u64 *)&action = 0; 898 action.op = NIX_RX_ACTIONOP_UCAST; 899 action.pf_func = pcifunc; 900 } 901 902 /* RX_ACTION set to MCAST for CGX PF's */ 903 if (hw->cap.nix_rx_multicast && pfvf->use_mce_list) { 904 *(u64 *)&action = 0; 905 action.op = NIX_RX_ACTIONOP_MCAST; 906 action.index = pfvf->mcast_mce_idx; 907 } 908 909 mac_addr[0] = 0x01; /* LSB bit of 1st byte in DMAC */ 910 ether_addr_copy(req.packet.dmac, mac_addr); 911 ether_addr_copy(req.mask.dmac, mac_addr); 912 req.features = BIT_ULL(NPC_DMAC); 913 914 /* For cn10k the upper two bits of the channel number are 915 * cpt channel number. with masking out these bits in the 916 * mcam entry, same entry used for NIX will allow packets 917 * received from cpt for parsing. 918 */ 919 if (!is_rvu_otx2(rvu)) 920 req.chan_mask = NIX_CHAN_CPT_X2P_MASK; 921 else 922 req.chan_mask = 0xFFFU; 923 924 req.channel = chan; 925 req.intf = pfvf->nix_rx_intf; 926 req.entry = index; 927 req.op = action.op; 928 req.hdr.pcifunc = 0; /* AF is requester */ 929 req.vf = pcifunc | vf_func; 930 req.index = action.index; 931 req.match_id = action.match_id; 932 req.flow_key_alg = flow_key_alg; 933 934 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 935 } 936 937 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 938 bool enable) 939 { 940 struct npc_mcam *mcam = &rvu->hw->mcam; 941 int blkaddr, index; 942 943 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 944 if (blkaddr < 0) 945 return; 946 947 /* Get 'pcifunc' of PF device */ 948 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 949 950 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, 951 NIXLF_ALLMULTI_ENTRY); 952 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 953 } 954 955 static void npc_update_vf_flow_entry(struct rvu *rvu, struct npc_mcam *mcam, 956 int blkaddr, u16 pcifunc, u64 rx_action) 957 { 958 int actindex, index, bank, entry; 959 struct rvu_npc_mcam_rule *rule; 960 bool enable, update; 961 962 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 963 return; 964 965 mutex_lock(&mcam->lock); 966 for (index = 0; index < mcam->bmap_entries; index++) { 967 if (mcam->entry2target_pffunc[index] == pcifunc) { 968 update = true; 969 /* update not needed for the rules added via ntuple filters */ 970 list_for_each_entry(rule, &mcam->mcam_rules, list) { 971 if (rule->entry == index) 972 update = false; 973 } 974 if (!update) 975 continue; 976 bank = npc_get_bank(mcam, index); 977 actindex = index; 978 entry = index & (mcam->banksize - 1); 979 980 /* read vf flow entry enable status */ 981 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, 982 actindex); 983 /* disable before mcam entry update */ 984 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, 985 false); 986 /* update 'action' */ 987 rvu_write64(rvu, blkaddr, 988 NPC_AF_MCAMEX_BANKX_ACTION(entry, bank), 989 rx_action); 990 if (enable) 991 npc_enable_mcam_entry(rvu, mcam, blkaddr, 992 actindex, true); 993 } 994 } 995 mutex_unlock(&mcam->lock); 996 } 997 998 static void npc_update_rx_action_with_alg_idx(struct rvu *rvu, struct nix_rx_action action, 999 struct rvu_pfvf *pfvf, int mcam_index, int blkaddr, 1000 int alg_idx) 1001 1002 { 1003 struct npc_mcam *mcam = &rvu->hw->mcam; 1004 struct rvu_hwinfo *hw = rvu->hw; 1005 int bank, op_rss; 1006 1007 if (!is_mcam_entry_enabled(rvu, mcam, blkaddr, mcam_index)) 1008 return; 1009 1010 op_rss = (!hw->cap.nix_rx_multicast || !pfvf->use_mce_list); 1011 1012 bank = npc_get_bank(mcam, mcam_index); 1013 mcam_index &= (mcam->banksize - 1); 1014 1015 /* If Rx action is MCAST update only RSS algorithm index */ 1016 if (!op_rss) { 1017 *(u64 *)&action = rvu_read64(rvu, blkaddr, 1018 NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank)); 1019 1020 action.flow_key_alg = alg_idx; 1021 } 1022 rvu_write64(rvu, blkaddr, 1023 NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank), *(u64 *)&action); 1024 } 1025 1026 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 1027 int group, int alg_idx, int mcam_index) 1028 { 1029 struct npc_mcam *mcam = &rvu->hw->mcam; 1030 struct nix_rx_action action; 1031 int blkaddr, index, bank; 1032 struct rvu_pfvf *pfvf; 1033 1034 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1035 if (blkaddr < 0) 1036 return; 1037 1038 /* Check if this is for reserved default entry */ 1039 if (mcam_index < 0) { 1040 if (group != DEFAULT_RSS_CONTEXT_GROUP) 1041 return; 1042 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1043 nixlf, NIXLF_UCAST_ENTRY); 1044 } else { 1045 /* TODO: validate this mcam index */ 1046 index = mcam_index; 1047 } 1048 1049 if (index >= mcam->total_entries) 1050 return; 1051 1052 bank = npc_get_bank(mcam, index); 1053 index &= (mcam->banksize - 1); 1054 1055 *(u64 *)&action = rvu_read64(rvu, blkaddr, 1056 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 1057 /* Ignore if no action was set earlier */ 1058 if (!*(u64 *)&action) 1059 return; 1060 1061 action.op = NIX_RX_ACTIONOP_RSS; 1062 action.pf_func = pcifunc; 1063 action.index = group; 1064 action.flow_key_alg = alg_idx; 1065 1066 rvu_write64(rvu, blkaddr, 1067 NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action); 1068 1069 /* update the VF flow rule action with the VF default entry action */ 1070 if (mcam_index < 0) 1071 npc_update_vf_flow_entry(rvu, mcam, blkaddr, pcifunc, 1072 *(u64 *)&action); 1073 1074 /* update the action change in default rule */ 1075 pfvf = rvu_get_pfvf(rvu, pcifunc); 1076 if (pfvf->def_ucast_rule) 1077 pfvf->def_ucast_rule->rx_action = action; 1078 1079 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1080 nixlf, NIXLF_PROMISC_ENTRY); 1081 1082 /* If PF's promiscuous entry is enabled, 1083 * Set RSS action for that entry as well 1084 */ 1085 npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, blkaddr, 1086 alg_idx); 1087 1088 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1089 nixlf, NIXLF_ALLMULTI_ENTRY); 1090 /* If PF's allmulti entry is enabled, 1091 * Set RSS action for that entry as well 1092 */ 1093 npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, blkaddr, 1094 alg_idx); 1095 } 1096 1097 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 1098 int nixlf, int type, bool enable) 1099 { 1100 struct npc_mcam *mcam = &rvu->hw->mcam; 1101 struct rvu_hwinfo *hw = rvu->hw; 1102 struct nix_mce_list *mce_list; 1103 int index, blkaddr, mce_idx; 1104 struct rvu_pfvf *pfvf; 1105 1106 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1107 if (blkaddr < 0) 1108 return; 1109 1110 index = npc_get_nixlf_mcam_index(mcam, pcifunc & ~RVU_PFVF_FUNC_MASK, 1111 nixlf, type); 1112 1113 /* disable MCAM entry when packet replication is not supported by hw */ 1114 if (!hw->cap.nix_rx_multicast && !is_vf(pcifunc)) { 1115 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 1116 return; 1117 } 1118 1119 /* return incase mce list is not enabled */ 1120 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1121 if (hw->cap.nix_rx_multicast && is_vf(pcifunc) && 1122 type != NIXLF_BCAST_ENTRY && !pfvf->use_mce_list) 1123 return; 1124 1125 nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx); 1126 1127 nix_update_mce_list(rvu, pcifunc, mce_list, 1128 mce_idx, index, enable); 1129 if (enable) 1130 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 1131 } 1132 1133 static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc, 1134 int nixlf, bool enable) 1135 { 1136 struct npc_mcam *mcam = &rvu->hw->mcam; 1137 int index, blkaddr; 1138 1139 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1140 if (blkaddr < 0) 1141 return; 1142 1143 /* Ucast MCAM match entry of this PF/VF */ 1144 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1145 nixlf, NIXLF_UCAST_ENTRY); 1146 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 1147 1148 /* Nothing to do for VFs, on platforms where pkt replication 1149 * is not supported 1150 */ 1151 if ((pcifunc & RVU_PFVF_FUNC_MASK) && !rvu->hw->cap.nix_rx_multicast) 1152 return; 1153 1154 /* add/delete pf_func to broadcast MCE list */ 1155 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, 1156 NIXLF_BCAST_ENTRY, enable); 1157 } 1158 1159 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1160 { 1161 if (nixlf < 0) 1162 return; 1163 1164 npc_enadis_default_entries(rvu, pcifunc, nixlf, false); 1165 1166 /* Delete multicast and promisc MCAM entries */ 1167 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, 1168 NIXLF_ALLMULTI_ENTRY, false); 1169 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, 1170 NIXLF_PROMISC_ENTRY, false); 1171 } 1172 1173 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable) 1174 { 1175 int blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1176 struct npc_mcam *mcam = &rvu->hw->mcam; 1177 struct rvu_npc_mcam_rule *rule, *tmp; 1178 1179 mutex_lock(&mcam->lock); 1180 1181 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { 1182 if (rule->intf != intf) 1183 continue; 1184 1185 if (rule->entry != entry) 1186 continue; 1187 1188 rule->enable = enable; 1189 mutex_unlock(&mcam->lock); 1190 1191 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1192 entry, enable); 1193 1194 return true; 1195 } 1196 1197 mutex_unlock(&mcam->lock); 1198 return false; 1199 } 1200 1201 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1202 { 1203 if (nixlf < 0) 1204 return; 1205 1206 /* Enables only broadcast match entry. Promisc/Allmulti are enabled 1207 * in set_rx_mode mbox handler. 1208 */ 1209 npc_enadis_default_entries(rvu, pcifunc, nixlf, true); 1210 } 1211 1212 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1213 { 1214 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1215 struct npc_mcam *mcam = &rvu->hw->mcam; 1216 struct rvu_npc_mcam_rule *rule, *tmp; 1217 int blkaddr; 1218 1219 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1220 if (blkaddr < 0) 1221 return; 1222 1223 mutex_lock(&mcam->lock); 1224 1225 /* Disable MCAM entries directing traffic to this 'pcifunc' */ 1226 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { 1227 if (is_npc_intf_rx(rule->intf) && 1228 rule->rx_action.pf_func == pcifunc && 1229 rule->rx_action.op != NIX_RX_ACTIONOP_MCAST) { 1230 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1231 rule->entry, false); 1232 rule->enable = false; 1233 /* Indicate that default rule is disabled */ 1234 if (rule->default_rule) { 1235 pfvf->def_ucast_rule = NULL; 1236 list_del(&rule->list); 1237 kfree(rule); 1238 } 1239 } 1240 } 1241 1242 mutex_unlock(&mcam->lock); 1243 1244 npc_mcam_disable_flows(rvu, pcifunc); 1245 1246 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 1247 } 1248 1249 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1250 { 1251 struct npc_mcam *mcam = &rvu->hw->mcam; 1252 struct rvu_npc_mcam_rule *rule, *tmp; 1253 int blkaddr; 1254 1255 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1256 if (blkaddr < 0) 1257 return; 1258 1259 mutex_lock(&mcam->lock); 1260 1261 /* Free all MCAM entries owned by this 'pcifunc' */ 1262 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); 1263 1264 /* Free all MCAM counters owned by this 'pcifunc' */ 1265 npc_mcam_free_all_counters(rvu, mcam, pcifunc); 1266 1267 /* Delete MCAM entries owned by this 'pcifunc' */ 1268 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { 1269 if (rule->owner == pcifunc && !rule->default_rule) { 1270 list_del(&rule->list); 1271 kfree(rule); 1272 } 1273 } 1274 1275 mutex_unlock(&mcam->lock); 1276 1277 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 1278 } 1279 1280 static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr, 1281 struct npc_mcam_kex *mkex, u8 intf) 1282 { 1283 int lid, lt, ld, fl; 1284 1285 if (is_npc_intf_tx(intf)) 1286 return; 1287 1288 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 1289 mkex->keyx_cfg[NIX_INTF_RX]); 1290 1291 /* Program LDATA */ 1292 for (lid = 0; lid < NPC_MAX_LID; lid++) { 1293 for (lt = 0; lt < NPC_MAX_LT; lt++) { 1294 for (ld = 0; ld < NPC_MAX_LD; ld++) 1295 SET_KEX_LD(intf, lid, lt, ld, 1296 mkex->intf_lid_lt_ld[NIX_INTF_RX] 1297 [lid][lt][ld]); 1298 } 1299 } 1300 /* Program LFLAGS */ 1301 for (ld = 0; ld < NPC_MAX_LD; ld++) { 1302 for (fl = 0; fl < NPC_MAX_LFL; fl++) 1303 SET_KEX_LDFLAGS(intf, ld, fl, 1304 mkex->intf_ld_flags[NIX_INTF_RX] 1305 [ld][fl]); 1306 } 1307 } 1308 1309 static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr, 1310 struct npc_mcam_kex *mkex, u8 intf) 1311 { 1312 int lid, lt, ld, fl; 1313 1314 if (is_npc_intf_rx(intf)) 1315 return; 1316 1317 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 1318 mkex->keyx_cfg[NIX_INTF_TX]); 1319 1320 /* Program LDATA */ 1321 for (lid = 0; lid < NPC_MAX_LID; lid++) { 1322 for (lt = 0; lt < NPC_MAX_LT; lt++) { 1323 for (ld = 0; ld < NPC_MAX_LD; ld++) 1324 SET_KEX_LD(intf, lid, lt, ld, 1325 mkex->intf_lid_lt_ld[NIX_INTF_TX] 1326 [lid][lt][ld]); 1327 } 1328 } 1329 /* Program LFLAGS */ 1330 for (ld = 0; ld < NPC_MAX_LD; ld++) { 1331 for (fl = 0; fl < NPC_MAX_LFL; fl++) 1332 SET_KEX_LDFLAGS(intf, ld, fl, 1333 mkex->intf_ld_flags[NIX_INTF_TX] 1334 [ld][fl]); 1335 } 1336 } 1337 1338 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr, 1339 struct npc_mcam_kex *mkex) 1340 { 1341 struct rvu_hwinfo *hw = rvu->hw; 1342 u8 intf; 1343 int ld; 1344 1345 for (ld = 0; ld < NPC_MAX_LD; ld++) 1346 rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld), 1347 mkex->kex_ld_flags[ld]); 1348 1349 for (intf = 0; intf < hw->npc_intfs; intf++) { 1350 npc_program_mkex_rx(rvu, blkaddr, mkex, intf); 1351 npc_program_mkex_tx(rvu, blkaddr, mkex, intf); 1352 } 1353 1354 /* Programme mkex hash profile */ 1355 npc_program_mkex_hash(rvu, blkaddr); 1356 } 1357 1358 static int npc_fwdb_prfl_img_map(struct rvu *rvu, void __iomem **prfl_img_addr, 1359 u64 *size) 1360 { 1361 u64 prfl_addr, prfl_sz; 1362 1363 if (!rvu->fwdata) 1364 return -EINVAL; 1365 1366 prfl_addr = rvu->fwdata->mcam_addr; 1367 prfl_sz = rvu->fwdata->mcam_sz; 1368 1369 if (!prfl_addr || !prfl_sz) 1370 return -EINVAL; 1371 1372 *prfl_img_addr = ioremap_wc(prfl_addr, prfl_sz); 1373 if (!(*prfl_img_addr)) 1374 return -ENOMEM; 1375 1376 *size = prfl_sz; 1377 1378 return 0; 1379 } 1380 1381 /* strtoull of "mkexprof" with base:36 */ 1382 #define MKEX_END_SIGN 0xdeadbeef 1383 1384 static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr, 1385 const char *mkex_profile) 1386 { 1387 struct device *dev = &rvu->pdev->dev; 1388 struct npc_mcam_kex *mcam_kex; 1389 void __iomem *mkex_prfl_addr = NULL; 1390 u64 prfl_sz; 1391 int ret; 1392 1393 /* If user not selected mkex profile */ 1394 if (rvu->kpu_fwdata_sz || 1395 !strncmp(mkex_profile, def_pfl_name, MKEX_NAME_LEN)) 1396 goto program_mkex; 1397 1398 /* Setting up the mapping for mkex profile image */ 1399 ret = npc_fwdb_prfl_img_map(rvu, &mkex_prfl_addr, &prfl_sz); 1400 if (ret < 0) 1401 goto program_mkex; 1402 1403 mcam_kex = (struct npc_mcam_kex __force *)mkex_prfl_addr; 1404 1405 while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) { 1406 /* Compare with mkex mod_param name string */ 1407 if (mcam_kex->mkex_sign == MKEX_SIGN && 1408 !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) { 1409 /* Due to an errata (35786) in A0/B0 pass silicon, 1410 * parse nibble enable configuration has to be 1411 * identical for both Rx and Tx interfaces. 1412 */ 1413 if (!is_rvu_96xx_B0(rvu) || 1414 mcam_kex->keyx_cfg[NIX_INTF_RX] == mcam_kex->keyx_cfg[NIX_INTF_TX]) 1415 rvu->kpu.mkex = mcam_kex; 1416 goto program_mkex; 1417 } 1418 1419 mcam_kex++; 1420 prfl_sz -= sizeof(struct npc_mcam_kex); 1421 } 1422 dev_warn(dev, "Failed to load requested profile: %s\n", mkex_profile); 1423 1424 program_mkex: 1425 dev_info(rvu->dev, "Using %s mkex profile\n", rvu->kpu.mkex->name); 1426 /* Program selected mkex profile */ 1427 npc_program_mkex_profile(rvu, blkaddr, rvu->kpu.mkex); 1428 if (mkex_prfl_addr) 1429 iounmap(mkex_prfl_addr); 1430 } 1431 1432 static void npc_config_kpuaction(struct rvu *rvu, int blkaddr, 1433 const struct npc_kpu_profile_action *kpuaction, 1434 int kpu, int entry, bool pkind) 1435 { 1436 struct npc_kpu_action0 action0 = {0}; 1437 struct npc_kpu_action1 action1 = {0}; 1438 u64 reg; 1439 1440 action1.errlev = kpuaction->errlev; 1441 action1.errcode = kpuaction->errcode; 1442 action1.dp0_offset = kpuaction->dp0_offset; 1443 action1.dp1_offset = kpuaction->dp1_offset; 1444 action1.dp2_offset = kpuaction->dp2_offset; 1445 1446 if (pkind) 1447 reg = NPC_AF_PKINDX_ACTION1(entry); 1448 else 1449 reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry); 1450 1451 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1); 1452 1453 action0.byp_count = kpuaction->bypass_count; 1454 action0.capture_ena = kpuaction->cap_ena; 1455 action0.parse_done = kpuaction->parse_done; 1456 action0.next_state = kpuaction->next_state; 1457 action0.capture_lid = kpuaction->lid; 1458 action0.capture_ltype = kpuaction->ltype; 1459 action0.capture_flags = kpuaction->flags; 1460 action0.ptr_advance = kpuaction->ptr_advance; 1461 action0.var_len_offset = kpuaction->offset; 1462 action0.var_len_mask = kpuaction->mask; 1463 action0.var_len_right = kpuaction->right; 1464 action0.var_len_shift = kpuaction->shift; 1465 1466 if (pkind) 1467 reg = NPC_AF_PKINDX_ACTION0(entry); 1468 else 1469 reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry); 1470 1471 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0); 1472 } 1473 1474 static void npc_config_kpucam(struct rvu *rvu, int blkaddr, 1475 const struct npc_kpu_profile_cam *kpucam, 1476 int kpu, int entry) 1477 { 1478 struct npc_kpu_cam cam0 = {0}; 1479 struct npc_kpu_cam cam1 = {0}; 1480 1481 cam1.state = kpucam->state & kpucam->state_mask; 1482 cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask; 1483 cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask; 1484 cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask; 1485 1486 cam0.state = ~kpucam->state & kpucam->state_mask; 1487 cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask; 1488 cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask; 1489 cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask; 1490 1491 rvu_write64(rvu, blkaddr, 1492 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0); 1493 rvu_write64(rvu, blkaddr, 1494 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1); 1495 } 1496 1497 static inline u64 enable_mask(int count) 1498 { 1499 return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL)); 1500 } 1501 1502 static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu, 1503 const struct npc_kpu_profile *profile) 1504 { 1505 int entry, num_entries, max_entries; 1506 u64 entry_mask; 1507 1508 if (profile->cam_entries != profile->action_entries) { 1509 dev_err(rvu->dev, 1510 "KPU%d: CAM and action entries [%d != %d] not equal\n", 1511 kpu, profile->cam_entries, profile->action_entries); 1512 } 1513 1514 max_entries = rvu->hw->npc_kpu_entries; 1515 1516 /* Program CAM match entries for previous KPU extracted data */ 1517 num_entries = min_t(int, profile->cam_entries, max_entries); 1518 for (entry = 0; entry < num_entries; entry++) 1519 npc_config_kpucam(rvu, blkaddr, 1520 &profile->cam[entry], kpu, entry); 1521 1522 /* Program this KPU's actions */ 1523 num_entries = min_t(int, profile->action_entries, max_entries); 1524 for (entry = 0; entry < num_entries; entry++) 1525 npc_config_kpuaction(rvu, blkaddr, &profile->action[entry], 1526 kpu, entry, false); 1527 1528 /* Enable all programmed entries */ 1529 num_entries = min_t(int, profile->action_entries, profile->cam_entries); 1530 entry_mask = enable_mask(num_entries); 1531 /* Disable first KPU_MAX_CST_ENT entries for built-in profile */ 1532 if (!rvu->kpu.custom) 1533 entry_mask |= GENMASK_ULL(KPU_MAX_CST_ENT - 1, 0); 1534 rvu_write64(rvu, blkaddr, 1535 NPC_AF_KPUX_ENTRY_DISX(kpu, 0), entry_mask); 1536 if (num_entries > 64) { 1537 rvu_write64(rvu, blkaddr, 1538 NPC_AF_KPUX_ENTRY_DISX(kpu, 1), 1539 enable_mask(num_entries - 64)); 1540 } 1541 1542 /* Enable this KPU */ 1543 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01); 1544 } 1545 1546 static int npc_prepare_default_kpu(struct npc_kpu_profile_adapter *profile) 1547 { 1548 profile->custom = 0; 1549 profile->name = def_pfl_name; 1550 profile->version = NPC_KPU_PROFILE_VER; 1551 profile->ikpu = ikpu_action_entries; 1552 profile->pkinds = ARRAY_SIZE(ikpu_action_entries); 1553 profile->kpu = npc_kpu_profiles; 1554 profile->kpus = ARRAY_SIZE(npc_kpu_profiles); 1555 profile->lt_def = &npc_lt_defaults; 1556 profile->mkex = &npc_mkex_default; 1557 profile->mkex_hash = &npc_mkex_hash_default; 1558 1559 return 0; 1560 } 1561 1562 static int npc_apply_custom_kpu(struct rvu *rvu, 1563 struct npc_kpu_profile_adapter *profile) 1564 { 1565 size_t hdr_sz = sizeof(struct npc_kpu_profile_fwdata), offset = 0; 1566 struct npc_kpu_profile_fwdata *fw = rvu->kpu_fwdata; 1567 struct npc_kpu_profile_action *action; 1568 struct npc_kpu_profile_cam *cam; 1569 struct npc_kpu_fwdata *fw_kpu; 1570 int entries; 1571 u16 kpu, entry; 1572 1573 if (rvu->kpu_fwdata_sz < hdr_sz) { 1574 dev_warn(rvu->dev, "Invalid KPU profile size\n"); 1575 return -EINVAL; 1576 } 1577 if (le64_to_cpu(fw->signature) != KPU_SIGN) { 1578 dev_warn(rvu->dev, "Invalid KPU profile signature %llx\n", 1579 fw->signature); 1580 return -EINVAL; 1581 } 1582 /* Verify if the using known profile structure */ 1583 if (NPC_KPU_VER_MAJ(profile->version) > 1584 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)) { 1585 dev_warn(rvu->dev, "Not supported Major version: %d > %d\n", 1586 NPC_KPU_VER_MAJ(profile->version), 1587 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)); 1588 return -EINVAL; 1589 } 1590 /* Verify if profile is aligned with the required kernel changes */ 1591 if (NPC_KPU_VER_MIN(profile->version) < 1592 NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER)) { 1593 dev_warn(rvu->dev, 1594 "Invalid KPU profile version: %d.%d.%d expected version <= %d.%d.%d\n", 1595 NPC_KPU_VER_MAJ(profile->version), 1596 NPC_KPU_VER_MIN(profile->version), 1597 NPC_KPU_VER_PATCH(profile->version), 1598 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER), 1599 NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER), 1600 NPC_KPU_VER_PATCH(NPC_KPU_PROFILE_VER)); 1601 return -EINVAL; 1602 } 1603 /* Verify if profile fits the HW */ 1604 if (fw->kpus > profile->kpus) { 1605 dev_warn(rvu->dev, "Not enough KPUs: %d > %ld\n", fw->kpus, 1606 profile->kpus); 1607 return -EINVAL; 1608 } 1609 1610 profile->custom = 1; 1611 profile->name = fw->name; 1612 profile->version = le64_to_cpu(fw->version); 1613 profile->mkex = &fw->mkex; 1614 profile->lt_def = &fw->lt_def; 1615 1616 for (kpu = 0; kpu < fw->kpus; kpu++) { 1617 fw_kpu = (struct npc_kpu_fwdata *)(fw->data + offset); 1618 if (fw_kpu->entries > KPU_MAX_CST_ENT) 1619 dev_warn(rvu->dev, 1620 "Too many custom entries on KPU%d: %d > %d\n", 1621 kpu, fw_kpu->entries, KPU_MAX_CST_ENT); 1622 entries = min(fw_kpu->entries, KPU_MAX_CST_ENT); 1623 cam = (struct npc_kpu_profile_cam *)fw_kpu->data; 1624 offset += sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam); 1625 action = (struct npc_kpu_profile_action *)(fw->data + offset); 1626 offset += fw_kpu->entries * sizeof(*action); 1627 if (rvu->kpu_fwdata_sz < hdr_sz + offset) { 1628 dev_warn(rvu->dev, 1629 "Profile size mismatch on KPU%i parsing.\n", 1630 kpu + 1); 1631 return -EINVAL; 1632 } 1633 for (entry = 0; entry < entries; entry++) { 1634 profile->kpu[kpu].cam[entry] = cam[entry]; 1635 profile->kpu[kpu].action[entry] = action[entry]; 1636 } 1637 } 1638 1639 return 0; 1640 } 1641 1642 static int npc_load_kpu_prfl_img(struct rvu *rvu, void __iomem *prfl_addr, 1643 u64 prfl_sz, const char *kpu_profile) 1644 { 1645 struct npc_kpu_profile_fwdata *kpu_data = NULL; 1646 int rc = -EINVAL; 1647 1648 kpu_data = (struct npc_kpu_profile_fwdata __force *)prfl_addr; 1649 if (le64_to_cpu(kpu_data->signature) == KPU_SIGN && 1650 !strncmp(kpu_data->name, kpu_profile, KPU_NAME_LEN)) { 1651 dev_info(rvu->dev, "Loading KPU profile from firmware db: %s\n", 1652 kpu_profile); 1653 rvu->kpu_fwdata = kpu_data; 1654 rvu->kpu_fwdata_sz = prfl_sz; 1655 rvu->kpu_prfl_addr = prfl_addr; 1656 rc = 0; 1657 } 1658 1659 return rc; 1660 } 1661 1662 static int npc_fwdb_detect_load_prfl_img(struct rvu *rvu, uint64_t prfl_sz, 1663 const char *kpu_profile) 1664 { 1665 struct npc_coalesced_kpu_prfl *img_data = NULL; 1666 int i = 0, rc = -EINVAL; 1667 void __iomem *kpu_prfl_addr; 1668 u16 offset; 1669 1670 img_data = (struct npc_coalesced_kpu_prfl __force *)rvu->kpu_prfl_addr; 1671 if (le64_to_cpu(img_data->signature) == KPU_SIGN && 1672 !strncmp(img_data->name, kpu_profile, KPU_NAME_LEN)) { 1673 /* Loaded profile is a single KPU profile. */ 1674 rc = npc_load_kpu_prfl_img(rvu, rvu->kpu_prfl_addr, 1675 prfl_sz, kpu_profile); 1676 goto done; 1677 } 1678 1679 /* Loaded profile is coalesced image, offset of first KPU profile.*/ 1680 offset = offsetof(struct npc_coalesced_kpu_prfl, prfl_sz) + 1681 (img_data->num_prfl * sizeof(uint16_t)); 1682 /* Check if mapped image is coalesced image. */ 1683 while (i < img_data->num_prfl) { 1684 /* Profile image offsets are rounded up to next 8 multiple.*/ 1685 offset = ALIGN_8B_CEIL(offset); 1686 kpu_prfl_addr = (void __iomem *)((uintptr_t)rvu->kpu_prfl_addr + 1687 offset); 1688 rc = npc_load_kpu_prfl_img(rvu, kpu_prfl_addr, 1689 img_data->prfl_sz[i], kpu_profile); 1690 if (!rc) 1691 break; 1692 /* Calculating offset of profile image based on profile size.*/ 1693 offset += img_data->prfl_sz[i]; 1694 i++; 1695 } 1696 done: 1697 return rc; 1698 } 1699 1700 static int npc_load_kpu_profile_fwdb(struct rvu *rvu, const char *kpu_profile) 1701 { 1702 int ret = -EINVAL; 1703 u64 prfl_sz; 1704 1705 /* Setting up the mapping for NPC profile image */ 1706 ret = npc_fwdb_prfl_img_map(rvu, &rvu->kpu_prfl_addr, &prfl_sz); 1707 if (ret < 0) 1708 goto done; 1709 1710 /* Detect if profile is coalesced or single KPU profile and load */ 1711 ret = npc_fwdb_detect_load_prfl_img(rvu, prfl_sz, kpu_profile); 1712 if (ret == 0) 1713 goto done; 1714 1715 /* Cleaning up if KPU profile image from fwdata is not valid. */ 1716 if (rvu->kpu_prfl_addr) { 1717 iounmap(rvu->kpu_prfl_addr); 1718 rvu->kpu_prfl_addr = NULL; 1719 rvu->kpu_fwdata_sz = 0; 1720 rvu->kpu_fwdata = NULL; 1721 } 1722 1723 done: 1724 return ret; 1725 } 1726 1727 static void npc_load_kpu_profile(struct rvu *rvu) 1728 { 1729 struct npc_kpu_profile_adapter *profile = &rvu->kpu; 1730 const char *kpu_profile = rvu->kpu_pfl_name; 1731 const struct firmware *fw = NULL; 1732 bool retry_fwdb = false; 1733 1734 /* If user not specified profile customization */ 1735 if (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN)) 1736 goto revert_to_default; 1737 /* First prepare default KPU, then we'll customize top entries. */ 1738 npc_prepare_default_kpu(profile); 1739 1740 /* Order of preceedence for load loading NPC profile (high to low) 1741 * Firmware binary in filesystem. 1742 * Firmware database method. 1743 * Default KPU profile. 1744 */ 1745 if (!request_firmware_direct(&fw, kpu_profile, rvu->dev)) { 1746 dev_info(rvu->dev, "Loading KPU profile from firmware: %s\n", 1747 kpu_profile); 1748 rvu->kpu_fwdata = kzalloc(fw->size, GFP_KERNEL); 1749 if (rvu->kpu_fwdata) { 1750 memcpy(rvu->kpu_fwdata, fw->data, fw->size); 1751 rvu->kpu_fwdata_sz = fw->size; 1752 } 1753 release_firmware(fw); 1754 retry_fwdb = true; 1755 goto program_kpu; 1756 } 1757 1758 load_image_fwdb: 1759 /* Loading the KPU profile using firmware database */ 1760 if (npc_load_kpu_profile_fwdb(rvu, kpu_profile)) 1761 goto revert_to_default; 1762 1763 program_kpu: 1764 /* Apply profile customization if firmware was loaded. */ 1765 if (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile)) { 1766 /* If image from firmware filesystem fails to load or invalid 1767 * retry with firmware database method. 1768 */ 1769 if (rvu->kpu_fwdata || rvu->kpu_fwdata_sz) { 1770 /* Loading image from firmware database failed. */ 1771 if (rvu->kpu_prfl_addr) { 1772 iounmap(rvu->kpu_prfl_addr); 1773 rvu->kpu_prfl_addr = NULL; 1774 } else { 1775 kfree(rvu->kpu_fwdata); 1776 } 1777 rvu->kpu_fwdata = NULL; 1778 rvu->kpu_fwdata_sz = 0; 1779 if (retry_fwdb) { 1780 retry_fwdb = false; 1781 goto load_image_fwdb; 1782 } 1783 } 1784 1785 dev_warn(rvu->dev, 1786 "Can't load KPU profile %s. Using default.\n", 1787 kpu_profile); 1788 kfree(rvu->kpu_fwdata); 1789 rvu->kpu_fwdata = NULL; 1790 goto revert_to_default; 1791 } 1792 1793 dev_info(rvu->dev, "Using custom profile '%s', version %d.%d.%d\n", 1794 profile->name, NPC_KPU_VER_MAJ(profile->version), 1795 NPC_KPU_VER_MIN(profile->version), 1796 NPC_KPU_VER_PATCH(profile->version)); 1797 1798 return; 1799 1800 revert_to_default: 1801 npc_prepare_default_kpu(profile); 1802 } 1803 1804 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr) 1805 { 1806 struct rvu_hwinfo *hw = rvu->hw; 1807 int num_pkinds, num_kpus, idx; 1808 1809 /* Disable all KPUs and their entries */ 1810 for (idx = 0; idx < hw->npc_kpus; idx++) { 1811 rvu_write64(rvu, blkaddr, 1812 NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL); 1813 rvu_write64(rvu, blkaddr, 1814 NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL); 1815 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00); 1816 } 1817 1818 /* Load and customize KPU profile. */ 1819 npc_load_kpu_profile(rvu); 1820 1821 /* First program IKPU profile i.e PKIND configs. 1822 * Check HW max count to avoid configuring junk or 1823 * writing to unsupported CSR addresses. 1824 */ 1825 num_pkinds = rvu->kpu.pkinds; 1826 num_pkinds = min_t(int, hw->npc_pkinds, num_pkinds); 1827 1828 for (idx = 0; idx < num_pkinds; idx++) 1829 npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true); 1830 1831 /* Program KPU CAM and Action profiles */ 1832 num_kpus = rvu->kpu.kpus; 1833 num_kpus = min_t(int, hw->npc_kpus, num_kpus); 1834 1835 for (idx = 0; idx < num_kpus; idx++) 1836 npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]); 1837 } 1838 1839 static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr) 1840 { 1841 int nixlf_count = rvu_get_nixlf_count(rvu); 1842 struct npc_mcam *mcam = &rvu->hw->mcam; 1843 int rsvd, err; 1844 u16 index; 1845 int cntr; 1846 u64 cfg; 1847 1848 /* Actual number of MCAM entries vary by entry size */ 1849 cfg = (rvu_read64(rvu, blkaddr, 1850 NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07; 1851 mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize; 1852 mcam->keysize = cfg; 1853 1854 /* Number of banks combined per MCAM entry */ 1855 if (cfg == NPC_MCAM_KEY_X4) 1856 mcam->banks_per_entry = 4; 1857 else if (cfg == NPC_MCAM_KEY_X2) 1858 mcam->banks_per_entry = 2; 1859 else 1860 mcam->banks_per_entry = 1; 1861 1862 /* Reserve one MCAM entry for each of the NIX LF to 1863 * guarantee space to install default matching DMAC rule. 1864 * Also reserve 2 MCAM entries for each PF for default 1865 * channel based matching or 'bcast & promisc' matching to 1866 * support BCAST and PROMISC modes of operation for PFs. 1867 * PF0 is excluded. 1868 */ 1869 rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) + 1870 ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF); 1871 if (mcam->total_entries <= rsvd) { 1872 dev_warn(rvu->dev, 1873 "Insufficient NPC MCAM size %d for pkt I/O, exiting\n", 1874 mcam->total_entries); 1875 return -ENOMEM; 1876 } 1877 1878 mcam->bmap_entries = mcam->total_entries - rsvd; 1879 mcam->nixlf_offset = mcam->bmap_entries; 1880 mcam->pf_offset = mcam->nixlf_offset + nixlf_count; 1881 1882 /* Allocate bitmaps for managing MCAM entries */ 1883 mcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries), 1884 sizeof(long), GFP_KERNEL); 1885 if (!mcam->bmap) 1886 return -ENOMEM; 1887 1888 mcam->bmap_reverse = devm_kcalloc(rvu->dev, 1889 BITS_TO_LONGS(mcam->bmap_entries), 1890 sizeof(long), GFP_KERNEL); 1891 if (!mcam->bmap_reverse) 1892 return -ENOMEM; 1893 1894 mcam->bmap_fcnt = mcam->bmap_entries; 1895 1896 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */ 1897 mcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries, 1898 sizeof(u16), GFP_KERNEL); 1899 if (!mcam->entry2pfvf_map) 1900 return -ENOMEM; 1901 1902 /* Reserve 1/8th of MCAM entries at the bottom for low priority 1903 * allocations and another 1/8th at the top for high priority 1904 * allocations. 1905 */ 1906 mcam->lprio_count = mcam->bmap_entries / 8; 1907 if (mcam->lprio_count > BITS_PER_LONG) 1908 mcam->lprio_count = round_down(mcam->lprio_count, 1909 BITS_PER_LONG); 1910 mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count; 1911 mcam->hprio_count = mcam->lprio_count; 1912 mcam->hprio_end = mcam->hprio_count; 1913 1914 /* Allocate bitmap for managing MCAM counters and memory 1915 * for saving counter to RVU PFFUNC allocation mapping. 1916 */ 1917 err = rvu_alloc_bitmap(&mcam->counters); 1918 if (err) 1919 return err; 1920 1921 mcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max, 1922 sizeof(u16), GFP_KERNEL); 1923 if (!mcam->cntr2pfvf_map) 1924 goto free_mem; 1925 1926 /* Alloc memory for MCAM entry to counter mapping and for tracking 1927 * counter's reference count. 1928 */ 1929 mcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries, 1930 sizeof(u16), GFP_KERNEL); 1931 if (!mcam->entry2cntr_map) 1932 goto free_mem; 1933 1934 mcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max, 1935 sizeof(u16), GFP_KERNEL); 1936 if (!mcam->cntr_refcnt) 1937 goto free_mem; 1938 1939 /* Alloc memory for saving target device of mcam rule */ 1940 mcam->entry2target_pffunc = devm_kcalloc(rvu->dev, mcam->total_entries, 1941 sizeof(u16), GFP_KERNEL); 1942 if (!mcam->entry2target_pffunc) 1943 goto free_mem; 1944 1945 for (index = 0; index < mcam->bmap_entries; index++) { 1946 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP; 1947 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP; 1948 } 1949 1950 for (cntr = 0; cntr < mcam->counters.max; cntr++) 1951 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP; 1952 1953 mutex_init(&mcam->lock); 1954 1955 return 0; 1956 1957 free_mem: 1958 kfree(mcam->counters.bmap); 1959 return -ENOMEM; 1960 } 1961 1962 static void rvu_npc_hw_init(struct rvu *rvu, int blkaddr) 1963 { 1964 struct npc_pkind *pkind = &rvu->hw->pkind; 1965 struct npc_mcam *mcam = &rvu->hw->mcam; 1966 struct rvu_hwinfo *hw = rvu->hw; 1967 u64 npc_const, npc_const1; 1968 u64 npc_const2 = 0; 1969 1970 npc_const = rvu_read64(rvu, blkaddr, NPC_AF_CONST); 1971 npc_const1 = rvu_read64(rvu, blkaddr, NPC_AF_CONST1); 1972 if (npc_const1 & BIT_ULL(63)) 1973 npc_const2 = rvu_read64(rvu, blkaddr, NPC_AF_CONST2); 1974 1975 pkind->rsrc.max = NPC_UNRESERVED_PKIND_COUNT; 1976 hw->npc_pkinds = (npc_const1 >> 12) & 0xFFULL; 1977 hw->npc_kpu_entries = npc_const1 & 0xFFFULL; 1978 hw->npc_kpus = (npc_const >> 8) & 0x1FULL; 1979 hw->npc_intfs = npc_const & 0xFULL; 1980 hw->npc_counters = (npc_const >> 48) & 0xFFFFULL; 1981 1982 mcam->banks = (npc_const >> 44) & 0xFULL; 1983 mcam->banksize = (npc_const >> 28) & 0xFFFFULL; 1984 hw->npc_stat_ena = BIT_ULL(9); 1985 /* Extended set */ 1986 if (npc_const2) { 1987 hw->npc_ext_set = true; 1988 /* 96xx supports only match_stats and npc_counters 1989 * reflected in NPC_AF_CONST reg. 1990 * STAT_SEL and ENA are at [0:8] and 9 bit positions. 1991 * 98xx has both match_stat and ext and npc_counter 1992 * reflected in NPC_AF_CONST2 1993 * STAT_SEL_EXT added at [12:14] bit position. 1994 * cn10k supports only ext and hence npc_counters in 1995 * NPC_AF_CONST is 0 and npc_counters reflected in NPC_AF_CONST2. 1996 * STAT_SEL bitpos incremented from [0:8] to [0:11] and ENA bit moved to 63 1997 */ 1998 if (!hw->npc_counters) 1999 hw->npc_stat_ena = BIT_ULL(63); 2000 hw->npc_counters = (npc_const2 >> 16) & 0xFFFFULL; 2001 mcam->banksize = npc_const2 & 0xFFFFULL; 2002 } 2003 2004 mcam->counters.max = hw->npc_counters; 2005 } 2006 2007 static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr) 2008 { 2009 struct npc_mcam_kex *mkex = rvu->kpu.mkex; 2010 struct npc_mcam *mcam = &rvu->hw->mcam; 2011 struct rvu_hwinfo *hw = rvu->hw; 2012 u64 nibble_ena, rx_kex, tx_kex; 2013 u8 intf; 2014 2015 /* Reserve last counter for MCAM RX miss action which is set to 2016 * drop packet. This way we will know how many pkts didn't match 2017 * any MCAM entry. 2018 */ 2019 mcam->counters.max--; 2020 mcam->rx_miss_act_cntr = mcam->counters.max; 2021 2022 rx_kex = mkex->keyx_cfg[NIX_INTF_RX]; 2023 tx_kex = mkex->keyx_cfg[NIX_INTF_TX]; 2024 nibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex); 2025 2026 nibble_ena = rvu_npc_get_tx_nibble_cfg(rvu, nibble_ena); 2027 if (nibble_ena) { 2028 tx_kex &= ~NPC_PARSE_NIBBLE; 2029 tx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena); 2030 mkex->keyx_cfg[NIX_INTF_TX] = tx_kex; 2031 } 2032 2033 /* Configure RX interfaces */ 2034 for (intf = 0; intf < hw->npc_intfs; intf++) { 2035 if (is_npc_intf_tx(intf)) 2036 continue; 2037 2038 /* Set RX MCAM search key size. LA..LE (ltype only) + Channel */ 2039 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 2040 rx_kex); 2041 2042 /* If MCAM lookup doesn't result in a match, drop the received 2043 * packet. And map this action to a counter to count dropped 2044 * packets. 2045 */ 2046 rvu_write64(rvu, blkaddr, 2047 NPC_AF_INTFX_MISS_ACT(intf), NIX_RX_ACTIONOP_DROP); 2048 2049 /* NPC_AF_INTFX_MISS_STAT_ACT[14:12] - counter[11:9] 2050 * NPC_AF_INTFX_MISS_STAT_ACT[8:0] - counter[8:0] 2051 */ 2052 rvu_write64(rvu, blkaddr, 2053 NPC_AF_INTFX_MISS_STAT_ACT(intf), 2054 ((mcam->rx_miss_act_cntr >> 9) << 12) | 2055 hw->npc_stat_ena | mcam->rx_miss_act_cntr); 2056 } 2057 2058 /* Configure TX interfaces */ 2059 for (intf = 0; intf < hw->npc_intfs; intf++) { 2060 if (is_npc_intf_rx(intf)) 2061 continue; 2062 2063 /* Extract Ltypes LID_LA to LID_LE */ 2064 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 2065 tx_kex); 2066 2067 /* Set TX miss action to UCAST_DEFAULT i.e 2068 * transmit the packet on NIX LF SQ's default channel. 2069 */ 2070 rvu_write64(rvu, blkaddr, 2071 NPC_AF_INTFX_MISS_ACT(intf), 2072 NIX_TX_ACTIONOP_UCAST_DEFAULT); 2073 } 2074 } 2075 2076 int rvu_npc_init(struct rvu *rvu) 2077 { 2078 struct npc_kpu_profile_adapter *kpu = &rvu->kpu; 2079 struct npc_pkind *pkind = &rvu->hw->pkind; 2080 struct npc_mcam *mcam = &rvu->hw->mcam; 2081 int blkaddr, entry, bank, err; 2082 2083 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2084 if (blkaddr < 0) { 2085 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 2086 return -ENODEV; 2087 } 2088 2089 rvu_npc_hw_init(rvu, blkaddr); 2090 2091 /* First disable all MCAM entries, to stop traffic towards NIXLFs */ 2092 for (bank = 0; bank < mcam->banks; bank++) { 2093 for (entry = 0; entry < mcam->banksize; entry++) 2094 rvu_write64(rvu, blkaddr, 2095 NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0); 2096 } 2097 2098 err = rvu_alloc_bitmap(&pkind->rsrc); 2099 if (err) 2100 return err; 2101 /* Reserve PKIND#0 for LBKs. Power reset value of LBK_CH_PKIND is '0', 2102 * no need to configure PKIND for all LBKs separately. 2103 */ 2104 rvu_alloc_rsrc(&pkind->rsrc); 2105 2106 /* Allocate mem for pkind to PF and channel mapping info */ 2107 pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max, 2108 sizeof(u32), GFP_KERNEL); 2109 if (!pkind->pfchan_map) 2110 return -ENOMEM; 2111 2112 /* Configure KPU profile */ 2113 npc_parser_profile_init(rvu, blkaddr); 2114 2115 /* Config Outer L2, IPv4's NPC layer info */ 2116 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2, 2117 (kpu->lt_def->pck_ol2.lid << 8) | (kpu->lt_def->pck_ol2.ltype_match << 4) | 2118 kpu->lt_def->pck_ol2.ltype_mask); 2119 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4, 2120 (kpu->lt_def->pck_oip4.lid << 8) | (kpu->lt_def->pck_oip4.ltype_match << 4) | 2121 kpu->lt_def->pck_oip4.ltype_mask); 2122 2123 /* Config Inner IPV4 NPC layer info */ 2124 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4, 2125 (kpu->lt_def->pck_iip4.lid << 8) | (kpu->lt_def->pck_iip4.ltype_match << 4) | 2126 kpu->lt_def->pck_iip4.ltype_mask); 2127 2128 /* Enable below for Rx pkts. 2129 * - Outer IPv4 header checksum validation. 2130 * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2B]. 2131 * - Detect outer L2 multicast address and set NPC_RESULT_S[L2M]. 2132 * - Inner IPv4 header checksum validation. 2133 * - Set non zero checksum error code value 2134 */ 2135 rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG, 2136 rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) | 2137 ((u64)NPC_EC_OIP4_CSUM << 32) | (NPC_EC_IIP4_CSUM << 24) | 2138 BIT_ULL(7) | BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1)); 2139 2140 rvu_npc_setup_interfaces(rvu, blkaddr); 2141 2142 npc_config_secret_key(rvu, blkaddr); 2143 /* Configure MKEX profile */ 2144 npc_load_mkex_profile(rvu, blkaddr, rvu->mkex_pfl_name); 2145 2146 err = npc_mcam_rsrcs_init(rvu, blkaddr); 2147 if (err) 2148 return err; 2149 2150 err = npc_flow_steering_init(rvu, blkaddr); 2151 if (err) { 2152 dev_err(rvu->dev, 2153 "Incorrect mkex profile loaded using default mkex\n"); 2154 npc_load_mkex_profile(rvu, blkaddr, def_pfl_name); 2155 } 2156 2157 return 0; 2158 } 2159 2160 void rvu_npc_freemem(struct rvu *rvu) 2161 { 2162 struct npc_pkind *pkind = &rvu->hw->pkind; 2163 struct npc_mcam *mcam = &rvu->hw->mcam; 2164 2165 kfree(pkind->rsrc.bmap); 2166 kfree(mcam->counters.bmap); 2167 if (rvu->kpu_prfl_addr) 2168 iounmap(rvu->kpu_prfl_addr); 2169 else 2170 kfree(rvu->kpu_fwdata); 2171 mutex_destroy(&mcam->lock); 2172 } 2173 2174 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 2175 int blkaddr, int *alloc_cnt, 2176 int *enable_cnt) 2177 { 2178 struct npc_mcam *mcam = &rvu->hw->mcam; 2179 int entry; 2180 2181 *alloc_cnt = 0; 2182 *enable_cnt = 0; 2183 2184 for (entry = 0; entry < mcam->bmap_entries; entry++) { 2185 if (mcam->entry2pfvf_map[entry] == pcifunc) { 2186 (*alloc_cnt)++; 2187 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry)) 2188 (*enable_cnt)++; 2189 } 2190 } 2191 } 2192 2193 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 2194 int blkaddr, int *alloc_cnt, 2195 int *enable_cnt) 2196 { 2197 struct npc_mcam *mcam = &rvu->hw->mcam; 2198 int cntr; 2199 2200 *alloc_cnt = 0; 2201 *enable_cnt = 0; 2202 2203 for (cntr = 0; cntr < mcam->counters.max; cntr++) { 2204 if (mcam->cntr2pfvf_map[cntr] == pcifunc) { 2205 (*alloc_cnt)++; 2206 if (mcam->cntr_refcnt[cntr]) 2207 (*enable_cnt)++; 2208 } 2209 } 2210 } 2211 2212 static int npc_mcam_verify_entry(struct npc_mcam *mcam, 2213 u16 pcifunc, int entry) 2214 { 2215 /* verify AF installed entries */ 2216 if (is_pffunc_af(pcifunc)) 2217 return 0; 2218 /* Verify if entry is valid and if it is indeed 2219 * allocated to the requesting PFFUNC. 2220 */ 2221 if (entry >= mcam->bmap_entries) 2222 return NPC_MCAM_INVALID_REQ; 2223 2224 if (pcifunc != mcam->entry2pfvf_map[entry]) 2225 return NPC_MCAM_PERM_DENIED; 2226 2227 return 0; 2228 } 2229 2230 static int npc_mcam_verify_counter(struct npc_mcam *mcam, 2231 u16 pcifunc, int cntr) 2232 { 2233 /* Verify if counter is valid and if it is indeed 2234 * allocated to the requesting PFFUNC. 2235 */ 2236 if (cntr >= mcam->counters.max) 2237 return NPC_MCAM_INVALID_REQ; 2238 2239 if (pcifunc != mcam->cntr2pfvf_map[cntr]) 2240 return NPC_MCAM_PERM_DENIED; 2241 2242 return 0; 2243 } 2244 2245 static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam, 2246 int blkaddr, u16 entry, u16 cntr) 2247 { 2248 u16 index = entry & (mcam->banksize - 1); 2249 u32 bank = npc_get_bank(mcam, entry); 2250 struct rvu_hwinfo *hw = rvu->hw; 2251 2252 /* Set mapping and increment counter's refcnt */ 2253 mcam->entry2cntr_map[entry] = cntr; 2254 mcam->cntr_refcnt[cntr]++; 2255 /* Enable stats */ 2256 rvu_write64(rvu, blkaddr, 2257 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 2258 ((cntr >> 9) << 12) | hw->npc_stat_ena | cntr); 2259 } 2260 2261 static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu, 2262 struct npc_mcam *mcam, 2263 int blkaddr, u16 entry, u16 cntr) 2264 { 2265 u16 index = entry & (mcam->banksize - 1); 2266 u32 bank = npc_get_bank(mcam, entry); 2267 2268 /* Remove mapping and reduce counter's refcnt */ 2269 mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP; 2270 mcam->cntr_refcnt[cntr]--; 2271 /* Disable stats */ 2272 rvu_write64(rvu, blkaddr, 2273 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00); 2274 } 2275 2276 /* Sets MCAM entry in bitmap as used. Update 2277 * reverse bitmap too. Should be called with 2278 * 'mcam->lock' held. 2279 */ 2280 static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index) 2281 { 2282 u16 entry, rentry; 2283 2284 entry = index; 2285 rentry = mcam->bmap_entries - index - 1; 2286 2287 __set_bit(entry, mcam->bmap); 2288 __set_bit(rentry, mcam->bmap_reverse); 2289 mcam->bmap_fcnt--; 2290 } 2291 2292 /* Sets MCAM entry in bitmap as free. Update 2293 * reverse bitmap too. Should be called with 2294 * 'mcam->lock' held. 2295 */ 2296 static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index) 2297 { 2298 u16 entry, rentry; 2299 2300 entry = index; 2301 rentry = mcam->bmap_entries - index - 1; 2302 2303 __clear_bit(entry, mcam->bmap); 2304 __clear_bit(rentry, mcam->bmap_reverse); 2305 mcam->bmap_fcnt++; 2306 } 2307 2308 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, 2309 int blkaddr, u16 pcifunc) 2310 { 2311 u16 index, cntr; 2312 2313 /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */ 2314 for (index = 0; index < mcam->bmap_entries; index++) { 2315 if (mcam->entry2pfvf_map[index] == pcifunc) { 2316 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP; 2317 /* Free the entry in bitmap */ 2318 npc_mcam_clear_bit(mcam, index); 2319 /* Disable the entry */ 2320 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); 2321 2322 /* Update entry2counter mapping */ 2323 cntr = mcam->entry2cntr_map[index]; 2324 if (cntr != NPC_MCAM_INVALID_MAP) 2325 npc_unmap_mcam_entry_and_cntr(rvu, mcam, 2326 blkaddr, index, 2327 cntr); 2328 mcam->entry2target_pffunc[index] = 0x0; 2329 } 2330 } 2331 } 2332 2333 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, 2334 u16 pcifunc) 2335 { 2336 u16 cntr; 2337 2338 /* Scan all MCAM counters and free the ones mapped to 'pcifunc' */ 2339 for (cntr = 0; cntr < mcam->counters.max; cntr++) { 2340 if (mcam->cntr2pfvf_map[cntr] == pcifunc) { 2341 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP; 2342 mcam->cntr_refcnt[cntr] = 0; 2343 rvu_free_rsrc(&mcam->counters, cntr); 2344 /* This API is expected to be called after freeing 2345 * MCAM entries, which inturn will remove 2346 * 'entry to counter' mapping. 2347 * No need to do it again. 2348 */ 2349 } 2350 } 2351 } 2352 2353 /* Find area of contiguous free entries of size 'nr'. 2354 * If not found return max contiguous free entries available. 2355 */ 2356 static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start, 2357 u16 nr, u16 *max_area) 2358 { 2359 u16 max_area_start = 0; 2360 u16 index, next, end; 2361 2362 *max_area = 0; 2363 2364 again: 2365 index = find_next_zero_bit(map, size, start); 2366 if (index >= size) 2367 return max_area_start; 2368 2369 end = ((index + nr) >= size) ? size : index + nr; 2370 next = find_next_bit(map, end, index); 2371 if (*max_area < (next - index)) { 2372 *max_area = next - index; 2373 max_area_start = index; 2374 } 2375 2376 if (next < end) { 2377 start = next + 1; 2378 goto again; 2379 } 2380 2381 return max_area_start; 2382 } 2383 2384 /* Find number of free MCAM entries available 2385 * within range i.e in between 'start' and 'end'. 2386 */ 2387 static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end) 2388 { 2389 u16 index, next; 2390 u16 fcnt = 0; 2391 2392 again: 2393 if (start >= end) 2394 return fcnt; 2395 2396 index = find_next_zero_bit(map, end, start); 2397 if (index >= end) 2398 return fcnt; 2399 2400 next = find_next_bit(map, end, index); 2401 if (next <= end) { 2402 fcnt += next - index; 2403 start = next + 1; 2404 goto again; 2405 } 2406 2407 fcnt += end - index; 2408 return fcnt; 2409 } 2410 2411 static void 2412 npc_get_mcam_search_range_priority(struct npc_mcam *mcam, 2413 struct npc_mcam_alloc_entry_req *req, 2414 u16 *start, u16 *end, bool *reverse) 2415 { 2416 u16 fcnt; 2417 2418 if (req->priority == NPC_MCAM_HIGHER_PRIO) 2419 goto hprio; 2420 2421 /* For a low priority entry allocation 2422 * - If reference entry is not in hprio zone then 2423 * search range: ref_entry to end. 2424 * - If reference entry is in hprio zone and if 2425 * request can be accomodated in non-hprio zone then 2426 * search range: 'start of middle zone' to 'end' 2427 * - else search in reverse, so that less number of hprio 2428 * zone entries are allocated. 2429 */ 2430 2431 *reverse = false; 2432 *start = req->ref_entry + 1; 2433 *end = mcam->bmap_entries; 2434 2435 if (req->ref_entry >= mcam->hprio_end) 2436 return; 2437 2438 fcnt = npc_mcam_get_free_count(mcam->bmap, 2439 mcam->hprio_end, mcam->bmap_entries); 2440 if (fcnt > req->count) 2441 *start = mcam->hprio_end; 2442 else 2443 *reverse = true; 2444 return; 2445 2446 hprio: 2447 /* For a high priority entry allocation, search is always 2448 * in reverse to preserve hprio zone entries. 2449 * - If reference entry is not in lprio zone then 2450 * search range: 0 to ref_entry. 2451 * - If reference entry is in lprio zone and if 2452 * request can be accomodated in middle zone then 2453 * search range: 'hprio_end' to 'lprio_start' 2454 */ 2455 2456 *reverse = true; 2457 *start = 0; 2458 *end = req->ref_entry; 2459 2460 if (req->ref_entry <= mcam->lprio_start) 2461 return; 2462 2463 fcnt = npc_mcam_get_free_count(mcam->bmap, 2464 mcam->hprio_end, mcam->lprio_start); 2465 if (fcnt < req->count) 2466 return; 2467 *start = mcam->hprio_end; 2468 *end = mcam->lprio_start; 2469 } 2470 2471 static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc, 2472 struct npc_mcam_alloc_entry_req *req, 2473 struct npc_mcam_alloc_entry_rsp *rsp) 2474 { 2475 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 2476 u16 fcnt, hp_fcnt, lp_fcnt; 2477 u16 start, end, index; 2478 int entry, next_start; 2479 bool reverse = false; 2480 unsigned long *bmap; 2481 u16 max_contig; 2482 2483 mutex_lock(&mcam->lock); 2484 2485 /* Check if there are any free entries */ 2486 if (!mcam->bmap_fcnt) { 2487 mutex_unlock(&mcam->lock); 2488 return NPC_MCAM_ALLOC_FAILED; 2489 } 2490 2491 /* MCAM entries are divided into high priority, middle and 2492 * low priority zones. Idea is to not allocate top and lower 2493 * most entries as much as possible, this is to increase 2494 * probability of honouring priority allocation requests. 2495 * 2496 * Two bitmaps are used for mcam entry management, 2497 * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'. 2498 * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'. 2499 * 2500 * Reverse bitmap is used to allocate entries 2501 * - when a higher priority entry is requested 2502 * - when available free entries are less. 2503 * Lower priority ones out of avaialble free entries are always 2504 * chosen when 'high vs low' question arises. 2505 */ 2506 2507 /* Get the search range for priority allocation request */ 2508 if (req->priority) { 2509 npc_get_mcam_search_range_priority(mcam, req, 2510 &start, &end, &reverse); 2511 goto alloc; 2512 } 2513 2514 /* For a VF base MCAM match rule is set by its PF. And all the 2515 * further MCAM rules installed by VF on its own are 2516 * concatenated with the base rule set by its PF. Hence PF entries 2517 * should be at lower priority compared to VF entries. Otherwise 2518 * base rule is hit always and rules installed by VF will be of 2519 * no use. Hence if the request is from PF and NOT a priority 2520 * allocation request then allocate low priority entries. 2521 */ 2522 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 2523 goto lprio_alloc; 2524 2525 /* Find out the search range for non-priority allocation request 2526 * 2527 * Get MCAM free entry count in middle zone. 2528 */ 2529 lp_fcnt = npc_mcam_get_free_count(mcam->bmap, 2530 mcam->lprio_start, 2531 mcam->bmap_entries); 2532 hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end); 2533 fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt; 2534 2535 /* Check if request can be accomodated in the middle zone */ 2536 if (fcnt > req->count) { 2537 start = mcam->hprio_end; 2538 end = mcam->lprio_start; 2539 } else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) { 2540 /* Expand search zone from half of hprio zone to 2541 * half of lprio zone. 2542 */ 2543 start = mcam->hprio_end / 2; 2544 end = mcam->bmap_entries - (mcam->lprio_count / 2); 2545 reverse = true; 2546 } else { 2547 /* Not enough free entries, search all entries in reverse, 2548 * so that low priority ones will get used up. 2549 */ 2550 lprio_alloc: 2551 reverse = true; 2552 start = 0; 2553 end = mcam->bmap_entries; 2554 } 2555 2556 alloc: 2557 if (reverse) { 2558 bmap = mcam->bmap_reverse; 2559 start = mcam->bmap_entries - start; 2560 end = mcam->bmap_entries - end; 2561 swap(start, end); 2562 } else { 2563 bmap = mcam->bmap; 2564 } 2565 2566 if (req->contig) { 2567 /* Allocate requested number of contiguous entries, if 2568 * unsuccessful find max contiguous entries available. 2569 */ 2570 index = npc_mcam_find_zero_area(bmap, end, start, 2571 req->count, &max_contig); 2572 rsp->count = max_contig; 2573 if (reverse) 2574 rsp->entry = mcam->bmap_entries - index - max_contig; 2575 else 2576 rsp->entry = index; 2577 } else { 2578 /* Allocate requested number of non-contiguous entries, 2579 * if unsuccessful allocate as many as possible. 2580 */ 2581 rsp->count = 0; 2582 next_start = start; 2583 for (entry = 0; entry < req->count; entry++) { 2584 index = find_next_zero_bit(bmap, end, next_start); 2585 if (index >= end) 2586 break; 2587 2588 next_start = start + (index - start) + 1; 2589 2590 /* Save the entry's index */ 2591 if (reverse) 2592 index = mcam->bmap_entries - index - 1; 2593 entry_list[entry] = index; 2594 rsp->count++; 2595 } 2596 } 2597 2598 /* If allocating requested no of entries is unsucessful, 2599 * expand the search range to full bitmap length and retry. 2600 */ 2601 if (!req->priority && (rsp->count < req->count) && 2602 ((end - start) != mcam->bmap_entries)) { 2603 reverse = true; 2604 start = 0; 2605 end = mcam->bmap_entries; 2606 goto alloc; 2607 } 2608 2609 /* For priority entry allocation requests, if allocation is 2610 * failed then expand search to max possible range and retry. 2611 */ 2612 if (req->priority && rsp->count < req->count) { 2613 if (req->priority == NPC_MCAM_LOWER_PRIO && 2614 (start != (req->ref_entry + 1))) { 2615 start = req->ref_entry + 1; 2616 end = mcam->bmap_entries; 2617 reverse = false; 2618 goto alloc; 2619 } else if ((req->priority == NPC_MCAM_HIGHER_PRIO) && 2620 ((end - start) != req->ref_entry)) { 2621 start = 0; 2622 end = req->ref_entry; 2623 reverse = true; 2624 goto alloc; 2625 } 2626 } 2627 2628 /* Copy MCAM entry indices into mbox response entry_list. 2629 * Requester always expects indices in ascending order, so 2630 * reverse the list if reverse bitmap is used for allocation. 2631 */ 2632 if (!req->contig && rsp->count) { 2633 index = 0; 2634 for (entry = rsp->count - 1; entry >= 0; entry--) { 2635 if (reverse) 2636 rsp->entry_list[index++] = entry_list[entry]; 2637 else 2638 rsp->entry_list[entry] = entry_list[entry]; 2639 } 2640 } 2641 2642 /* Mark the allocated entries as used and set nixlf mapping */ 2643 for (entry = 0; entry < rsp->count; entry++) { 2644 index = req->contig ? 2645 (rsp->entry + entry) : rsp->entry_list[entry]; 2646 npc_mcam_set_bit(mcam, index); 2647 mcam->entry2pfvf_map[index] = pcifunc; 2648 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP; 2649 } 2650 2651 /* Update available free count in mbox response */ 2652 rsp->free_count = mcam->bmap_fcnt; 2653 2654 mutex_unlock(&mcam->lock); 2655 return 0; 2656 } 2657 2658 /* Marks bitmaps to reserved the mcam slot */ 2659 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx) 2660 { 2661 struct npc_mcam *mcam = &rvu->hw->mcam; 2662 2663 npc_mcam_set_bit(mcam, entry_idx); 2664 } 2665 2666 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu, 2667 struct npc_mcam_alloc_entry_req *req, 2668 struct npc_mcam_alloc_entry_rsp *rsp) 2669 { 2670 struct npc_mcam *mcam = &rvu->hw->mcam; 2671 u16 pcifunc = req->hdr.pcifunc; 2672 int blkaddr; 2673 2674 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2675 if (blkaddr < 0) 2676 return NPC_MCAM_INVALID_REQ; 2677 2678 rsp->entry = NPC_MCAM_ENTRY_INVALID; 2679 rsp->free_count = 0; 2680 2681 /* Check if ref_entry is within range */ 2682 if (req->priority && req->ref_entry >= mcam->bmap_entries) { 2683 dev_err(rvu->dev, "%s: reference entry %d is out of range\n", 2684 __func__, req->ref_entry); 2685 return NPC_MCAM_INVALID_REQ; 2686 } 2687 2688 /* ref_entry can't be '0' if requested priority is high. 2689 * Can't be last entry if requested priority is low. 2690 */ 2691 if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) || 2692 ((req->ref_entry == (mcam->bmap_entries - 1)) && 2693 req->priority == NPC_MCAM_LOWER_PRIO)) 2694 return NPC_MCAM_INVALID_REQ; 2695 2696 /* Since list of allocated indices needs to be sent to requester, 2697 * max number of non-contiguous entries per mbox msg is limited. 2698 */ 2699 if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES) { 2700 dev_err(rvu->dev, 2701 "%s: %d Non-contiguous MCAM entries requested is more than max (%d) allowed\n", 2702 __func__, req->count, NPC_MAX_NONCONTIG_ENTRIES); 2703 return NPC_MCAM_INVALID_REQ; 2704 } 2705 2706 /* Alloc request from PFFUNC with no NIXLF attached should be denied */ 2707 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) 2708 return NPC_MCAM_ALLOC_DENIED; 2709 2710 return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp); 2711 } 2712 2713 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu, 2714 struct npc_mcam_free_entry_req *req, 2715 struct msg_rsp *rsp) 2716 { 2717 struct npc_mcam *mcam = &rvu->hw->mcam; 2718 u16 pcifunc = req->hdr.pcifunc; 2719 int blkaddr, rc = 0; 2720 u16 cntr; 2721 2722 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2723 if (blkaddr < 0) 2724 return NPC_MCAM_INVALID_REQ; 2725 2726 /* Free request from PFFUNC with no NIXLF attached, ignore */ 2727 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) 2728 return NPC_MCAM_INVALID_REQ; 2729 2730 mutex_lock(&mcam->lock); 2731 2732 if (req->all) 2733 goto free_all; 2734 2735 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2736 if (rc) 2737 goto exit; 2738 2739 mcam->entry2pfvf_map[req->entry] = NPC_MCAM_INVALID_MAP; 2740 mcam->entry2target_pffunc[req->entry] = 0x0; 2741 npc_mcam_clear_bit(mcam, req->entry); 2742 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false); 2743 2744 /* Update entry2counter mapping */ 2745 cntr = mcam->entry2cntr_map[req->entry]; 2746 if (cntr != NPC_MCAM_INVALID_MAP) 2747 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2748 req->entry, cntr); 2749 2750 goto exit; 2751 2752 free_all: 2753 /* Free up all entries allocated to requesting PFFUNC */ 2754 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); 2755 exit: 2756 mutex_unlock(&mcam->lock); 2757 return rc; 2758 } 2759 2760 int rvu_mbox_handler_npc_mcam_read_entry(struct rvu *rvu, 2761 struct npc_mcam_read_entry_req *req, 2762 struct npc_mcam_read_entry_rsp *rsp) 2763 { 2764 struct npc_mcam *mcam = &rvu->hw->mcam; 2765 u16 pcifunc = req->hdr.pcifunc; 2766 int blkaddr, rc; 2767 2768 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2769 if (blkaddr < 0) 2770 return NPC_MCAM_INVALID_REQ; 2771 2772 mutex_lock(&mcam->lock); 2773 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2774 if (!rc) { 2775 npc_read_mcam_entry(rvu, mcam, blkaddr, req->entry, 2776 &rsp->entry_data, 2777 &rsp->intf, &rsp->enable); 2778 } 2779 2780 mutex_unlock(&mcam->lock); 2781 return rc; 2782 } 2783 2784 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu, 2785 struct npc_mcam_write_entry_req *req, 2786 struct msg_rsp *rsp) 2787 { 2788 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 2789 struct npc_mcam *mcam = &rvu->hw->mcam; 2790 u16 pcifunc = req->hdr.pcifunc; 2791 int blkaddr, rc; 2792 u8 nix_intf; 2793 2794 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2795 if (blkaddr < 0) 2796 return NPC_MCAM_INVALID_REQ; 2797 2798 mutex_lock(&mcam->lock); 2799 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2800 if (rc) 2801 goto exit; 2802 2803 if (req->set_cntr && 2804 npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) { 2805 rc = NPC_MCAM_INVALID_REQ; 2806 goto exit; 2807 } 2808 2809 if (!is_npc_interface_valid(rvu, req->intf)) { 2810 rc = NPC_MCAM_INVALID_REQ; 2811 goto exit; 2812 } 2813 2814 if (is_npc_intf_tx(req->intf)) 2815 nix_intf = pfvf->nix_tx_intf; 2816 else 2817 nix_intf = pfvf->nix_rx_intf; 2818 2819 if (!is_pffunc_af(pcifunc) && 2820 npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf, pcifunc)) { 2821 rc = NPC_MCAM_INVALID_REQ; 2822 goto exit; 2823 } 2824 2825 /* For AF installed rules, the nix_intf should be set to target NIX */ 2826 if (is_pffunc_af(req->hdr.pcifunc)) 2827 nix_intf = req->intf; 2828 2829 npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, nix_intf, 2830 &req->entry_data, req->enable_entry); 2831 2832 if (req->set_cntr) 2833 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2834 req->entry, req->cntr); 2835 2836 rc = 0; 2837 exit: 2838 mutex_unlock(&mcam->lock); 2839 return rc; 2840 } 2841 2842 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu, 2843 struct npc_mcam_ena_dis_entry_req *req, 2844 struct msg_rsp *rsp) 2845 { 2846 struct npc_mcam *mcam = &rvu->hw->mcam; 2847 u16 pcifunc = req->hdr.pcifunc; 2848 int blkaddr, rc; 2849 2850 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2851 if (blkaddr < 0) 2852 return NPC_MCAM_INVALID_REQ; 2853 2854 mutex_lock(&mcam->lock); 2855 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2856 mutex_unlock(&mcam->lock); 2857 if (rc) 2858 return rc; 2859 2860 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true); 2861 2862 return 0; 2863 } 2864 2865 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu, 2866 struct npc_mcam_ena_dis_entry_req *req, 2867 struct msg_rsp *rsp) 2868 { 2869 struct npc_mcam *mcam = &rvu->hw->mcam; 2870 u16 pcifunc = req->hdr.pcifunc; 2871 int blkaddr, rc; 2872 2873 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2874 if (blkaddr < 0) 2875 return NPC_MCAM_INVALID_REQ; 2876 2877 mutex_lock(&mcam->lock); 2878 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2879 mutex_unlock(&mcam->lock); 2880 if (rc) 2881 return rc; 2882 2883 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false); 2884 2885 return 0; 2886 } 2887 2888 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu, 2889 struct npc_mcam_shift_entry_req *req, 2890 struct npc_mcam_shift_entry_rsp *rsp) 2891 { 2892 struct npc_mcam *mcam = &rvu->hw->mcam; 2893 u16 pcifunc = req->hdr.pcifunc; 2894 u16 old_entry, new_entry; 2895 int blkaddr, rc = 0; 2896 u16 index, cntr; 2897 2898 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2899 if (blkaddr < 0) 2900 return NPC_MCAM_INVALID_REQ; 2901 2902 if (req->shift_count > NPC_MCAM_MAX_SHIFTS) 2903 return NPC_MCAM_INVALID_REQ; 2904 2905 mutex_lock(&mcam->lock); 2906 for (index = 0; index < req->shift_count; index++) { 2907 old_entry = req->curr_entry[index]; 2908 new_entry = req->new_entry[index]; 2909 2910 /* Check if both old and new entries are valid and 2911 * does belong to this PFFUNC or not. 2912 */ 2913 rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry); 2914 if (rc) 2915 break; 2916 2917 rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry); 2918 if (rc) 2919 break; 2920 2921 /* new_entry should not have a counter mapped */ 2922 if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) { 2923 rc = NPC_MCAM_PERM_DENIED; 2924 break; 2925 } 2926 2927 /* Disable the new_entry */ 2928 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false); 2929 2930 /* Copy rule from old entry to new entry */ 2931 npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry); 2932 2933 /* Copy counter mapping, if any */ 2934 cntr = mcam->entry2cntr_map[old_entry]; 2935 if (cntr != NPC_MCAM_INVALID_MAP) { 2936 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2937 old_entry, cntr); 2938 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2939 new_entry, cntr); 2940 } 2941 2942 /* Enable new_entry and disable old_entry */ 2943 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true); 2944 npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false); 2945 } 2946 2947 /* If shift has failed then report the failed index */ 2948 if (index != req->shift_count) { 2949 rc = NPC_MCAM_PERM_DENIED; 2950 rsp->failed_entry_idx = index; 2951 } 2952 2953 mutex_unlock(&mcam->lock); 2954 return rc; 2955 } 2956 2957 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, 2958 struct npc_mcam_alloc_counter_req *req, 2959 struct npc_mcam_alloc_counter_rsp *rsp) 2960 { 2961 struct npc_mcam *mcam = &rvu->hw->mcam; 2962 u16 pcifunc = req->hdr.pcifunc; 2963 u16 max_contig, cntr; 2964 int blkaddr, index; 2965 2966 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2967 if (blkaddr < 0) 2968 return NPC_MCAM_INVALID_REQ; 2969 2970 /* If the request is from a PFFUNC with no NIXLF attached, ignore */ 2971 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) 2972 return NPC_MCAM_INVALID_REQ; 2973 2974 /* Since list of allocated counter IDs needs to be sent to requester, 2975 * max number of non-contiguous counters per mbox msg is limited. 2976 */ 2977 if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS) 2978 return NPC_MCAM_INVALID_REQ; 2979 2980 mutex_lock(&mcam->lock); 2981 2982 /* Check if unused counters are available or not */ 2983 if (!rvu_rsrc_free_count(&mcam->counters)) { 2984 mutex_unlock(&mcam->lock); 2985 return NPC_MCAM_ALLOC_FAILED; 2986 } 2987 2988 rsp->count = 0; 2989 2990 if (req->contig) { 2991 /* Allocate requested number of contiguous counters, if 2992 * unsuccessful find max contiguous entries available. 2993 */ 2994 index = npc_mcam_find_zero_area(mcam->counters.bmap, 2995 mcam->counters.max, 0, 2996 req->count, &max_contig); 2997 rsp->count = max_contig; 2998 rsp->cntr = index; 2999 for (cntr = index; cntr < (index + max_contig); cntr++) { 3000 __set_bit(cntr, mcam->counters.bmap); 3001 mcam->cntr2pfvf_map[cntr] = pcifunc; 3002 } 3003 } else { 3004 /* Allocate requested number of non-contiguous counters, 3005 * if unsuccessful allocate as many as possible. 3006 */ 3007 for (cntr = 0; cntr < req->count; cntr++) { 3008 index = rvu_alloc_rsrc(&mcam->counters); 3009 if (index < 0) 3010 break; 3011 rsp->cntr_list[cntr] = index; 3012 rsp->count++; 3013 mcam->cntr2pfvf_map[index] = pcifunc; 3014 } 3015 } 3016 3017 mutex_unlock(&mcam->lock); 3018 return 0; 3019 } 3020 3021 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, 3022 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) 3023 { 3024 struct npc_mcam *mcam = &rvu->hw->mcam; 3025 u16 index, entry = 0; 3026 int blkaddr, err; 3027 3028 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3029 if (blkaddr < 0) 3030 return NPC_MCAM_INVALID_REQ; 3031 3032 mutex_lock(&mcam->lock); 3033 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3034 if (err) { 3035 mutex_unlock(&mcam->lock); 3036 return err; 3037 } 3038 3039 /* Mark counter as free/unused */ 3040 mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP; 3041 rvu_free_rsrc(&mcam->counters, req->cntr); 3042 3043 /* Disable all MCAM entry's stats which are using this counter */ 3044 while (entry < mcam->bmap_entries) { 3045 if (!mcam->cntr_refcnt[req->cntr]) 3046 break; 3047 3048 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry); 3049 if (index >= mcam->bmap_entries) 3050 break; 3051 entry = index + 1; 3052 if (mcam->entry2cntr_map[index] != req->cntr) 3053 continue; 3054 3055 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 3056 index, req->cntr); 3057 } 3058 3059 mutex_unlock(&mcam->lock); 3060 return 0; 3061 } 3062 3063 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, 3064 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp) 3065 { 3066 struct npc_mcam *mcam = &rvu->hw->mcam; 3067 u16 index, entry = 0; 3068 int blkaddr, rc; 3069 3070 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3071 if (blkaddr < 0) 3072 return NPC_MCAM_INVALID_REQ; 3073 3074 mutex_lock(&mcam->lock); 3075 rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3076 if (rc) 3077 goto exit; 3078 3079 /* Unmap the MCAM entry and counter */ 3080 if (!req->all) { 3081 rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry); 3082 if (rc) 3083 goto exit; 3084 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 3085 req->entry, req->cntr); 3086 goto exit; 3087 } 3088 3089 /* Disable all MCAM entry's stats which are using this counter */ 3090 while (entry < mcam->bmap_entries) { 3091 if (!mcam->cntr_refcnt[req->cntr]) 3092 break; 3093 3094 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry); 3095 if (index >= mcam->bmap_entries) 3096 break; 3097 entry = index + 1; 3098 3099 if (mcam->entry2cntr_map[index] != req->cntr) 3100 continue; 3101 3102 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 3103 index, req->cntr); 3104 } 3105 exit: 3106 mutex_unlock(&mcam->lock); 3107 return rc; 3108 } 3109 3110 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu, 3111 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) 3112 { 3113 struct npc_mcam *mcam = &rvu->hw->mcam; 3114 int blkaddr, err; 3115 3116 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3117 if (blkaddr < 0) 3118 return NPC_MCAM_INVALID_REQ; 3119 3120 mutex_lock(&mcam->lock); 3121 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3122 mutex_unlock(&mcam->lock); 3123 if (err) 3124 return err; 3125 3126 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00); 3127 3128 return 0; 3129 } 3130 3131 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu, 3132 struct npc_mcam_oper_counter_req *req, 3133 struct npc_mcam_oper_counter_rsp *rsp) 3134 { 3135 struct npc_mcam *mcam = &rvu->hw->mcam; 3136 int blkaddr, err; 3137 3138 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3139 if (blkaddr < 0) 3140 return NPC_MCAM_INVALID_REQ; 3141 3142 mutex_lock(&mcam->lock); 3143 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3144 mutex_unlock(&mcam->lock); 3145 if (err) 3146 return err; 3147 3148 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr)); 3149 rsp->stat &= BIT_ULL(48) - 1; 3150 3151 return 0; 3152 } 3153 3154 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu, 3155 struct npc_mcam_alloc_and_write_entry_req *req, 3156 struct npc_mcam_alloc_and_write_entry_rsp *rsp) 3157 { 3158 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 3159 struct npc_mcam_alloc_counter_req cntr_req; 3160 struct npc_mcam_alloc_counter_rsp cntr_rsp; 3161 struct npc_mcam_alloc_entry_req entry_req; 3162 struct npc_mcam_alloc_entry_rsp entry_rsp; 3163 struct npc_mcam *mcam = &rvu->hw->mcam; 3164 u16 entry = NPC_MCAM_ENTRY_INVALID; 3165 u16 cntr = NPC_MCAM_ENTRY_INVALID; 3166 int blkaddr, rc; 3167 u8 nix_intf; 3168 3169 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3170 if (blkaddr < 0) 3171 return NPC_MCAM_INVALID_REQ; 3172 3173 if (!is_npc_interface_valid(rvu, req->intf)) 3174 return NPC_MCAM_INVALID_REQ; 3175 3176 if (npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf, 3177 req->hdr.pcifunc)) 3178 return NPC_MCAM_INVALID_REQ; 3179 3180 /* Try to allocate a MCAM entry */ 3181 entry_req.hdr.pcifunc = req->hdr.pcifunc; 3182 entry_req.contig = true; 3183 entry_req.priority = req->priority; 3184 entry_req.ref_entry = req->ref_entry; 3185 entry_req.count = 1; 3186 3187 rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, 3188 &entry_req, &entry_rsp); 3189 if (rc) 3190 return rc; 3191 3192 if (!entry_rsp.count) 3193 return NPC_MCAM_ALLOC_FAILED; 3194 3195 entry = entry_rsp.entry; 3196 3197 if (!req->alloc_cntr) 3198 goto write_entry; 3199 3200 /* Now allocate counter */ 3201 cntr_req.hdr.pcifunc = req->hdr.pcifunc; 3202 cntr_req.contig = true; 3203 cntr_req.count = 1; 3204 3205 rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp); 3206 if (rc) { 3207 /* Free allocated MCAM entry */ 3208 mutex_lock(&mcam->lock); 3209 mcam->entry2pfvf_map[entry] = NPC_MCAM_INVALID_MAP; 3210 npc_mcam_clear_bit(mcam, entry); 3211 mutex_unlock(&mcam->lock); 3212 return rc; 3213 } 3214 3215 cntr = cntr_rsp.cntr; 3216 3217 write_entry: 3218 mutex_lock(&mcam->lock); 3219 3220 if (is_npc_intf_tx(req->intf)) 3221 nix_intf = pfvf->nix_tx_intf; 3222 else 3223 nix_intf = pfvf->nix_rx_intf; 3224 3225 npc_config_mcam_entry(rvu, mcam, blkaddr, entry, nix_intf, 3226 &req->entry_data, req->enable_entry); 3227 3228 if (req->alloc_cntr) 3229 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr); 3230 mutex_unlock(&mcam->lock); 3231 3232 rsp->entry = entry; 3233 rsp->cntr = cntr; 3234 3235 return 0; 3236 } 3237 3238 #define GET_KEX_CFG(intf) \ 3239 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf)) 3240 3241 #define GET_KEX_FLAGS(ld) \ 3242 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld)) 3243 3244 #define GET_KEX_LD(intf, lid, lt, ld) \ 3245 rvu_read64(rvu, BLKADDR_NPC, \ 3246 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld)) 3247 3248 #define GET_KEX_LDFLAGS(intf, ld, fl) \ 3249 rvu_read64(rvu, BLKADDR_NPC, \ 3250 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl)) 3251 3252 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req, 3253 struct npc_get_kex_cfg_rsp *rsp) 3254 { 3255 int lid, lt, ld, fl; 3256 3257 rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX); 3258 rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX); 3259 for (lid = 0; lid < NPC_MAX_LID; lid++) { 3260 for (lt = 0; lt < NPC_MAX_LT; lt++) { 3261 for (ld = 0; ld < NPC_MAX_LD; ld++) { 3262 rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] = 3263 GET_KEX_LD(NIX_INTF_RX, lid, lt, ld); 3264 rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] = 3265 GET_KEX_LD(NIX_INTF_TX, lid, lt, ld); 3266 } 3267 } 3268 } 3269 for (ld = 0; ld < NPC_MAX_LD; ld++) 3270 rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld); 3271 3272 for (ld = 0; ld < NPC_MAX_LD; ld++) { 3273 for (fl = 0; fl < NPC_MAX_LFL; fl++) { 3274 rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] = 3275 GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl); 3276 rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] = 3277 GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl); 3278 } 3279 } 3280 memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN); 3281 return 0; 3282 } 3283 3284 static int 3285 npc_set_var_len_offset_pkind(struct rvu *rvu, u16 pcifunc, u64 pkind, 3286 u8 var_len_off, u8 var_len_off_mask, u8 shift_dir) 3287 { 3288 struct npc_kpu_action0 *act0; 3289 u8 shift_count = 0; 3290 int blkaddr; 3291 u64 val; 3292 3293 if (!var_len_off_mask) 3294 return -EINVAL; 3295 3296 if (var_len_off_mask != 0xff) { 3297 if (shift_dir) 3298 shift_count = __ffs(var_len_off_mask); 3299 else 3300 shift_count = (8 - __fls(var_len_off_mask)); 3301 } 3302 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc); 3303 if (blkaddr < 0) { 3304 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 3305 return -EINVAL; 3306 } 3307 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind)); 3308 act0 = (struct npc_kpu_action0 *)&val; 3309 act0->var_len_shift = shift_count; 3310 act0->var_len_right = shift_dir; 3311 act0->var_len_mask = var_len_off_mask; 3312 act0->var_len_offset = var_len_off; 3313 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val); 3314 return 0; 3315 } 3316 3317 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 3318 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 3319 u8 shift_dir) 3320 3321 { 3322 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 3323 int blkaddr, nixlf, rc, intf_mode; 3324 int pf = rvu_get_pf(pcifunc); 3325 u64 rxpkind, txpkind; 3326 u8 cgx_id, lmac_id; 3327 3328 /* use default pkind to disable edsa/higig */ 3329 rxpkind = rvu_npc_get_pkind(rvu, pf); 3330 txpkind = NPC_TX_DEF_PKIND; 3331 intf_mode = NPC_INTF_MODE_DEF; 3332 3333 if (mode & OTX2_PRIV_FLAGS_CUSTOM) { 3334 if (pkind == NPC_RX_CUSTOM_PRE_L2_PKIND) { 3335 rc = npc_set_var_len_offset_pkind(rvu, pcifunc, pkind, 3336 var_len_off, 3337 var_len_off_mask, 3338 shift_dir); 3339 if (rc) 3340 return rc; 3341 } 3342 rxpkind = pkind; 3343 txpkind = pkind; 3344 } 3345 3346 if (dir & PKIND_RX) { 3347 /* rx pkind set req valid only for cgx mapped PFs */ 3348 if (!is_cgx_config_permitted(rvu, pcifunc)) 3349 return 0; 3350 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 3351 3352 rc = cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, 3353 rxpkind); 3354 if (rc) 3355 return rc; 3356 } 3357 3358 if (dir & PKIND_TX) { 3359 /* Tx pkind set request valid if PCIFUNC has NIXLF attached */ 3360 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3361 if (rc) 3362 return rc; 3363 3364 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), 3365 txpkind); 3366 } 3367 3368 pfvf->intf_mode = intf_mode; 3369 return 0; 3370 } 3371 3372 int rvu_mbox_handler_npc_set_pkind(struct rvu *rvu, struct npc_set_pkind *req, 3373 struct msg_rsp *rsp) 3374 { 3375 return rvu_npc_set_parse_mode(rvu, req->hdr.pcifunc, req->mode, 3376 req->dir, req->pkind, req->var_len_off, 3377 req->var_len_off_mask, req->shift_dir); 3378 } 3379 3380 int rvu_mbox_handler_npc_read_base_steer_rule(struct rvu *rvu, 3381 struct msg_req *req, 3382 struct npc_mcam_read_base_rule_rsp *rsp) 3383 { 3384 struct npc_mcam *mcam = &rvu->hw->mcam; 3385 int index, blkaddr, nixlf, rc = 0; 3386 u16 pcifunc = req->hdr.pcifunc; 3387 struct rvu_pfvf *pfvf; 3388 u8 intf, enable; 3389 3390 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3391 if (blkaddr < 0) 3392 return NPC_MCAM_INVALID_REQ; 3393 3394 /* Return the channel number in case of PF */ 3395 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) { 3396 pfvf = rvu_get_pfvf(rvu, pcifunc); 3397 rsp->entry.kw[0] = pfvf->rx_chan_base; 3398 rsp->entry.kw_mask[0] = 0xFFFULL; 3399 goto out; 3400 } 3401 3402 /* Find the pkt steering rule installed by PF to this VF */ 3403 mutex_lock(&mcam->lock); 3404 for (index = 0; index < mcam->bmap_entries; index++) { 3405 if (mcam->entry2target_pffunc[index] == pcifunc) 3406 goto read_entry; 3407 } 3408 3409 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 3410 if (rc < 0) { 3411 mutex_unlock(&mcam->lock); 3412 goto out; 3413 } 3414 /* Read the default ucast entry if there is no pkt steering rule */ 3415 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, 3416 NIXLF_UCAST_ENTRY); 3417 read_entry: 3418 /* Read the mcam entry */ 3419 npc_read_mcam_entry(rvu, mcam, blkaddr, index, &rsp->entry, &intf, 3420 &enable); 3421 mutex_unlock(&mcam->lock); 3422 out: 3423 return rc; 3424 } 3425 3426 int rvu_mbox_handler_npc_mcam_entry_stats(struct rvu *rvu, 3427 struct npc_mcam_get_stats_req *req, 3428 struct npc_mcam_get_stats_rsp *rsp) 3429 { 3430 struct npc_mcam *mcam = &rvu->hw->mcam; 3431 u16 index, cntr; 3432 int blkaddr; 3433 u64 regval; 3434 u32 bank; 3435 3436 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3437 if (blkaddr < 0) 3438 return NPC_MCAM_INVALID_REQ; 3439 3440 mutex_lock(&mcam->lock); 3441 3442 index = req->entry & (mcam->banksize - 1); 3443 bank = npc_get_bank(mcam, req->entry); 3444 3445 /* read MCAM entry STAT_ACT register */ 3446 regval = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank)); 3447 3448 if (!(regval & rvu->hw->npc_stat_ena)) { 3449 rsp->stat_ena = 0; 3450 mutex_unlock(&mcam->lock); 3451 return 0; 3452 } 3453 3454 cntr = regval & 0x1FF; 3455 3456 rsp->stat_ena = 1; 3457 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(cntr)); 3458 rsp->stat &= BIT_ULL(48) - 1; 3459 3460 mutex_unlock(&mcam->lock); 3461 3462 return 0; 3463 } 3464