1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 12 #include "rvu_struct.h" 13 #include "rvu_reg.h" 14 #include "rvu.h" 15 #include "npc.h" 16 #include "cgx.h" 17 #include "npc_profile.h" 18 #include "rvu_npc_hash.h" 19 20 #define RSVD_MCAM_ENTRIES_PER_PF 3 /* Broadcast, Promisc and AllMulticast */ 21 #define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */ 22 23 #define NPC_PARSE_RESULT_DMAC_OFFSET 8 24 #define NPC_HW_TSTAMP_OFFSET 8ULL 25 #define NPC_KEX_CHAN_MASK 0xFFFULL 26 #define NPC_KEX_PF_FUNC_MASK 0xFFFFULL 27 28 #define ALIGN_8B_CEIL(__a) (((__a) + 7) & (-8)) 29 30 static const char def_pfl_name[] = "default"; 31 32 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, 33 int blkaddr, u16 pcifunc); 34 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, 35 u16 pcifunc); 36 37 bool is_npc_intf_tx(u8 intf) 38 { 39 return !!(intf & 0x1); 40 } 41 42 bool is_npc_intf_rx(u8 intf) 43 { 44 return !(intf & 0x1); 45 } 46 47 bool is_npc_interface_valid(struct rvu *rvu, u8 intf) 48 { 49 struct rvu_hwinfo *hw = rvu->hw; 50 51 return intf < hw->npc_intfs; 52 } 53 54 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena) 55 { 56 /* Due to a HW issue in these silicon versions, parse nibble enable 57 * configuration has to be identical for both Rx and Tx interfaces. 58 */ 59 if (is_rvu_96xx_B0(rvu)) 60 return nibble_ena; 61 return 0; 62 } 63 64 static int npc_mcam_verify_pf_func(struct rvu *rvu, 65 struct mcam_entry *entry_data, u8 intf, 66 u16 pcifunc) 67 { 68 u16 pf_func, pf_func_mask; 69 70 if (is_npc_intf_rx(intf)) 71 return 0; 72 73 pf_func_mask = (entry_data->kw_mask[0] >> 32) & 74 NPC_KEX_PF_FUNC_MASK; 75 pf_func = (entry_data->kw[0] >> 32) & NPC_KEX_PF_FUNC_MASK; 76 77 pf_func = be16_to_cpu((__force __be16)pf_func); 78 if (pf_func_mask != NPC_KEX_PF_FUNC_MASK || 79 ((pf_func & ~RVU_PFVF_FUNC_MASK) != 80 (pcifunc & ~RVU_PFVF_FUNC_MASK))) 81 return -EINVAL; 82 83 return 0; 84 } 85 86 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf) 87 { 88 int blkaddr; 89 u64 val = 0; 90 91 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 92 if (blkaddr < 0) 93 return; 94 95 /* Config CPI base for the PKIND */ 96 val = pkind | 1ULL << 62; 97 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); 98 } 99 100 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf) 101 { 102 struct npc_pkind *pkind = &rvu->hw->pkind; 103 u32 map; 104 int i; 105 106 for (i = 0; i < pkind->rsrc.max; i++) { 107 map = pkind->pfchan_map[i]; 108 if (((map >> 16) & 0x3F) == pf) 109 return i; 110 } 111 return -1; 112 } 113 114 #define NPC_AF_ACTION0_PTR_ADVANCE GENMASK_ULL(27, 20) 115 116 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable) 117 { 118 int pkind, blkaddr; 119 u64 val; 120 121 pkind = rvu_npc_get_pkind(rvu, pf); 122 if (pkind < 0) { 123 dev_err(rvu->dev, "%s: pkind not mapped\n", __func__); 124 return -EINVAL; 125 } 126 127 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc); 128 if (blkaddr < 0) { 129 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 130 return -EINVAL; 131 } 132 133 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind)); 134 val &= ~NPC_AF_ACTION0_PTR_ADVANCE; 135 /* If timestamp is enabled then configure NPC to shift 8 bytes */ 136 if (enable) 137 val |= FIELD_PREP(NPC_AF_ACTION0_PTR_ADVANCE, 138 NPC_HW_TSTAMP_OFFSET); 139 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val); 140 141 return 0; 142 } 143 144 static int npc_get_ucast_mcam_index(struct npc_mcam *mcam, u16 pcifunc, 145 int nixlf) 146 { 147 struct rvu_hwinfo *hw = container_of(mcam, struct rvu_hwinfo, mcam); 148 struct rvu *rvu = hw->rvu; 149 int blkaddr = 0, max = 0; 150 struct rvu_block *block; 151 struct rvu_pfvf *pfvf; 152 153 pfvf = rvu_get_pfvf(rvu, pcifunc); 154 /* Given a PF/VF and NIX LF number calculate the unicast mcam 155 * entry index based on the NIX block assigned to the PF/VF. 156 */ 157 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 158 while (blkaddr) { 159 if (pfvf->nix_blkaddr == blkaddr) 160 break; 161 block = &rvu->hw->block[blkaddr]; 162 max += block->lf.max; 163 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 164 } 165 166 return mcam->nixlf_offset + (max + nixlf) * RSVD_MCAM_ENTRIES_PER_NIXLF; 167 } 168 169 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, 170 u16 pcifunc, int nixlf, int type) 171 { 172 int pf = rvu_get_pf(pcifunc); 173 int index; 174 175 /* Check if this is for a PF */ 176 if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) { 177 /* Reserved entries exclude PF0 */ 178 pf--; 179 index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF); 180 /* Broadcast address matching entry should be first so 181 * that the packet can be replicated to all VFs. 182 */ 183 if (type == NIXLF_BCAST_ENTRY) 184 return index; 185 else if (type == NIXLF_ALLMULTI_ENTRY) 186 return index + 1; 187 else if (type == NIXLF_PROMISC_ENTRY) 188 return index + 2; 189 } 190 191 return npc_get_ucast_mcam_index(mcam, pcifunc, nixlf); 192 } 193 194 int npc_get_bank(struct npc_mcam *mcam, int index) 195 { 196 int bank = index / mcam->banksize; 197 198 /* 0,1 & 2,3 banks are combined for this keysize */ 199 if (mcam->keysize == NPC_MCAM_KEY_X2) 200 return bank ? 2 : 0; 201 202 return bank; 203 } 204 205 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, 206 int blkaddr, int index) 207 { 208 int bank = npc_get_bank(mcam, index); 209 u64 cfg; 210 211 index &= (mcam->banksize - 1); 212 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank)); 213 return (cfg & 1); 214 } 215 216 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 217 int blkaddr, int index, bool enable) 218 { 219 int bank = npc_get_bank(mcam, index); 220 int actbank = bank; 221 222 index &= (mcam->banksize - 1); 223 for (; bank < (actbank + mcam->banks_per_entry); bank++) { 224 rvu_write64(rvu, blkaddr, 225 NPC_AF_MCAMEX_BANKX_CFG(index, bank), 226 enable ? 1 : 0); 227 } 228 } 229 230 static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 231 int blkaddr, int index) 232 { 233 int bank = npc_get_bank(mcam, index); 234 int actbank = bank; 235 236 index &= (mcam->banksize - 1); 237 for (; bank < (actbank + mcam->banks_per_entry); bank++) { 238 rvu_write64(rvu, blkaddr, 239 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0); 240 rvu_write64(rvu, blkaddr, 241 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0); 242 243 rvu_write64(rvu, blkaddr, 244 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0); 245 rvu_write64(rvu, blkaddr, 246 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0); 247 248 rvu_write64(rvu, blkaddr, 249 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0); 250 rvu_write64(rvu, blkaddr, 251 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0); 252 } 253 } 254 255 static void npc_get_keyword(struct mcam_entry *entry, int idx, 256 u64 *cam0, u64 *cam1) 257 { 258 u64 kw_mask = 0x00; 259 260 #define CAM_MASK(n) (BIT_ULL(n) - 1) 261 262 /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and 263 * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1. 264 * 265 * Also, only 48 bits of BANKX_CAMX_W1 are valid. 266 */ 267 switch (idx) { 268 case 0: 269 /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */ 270 *cam1 = entry->kw[0]; 271 kw_mask = entry->kw_mask[0]; 272 break; 273 case 1: 274 /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */ 275 *cam1 = entry->kw[1] & CAM_MASK(48); 276 kw_mask = entry->kw_mask[1] & CAM_MASK(48); 277 break; 278 case 2: 279 /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48> 280 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0> 281 */ 282 *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16); 283 *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16); 284 kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16); 285 kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16); 286 break; 287 case 3: 288 /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48> 289 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0> 290 */ 291 *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16); 292 *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16); 293 kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16); 294 kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16); 295 break; 296 case 4: 297 /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32> 298 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0> 299 */ 300 *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32); 301 *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32); 302 kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32); 303 kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32); 304 break; 305 case 5: 306 /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32> 307 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0> 308 */ 309 *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32); 310 *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32); 311 kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32); 312 kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32); 313 break; 314 case 6: 315 /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16> 316 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0> 317 */ 318 *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48); 319 *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48); 320 kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48); 321 kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48); 322 break; 323 case 7: 324 /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */ 325 *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48); 326 kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48); 327 break; 328 } 329 330 *cam1 &= kw_mask; 331 *cam0 = ~*cam1 & kw_mask; 332 } 333 334 static void npc_fill_entryword(struct mcam_entry *entry, int idx, 335 u64 cam0, u64 cam1) 336 { 337 /* Similar to npc_get_keyword, but fills mcam_entry structure from 338 * CAM registers. 339 */ 340 switch (idx) { 341 case 0: 342 entry->kw[0] = cam1; 343 entry->kw_mask[0] = cam1 ^ cam0; 344 break; 345 case 1: 346 entry->kw[1] = cam1; 347 entry->kw_mask[1] = cam1 ^ cam0; 348 break; 349 case 2: 350 entry->kw[1] |= (cam1 & CAM_MASK(16)) << 48; 351 entry->kw[2] = (cam1 >> 16) & CAM_MASK(48); 352 entry->kw_mask[1] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48; 353 entry->kw_mask[2] = ((cam1 ^ cam0) >> 16) & CAM_MASK(48); 354 break; 355 case 3: 356 entry->kw[2] |= (cam1 & CAM_MASK(16)) << 48; 357 entry->kw[3] = (cam1 >> 16) & CAM_MASK(32); 358 entry->kw_mask[2] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48; 359 entry->kw_mask[3] = ((cam1 ^ cam0) >> 16) & CAM_MASK(32); 360 break; 361 case 4: 362 entry->kw[3] |= (cam1 & CAM_MASK(32)) << 32; 363 entry->kw[4] = (cam1 >> 32) & CAM_MASK(32); 364 entry->kw_mask[3] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32; 365 entry->kw_mask[4] = ((cam1 ^ cam0) >> 32) & CAM_MASK(32); 366 break; 367 case 5: 368 entry->kw[4] |= (cam1 & CAM_MASK(32)) << 32; 369 entry->kw[5] = (cam1 >> 32) & CAM_MASK(16); 370 entry->kw_mask[4] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32; 371 entry->kw_mask[5] = ((cam1 ^ cam0) >> 32) & CAM_MASK(16); 372 break; 373 case 6: 374 entry->kw[5] |= (cam1 & CAM_MASK(48)) << 16; 375 entry->kw[6] = (cam1 >> 48) & CAM_MASK(16); 376 entry->kw_mask[5] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16; 377 entry->kw_mask[6] = ((cam1 ^ cam0) >> 48) & CAM_MASK(16); 378 break; 379 case 7: 380 entry->kw[6] |= (cam1 & CAM_MASK(48)) << 16; 381 entry->kw_mask[6] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16; 382 break; 383 } 384 } 385 386 static u64 npc_get_default_entry_action(struct rvu *rvu, struct npc_mcam *mcam, 387 int blkaddr, u16 pf_func) 388 { 389 int bank, nixlf, index; 390 391 /* get ucast entry rule entry index */ 392 if (nix_get_nixlf(rvu, pf_func, &nixlf, NULL)) { 393 dev_err(rvu->dev, "%s: nixlf not attached to pcifunc:0x%x\n", 394 __func__, pf_func); 395 /* Action 0 is drop */ 396 return 0; 397 } 398 399 index = npc_get_nixlf_mcam_index(mcam, pf_func, nixlf, 400 NIXLF_UCAST_ENTRY); 401 bank = npc_get_bank(mcam, index); 402 index &= (mcam->banksize - 1); 403 404 return rvu_read64(rvu, blkaddr, 405 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 406 } 407 408 static void npc_fixup_vf_rule(struct rvu *rvu, struct npc_mcam *mcam, 409 int blkaddr, int index, struct mcam_entry *entry, 410 bool *enable) 411 { 412 struct rvu_npc_mcam_rule *rule; 413 u16 owner, target_func; 414 struct rvu_pfvf *pfvf; 415 u64 rx_action; 416 417 owner = mcam->entry2pfvf_map[index]; 418 target_func = (entry->action >> 4) & 0xffff; 419 /* do nothing when target is LBK/PF or owner is not PF */ 420 if (is_pffunc_af(owner) || is_afvf(target_func) || 421 (owner & RVU_PFVF_FUNC_MASK) || 422 !(target_func & RVU_PFVF_FUNC_MASK)) 423 return; 424 425 /* save entry2target_pffunc */ 426 pfvf = rvu_get_pfvf(rvu, target_func); 427 mcam->entry2target_pffunc[index] = target_func; 428 429 /* don't enable rule when nixlf not attached or initialized */ 430 if (!(is_nixlf_attached(rvu, target_func) && 431 test_bit(NIXLF_INITIALIZED, &pfvf->flags))) 432 *enable = false; 433 434 /* fix up not needed for the rules added by user(ntuple filters) */ 435 list_for_each_entry(rule, &mcam->mcam_rules, list) { 436 if (rule->entry == index) 437 return; 438 } 439 440 /* AF modifies given action iff PF/VF has requested for it */ 441 if ((entry->action & 0xFULL) != NIX_RX_ACTION_DEFAULT) 442 return; 443 444 /* copy VF default entry action to the VF mcam entry */ 445 rx_action = npc_get_default_entry_action(rvu, mcam, blkaddr, 446 target_func); 447 if (rx_action) 448 entry->action = rx_action; 449 } 450 451 static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 452 int blkaddr, int index, u8 intf, 453 struct mcam_entry *entry, bool enable) 454 { 455 int bank = npc_get_bank(mcam, index); 456 int kw = 0, actbank, actindex; 457 u8 tx_intf_mask = ~intf & 0x3; 458 u8 tx_intf = intf; 459 u64 cam0, cam1; 460 461 actbank = bank; /* Save bank id, to set action later on */ 462 actindex = index; 463 index &= (mcam->banksize - 1); 464 465 /* Disable before mcam entry update */ 466 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false); 467 468 /* Clear mcam entry to avoid writes being suppressed by NPC */ 469 npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex); 470 471 /* CAM1 takes the comparison value and 472 * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'. 473 * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0 474 * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1 475 * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare. 476 */ 477 for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) { 478 /* Interface should be set in all banks */ 479 if (is_npc_intf_tx(intf)) { 480 /* Last bit must be set and rest don't care 481 * for TX interfaces 482 */ 483 tx_intf_mask = 0x1; 484 tx_intf = intf & tx_intf_mask; 485 tx_intf_mask = ~tx_intf & tx_intf_mask; 486 } 487 488 rvu_write64(rvu, blkaddr, 489 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 490 tx_intf); 491 rvu_write64(rvu, blkaddr, 492 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 493 tx_intf_mask); 494 495 /* Set the match key */ 496 npc_get_keyword(entry, kw, &cam0, &cam1); 497 rvu_write64(rvu, blkaddr, 498 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1); 499 rvu_write64(rvu, blkaddr, 500 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0); 501 502 npc_get_keyword(entry, kw + 1, &cam0, &cam1); 503 rvu_write64(rvu, blkaddr, 504 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1); 505 rvu_write64(rvu, blkaddr, 506 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0); 507 } 508 509 /* PF installing VF rule */ 510 if (is_npc_intf_rx(intf) && actindex < mcam->bmap_entries) 511 npc_fixup_vf_rule(rvu, mcam, blkaddr, actindex, entry, &enable); 512 513 /* Set 'action' */ 514 rvu_write64(rvu, blkaddr, 515 NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action); 516 517 /* Set TAG 'action' */ 518 rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank), 519 entry->vtag_action); 520 521 /* Enable the entry */ 522 if (enable) 523 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true); 524 } 525 526 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 527 int blkaddr, u16 src, 528 struct mcam_entry *entry, u8 *intf, u8 *ena) 529 { 530 int sbank = npc_get_bank(mcam, src); 531 int bank, kw = 0; 532 u64 cam0, cam1; 533 534 src &= (mcam->banksize - 1); 535 bank = sbank; 536 537 for (; bank < (sbank + mcam->banks_per_entry); bank++, kw = kw + 2) { 538 cam1 = rvu_read64(rvu, blkaddr, 539 NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1)); 540 cam0 = rvu_read64(rvu, blkaddr, 541 NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0)); 542 npc_fill_entryword(entry, kw, cam0, cam1); 543 544 cam1 = rvu_read64(rvu, blkaddr, 545 NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1)); 546 cam0 = rvu_read64(rvu, blkaddr, 547 NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0)); 548 npc_fill_entryword(entry, kw + 1, cam0, cam1); 549 } 550 551 entry->action = rvu_read64(rvu, blkaddr, 552 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank)); 553 entry->vtag_action = 554 rvu_read64(rvu, blkaddr, 555 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank)); 556 *intf = rvu_read64(rvu, blkaddr, 557 NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank, 1)) & 3; 558 *ena = rvu_read64(rvu, blkaddr, 559 NPC_AF_MCAMEX_BANKX_CFG(src, sbank)) & 1; 560 } 561 562 static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 563 int blkaddr, u16 src, u16 dest) 564 { 565 int dbank = npc_get_bank(mcam, dest); 566 int sbank = npc_get_bank(mcam, src); 567 u64 cfg, sreg, dreg; 568 int bank, i; 569 570 src &= (mcam->banksize - 1); 571 dest &= (mcam->banksize - 1); 572 573 /* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */ 574 for (bank = 0; bank < mcam->banks_per_entry; bank++) { 575 sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0); 576 dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0); 577 for (i = 0; i < 6; i++) { 578 cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8)); 579 rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg); 580 } 581 } 582 583 /* Copy action */ 584 cfg = rvu_read64(rvu, blkaddr, 585 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank)); 586 rvu_write64(rvu, blkaddr, 587 NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg); 588 589 /* Copy TAG action */ 590 cfg = rvu_read64(rvu, blkaddr, 591 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank)); 592 rvu_write64(rvu, blkaddr, 593 NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg); 594 595 /* Enable or disable */ 596 cfg = rvu_read64(rvu, blkaddr, 597 NPC_AF_MCAMEX_BANKX_CFG(src, sbank)); 598 rvu_write64(rvu, blkaddr, 599 NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg); 600 } 601 602 static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 603 int blkaddr, int index) 604 { 605 int bank = npc_get_bank(mcam, index); 606 607 index &= (mcam->banksize - 1); 608 return rvu_read64(rvu, blkaddr, 609 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 610 } 611 612 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 613 int nixlf, u64 chan, u8 *mac_addr) 614 { 615 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 616 struct npc_install_flow_req req = { 0 }; 617 struct npc_install_flow_rsp rsp = { 0 }; 618 struct npc_mcam *mcam = &rvu->hw->mcam; 619 struct nix_rx_action action = { 0 }; 620 int blkaddr, index; 621 622 /* AF's and SDP VFs work in promiscuous mode */ 623 if (is_afvf(pcifunc) || is_sdp_vf(pcifunc)) 624 return; 625 626 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 627 if (blkaddr < 0) 628 return; 629 630 /* Ucast rule should not be installed if DMAC 631 * extraction is not supported by the profile. 632 */ 633 if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf)) 634 return; 635 636 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 637 nixlf, NIXLF_UCAST_ENTRY); 638 639 /* Don't change the action if entry is already enabled 640 * Otherwise RSS action may get overwritten. 641 */ 642 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) { 643 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 644 blkaddr, index); 645 } else { 646 action.op = NIX_RX_ACTIONOP_UCAST; 647 action.pf_func = pcifunc; 648 } 649 650 req.default_rule = 1; 651 ether_addr_copy(req.packet.dmac, mac_addr); 652 eth_broadcast_addr((u8 *)&req.mask.dmac); 653 req.features = BIT_ULL(NPC_DMAC); 654 req.channel = chan; 655 req.chan_mask = 0xFFFU; 656 req.intf = pfvf->nix_rx_intf; 657 req.op = action.op; 658 req.hdr.pcifunc = 0; /* AF is requester */ 659 req.vf = action.pf_func; 660 req.index = action.index; 661 req.match_id = action.match_id; 662 req.flow_key_alg = action.flow_key_alg; 663 664 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 665 } 666 667 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 668 int nixlf, u64 chan, u8 chan_cnt) 669 { 670 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 671 struct npc_install_flow_req req = { 0 }; 672 struct npc_install_flow_rsp rsp = { 0 }; 673 struct npc_mcam *mcam = &rvu->hw->mcam; 674 struct rvu_hwinfo *hw = rvu->hw; 675 int blkaddr, ucast_idx, index; 676 struct nix_rx_action action = { 0 }; 677 u64 relaxed_mask; 678 u8 flow_key_alg; 679 680 if (!hw->cap.nix_rx_multicast && is_cgx_vf(rvu, pcifunc)) 681 return; 682 683 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 684 if (blkaddr < 0) 685 return; 686 687 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 688 nixlf, NIXLF_PROMISC_ENTRY); 689 690 if (is_cgx_vf(rvu, pcifunc)) 691 index = npc_get_nixlf_mcam_index(mcam, 692 pcifunc & ~RVU_PFVF_FUNC_MASK, 693 nixlf, NIXLF_PROMISC_ENTRY); 694 695 /* If the corresponding PF's ucast action is RSS, 696 * use the same action for promisc also 697 */ 698 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc, 699 nixlf, NIXLF_UCAST_ENTRY); 700 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx)) 701 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 702 blkaddr, ucast_idx); 703 704 if (action.op != NIX_RX_ACTIONOP_RSS) { 705 *(u64 *)&action = 0; 706 action.op = NIX_RX_ACTIONOP_UCAST; 707 } 708 709 flow_key_alg = action.flow_key_alg; 710 711 /* RX_ACTION set to MCAST for CGX PF's */ 712 if (hw->cap.nix_rx_multicast && pfvf->use_mce_list && 713 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 714 *(u64 *)&action = 0; 715 action.op = NIX_RX_ACTIONOP_MCAST; 716 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 717 action.index = pfvf->promisc_mce_idx; 718 } 719 720 /* For cn10k the upper two bits of the channel number are 721 * cpt channel number. with masking out these bits in the 722 * mcam entry, same entry used for NIX will allow packets 723 * received from cpt for parsing. 724 */ 725 if (!is_rvu_otx2(rvu)) { 726 req.chan_mask = NIX_CHAN_CPT_X2P_MASK; 727 } else { 728 req.chan_mask = 0xFFFU; 729 } 730 731 if (chan_cnt > 1) { 732 if (!is_power_of_2(chan_cnt)) { 733 dev_err(rvu->dev, 734 "%s: channel count more than 1, must be power of 2\n", __func__); 735 return; 736 } 737 relaxed_mask = GENMASK_ULL(BITS_PER_LONG_LONG - 1, 738 ilog2(chan_cnt)); 739 req.chan_mask &= relaxed_mask; 740 } 741 742 req.channel = chan; 743 req.intf = pfvf->nix_rx_intf; 744 req.entry = index; 745 req.op = action.op; 746 req.hdr.pcifunc = 0; /* AF is requester */ 747 req.vf = pcifunc; 748 req.index = action.index; 749 req.match_id = action.match_id; 750 req.flow_key_alg = flow_key_alg; 751 752 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 753 } 754 755 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, 756 int nixlf, bool enable) 757 { 758 struct npc_mcam *mcam = &rvu->hw->mcam; 759 int blkaddr, index; 760 761 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 762 if (blkaddr < 0) 763 return; 764 765 /* Get 'pcifunc' of PF device */ 766 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 767 768 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 769 nixlf, NIXLF_PROMISC_ENTRY); 770 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 771 } 772 773 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 774 int nixlf, u64 chan) 775 { 776 struct rvu_pfvf *pfvf; 777 struct npc_install_flow_req req = { 0 }; 778 struct npc_install_flow_rsp rsp = { 0 }; 779 struct npc_mcam *mcam = &rvu->hw->mcam; 780 struct rvu_hwinfo *hw = rvu->hw; 781 int blkaddr, index; 782 783 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 784 if (blkaddr < 0) 785 return; 786 787 /* Skip LBK VFs */ 788 if (is_afvf(pcifunc)) 789 return; 790 791 /* If pkt replication is not supported, 792 * then only PF is allowed to add a bcast match entry. 793 */ 794 if (!hw->cap.nix_rx_multicast && is_vf(pcifunc)) 795 return; 796 797 /* Get 'pcifunc' of PF device */ 798 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 799 pfvf = rvu_get_pfvf(rvu, pcifunc); 800 801 /* Bcast rule should not be installed if both DMAC 802 * and LXMB extraction is not supported by the profile. 803 */ 804 if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf) && 805 !npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), pfvf->nix_rx_intf)) 806 return; 807 808 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 809 nixlf, NIXLF_BCAST_ENTRY); 810 811 if (!hw->cap.nix_rx_multicast) { 812 /* Early silicon doesn't support pkt replication, 813 * so install entry with UCAST action, so that PF 814 * receives all broadcast packets. 815 */ 816 req.op = NIX_RX_ACTIONOP_UCAST; 817 } else { 818 req.op = NIX_RX_ACTIONOP_MCAST; 819 req.index = pfvf->bcast_mce_idx; 820 } 821 822 eth_broadcast_addr((u8 *)&req.packet.dmac); 823 eth_broadcast_addr((u8 *)&req.mask.dmac); 824 req.features = BIT_ULL(NPC_DMAC); 825 req.channel = chan; 826 req.chan_mask = 0xFFFU; 827 req.intf = pfvf->nix_rx_intf; 828 req.entry = index; 829 req.hdr.pcifunc = 0; /* AF is requester */ 830 req.vf = pcifunc; 831 832 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 833 } 834 835 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 836 bool enable) 837 { 838 struct npc_mcam *mcam = &rvu->hw->mcam; 839 int blkaddr, index; 840 841 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 842 if (blkaddr < 0) 843 return; 844 845 /* Get 'pcifunc' of PF device */ 846 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 847 848 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, 849 NIXLF_BCAST_ENTRY); 850 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 851 } 852 853 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 854 u64 chan) 855 { 856 struct npc_install_flow_req req = { 0 }; 857 struct npc_install_flow_rsp rsp = { 0 }; 858 struct npc_mcam *mcam = &rvu->hw->mcam; 859 struct rvu_hwinfo *hw = rvu->hw; 860 int blkaddr, ucast_idx, index; 861 u8 mac_addr[ETH_ALEN] = { 0 }; 862 struct nix_rx_action action = { 0 }; 863 struct rvu_pfvf *pfvf; 864 u8 flow_key_alg; 865 u16 vf_func; 866 867 /* Only CGX PF/VF can add allmulticast entry */ 868 if (is_afvf(pcifunc) && is_sdp_vf(pcifunc)) 869 return; 870 871 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 872 if (blkaddr < 0) 873 return; 874 875 /* Get 'pcifunc' of PF device */ 876 vf_func = pcifunc & RVU_PFVF_FUNC_MASK; 877 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 878 pfvf = rvu_get_pfvf(rvu, pcifunc); 879 880 /* Mcast rule should not be installed if both DMAC 881 * and LXMB extraction is not supported by the profile. 882 */ 883 if (!npc_is_feature_supported(rvu, BIT_ULL(NPC_DMAC), pfvf->nix_rx_intf) && 884 !npc_is_feature_supported(rvu, BIT_ULL(NPC_LXMB), pfvf->nix_rx_intf)) 885 return; 886 887 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 888 nixlf, NIXLF_ALLMULTI_ENTRY); 889 890 /* If the corresponding PF's ucast action is RSS, 891 * use the same action for multicast entry also 892 */ 893 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc, 894 nixlf, NIXLF_UCAST_ENTRY); 895 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx)) 896 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 897 blkaddr, ucast_idx); 898 899 flow_key_alg = action.flow_key_alg; 900 if (action.op != NIX_RX_ACTIONOP_RSS) { 901 *(u64 *)&action = 0; 902 action.op = NIX_RX_ACTIONOP_UCAST; 903 action.pf_func = pcifunc; 904 } 905 906 /* RX_ACTION set to MCAST for CGX PF's */ 907 if (hw->cap.nix_rx_multicast && pfvf->use_mce_list) { 908 *(u64 *)&action = 0; 909 action.op = NIX_RX_ACTIONOP_MCAST; 910 action.index = pfvf->mcast_mce_idx; 911 } 912 913 mac_addr[0] = 0x01; /* LSB bit of 1st byte in DMAC */ 914 ether_addr_copy(req.packet.dmac, mac_addr); 915 ether_addr_copy(req.mask.dmac, mac_addr); 916 req.features = BIT_ULL(NPC_DMAC); 917 918 /* For cn10k the upper two bits of the channel number are 919 * cpt channel number. with masking out these bits in the 920 * mcam entry, same entry used for NIX will allow packets 921 * received from cpt for parsing. 922 */ 923 if (!is_rvu_otx2(rvu)) 924 req.chan_mask = NIX_CHAN_CPT_X2P_MASK; 925 else 926 req.chan_mask = 0xFFFU; 927 928 req.channel = chan; 929 req.intf = pfvf->nix_rx_intf; 930 req.entry = index; 931 req.op = action.op; 932 req.hdr.pcifunc = 0; /* AF is requester */ 933 req.vf = pcifunc | vf_func; 934 req.index = action.index; 935 req.match_id = action.match_id; 936 req.flow_key_alg = flow_key_alg; 937 938 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); 939 } 940 941 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 942 bool enable) 943 { 944 struct npc_mcam *mcam = &rvu->hw->mcam; 945 int blkaddr, index; 946 947 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 948 if (blkaddr < 0) 949 return; 950 951 /* Get 'pcifunc' of PF device */ 952 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 953 954 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, 955 NIXLF_ALLMULTI_ENTRY); 956 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 957 } 958 959 static void npc_update_vf_flow_entry(struct rvu *rvu, struct npc_mcam *mcam, 960 int blkaddr, u16 pcifunc, u64 rx_action) 961 { 962 int actindex, index, bank, entry; 963 struct rvu_npc_mcam_rule *rule; 964 bool enable, update; 965 966 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 967 return; 968 969 mutex_lock(&mcam->lock); 970 for (index = 0; index < mcam->bmap_entries; index++) { 971 if (mcam->entry2target_pffunc[index] == pcifunc) { 972 update = true; 973 /* update not needed for the rules added via ntuple filters */ 974 list_for_each_entry(rule, &mcam->mcam_rules, list) { 975 if (rule->entry == index) 976 update = false; 977 } 978 if (!update) 979 continue; 980 bank = npc_get_bank(mcam, index); 981 actindex = index; 982 entry = index & (mcam->banksize - 1); 983 984 /* read vf flow entry enable status */ 985 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, 986 actindex); 987 /* disable before mcam entry update */ 988 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, 989 false); 990 /* update 'action' */ 991 rvu_write64(rvu, blkaddr, 992 NPC_AF_MCAMEX_BANKX_ACTION(entry, bank), 993 rx_action); 994 if (enable) 995 npc_enable_mcam_entry(rvu, mcam, blkaddr, 996 actindex, true); 997 } 998 } 999 mutex_unlock(&mcam->lock); 1000 } 1001 1002 static void npc_update_rx_action_with_alg_idx(struct rvu *rvu, struct nix_rx_action action, 1003 struct rvu_pfvf *pfvf, int mcam_index, int blkaddr, 1004 int alg_idx) 1005 1006 { 1007 struct npc_mcam *mcam = &rvu->hw->mcam; 1008 struct rvu_hwinfo *hw = rvu->hw; 1009 int bank, op_rss; 1010 1011 if (!is_mcam_entry_enabled(rvu, mcam, blkaddr, mcam_index)) 1012 return; 1013 1014 op_rss = (!hw->cap.nix_rx_multicast || !pfvf->use_mce_list); 1015 1016 bank = npc_get_bank(mcam, mcam_index); 1017 mcam_index &= (mcam->banksize - 1); 1018 1019 /* If Rx action is MCAST update only RSS algorithm index */ 1020 if (!op_rss) { 1021 *(u64 *)&action = rvu_read64(rvu, blkaddr, 1022 NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank)); 1023 1024 action.flow_key_alg = alg_idx; 1025 } 1026 rvu_write64(rvu, blkaddr, 1027 NPC_AF_MCAMEX_BANKX_ACTION(mcam_index, bank), *(u64 *)&action); 1028 } 1029 1030 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 1031 int group, int alg_idx, int mcam_index) 1032 { 1033 struct npc_mcam *mcam = &rvu->hw->mcam; 1034 struct nix_rx_action action; 1035 int blkaddr, index, bank; 1036 struct rvu_pfvf *pfvf; 1037 1038 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1039 if (blkaddr < 0) 1040 return; 1041 1042 /* Check if this is for reserved default entry */ 1043 if (mcam_index < 0) { 1044 if (group != DEFAULT_RSS_CONTEXT_GROUP) 1045 return; 1046 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1047 nixlf, NIXLF_UCAST_ENTRY); 1048 } else { 1049 /* TODO: validate this mcam index */ 1050 index = mcam_index; 1051 } 1052 1053 if (index >= mcam->total_entries) 1054 return; 1055 1056 bank = npc_get_bank(mcam, index); 1057 index &= (mcam->banksize - 1); 1058 1059 *(u64 *)&action = rvu_read64(rvu, blkaddr, 1060 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 1061 /* Ignore if no action was set earlier */ 1062 if (!*(u64 *)&action) 1063 return; 1064 1065 action.op = NIX_RX_ACTIONOP_RSS; 1066 action.pf_func = pcifunc; 1067 action.index = group; 1068 action.flow_key_alg = alg_idx; 1069 1070 rvu_write64(rvu, blkaddr, 1071 NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action); 1072 1073 /* update the VF flow rule action with the VF default entry action */ 1074 if (mcam_index < 0) 1075 npc_update_vf_flow_entry(rvu, mcam, blkaddr, pcifunc, 1076 *(u64 *)&action); 1077 1078 /* update the action change in default rule */ 1079 pfvf = rvu_get_pfvf(rvu, pcifunc); 1080 if (pfvf->def_ucast_rule) 1081 pfvf->def_ucast_rule->rx_action = action; 1082 1083 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1084 nixlf, NIXLF_PROMISC_ENTRY); 1085 1086 /* If PF's promiscuous entry is enabled, 1087 * Set RSS action for that entry as well 1088 */ 1089 npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, blkaddr, 1090 alg_idx); 1091 1092 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1093 nixlf, NIXLF_ALLMULTI_ENTRY); 1094 /* If PF's allmulti entry is enabled, 1095 * Set RSS action for that entry as well 1096 */ 1097 npc_update_rx_action_with_alg_idx(rvu, action, pfvf, index, blkaddr, 1098 alg_idx); 1099 } 1100 1101 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 1102 int nixlf, int type, bool enable) 1103 { 1104 struct npc_mcam *mcam = &rvu->hw->mcam; 1105 struct rvu_hwinfo *hw = rvu->hw; 1106 struct nix_mce_list *mce_list; 1107 int index, blkaddr, mce_idx; 1108 struct rvu_pfvf *pfvf; 1109 1110 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1111 if (blkaddr < 0) 1112 return; 1113 1114 index = npc_get_nixlf_mcam_index(mcam, pcifunc & ~RVU_PFVF_FUNC_MASK, 1115 nixlf, type); 1116 1117 /* disable MCAM entry when packet replication is not supported by hw */ 1118 if (!hw->cap.nix_rx_multicast && !is_vf(pcifunc)) { 1119 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 1120 return; 1121 } 1122 1123 /* return incase mce list is not enabled */ 1124 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1125 if (hw->cap.nix_rx_multicast && is_vf(pcifunc) && 1126 type != NIXLF_BCAST_ENTRY && !pfvf->use_mce_list) 1127 return; 1128 1129 nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx); 1130 1131 nix_update_mce_list(rvu, pcifunc, mce_list, 1132 mce_idx, index, enable); 1133 if (enable) 1134 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 1135 } 1136 1137 static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc, 1138 int nixlf, bool enable) 1139 { 1140 struct npc_mcam *mcam = &rvu->hw->mcam; 1141 int index, blkaddr; 1142 1143 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1144 if (blkaddr < 0) 1145 return; 1146 1147 /* Ucast MCAM match entry of this PF/VF */ 1148 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 1149 nixlf, NIXLF_UCAST_ENTRY); 1150 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 1151 1152 /* Nothing to do for VFs, on platforms where pkt replication 1153 * is not supported 1154 */ 1155 if ((pcifunc & RVU_PFVF_FUNC_MASK) && !rvu->hw->cap.nix_rx_multicast) 1156 return; 1157 1158 /* add/delete pf_func to broadcast MCE list */ 1159 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, 1160 NIXLF_BCAST_ENTRY, enable); 1161 } 1162 1163 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1164 { 1165 if (nixlf < 0) 1166 return; 1167 1168 npc_enadis_default_entries(rvu, pcifunc, nixlf, false); 1169 1170 /* Delete multicast and promisc MCAM entries */ 1171 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, 1172 NIXLF_ALLMULTI_ENTRY, false); 1173 npc_enadis_default_mce_entry(rvu, pcifunc, nixlf, 1174 NIXLF_PROMISC_ENTRY, false); 1175 } 1176 1177 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable) 1178 { 1179 int blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1180 struct npc_mcam *mcam = &rvu->hw->mcam; 1181 struct rvu_npc_mcam_rule *rule, *tmp; 1182 1183 mutex_lock(&mcam->lock); 1184 1185 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { 1186 if (rule->intf != intf) 1187 continue; 1188 1189 if (rule->entry != entry) 1190 continue; 1191 1192 rule->enable = enable; 1193 mutex_unlock(&mcam->lock); 1194 1195 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1196 entry, enable); 1197 1198 return true; 1199 } 1200 1201 mutex_unlock(&mcam->lock); 1202 return false; 1203 } 1204 1205 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1206 { 1207 if (nixlf < 0) 1208 return; 1209 1210 /* Enables only broadcast match entry. Promisc/Allmulti are enabled 1211 * in set_rx_mode mbox handler. 1212 */ 1213 npc_enadis_default_entries(rvu, pcifunc, nixlf, true); 1214 } 1215 1216 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1217 { 1218 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1219 struct npc_mcam *mcam = &rvu->hw->mcam; 1220 struct rvu_npc_mcam_rule *rule, *tmp; 1221 int blkaddr; 1222 1223 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1224 if (blkaddr < 0) 1225 return; 1226 1227 mutex_lock(&mcam->lock); 1228 1229 /* Disable MCAM entries directing traffic to this 'pcifunc' */ 1230 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { 1231 if (is_npc_intf_rx(rule->intf) && 1232 rule->rx_action.pf_func == pcifunc && 1233 rule->rx_action.op != NIX_RX_ACTIONOP_MCAST) { 1234 npc_enable_mcam_entry(rvu, mcam, blkaddr, 1235 rule->entry, false); 1236 rule->enable = false; 1237 /* Indicate that default rule is disabled */ 1238 if (rule->default_rule) { 1239 pfvf->def_ucast_rule = NULL; 1240 list_del(&rule->list); 1241 kfree(rule); 1242 } 1243 } 1244 } 1245 1246 mutex_unlock(&mcam->lock); 1247 1248 npc_mcam_disable_flows(rvu, pcifunc); 1249 1250 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 1251 } 1252 1253 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 1254 { 1255 struct npc_mcam *mcam = &rvu->hw->mcam; 1256 struct rvu_npc_mcam_rule *rule, *tmp; 1257 int blkaddr; 1258 1259 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1260 if (blkaddr < 0) 1261 return; 1262 1263 mutex_lock(&mcam->lock); 1264 1265 /* Free all MCAM entries owned by this 'pcifunc' */ 1266 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); 1267 1268 /* Free all MCAM counters owned by this 'pcifunc' */ 1269 npc_mcam_free_all_counters(rvu, mcam, pcifunc); 1270 1271 /* Delete MCAM entries owned by this 'pcifunc' */ 1272 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) { 1273 if (rule->owner == pcifunc && !rule->default_rule) { 1274 list_del(&rule->list); 1275 kfree(rule); 1276 } 1277 } 1278 1279 mutex_unlock(&mcam->lock); 1280 1281 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 1282 } 1283 1284 static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr, 1285 struct npc_mcam_kex *mkex, u8 intf) 1286 { 1287 int lid, lt, ld, fl; 1288 1289 if (is_npc_intf_tx(intf)) 1290 return; 1291 1292 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 1293 mkex->keyx_cfg[NIX_INTF_RX]); 1294 1295 /* Program LDATA */ 1296 for (lid = 0; lid < NPC_MAX_LID; lid++) { 1297 for (lt = 0; lt < NPC_MAX_LT; lt++) { 1298 for (ld = 0; ld < NPC_MAX_LD; ld++) 1299 SET_KEX_LD(intf, lid, lt, ld, 1300 mkex->intf_lid_lt_ld[NIX_INTF_RX] 1301 [lid][lt][ld]); 1302 } 1303 } 1304 /* Program LFLAGS */ 1305 for (ld = 0; ld < NPC_MAX_LD; ld++) { 1306 for (fl = 0; fl < NPC_MAX_LFL; fl++) 1307 SET_KEX_LDFLAGS(intf, ld, fl, 1308 mkex->intf_ld_flags[NIX_INTF_RX] 1309 [ld][fl]); 1310 } 1311 } 1312 1313 static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr, 1314 struct npc_mcam_kex *mkex, u8 intf) 1315 { 1316 int lid, lt, ld, fl; 1317 1318 if (is_npc_intf_rx(intf)) 1319 return; 1320 1321 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 1322 mkex->keyx_cfg[NIX_INTF_TX]); 1323 1324 /* Program LDATA */ 1325 for (lid = 0; lid < NPC_MAX_LID; lid++) { 1326 for (lt = 0; lt < NPC_MAX_LT; lt++) { 1327 for (ld = 0; ld < NPC_MAX_LD; ld++) 1328 SET_KEX_LD(intf, lid, lt, ld, 1329 mkex->intf_lid_lt_ld[NIX_INTF_TX] 1330 [lid][lt][ld]); 1331 } 1332 } 1333 /* Program LFLAGS */ 1334 for (ld = 0; ld < NPC_MAX_LD; ld++) { 1335 for (fl = 0; fl < NPC_MAX_LFL; fl++) 1336 SET_KEX_LDFLAGS(intf, ld, fl, 1337 mkex->intf_ld_flags[NIX_INTF_TX] 1338 [ld][fl]); 1339 } 1340 } 1341 1342 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr, 1343 struct npc_mcam_kex *mkex) 1344 { 1345 struct rvu_hwinfo *hw = rvu->hw; 1346 u8 intf; 1347 int ld; 1348 1349 for (ld = 0; ld < NPC_MAX_LD; ld++) 1350 rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld), 1351 mkex->kex_ld_flags[ld]); 1352 1353 for (intf = 0; intf < hw->npc_intfs; intf++) { 1354 npc_program_mkex_rx(rvu, blkaddr, mkex, intf); 1355 npc_program_mkex_tx(rvu, blkaddr, mkex, intf); 1356 } 1357 1358 /* Programme mkex hash profile */ 1359 npc_program_mkex_hash(rvu, blkaddr); 1360 } 1361 1362 static int npc_fwdb_prfl_img_map(struct rvu *rvu, void __iomem **prfl_img_addr, 1363 u64 *size) 1364 { 1365 u64 prfl_addr, prfl_sz; 1366 1367 if (!rvu->fwdata) 1368 return -EINVAL; 1369 1370 prfl_addr = rvu->fwdata->mcam_addr; 1371 prfl_sz = rvu->fwdata->mcam_sz; 1372 1373 if (!prfl_addr || !prfl_sz) 1374 return -EINVAL; 1375 1376 *prfl_img_addr = ioremap_wc(prfl_addr, prfl_sz); 1377 if (!(*prfl_img_addr)) 1378 return -ENOMEM; 1379 1380 *size = prfl_sz; 1381 1382 return 0; 1383 } 1384 1385 /* strtoull of "mkexprof" with base:36 */ 1386 #define MKEX_END_SIGN 0xdeadbeef 1387 1388 static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr, 1389 const char *mkex_profile) 1390 { 1391 struct device *dev = &rvu->pdev->dev; 1392 struct npc_mcam_kex *mcam_kex; 1393 void __iomem *mkex_prfl_addr = NULL; 1394 u64 prfl_sz; 1395 int ret; 1396 1397 /* If user not selected mkex profile */ 1398 if (rvu->kpu_fwdata_sz || 1399 !strncmp(mkex_profile, def_pfl_name, MKEX_NAME_LEN)) 1400 goto program_mkex; 1401 1402 /* Setting up the mapping for mkex profile image */ 1403 ret = npc_fwdb_prfl_img_map(rvu, &mkex_prfl_addr, &prfl_sz); 1404 if (ret < 0) 1405 goto program_mkex; 1406 1407 mcam_kex = (struct npc_mcam_kex __force *)mkex_prfl_addr; 1408 1409 while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) { 1410 /* Compare with mkex mod_param name string */ 1411 if (mcam_kex->mkex_sign == MKEX_SIGN && 1412 !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) { 1413 /* Due to an errata (35786) in A0/B0 pass silicon, 1414 * parse nibble enable configuration has to be 1415 * identical for both Rx and Tx interfaces. 1416 */ 1417 if (!is_rvu_96xx_B0(rvu) || 1418 mcam_kex->keyx_cfg[NIX_INTF_RX] == mcam_kex->keyx_cfg[NIX_INTF_TX]) 1419 rvu->kpu.mkex = mcam_kex; 1420 goto program_mkex; 1421 } 1422 1423 mcam_kex++; 1424 prfl_sz -= sizeof(struct npc_mcam_kex); 1425 } 1426 dev_warn(dev, "Failed to load requested profile: %s\n", mkex_profile); 1427 1428 program_mkex: 1429 dev_info(rvu->dev, "Using %s mkex profile\n", rvu->kpu.mkex->name); 1430 /* Program selected mkex profile */ 1431 npc_program_mkex_profile(rvu, blkaddr, rvu->kpu.mkex); 1432 if (mkex_prfl_addr) 1433 iounmap(mkex_prfl_addr); 1434 } 1435 1436 static void npc_config_kpuaction(struct rvu *rvu, int blkaddr, 1437 const struct npc_kpu_profile_action *kpuaction, 1438 int kpu, int entry, bool pkind) 1439 { 1440 struct npc_kpu_action0 action0 = {0}; 1441 struct npc_kpu_action1 action1 = {0}; 1442 u64 reg; 1443 1444 action1.errlev = kpuaction->errlev; 1445 action1.errcode = kpuaction->errcode; 1446 action1.dp0_offset = kpuaction->dp0_offset; 1447 action1.dp1_offset = kpuaction->dp1_offset; 1448 action1.dp2_offset = kpuaction->dp2_offset; 1449 1450 if (pkind) 1451 reg = NPC_AF_PKINDX_ACTION1(entry); 1452 else 1453 reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry); 1454 1455 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1); 1456 1457 action0.byp_count = kpuaction->bypass_count; 1458 action0.capture_ena = kpuaction->cap_ena; 1459 action0.parse_done = kpuaction->parse_done; 1460 action0.next_state = kpuaction->next_state; 1461 action0.capture_lid = kpuaction->lid; 1462 action0.capture_ltype = kpuaction->ltype; 1463 action0.capture_flags = kpuaction->flags; 1464 action0.ptr_advance = kpuaction->ptr_advance; 1465 action0.var_len_offset = kpuaction->offset; 1466 action0.var_len_mask = kpuaction->mask; 1467 action0.var_len_right = kpuaction->right; 1468 action0.var_len_shift = kpuaction->shift; 1469 1470 if (pkind) 1471 reg = NPC_AF_PKINDX_ACTION0(entry); 1472 else 1473 reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry); 1474 1475 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0); 1476 } 1477 1478 static void npc_config_kpucam(struct rvu *rvu, int blkaddr, 1479 const struct npc_kpu_profile_cam *kpucam, 1480 int kpu, int entry) 1481 { 1482 struct npc_kpu_cam cam0 = {0}; 1483 struct npc_kpu_cam cam1 = {0}; 1484 1485 cam1.state = kpucam->state & kpucam->state_mask; 1486 cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask; 1487 cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask; 1488 cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask; 1489 1490 cam0.state = ~kpucam->state & kpucam->state_mask; 1491 cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask; 1492 cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask; 1493 cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask; 1494 1495 rvu_write64(rvu, blkaddr, 1496 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0); 1497 rvu_write64(rvu, blkaddr, 1498 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1); 1499 } 1500 1501 static inline u64 enable_mask(int count) 1502 { 1503 return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL)); 1504 } 1505 1506 static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu, 1507 const struct npc_kpu_profile *profile) 1508 { 1509 int entry, num_entries, max_entries; 1510 u64 entry_mask; 1511 1512 if (profile->cam_entries != profile->action_entries) { 1513 dev_err(rvu->dev, 1514 "KPU%d: CAM and action entries [%d != %d] not equal\n", 1515 kpu, profile->cam_entries, profile->action_entries); 1516 } 1517 1518 max_entries = rvu->hw->npc_kpu_entries; 1519 1520 /* Program CAM match entries for previous KPU extracted data */ 1521 num_entries = min_t(int, profile->cam_entries, max_entries); 1522 for (entry = 0; entry < num_entries; entry++) 1523 npc_config_kpucam(rvu, blkaddr, 1524 &profile->cam[entry], kpu, entry); 1525 1526 /* Program this KPU's actions */ 1527 num_entries = min_t(int, profile->action_entries, max_entries); 1528 for (entry = 0; entry < num_entries; entry++) 1529 npc_config_kpuaction(rvu, blkaddr, &profile->action[entry], 1530 kpu, entry, false); 1531 1532 /* Enable all programmed entries */ 1533 num_entries = min_t(int, profile->action_entries, profile->cam_entries); 1534 entry_mask = enable_mask(num_entries); 1535 /* Disable first KPU_MAX_CST_ENT entries for built-in profile */ 1536 if (!rvu->kpu.custom) 1537 entry_mask |= GENMASK_ULL(KPU_MAX_CST_ENT - 1, 0); 1538 rvu_write64(rvu, blkaddr, 1539 NPC_AF_KPUX_ENTRY_DISX(kpu, 0), entry_mask); 1540 if (num_entries > 64) { 1541 rvu_write64(rvu, blkaddr, 1542 NPC_AF_KPUX_ENTRY_DISX(kpu, 1), 1543 enable_mask(num_entries - 64)); 1544 } 1545 1546 /* Enable this KPU */ 1547 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01); 1548 } 1549 1550 static int npc_prepare_default_kpu(struct npc_kpu_profile_adapter *profile) 1551 { 1552 profile->custom = 0; 1553 profile->name = def_pfl_name; 1554 profile->version = NPC_KPU_PROFILE_VER; 1555 profile->ikpu = ikpu_action_entries; 1556 profile->pkinds = ARRAY_SIZE(ikpu_action_entries); 1557 profile->kpu = npc_kpu_profiles; 1558 profile->kpus = ARRAY_SIZE(npc_kpu_profiles); 1559 profile->lt_def = &npc_lt_defaults; 1560 profile->mkex = &npc_mkex_default; 1561 profile->mkex_hash = &npc_mkex_hash_default; 1562 1563 return 0; 1564 } 1565 1566 static int npc_apply_custom_kpu(struct rvu *rvu, 1567 struct npc_kpu_profile_adapter *profile) 1568 { 1569 size_t hdr_sz = sizeof(struct npc_kpu_profile_fwdata), offset = 0; 1570 struct npc_kpu_profile_fwdata *fw = rvu->kpu_fwdata; 1571 struct npc_kpu_profile_action *action; 1572 struct npc_kpu_profile_cam *cam; 1573 struct npc_kpu_fwdata *fw_kpu; 1574 int entries; 1575 u16 kpu, entry; 1576 1577 if (rvu->kpu_fwdata_sz < hdr_sz) { 1578 dev_warn(rvu->dev, "Invalid KPU profile size\n"); 1579 return -EINVAL; 1580 } 1581 if (le64_to_cpu(fw->signature) != KPU_SIGN) { 1582 dev_warn(rvu->dev, "Invalid KPU profile signature %llx\n", 1583 fw->signature); 1584 return -EINVAL; 1585 } 1586 /* Verify if the using known profile structure */ 1587 if (NPC_KPU_VER_MAJ(profile->version) > 1588 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)) { 1589 dev_warn(rvu->dev, "Not supported Major version: %d > %d\n", 1590 NPC_KPU_VER_MAJ(profile->version), 1591 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER)); 1592 return -EINVAL; 1593 } 1594 /* Verify if profile is aligned with the required kernel changes */ 1595 if (NPC_KPU_VER_MIN(profile->version) < 1596 NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER)) { 1597 dev_warn(rvu->dev, 1598 "Invalid KPU profile version: %d.%d.%d expected version <= %d.%d.%d\n", 1599 NPC_KPU_VER_MAJ(profile->version), 1600 NPC_KPU_VER_MIN(profile->version), 1601 NPC_KPU_VER_PATCH(profile->version), 1602 NPC_KPU_VER_MAJ(NPC_KPU_PROFILE_VER), 1603 NPC_KPU_VER_MIN(NPC_KPU_PROFILE_VER), 1604 NPC_KPU_VER_PATCH(NPC_KPU_PROFILE_VER)); 1605 return -EINVAL; 1606 } 1607 /* Verify if profile fits the HW */ 1608 if (fw->kpus > profile->kpus) { 1609 dev_warn(rvu->dev, "Not enough KPUs: %d > %ld\n", fw->kpus, 1610 profile->kpus); 1611 return -EINVAL; 1612 } 1613 1614 profile->custom = 1; 1615 profile->name = fw->name; 1616 profile->version = le64_to_cpu(fw->version); 1617 profile->mkex = &fw->mkex; 1618 profile->lt_def = &fw->lt_def; 1619 1620 for (kpu = 0; kpu < fw->kpus; kpu++) { 1621 fw_kpu = (struct npc_kpu_fwdata *)(fw->data + offset); 1622 if (fw_kpu->entries > KPU_MAX_CST_ENT) 1623 dev_warn(rvu->dev, 1624 "Too many custom entries on KPU%d: %d > %d\n", 1625 kpu, fw_kpu->entries, KPU_MAX_CST_ENT); 1626 entries = min(fw_kpu->entries, KPU_MAX_CST_ENT); 1627 cam = (struct npc_kpu_profile_cam *)fw_kpu->data; 1628 offset += sizeof(*fw_kpu) + fw_kpu->entries * sizeof(*cam); 1629 action = (struct npc_kpu_profile_action *)(fw->data + offset); 1630 offset += fw_kpu->entries * sizeof(*action); 1631 if (rvu->kpu_fwdata_sz < hdr_sz + offset) { 1632 dev_warn(rvu->dev, 1633 "Profile size mismatch on KPU%i parsing.\n", 1634 kpu + 1); 1635 return -EINVAL; 1636 } 1637 for (entry = 0; entry < entries; entry++) { 1638 profile->kpu[kpu].cam[entry] = cam[entry]; 1639 profile->kpu[kpu].action[entry] = action[entry]; 1640 } 1641 } 1642 1643 return 0; 1644 } 1645 1646 static int npc_load_kpu_prfl_img(struct rvu *rvu, void __iomem *prfl_addr, 1647 u64 prfl_sz, const char *kpu_profile) 1648 { 1649 struct npc_kpu_profile_fwdata *kpu_data = NULL; 1650 int rc = -EINVAL; 1651 1652 kpu_data = (struct npc_kpu_profile_fwdata __force *)prfl_addr; 1653 if (le64_to_cpu(kpu_data->signature) == KPU_SIGN && 1654 !strncmp(kpu_data->name, kpu_profile, KPU_NAME_LEN)) { 1655 dev_info(rvu->dev, "Loading KPU profile from firmware db: %s\n", 1656 kpu_profile); 1657 rvu->kpu_fwdata = kpu_data; 1658 rvu->kpu_fwdata_sz = prfl_sz; 1659 rvu->kpu_prfl_addr = prfl_addr; 1660 rc = 0; 1661 } 1662 1663 return rc; 1664 } 1665 1666 static int npc_fwdb_detect_load_prfl_img(struct rvu *rvu, uint64_t prfl_sz, 1667 const char *kpu_profile) 1668 { 1669 struct npc_coalesced_kpu_prfl *img_data = NULL; 1670 int i = 0, rc = -EINVAL; 1671 void __iomem *kpu_prfl_addr; 1672 u32 offset; 1673 1674 img_data = (struct npc_coalesced_kpu_prfl __force *)rvu->kpu_prfl_addr; 1675 if (le64_to_cpu(img_data->signature) == KPU_SIGN && 1676 !strncmp(img_data->name, kpu_profile, KPU_NAME_LEN)) { 1677 /* Loaded profile is a single KPU profile. */ 1678 rc = npc_load_kpu_prfl_img(rvu, rvu->kpu_prfl_addr, 1679 prfl_sz, kpu_profile); 1680 goto done; 1681 } 1682 1683 /* Loaded profile is coalesced image, offset of first KPU profile.*/ 1684 offset = offsetof(struct npc_coalesced_kpu_prfl, prfl_sz) + 1685 (img_data->num_prfl * sizeof(uint16_t)); 1686 /* Check if mapped image is coalesced image. */ 1687 while (i < img_data->num_prfl) { 1688 /* Profile image offsets are rounded up to next 8 multiple.*/ 1689 offset = ALIGN_8B_CEIL(offset); 1690 kpu_prfl_addr = (void __iomem *)((uintptr_t)rvu->kpu_prfl_addr + 1691 offset); 1692 rc = npc_load_kpu_prfl_img(rvu, kpu_prfl_addr, 1693 img_data->prfl_sz[i], kpu_profile); 1694 if (!rc) 1695 break; 1696 /* Calculating offset of profile image based on profile size.*/ 1697 offset += img_data->prfl_sz[i]; 1698 i++; 1699 } 1700 done: 1701 return rc; 1702 } 1703 1704 static int npc_load_kpu_profile_fwdb(struct rvu *rvu, const char *kpu_profile) 1705 { 1706 int ret = -EINVAL; 1707 u64 prfl_sz; 1708 1709 /* Setting up the mapping for NPC profile image */ 1710 ret = npc_fwdb_prfl_img_map(rvu, &rvu->kpu_prfl_addr, &prfl_sz); 1711 if (ret < 0) 1712 goto done; 1713 1714 /* Detect if profile is coalesced or single KPU profile and load */ 1715 ret = npc_fwdb_detect_load_prfl_img(rvu, prfl_sz, kpu_profile); 1716 if (ret == 0) 1717 goto done; 1718 1719 /* Cleaning up if KPU profile image from fwdata is not valid. */ 1720 if (rvu->kpu_prfl_addr) { 1721 iounmap(rvu->kpu_prfl_addr); 1722 rvu->kpu_prfl_addr = NULL; 1723 rvu->kpu_fwdata_sz = 0; 1724 rvu->kpu_fwdata = NULL; 1725 } 1726 1727 done: 1728 return ret; 1729 } 1730 1731 static void npc_load_kpu_profile(struct rvu *rvu) 1732 { 1733 struct npc_kpu_profile_adapter *profile = &rvu->kpu; 1734 const char *kpu_profile = rvu->kpu_pfl_name; 1735 const struct firmware *fw = NULL; 1736 bool retry_fwdb = false; 1737 1738 /* If user not specified profile customization */ 1739 if (!strncmp(kpu_profile, def_pfl_name, KPU_NAME_LEN)) 1740 goto revert_to_default; 1741 /* First prepare default KPU, then we'll customize top entries. */ 1742 npc_prepare_default_kpu(profile); 1743 1744 /* Order of preceedence for load loading NPC profile (high to low) 1745 * Firmware binary in filesystem. 1746 * Firmware database method. 1747 * Default KPU profile. 1748 */ 1749 if (!request_firmware_direct(&fw, kpu_profile, rvu->dev)) { 1750 dev_info(rvu->dev, "Loading KPU profile from firmware: %s\n", 1751 kpu_profile); 1752 rvu->kpu_fwdata = kzalloc(fw->size, GFP_KERNEL); 1753 if (rvu->kpu_fwdata) { 1754 memcpy(rvu->kpu_fwdata, fw->data, fw->size); 1755 rvu->kpu_fwdata_sz = fw->size; 1756 } 1757 release_firmware(fw); 1758 retry_fwdb = true; 1759 goto program_kpu; 1760 } 1761 1762 load_image_fwdb: 1763 /* Loading the KPU profile using firmware database */ 1764 if (npc_load_kpu_profile_fwdb(rvu, kpu_profile)) 1765 goto revert_to_default; 1766 1767 program_kpu: 1768 /* Apply profile customization if firmware was loaded. */ 1769 if (!rvu->kpu_fwdata_sz || npc_apply_custom_kpu(rvu, profile)) { 1770 /* If image from firmware filesystem fails to load or invalid 1771 * retry with firmware database method. 1772 */ 1773 if (rvu->kpu_fwdata || rvu->kpu_fwdata_sz) { 1774 /* Loading image from firmware database failed. */ 1775 if (rvu->kpu_prfl_addr) { 1776 iounmap(rvu->kpu_prfl_addr); 1777 rvu->kpu_prfl_addr = NULL; 1778 } else { 1779 kfree(rvu->kpu_fwdata); 1780 } 1781 rvu->kpu_fwdata = NULL; 1782 rvu->kpu_fwdata_sz = 0; 1783 if (retry_fwdb) { 1784 retry_fwdb = false; 1785 goto load_image_fwdb; 1786 } 1787 } 1788 1789 dev_warn(rvu->dev, 1790 "Can't load KPU profile %s. Using default.\n", 1791 kpu_profile); 1792 kfree(rvu->kpu_fwdata); 1793 rvu->kpu_fwdata = NULL; 1794 goto revert_to_default; 1795 } 1796 1797 dev_info(rvu->dev, "Using custom profile '%s', version %d.%d.%d\n", 1798 profile->name, NPC_KPU_VER_MAJ(profile->version), 1799 NPC_KPU_VER_MIN(profile->version), 1800 NPC_KPU_VER_PATCH(profile->version)); 1801 1802 return; 1803 1804 revert_to_default: 1805 npc_prepare_default_kpu(profile); 1806 } 1807 1808 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr) 1809 { 1810 struct rvu_hwinfo *hw = rvu->hw; 1811 int num_pkinds, num_kpus, idx; 1812 1813 /* Disable all KPUs and their entries */ 1814 for (idx = 0; idx < hw->npc_kpus; idx++) { 1815 rvu_write64(rvu, blkaddr, 1816 NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL); 1817 rvu_write64(rvu, blkaddr, 1818 NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL); 1819 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00); 1820 } 1821 1822 /* Load and customize KPU profile. */ 1823 npc_load_kpu_profile(rvu); 1824 1825 /* First program IKPU profile i.e PKIND configs. 1826 * Check HW max count to avoid configuring junk or 1827 * writing to unsupported CSR addresses. 1828 */ 1829 num_pkinds = rvu->kpu.pkinds; 1830 num_pkinds = min_t(int, hw->npc_pkinds, num_pkinds); 1831 1832 for (idx = 0; idx < num_pkinds; idx++) 1833 npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true); 1834 1835 /* Program KPU CAM and Action profiles */ 1836 num_kpus = rvu->kpu.kpus; 1837 num_kpus = min_t(int, hw->npc_kpus, num_kpus); 1838 1839 for (idx = 0; idx < num_kpus; idx++) 1840 npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]); 1841 } 1842 1843 static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr) 1844 { 1845 int nixlf_count = rvu_get_nixlf_count(rvu); 1846 struct npc_mcam *mcam = &rvu->hw->mcam; 1847 int rsvd, err; 1848 u16 index; 1849 int cntr; 1850 u64 cfg; 1851 1852 /* Actual number of MCAM entries vary by entry size */ 1853 cfg = (rvu_read64(rvu, blkaddr, 1854 NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07; 1855 mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize; 1856 mcam->keysize = cfg; 1857 1858 /* Number of banks combined per MCAM entry */ 1859 if (cfg == NPC_MCAM_KEY_X4) 1860 mcam->banks_per_entry = 4; 1861 else if (cfg == NPC_MCAM_KEY_X2) 1862 mcam->banks_per_entry = 2; 1863 else 1864 mcam->banks_per_entry = 1; 1865 1866 /* Reserve one MCAM entry for each of the NIX LF to 1867 * guarantee space to install default matching DMAC rule. 1868 * Also reserve 2 MCAM entries for each PF for default 1869 * channel based matching or 'bcast & promisc' matching to 1870 * support BCAST and PROMISC modes of operation for PFs. 1871 * PF0 is excluded. 1872 */ 1873 rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) + 1874 ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF); 1875 if (mcam->total_entries <= rsvd) { 1876 dev_warn(rvu->dev, 1877 "Insufficient NPC MCAM size %d for pkt I/O, exiting\n", 1878 mcam->total_entries); 1879 return -ENOMEM; 1880 } 1881 1882 mcam->bmap_entries = mcam->total_entries - rsvd; 1883 mcam->nixlf_offset = mcam->bmap_entries; 1884 mcam->pf_offset = mcam->nixlf_offset + nixlf_count; 1885 1886 /* Allocate bitmaps for managing MCAM entries */ 1887 mcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries), 1888 sizeof(long), GFP_KERNEL); 1889 if (!mcam->bmap) 1890 return -ENOMEM; 1891 1892 mcam->bmap_reverse = devm_kcalloc(rvu->dev, 1893 BITS_TO_LONGS(mcam->bmap_entries), 1894 sizeof(long), GFP_KERNEL); 1895 if (!mcam->bmap_reverse) 1896 return -ENOMEM; 1897 1898 mcam->bmap_fcnt = mcam->bmap_entries; 1899 1900 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */ 1901 mcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries, 1902 sizeof(u16), GFP_KERNEL); 1903 if (!mcam->entry2pfvf_map) 1904 return -ENOMEM; 1905 1906 /* Reserve 1/8th of MCAM entries at the bottom for low priority 1907 * allocations and another 1/8th at the top for high priority 1908 * allocations. 1909 */ 1910 mcam->lprio_count = mcam->bmap_entries / 8; 1911 if (mcam->lprio_count > BITS_PER_LONG) 1912 mcam->lprio_count = round_down(mcam->lprio_count, 1913 BITS_PER_LONG); 1914 mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count; 1915 mcam->hprio_count = mcam->lprio_count; 1916 mcam->hprio_end = mcam->hprio_count; 1917 1918 /* Allocate bitmap for managing MCAM counters and memory 1919 * for saving counter to RVU PFFUNC allocation mapping. 1920 */ 1921 err = rvu_alloc_bitmap(&mcam->counters); 1922 if (err) 1923 return err; 1924 1925 mcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max, 1926 sizeof(u16), GFP_KERNEL); 1927 if (!mcam->cntr2pfvf_map) 1928 goto free_mem; 1929 1930 /* Alloc memory for MCAM entry to counter mapping and for tracking 1931 * counter's reference count. 1932 */ 1933 mcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries, 1934 sizeof(u16), GFP_KERNEL); 1935 if (!mcam->entry2cntr_map) 1936 goto free_mem; 1937 1938 mcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max, 1939 sizeof(u16), GFP_KERNEL); 1940 if (!mcam->cntr_refcnt) 1941 goto free_mem; 1942 1943 /* Alloc memory for saving target device of mcam rule */ 1944 mcam->entry2target_pffunc = devm_kcalloc(rvu->dev, mcam->total_entries, 1945 sizeof(u16), GFP_KERNEL); 1946 if (!mcam->entry2target_pffunc) 1947 goto free_mem; 1948 1949 for (index = 0; index < mcam->bmap_entries; index++) { 1950 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP; 1951 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP; 1952 } 1953 1954 for (cntr = 0; cntr < mcam->counters.max; cntr++) 1955 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP; 1956 1957 mutex_init(&mcam->lock); 1958 1959 return 0; 1960 1961 free_mem: 1962 kfree(mcam->counters.bmap); 1963 return -ENOMEM; 1964 } 1965 1966 static void rvu_npc_hw_init(struct rvu *rvu, int blkaddr) 1967 { 1968 struct npc_pkind *pkind = &rvu->hw->pkind; 1969 struct npc_mcam *mcam = &rvu->hw->mcam; 1970 struct rvu_hwinfo *hw = rvu->hw; 1971 u64 npc_const, npc_const1; 1972 u64 npc_const2 = 0; 1973 1974 npc_const = rvu_read64(rvu, blkaddr, NPC_AF_CONST); 1975 npc_const1 = rvu_read64(rvu, blkaddr, NPC_AF_CONST1); 1976 if (npc_const1 & BIT_ULL(63)) 1977 npc_const2 = rvu_read64(rvu, blkaddr, NPC_AF_CONST2); 1978 1979 pkind->rsrc.max = NPC_UNRESERVED_PKIND_COUNT; 1980 hw->npc_pkinds = (npc_const1 >> 12) & 0xFFULL; 1981 hw->npc_kpu_entries = npc_const1 & 0xFFFULL; 1982 hw->npc_kpus = (npc_const >> 8) & 0x1FULL; 1983 hw->npc_intfs = npc_const & 0xFULL; 1984 hw->npc_counters = (npc_const >> 48) & 0xFFFFULL; 1985 1986 mcam->banks = (npc_const >> 44) & 0xFULL; 1987 mcam->banksize = (npc_const >> 28) & 0xFFFFULL; 1988 hw->npc_stat_ena = BIT_ULL(9); 1989 /* Extended set */ 1990 if (npc_const2) { 1991 hw->npc_ext_set = true; 1992 /* 96xx supports only match_stats and npc_counters 1993 * reflected in NPC_AF_CONST reg. 1994 * STAT_SEL and ENA are at [0:8] and 9 bit positions. 1995 * 98xx has both match_stat and ext and npc_counter 1996 * reflected in NPC_AF_CONST2 1997 * STAT_SEL_EXT added at [12:14] bit position. 1998 * cn10k supports only ext and hence npc_counters in 1999 * NPC_AF_CONST is 0 and npc_counters reflected in NPC_AF_CONST2. 2000 * STAT_SEL bitpos incremented from [0:8] to [0:11] and ENA bit moved to 63 2001 */ 2002 if (!hw->npc_counters) 2003 hw->npc_stat_ena = BIT_ULL(63); 2004 hw->npc_counters = (npc_const2 >> 16) & 0xFFFFULL; 2005 mcam->banksize = npc_const2 & 0xFFFFULL; 2006 } 2007 2008 mcam->counters.max = hw->npc_counters; 2009 } 2010 2011 static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr) 2012 { 2013 struct npc_mcam_kex *mkex = rvu->kpu.mkex; 2014 struct npc_mcam *mcam = &rvu->hw->mcam; 2015 struct rvu_hwinfo *hw = rvu->hw; 2016 u64 nibble_ena, rx_kex, tx_kex; 2017 u8 intf; 2018 2019 /* Reserve last counter for MCAM RX miss action which is set to 2020 * drop packet. This way we will know how many pkts didn't match 2021 * any MCAM entry. 2022 */ 2023 mcam->counters.max--; 2024 mcam->rx_miss_act_cntr = mcam->counters.max; 2025 2026 rx_kex = mkex->keyx_cfg[NIX_INTF_RX]; 2027 tx_kex = mkex->keyx_cfg[NIX_INTF_TX]; 2028 nibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex); 2029 2030 nibble_ena = rvu_npc_get_tx_nibble_cfg(rvu, nibble_ena); 2031 if (nibble_ena) { 2032 tx_kex &= ~NPC_PARSE_NIBBLE; 2033 tx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena); 2034 mkex->keyx_cfg[NIX_INTF_TX] = tx_kex; 2035 } 2036 2037 /* Configure RX interfaces */ 2038 for (intf = 0; intf < hw->npc_intfs; intf++) { 2039 if (is_npc_intf_tx(intf)) 2040 continue; 2041 2042 /* Set RX MCAM search key size. LA..LE (ltype only) + Channel */ 2043 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 2044 rx_kex); 2045 2046 /* If MCAM lookup doesn't result in a match, drop the received 2047 * packet. And map this action to a counter to count dropped 2048 * packets. 2049 */ 2050 rvu_write64(rvu, blkaddr, 2051 NPC_AF_INTFX_MISS_ACT(intf), NIX_RX_ACTIONOP_DROP); 2052 2053 /* NPC_AF_INTFX_MISS_STAT_ACT[14:12] - counter[11:9] 2054 * NPC_AF_INTFX_MISS_STAT_ACT[8:0] - counter[8:0] 2055 */ 2056 rvu_write64(rvu, blkaddr, 2057 NPC_AF_INTFX_MISS_STAT_ACT(intf), 2058 ((mcam->rx_miss_act_cntr >> 9) << 12) | 2059 hw->npc_stat_ena | mcam->rx_miss_act_cntr); 2060 } 2061 2062 /* Configure TX interfaces */ 2063 for (intf = 0; intf < hw->npc_intfs; intf++) { 2064 if (is_npc_intf_rx(intf)) 2065 continue; 2066 2067 /* Extract Ltypes LID_LA to LID_LE */ 2068 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf), 2069 tx_kex); 2070 2071 /* Set TX miss action to UCAST_DEFAULT i.e 2072 * transmit the packet on NIX LF SQ's default channel. 2073 */ 2074 rvu_write64(rvu, blkaddr, 2075 NPC_AF_INTFX_MISS_ACT(intf), 2076 NIX_TX_ACTIONOP_UCAST_DEFAULT); 2077 } 2078 } 2079 2080 int rvu_npc_init(struct rvu *rvu) 2081 { 2082 struct npc_kpu_profile_adapter *kpu = &rvu->kpu; 2083 struct npc_pkind *pkind = &rvu->hw->pkind; 2084 struct npc_mcam *mcam = &rvu->hw->mcam; 2085 int blkaddr, entry, bank, err; 2086 2087 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2088 if (blkaddr < 0) { 2089 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 2090 return -ENODEV; 2091 } 2092 2093 rvu_npc_hw_init(rvu, blkaddr); 2094 2095 /* First disable all MCAM entries, to stop traffic towards NIXLFs */ 2096 for (bank = 0; bank < mcam->banks; bank++) { 2097 for (entry = 0; entry < mcam->banksize; entry++) 2098 rvu_write64(rvu, blkaddr, 2099 NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0); 2100 } 2101 2102 err = rvu_alloc_bitmap(&pkind->rsrc); 2103 if (err) 2104 return err; 2105 /* Reserve PKIND#0 for LBKs. Power reset value of LBK_CH_PKIND is '0', 2106 * no need to configure PKIND for all LBKs separately. 2107 */ 2108 rvu_alloc_rsrc(&pkind->rsrc); 2109 2110 /* Allocate mem for pkind to PF and channel mapping info */ 2111 pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max, 2112 sizeof(u32), GFP_KERNEL); 2113 if (!pkind->pfchan_map) 2114 return -ENOMEM; 2115 2116 /* Configure KPU profile */ 2117 npc_parser_profile_init(rvu, blkaddr); 2118 2119 /* Config Outer L2, IPv4's NPC layer info */ 2120 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2, 2121 (kpu->lt_def->pck_ol2.lid << 8) | (kpu->lt_def->pck_ol2.ltype_match << 4) | 2122 kpu->lt_def->pck_ol2.ltype_mask); 2123 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4, 2124 (kpu->lt_def->pck_oip4.lid << 8) | (kpu->lt_def->pck_oip4.ltype_match << 4) | 2125 kpu->lt_def->pck_oip4.ltype_mask); 2126 2127 /* Config Inner IPV4 NPC layer info */ 2128 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4, 2129 (kpu->lt_def->pck_iip4.lid << 8) | (kpu->lt_def->pck_iip4.ltype_match << 4) | 2130 kpu->lt_def->pck_iip4.ltype_mask); 2131 2132 /* Enable below for Rx pkts. 2133 * - Outer IPv4 header checksum validation. 2134 * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2B]. 2135 * - Detect outer L2 multicast address and set NPC_RESULT_S[L2M]. 2136 * - Inner IPv4 header checksum validation. 2137 * - Set non zero checksum error code value 2138 */ 2139 rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG, 2140 rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) | 2141 ((u64)NPC_EC_OIP4_CSUM << 32) | (NPC_EC_IIP4_CSUM << 24) | 2142 BIT_ULL(7) | BIT_ULL(6) | BIT_ULL(2) | BIT_ULL(1)); 2143 2144 rvu_npc_setup_interfaces(rvu, blkaddr); 2145 2146 npc_config_secret_key(rvu, blkaddr); 2147 /* Configure MKEX profile */ 2148 npc_load_mkex_profile(rvu, blkaddr, rvu->mkex_pfl_name); 2149 2150 err = npc_mcam_rsrcs_init(rvu, blkaddr); 2151 if (err) 2152 return err; 2153 2154 err = npc_flow_steering_init(rvu, blkaddr); 2155 if (err) { 2156 dev_err(rvu->dev, 2157 "Incorrect mkex profile loaded using default mkex\n"); 2158 npc_load_mkex_profile(rvu, blkaddr, def_pfl_name); 2159 } 2160 2161 return 0; 2162 } 2163 2164 void rvu_npc_freemem(struct rvu *rvu) 2165 { 2166 struct npc_pkind *pkind = &rvu->hw->pkind; 2167 struct npc_mcam *mcam = &rvu->hw->mcam; 2168 2169 kfree(pkind->rsrc.bmap); 2170 kfree(mcam->counters.bmap); 2171 if (rvu->kpu_prfl_addr) 2172 iounmap(rvu->kpu_prfl_addr); 2173 else 2174 kfree(rvu->kpu_fwdata); 2175 mutex_destroy(&mcam->lock); 2176 } 2177 2178 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 2179 int blkaddr, int *alloc_cnt, 2180 int *enable_cnt) 2181 { 2182 struct npc_mcam *mcam = &rvu->hw->mcam; 2183 int entry; 2184 2185 *alloc_cnt = 0; 2186 *enable_cnt = 0; 2187 2188 for (entry = 0; entry < mcam->bmap_entries; entry++) { 2189 if (mcam->entry2pfvf_map[entry] == pcifunc) { 2190 (*alloc_cnt)++; 2191 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry)) 2192 (*enable_cnt)++; 2193 } 2194 } 2195 } 2196 2197 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 2198 int blkaddr, int *alloc_cnt, 2199 int *enable_cnt) 2200 { 2201 struct npc_mcam *mcam = &rvu->hw->mcam; 2202 int cntr; 2203 2204 *alloc_cnt = 0; 2205 *enable_cnt = 0; 2206 2207 for (cntr = 0; cntr < mcam->counters.max; cntr++) { 2208 if (mcam->cntr2pfvf_map[cntr] == pcifunc) { 2209 (*alloc_cnt)++; 2210 if (mcam->cntr_refcnt[cntr]) 2211 (*enable_cnt)++; 2212 } 2213 } 2214 } 2215 2216 static int npc_mcam_verify_entry(struct npc_mcam *mcam, 2217 u16 pcifunc, int entry) 2218 { 2219 /* verify AF installed entries */ 2220 if (is_pffunc_af(pcifunc)) 2221 return 0; 2222 /* Verify if entry is valid and if it is indeed 2223 * allocated to the requesting PFFUNC. 2224 */ 2225 if (entry >= mcam->bmap_entries) 2226 return NPC_MCAM_INVALID_REQ; 2227 2228 if (pcifunc != mcam->entry2pfvf_map[entry]) 2229 return NPC_MCAM_PERM_DENIED; 2230 2231 return 0; 2232 } 2233 2234 static int npc_mcam_verify_counter(struct npc_mcam *mcam, 2235 u16 pcifunc, int cntr) 2236 { 2237 /* Verify if counter is valid and if it is indeed 2238 * allocated to the requesting PFFUNC. 2239 */ 2240 if (cntr >= mcam->counters.max) 2241 return NPC_MCAM_INVALID_REQ; 2242 2243 if (pcifunc != mcam->cntr2pfvf_map[cntr]) 2244 return NPC_MCAM_PERM_DENIED; 2245 2246 return 0; 2247 } 2248 2249 static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam, 2250 int blkaddr, u16 entry, u16 cntr) 2251 { 2252 u16 index = entry & (mcam->banksize - 1); 2253 u32 bank = npc_get_bank(mcam, entry); 2254 struct rvu_hwinfo *hw = rvu->hw; 2255 2256 /* Set mapping and increment counter's refcnt */ 2257 mcam->entry2cntr_map[entry] = cntr; 2258 mcam->cntr_refcnt[cntr]++; 2259 /* Enable stats */ 2260 rvu_write64(rvu, blkaddr, 2261 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 2262 ((cntr >> 9) << 12) | hw->npc_stat_ena | cntr); 2263 } 2264 2265 static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu, 2266 struct npc_mcam *mcam, 2267 int blkaddr, u16 entry, u16 cntr) 2268 { 2269 u16 index = entry & (mcam->banksize - 1); 2270 u32 bank = npc_get_bank(mcam, entry); 2271 2272 /* Remove mapping and reduce counter's refcnt */ 2273 mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP; 2274 mcam->cntr_refcnt[cntr]--; 2275 /* Disable stats */ 2276 rvu_write64(rvu, blkaddr, 2277 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00); 2278 } 2279 2280 /* Sets MCAM entry in bitmap as used. Update 2281 * reverse bitmap too. Should be called with 2282 * 'mcam->lock' held. 2283 */ 2284 static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index) 2285 { 2286 u16 entry, rentry; 2287 2288 entry = index; 2289 rentry = mcam->bmap_entries - index - 1; 2290 2291 __set_bit(entry, mcam->bmap); 2292 __set_bit(rentry, mcam->bmap_reverse); 2293 mcam->bmap_fcnt--; 2294 } 2295 2296 /* Sets MCAM entry in bitmap as free. Update 2297 * reverse bitmap too. Should be called with 2298 * 'mcam->lock' held. 2299 */ 2300 static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index) 2301 { 2302 u16 entry, rentry; 2303 2304 entry = index; 2305 rentry = mcam->bmap_entries - index - 1; 2306 2307 __clear_bit(entry, mcam->bmap); 2308 __clear_bit(rentry, mcam->bmap_reverse); 2309 mcam->bmap_fcnt++; 2310 } 2311 2312 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, 2313 int blkaddr, u16 pcifunc) 2314 { 2315 u16 index, cntr; 2316 2317 /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */ 2318 for (index = 0; index < mcam->bmap_entries; index++) { 2319 if (mcam->entry2pfvf_map[index] == pcifunc) { 2320 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP; 2321 /* Free the entry in bitmap */ 2322 npc_mcam_clear_bit(mcam, index); 2323 /* Disable the entry */ 2324 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); 2325 2326 /* Update entry2counter mapping */ 2327 cntr = mcam->entry2cntr_map[index]; 2328 if (cntr != NPC_MCAM_INVALID_MAP) 2329 npc_unmap_mcam_entry_and_cntr(rvu, mcam, 2330 blkaddr, index, 2331 cntr); 2332 mcam->entry2target_pffunc[index] = 0x0; 2333 } 2334 } 2335 } 2336 2337 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, 2338 u16 pcifunc) 2339 { 2340 u16 cntr; 2341 2342 /* Scan all MCAM counters and free the ones mapped to 'pcifunc' */ 2343 for (cntr = 0; cntr < mcam->counters.max; cntr++) { 2344 if (mcam->cntr2pfvf_map[cntr] == pcifunc) { 2345 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP; 2346 mcam->cntr_refcnt[cntr] = 0; 2347 rvu_free_rsrc(&mcam->counters, cntr); 2348 /* This API is expected to be called after freeing 2349 * MCAM entries, which inturn will remove 2350 * 'entry to counter' mapping. 2351 * No need to do it again. 2352 */ 2353 } 2354 } 2355 } 2356 2357 /* Find area of contiguous free entries of size 'nr'. 2358 * If not found return max contiguous free entries available. 2359 */ 2360 static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start, 2361 u16 nr, u16 *max_area) 2362 { 2363 u16 max_area_start = 0; 2364 u16 index, next, end; 2365 2366 *max_area = 0; 2367 2368 again: 2369 index = find_next_zero_bit(map, size, start); 2370 if (index >= size) 2371 return max_area_start; 2372 2373 end = ((index + nr) >= size) ? size : index + nr; 2374 next = find_next_bit(map, end, index); 2375 if (*max_area < (next - index)) { 2376 *max_area = next - index; 2377 max_area_start = index; 2378 } 2379 2380 if (next < end) { 2381 start = next + 1; 2382 goto again; 2383 } 2384 2385 return max_area_start; 2386 } 2387 2388 /* Find number of free MCAM entries available 2389 * within range i.e in between 'start' and 'end'. 2390 */ 2391 static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end) 2392 { 2393 u16 index, next; 2394 u16 fcnt = 0; 2395 2396 again: 2397 if (start >= end) 2398 return fcnt; 2399 2400 index = find_next_zero_bit(map, end, start); 2401 if (index >= end) 2402 return fcnt; 2403 2404 next = find_next_bit(map, end, index); 2405 if (next <= end) { 2406 fcnt += next - index; 2407 start = next + 1; 2408 goto again; 2409 } 2410 2411 fcnt += end - index; 2412 return fcnt; 2413 } 2414 2415 static void 2416 npc_get_mcam_search_range_priority(struct npc_mcam *mcam, 2417 struct npc_mcam_alloc_entry_req *req, 2418 u16 *start, u16 *end, bool *reverse) 2419 { 2420 u16 fcnt; 2421 2422 if (req->priority == NPC_MCAM_HIGHER_PRIO) 2423 goto hprio; 2424 2425 /* For a low priority entry allocation 2426 * - If reference entry is not in hprio zone then 2427 * search range: ref_entry to end. 2428 * - If reference entry is in hprio zone and if 2429 * request can be accomodated in non-hprio zone then 2430 * search range: 'start of middle zone' to 'end' 2431 * - else search in reverse, so that less number of hprio 2432 * zone entries are allocated. 2433 */ 2434 2435 *reverse = false; 2436 *start = req->ref_entry + 1; 2437 *end = mcam->bmap_entries; 2438 2439 if (req->ref_entry >= mcam->hprio_end) 2440 return; 2441 2442 fcnt = npc_mcam_get_free_count(mcam->bmap, 2443 mcam->hprio_end, mcam->bmap_entries); 2444 if (fcnt > req->count) 2445 *start = mcam->hprio_end; 2446 else 2447 *reverse = true; 2448 return; 2449 2450 hprio: 2451 /* For a high priority entry allocation, search is always 2452 * in reverse to preserve hprio zone entries. 2453 * - If reference entry is not in lprio zone then 2454 * search range: 0 to ref_entry. 2455 * - If reference entry is in lprio zone and if 2456 * request can be accomodated in middle zone then 2457 * search range: 'hprio_end' to 'lprio_start' 2458 */ 2459 2460 *reverse = true; 2461 *start = 0; 2462 *end = req->ref_entry; 2463 2464 if (req->ref_entry <= mcam->lprio_start) 2465 return; 2466 2467 fcnt = npc_mcam_get_free_count(mcam->bmap, 2468 mcam->hprio_end, mcam->lprio_start); 2469 if (fcnt < req->count) 2470 return; 2471 *start = mcam->hprio_end; 2472 *end = mcam->lprio_start; 2473 } 2474 2475 static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc, 2476 struct npc_mcam_alloc_entry_req *req, 2477 struct npc_mcam_alloc_entry_rsp *rsp) 2478 { 2479 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 2480 u16 fcnt, hp_fcnt, lp_fcnt; 2481 u16 start, end, index; 2482 int entry, next_start; 2483 bool reverse = false; 2484 unsigned long *bmap; 2485 u16 max_contig; 2486 2487 mutex_lock(&mcam->lock); 2488 2489 /* Check if there are any free entries */ 2490 if (!mcam->bmap_fcnt) { 2491 mutex_unlock(&mcam->lock); 2492 return NPC_MCAM_ALLOC_FAILED; 2493 } 2494 2495 /* MCAM entries are divided into high priority, middle and 2496 * low priority zones. Idea is to not allocate top and lower 2497 * most entries as much as possible, this is to increase 2498 * probability of honouring priority allocation requests. 2499 * 2500 * Two bitmaps are used for mcam entry management, 2501 * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'. 2502 * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'. 2503 * 2504 * Reverse bitmap is used to allocate entries 2505 * - when a higher priority entry is requested 2506 * - when available free entries are less. 2507 * Lower priority ones out of avaialble free entries are always 2508 * chosen when 'high vs low' question arises. 2509 */ 2510 2511 /* Get the search range for priority allocation request */ 2512 if (req->priority) { 2513 npc_get_mcam_search_range_priority(mcam, req, 2514 &start, &end, &reverse); 2515 goto alloc; 2516 } 2517 2518 /* For a VF base MCAM match rule is set by its PF. And all the 2519 * further MCAM rules installed by VF on its own are 2520 * concatenated with the base rule set by its PF. Hence PF entries 2521 * should be at lower priority compared to VF entries. Otherwise 2522 * base rule is hit always and rules installed by VF will be of 2523 * no use. Hence if the request is from PF and NOT a priority 2524 * allocation request then allocate low priority entries. 2525 */ 2526 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 2527 goto lprio_alloc; 2528 2529 /* Find out the search range for non-priority allocation request 2530 * 2531 * Get MCAM free entry count in middle zone. 2532 */ 2533 lp_fcnt = npc_mcam_get_free_count(mcam->bmap, 2534 mcam->lprio_start, 2535 mcam->bmap_entries); 2536 hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end); 2537 fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt; 2538 2539 /* Check if request can be accomodated in the middle zone */ 2540 if (fcnt > req->count) { 2541 start = mcam->hprio_end; 2542 end = mcam->lprio_start; 2543 } else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) { 2544 /* Expand search zone from half of hprio zone to 2545 * half of lprio zone. 2546 */ 2547 start = mcam->hprio_end / 2; 2548 end = mcam->bmap_entries - (mcam->lprio_count / 2); 2549 reverse = true; 2550 } else { 2551 /* Not enough free entries, search all entries in reverse, 2552 * so that low priority ones will get used up. 2553 */ 2554 lprio_alloc: 2555 reverse = true; 2556 start = 0; 2557 end = mcam->bmap_entries; 2558 } 2559 2560 alloc: 2561 if (reverse) { 2562 bmap = mcam->bmap_reverse; 2563 start = mcam->bmap_entries - start; 2564 end = mcam->bmap_entries - end; 2565 swap(start, end); 2566 } else { 2567 bmap = mcam->bmap; 2568 } 2569 2570 if (req->contig) { 2571 /* Allocate requested number of contiguous entries, if 2572 * unsuccessful find max contiguous entries available. 2573 */ 2574 index = npc_mcam_find_zero_area(bmap, end, start, 2575 req->count, &max_contig); 2576 rsp->count = max_contig; 2577 if (reverse) 2578 rsp->entry = mcam->bmap_entries - index - max_contig; 2579 else 2580 rsp->entry = index; 2581 } else { 2582 /* Allocate requested number of non-contiguous entries, 2583 * if unsuccessful allocate as many as possible. 2584 */ 2585 rsp->count = 0; 2586 next_start = start; 2587 for (entry = 0; entry < req->count; entry++) { 2588 index = find_next_zero_bit(bmap, end, next_start); 2589 if (index >= end) 2590 break; 2591 2592 next_start = start + (index - start) + 1; 2593 2594 /* Save the entry's index */ 2595 if (reverse) 2596 index = mcam->bmap_entries - index - 1; 2597 entry_list[entry] = index; 2598 rsp->count++; 2599 } 2600 } 2601 2602 /* If allocating requested no of entries is unsucessful, 2603 * expand the search range to full bitmap length and retry. 2604 */ 2605 if (!req->priority && (rsp->count < req->count) && 2606 ((end - start) != mcam->bmap_entries)) { 2607 reverse = true; 2608 start = 0; 2609 end = mcam->bmap_entries; 2610 goto alloc; 2611 } 2612 2613 /* For priority entry allocation requests, if allocation is 2614 * failed then expand search to max possible range and retry. 2615 */ 2616 if (req->priority && rsp->count < req->count) { 2617 if (req->priority == NPC_MCAM_LOWER_PRIO && 2618 (start != (req->ref_entry + 1))) { 2619 start = req->ref_entry + 1; 2620 end = mcam->bmap_entries; 2621 reverse = false; 2622 goto alloc; 2623 } else if ((req->priority == NPC_MCAM_HIGHER_PRIO) && 2624 ((end - start) != req->ref_entry)) { 2625 start = 0; 2626 end = req->ref_entry; 2627 reverse = true; 2628 goto alloc; 2629 } 2630 } 2631 2632 /* Copy MCAM entry indices into mbox response entry_list. 2633 * Requester always expects indices in ascending order, so 2634 * reverse the list if reverse bitmap is used for allocation. 2635 */ 2636 if (!req->contig && rsp->count) { 2637 index = 0; 2638 for (entry = rsp->count - 1; entry >= 0; entry--) { 2639 if (reverse) 2640 rsp->entry_list[index++] = entry_list[entry]; 2641 else 2642 rsp->entry_list[entry] = entry_list[entry]; 2643 } 2644 } 2645 2646 /* Mark the allocated entries as used and set nixlf mapping */ 2647 for (entry = 0; entry < rsp->count; entry++) { 2648 index = req->contig ? 2649 (rsp->entry + entry) : rsp->entry_list[entry]; 2650 npc_mcam_set_bit(mcam, index); 2651 mcam->entry2pfvf_map[index] = pcifunc; 2652 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP; 2653 } 2654 2655 /* Update available free count in mbox response */ 2656 rsp->free_count = mcam->bmap_fcnt; 2657 2658 mutex_unlock(&mcam->lock); 2659 return 0; 2660 } 2661 2662 /* Marks bitmaps to reserved the mcam slot */ 2663 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx) 2664 { 2665 struct npc_mcam *mcam = &rvu->hw->mcam; 2666 2667 npc_mcam_set_bit(mcam, entry_idx); 2668 } 2669 2670 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu, 2671 struct npc_mcam_alloc_entry_req *req, 2672 struct npc_mcam_alloc_entry_rsp *rsp) 2673 { 2674 struct npc_mcam *mcam = &rvu->hw->mcam; 2675 u16 pcifunc = req->hdr.pcifunc; 2676 int blkaddr; 2677 2678 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2679 if (blkaddr < 0) 2680 return NPC_MCAM_INVALID_REQ; 2681 2682 rsp->entry = NPC_MCAM_ENTRY_INVALID; 2683 rsp->free_count = 0; 2684 2685 /* Check if ref_entry is greater that the range 2686 * then set it to max value. 2687 */ 2688 if (req->ref_entry > mcam->bmap_entries) 2689 req->ref_entry = mcam->bmap_entries; 2690 2691 /* ref_entry can't be '0' if requested priority is high. 2692 * Can't be last entry if requested priority is low. 2693 */ 2694 if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) || 2695 ((req->ref_entry == mcam->bmap_entries) && 2696 req->priority == NPC_MCAM_LOWER_PRIO)) 2697 return NPC_MCAM_INVALID_REQ; 2698 2699 /* Since list of allocated indices needs to be sent to requester, 2700 * max number of non-contiguous entries per mbox msg is limited. 2701 */ 2702 if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES) { 2703 dev_err(rvu->dev, 2704 "%s: %d Non-contiguous MCAM entries requested is more than max (%d) allowed\n", 2705 __func__, req->count, NPC_MAX_NONCONTIG_ENTRIES); 2706 return NPC_MCAM_INVALID_REQ; 2707 } 2708 2709 /* Alloc request from PFFUNC with no NIXLF attached should be denied */ 2710 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) 2711 return NPC_MCAM_ALLOC_DENIED; 2712 2713 return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp); 2714 } 2715 2716 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu, 2717 struct npc_mcam_free_entry_req *req, 2718 struct msg_rsp *rsp) 2719 { 2720 struct npc_mcam *mcam = &rvu->hw->mcam; 2721 u16 pcifunc = req->hdr.pcifunc; 2722 int blkaddr, rc = 0; 2723 u16 cntr; 2724 2725 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2726 if (blkaddr < 0) 2727 return NPC_MCAM_INVALID_REQ; 2728 2729 /* Free request from PFFUNC with no NIXLF attached, ignore */ 2730 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) 2731 return NPC_MCAM_INVALID_REQ; 2732 2733 mutex_lock(&mcam->lock); 2734 2735 if (req->all) 2736 goto free_all; 2737 2738 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2739 if (rc) 2740 goto exit; 2741 2742 mcam->entry2pfvf_map[req->entry] = NPC_MCAM_INVALID_MAP; 2743 mcam->entry2target_pffunc[req->entry] = 0x0; 2744 npc_mcam_clear_bit(mcam, req->entry); 2745 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false); 2746 2747 /* Update entry2counter mapping */ 2748 cntr = mcam->entry2cntr_map[req->entry]; 2749 if (cntr != NPC_MCAM_INVALID_MAP) 2750 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2751 req->entry, cntr); 2752 2753 goto exit; 2754 2755 free_all: 2756 /* Free up all entries allocated to requesting PFFUNC */ 2757 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); 2758 exit: 2759 mutex_unlock(&mcam->lock); 2760 return rc; 2761 } 2762 2763 int rvu_mbox_handler_npc_mcam_read_entry(struct rvu *rvu, 2764 struct npc_mcam_read_entry_req *req, 2765 struct npc_mcam_read_entry_rsp *rsp) 2766 { 2767 struct npc_mcam *mcam = &rvu->hw->mcam; 2768 u16 pcifunc = req->hdr.pcifunc; 2769 int blkaddr, rc; 2770 2771 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2772 if (blkaddr < 0) 2773 return NPC_MCAM_INVALID_REQ; 2774 2775 mutex_lock(&mcam->lock); 2776 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2777 if (!rc) { 2778 npc_read_mcam_entry(rvu, mcam, blkaddr, req->entry, 2779 &rsp->entry_data, 2780 &rsp->intf, &rsp->enable); 2781 } 2782 2783 mutex_unlock(&mcam->lock); 2784 return rc; 2785 } 2786 2787 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu, 2788 struct npc_mcam_write_entry_req *req, 2789 struct msg_rsp *rsp) 2790 { 2791 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 2792 struct npc_mcam *mcam = &rvu->hw->mcam; 2793 u16 pcifunc = req->hdr.pcifunc; 2794 int blkaddr, rc; 2795 u8 nix_intf; 2796 2797 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2798 if (blkaddr < 0) 2799 return NPC_MCAM_INVALID_REQ; 2800 2801 mutex_lock(&mcam->lock); 2802 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2803 if (rc) 2804 goto exit; 2805 2806 if (req->set_cntr && 2807 npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) { 2808 rc = NPC_MCAM_INVALID_REQ; 2809 goto exit; 2810 } 2811 2812 if (!is_npc_interface_valid(rvu, req->intf)) { 2813 rc = NPC_MCAM_INVALID_REQ; 2814 goto exit; 2815 } 2816 2817 if (is_npc_intf_tx(req->intf)) 2818 nix_intf = pfvf->nix_tx_intf; 2819 else 2820 nix_intf = pfvf->nix_rx_intf; 2821 2822 if (!is_pffunc_af(pcifunc) && 2823 npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf, pcifunc)) { 2824 rc = NPC_MCAM_INVALID_REQ; 2825 goto exit; 2826 } 2827 2828 /* For AF installed rules, the nix_intf should be set to target NIX */ 2829 if (is_pffunc_af(req->hdr.pcifunc)) 2830 nix_intf = req->intf; 2831 2832 npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, nix_intf, 2833 &req->entry_data, req->enable_entry); 2834 2835 if (req->set_cntr) 2836 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2837 req->entry, req->cntr); 2838 2839 rc = 0; 2840 exit: 2841 mutex_unlock(&mcam->lock); 2842 return rc; 2843 } 2844 2845 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu, 2846 struct npc_mcam_ena_dis_entry_req *req, 2847 struct msg_rsp *rsp) 2848 { 2849 struct npc_mcam *mcam = &rvu->hw->mcam; 2850 u16 pcifunc = req->hdr.pcifunc; 2851 int blkaddr, rc; 2852 2853 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2854 if (blkaddr < 0) 2855 return NPC_MCAM_INVALID_REQ; 2856 2857 mutex_lock(&mcam->lock); 2858 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2859 mutex_unlock(&mcam->lock); 2860 if (rc) 2861 return rc; 2862 2863 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true); 2864 2865 return 0; 2866 } 2867 2868 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu, 2869 struct npc_mcam_ena_dis_entry_req *req, 2870 struct msg_rsp *rsp) 2871 { 2872 struct npc_mcam *mcam = &rvu->hw->mcam; 2873 u16 pcifunc = req->hdr.pcifunc; 2874 int blkaddr, rc; 2875 2876 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2877 if (blkaddr < 0) 2878 return NPC_MCAM_INVALID_REQ; 2879 2880 mutex_lock(&mcam->lock); 2881 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 2882 mutex_unlock(&mcam->lock); 2883 if (rc) 2884 return rc; 2885 2886 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false); 2887 2888 return 0; 2889 } 2890 2891 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu, 2892 struct npc_mcam_shift_entry_req *req, 2893 struct npc_mcam_shift_entry_rsp *rsp) 2894 { 2895 struct npc_mcam *mcam = &rvu->hw->mcam; 2896 u16 pcifunc = req->hdr.pcifunc; 2897 u16 old_entry, new_entry; 2898 int blkaddr, rc = 0; 2899 u16 index, cntr; 2900 2901 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2902 if (blkaddr < 0) 2903 return NPC_MCAM_INVALID_REQ; 2904 2905 if (req->shift_count > NPC_MCAM_MAX_SHIFTS) 2906 return NPC_MCAM_INVALID_REQ; 2907 2908 mutex_lock(&mcam->lock); 2909 for (index = 0; index < req->shift_count; index++) { 2910 old_entry = req->curr_entry[index]; 2911 new_entry = req->new_entry[index]; 2912 2913 /* Check if both old and new entries are valid and 2914 * does belong to this PFFUNC or not. 2915 */ 2916 rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry); 2917 if (rc) 2918 break; 2919 2920 rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry); 2921 if (rc) 2922 break; 2923 2924 /* new_entry should not have a counter mapped */ 2925 if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) { 2926 rc = NPC_MCAM_PERM_DENIED; 2927 break; 2928 } 2929 2930 /* Disable the new_entry */ 2931 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false); 2932 2933 /* Copy rule from old entry to new entry */ 2934 npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry); 2935 2936 /* Copy counter mapping, if any */ 2937 cntr = mcam->entry2cntr_map[old_entry]; 2938 if (cntr != NPC_MCAM_INVALID_MAP) { 2939 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2940 old_entry, cntr); 2941 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2942 new_entry, cntr); 2943 } 2944 2945 /* Enable new_entry and disable old_entry */ 2946 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true); 2947 npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false); 2948 } 2949 2950 /* If shift has failed then report the failed index */ 2951 if (index != req->shift_count) { 2952 rc = NPC_MCAM_PERM_DENIED; 2953 rsp->failed_entry_idx = index; 2954 } 2955 2956 mutex_unlock(&mcam->lock); 2957 return rc; 2958 } 2959 2960 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, 2961 struct npc_mcam_alloc_counter_req *req, 2962 struct npc_mcam_alloc_counter_rsp *rsp) 2963 { 2964 struct npc_mcam *mcam = &rvu->hw->mcam; 2965 u16 pcifunc = req->hdr.pcifunc; 2966 u16 max_contig, cntr; 2967 int blkaddr, index; 2968 2969 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2970 if (blkaddr < 0) 2971 return NPC_MCAM_INVALID_REQ; 2972 2973 /* If the request is from a PFFUNC with no NIXLF attached, ignore */ 2974 if (!is_pffunc_af(pcifunc) && !is_nixlf_attached(rvu, pcifunc)) 2975 return NPC_MCAM_INVALID_REQ; 2976 2977 /* Since list of allocated counter IDs needs to be sent to requester, 2978 * max number of non-contiguous counters per mbox msg is limited. 2979 */ 2980 if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS) 2981 return NPC_MCAM_INVALID_REQ; 2982 2983 mutex_lock(&mcam->lock); 2984 2985 /* Check if unused counters are available or not */ 2986 if (!rvu_rsrc_free_count(&mcam->counters)) { 2987 mutex_unlock(&mcam->lock); 2988 return NPC_MCAM_ALLOC_FAILED; 2989 } 2990 2991 rsp->count = 0; 2992 2993 if (req->contig) { 2994 /* Allocate requested number of contiguous counters, if 2995 * unsuccessful find max contiguous entries available. 2996 */ 2997 index = npc_mcam_find_zero_area(mcam->counters.bmap, 2998 mcam->counters.max, 0, 2999 req->count, &max_contig); 3000 rsp->count = max_contig; 3001 rsp->cntr = index; 3002 for (cntr = index; cntr < (index + max_contig); cntr++) { 3003 __set_bit(cntr, mcam->counters.bmap); 3004 mcam->cntr2pfvf_map[cntr] = pcifunc; 3005 } 3006 } else { 3007 /* Allocate requested number of non-contiguous counters, 3008 * if unsuccessful allocate as many as possible. 3009 */ 3010 for (cntr = 0; cntr < req->count; cntr++) { 3011 index = rvu_alloc_rsrc(&mcam->counters); 3012 if (index < 0) 3013 break; 3014 rsp->cntr_list[cntr] = index; 3015 rsp->count++; 3016 mcam->cntr2pfvf_map[index] = pcifunc; 3017 } 3018 } 3019 3020 mutex_unlock(&mcam->lock); 3021 return 0; 3022 } 3023 3024 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, 3025 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) 3026 { 3027 struct npc_mcam *mcam = &rvu->hw->mcam; 3028 u16 index, entry = 0; 3029 int blkaddr, err; 3030 3031 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3032 if (blkaddr < 0) 3033 return NPC_MCAM_INVALID_REQ; 3034 3035 mutex_lock(&mcam->lock); 3036 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3037 if (err) { 3038 mutex_unlock(&mcam->lock); 3039 return err; 3040 } 3041 3042 /* Mark counter as free/unused */ 3043 mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP; 3044 rvu_free_rsrc(&mcam->counters, req->cntr); 3045 3046 /* Disable all MCAM entry's stats which are using this counter */ 3047 while (entry < mcam->bmap_entries) { 3048 if (!mcam->cntr_refcnt[req->cntr]) 3049 break; 3050 3051 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry); 3052 if (index >= mcam->bmap_entries) 3053 break; 3054 entry = index + 1; 3055 if (mcam->entry2cntr_map[index] != req->cntr) 3056 continue; 3057 3058 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 3059 index, req->cntr); 3060 } 3061 3062 mutex_unlock(&mcam->lock); 3063 return 0; 3064 } 3065 3066 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, 3067 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp) 3068 { 3069 struct npc_mcam *mcam = &rvu->hw->mcam; 3070 u16 index, entry = 0; 3071 int blkaddr, rc; 3072 3073 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3074 if (blkaddr < 0) 3075 return NPC_MCAM_INVALID_REQ; 3076 3077 mutex_lock(&mcam->lock); 3078 rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3079 if (rc) 3080 goto exit; 3081 3082 /* Unmap the MCAM entry and counter */ 3083 if (!req->all) { 3084 rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry); 3085 if (rc) 3086 goto exit; 3087 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 3088 req->entry, req->cntr); 3089 goto exit; 3090 } 3091 3092 /* Disable all MCAM entry's stats which are using this counter */ 3093 while (entry < mcam->bmap_entries) { 3094 if (!mcam->cntr_refcnt[req->cntr]) 3095 break; 3096 3097 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry); 3098 if (index >= mcam->bmap_entries) 3099 break; 3100 entry = index + 1; 3101 3102 if (mcam->entry2cntr_map[index] != req->cntr) 3103 continue; 3104 3105 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 3106 index, req->cntr); 3107 } 3108 exit: 3109 mutex_unlock(&mcam->lock); 3110 return rc; 3111 } 3112 3113 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu, 3114 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) 3115 { 3116 struct npc_mcam *mcam = &rvu->hw->mcam; 3117 int blkaddr, err; 3118 3119 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3120 if (blkaddr < 0) 3121 return NPC_MCAM_INVALID_REQ; 3122 3123 mutex_lock(&mcam->lock); 3124 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3125 mutex_unlock(&mcam->lock); 3126 if (err) 3127 return err; 3128 3129 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00); 3130 3131 return 0; 3132 } 3133 3134 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu, 3135 struct npc_mcam_oper_counter_req *req, 3136 struct npc_mcam_oper_counter_rsp *rsp) 3137 { 3138 struct npc_mcam *mcam = &rvu->hw->mcam; 3139 int blkaddr, err; 3140 3141 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3142 if (blkaddr < 0) 3143 return NPC_MCAM_INVALID_REQ; 3144 3145 mutex_lock(&mcam->lock); 3146 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 3147 mutex_unlock(&mcam->lock); 3148 if (err) 3149 return err; 3150 3151 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr)); 3152 rsp->stat &= BIT_ULL(48) - 1; 3153 3154 return 0; 3155 } 3156 3157 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu, 3158 struct npc_mcam_alloc_and_write_entry_req *req, 3159 struct npc_mcam_alloc_and_write_entry_rsp *rsp) 3160 { 3161 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 3162 struct npc_mcam_alloc_counter_req cntr_req; 3163 struct npc_mcam_alloc_counter_rsp cntr_rsp; 3164 struct npc_mcam_alloc_entry_req entry_req; 3165 struct npc_mcam_alloc_entry_rsp entry_rsp; 3166 struct npc_mcam *mcam = &rvu->hw->mcam; 3167 u16 entry = NPC_MCAM_ENTRY_INVALID; 3168 u16 cntr = NPC_MCAM_ENTRY_INVALID; 3169 int blkaddr, rc; 3170 u8 nix_intf; 3171 3172 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3173 if (blkaddr < 0) 3174 return NPC_MCAM_INVALID_REQ; 3175 3176 if (!is_npc_interface_valid(rvu, req->intf)) 3177 return NPC_MCAM_INVALID_REQ; 3178 3179 if (npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf, 3180 req->hdr.pcifunc)) 3181 return NPC_MCAM_INVALID_REQ; 3182 3183 /* Try to allocate a MCAM entry */ 3184 entry_req.hdr.pcifunc = req->hdr.pcifunc; 3185 entry_req.contig = true; 3186 entry_req.priority = req->priority; 3187 entry_req.ref_entry = req->ref_entry; 3188 entry_req.count = 1; 3189 3190 rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, 3191 &entry_req, &entry_rsp); 3192 if (rc) 3193 return rc; 3194 3195 if (!entry_rsp.count) 3196 return NPC_MCAM_ALLOC_FAILED; 3197 3198 entry = entry_rsp.entry; 3199 3200 if (!req->alloc_cntr) 3201 goto write_entry; 3202 3203 /* Now allocate counter */ 3204 cntr_req.hdr.pcifunc = req->hdr.pcifunc; 3205 cntr_req.contig = true; 3206 cntr_req.count = 1; 3207 3208 rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp); 3209 if (rc) { 3210 /* Free allocated MCAM entry */ 3211 mutex_lock(&mcam->lock); 3212 mcam->entry2pfvf_map[entry] = NPC_MCAM_INVALID_MAP; 3213 npc_mcam_clear_bit(mcam, entry); 3214 mutex_unlock(&mcam->lock); 3215 return rc; 3216 } 3217 3218 cntr = cntr_rsp.cntr; 3219 3220 write_entry: 3221 mutex_lock(&mcam->lock); 3222 3223 if (is_npc_intf_tx(req->intf)) 3224 nix_intf = pfvf->nix_tx_intf; 3225 else 3226 nix_intf = pfvf->nix_rx_intf; 3227 3228 npc_config_mcam_entry(rvu, mcam, blkaddr, entry, nix_intf, 3229 &req->entry_data, req->enable_entry); 3230 3231 if (req->alloc_cntr) 3232 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr); 3233 mutex_unlock(&mcam->lock); 3234 3235 rsp->entry = entry; 3236 rsp->cntr = cntr; 3237 3238 return 0; 3239 } 3240 3241 #define GET_KEX_CFG(intf) \ 3242 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf)) 3243 3244 #define GET_KEX_FLAGS(ld) \ 3245 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld)) 3246 3247 #define GET_KEX_LD(intf, lid, lt, ld) \ 3248 rvu_read64(rvu, BLKADDR_NPC, \ 3249 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld)) 3250 3251 #define GET_KEX_LDFLAGS(intf, ld, fl) \ 3252 rvu_read64(rvu, BLKADDR_NPC, \ 3253 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl)) 3254 3255 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req, 3256 struct npc_get_kex_cfg_rsp *rsp) 3257 { 3258 int lid, lt, ld, fl; 3259 3260 rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX); 3261 rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX); 3262 for (lid = 0; lid < NPC_MAX_LID; lid++) { 3263 for (lt = 0; lt < NPC_MAX_LT; lt++) { 3264 for (ld = 0; ld < NPC_MAX_LD; ld++) { 3265 rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] = 3266 GET_KEX_LD(NIX_INTF_RX, lid, lt, ld); 3267 rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] = 3268 GET_KEX_LD(NIX_INTF_TX, lid, lt, ld); 3269 } 3270 } 3271 } 3272 for (ld = 0; ld < NPC_MAX_LD; ld++) 3273 rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld); 3274 3275 for (ld = 0; ld < NPC_MAX_LD; ld++) { 3276 for (fl = 0; fl < NPC_MAX_LFL; fl++) { 3277 rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] = 3278 GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl); 3279 rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] = 3280 GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl); 3281 } 3282 } 3283 memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN); 3284 return 0; 3285 } 3286 3287 static int 3288 npc_set_var_len_offset_pkind(struct rvu *rvu, u16 pcifunc, u64 pkind, 3289 u8 var_len_off, u8 var_len_off_mask, u8 shift_dir) 3290 { 3291 struct npc_kpu_action0 *act0; 3292 u8 shift_count = 0; 3293 int blkaddr; 3294 u64 val; 3295 3296 if (!var_len_off_mask) 3297 return -EINVAL; 3298 3299 if (var_len_off_mask != 0xff) { 3300 if (shift_dir) 3301 shift_count = __ffs(var_len_off_mask); 3302 else 3303 shift_count = (8 - __fls(var_len_off_mask)); 3304 } 3305 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc); 3306 if (blkaddr < 0) { 3307 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 3308 return -EINVAL; 3309 } 3310 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind)); 3311 act0 = (struct npc_kpu_action0 *)&val; 3312 act0->var_len_shift = shift_count; 3313 act0->var_len_right = shift_dir; 3314 act0->var_len_mask = var_len_off_mask; 3315 act0->var_len_offset = var_len_off; 3316 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val); 3317 return 0; 3318 } 3319 3320 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 3321 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 3322 u8 shift_dir) 3323 3324 { 3325 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 3326 int blkaddr, nixlf, rc, intf_mode; 3327 int pf = rvu_get_pf(pcifunc); 3328 u64 rxpkind, txpkind; 3329 u8 cgx_id, lmac_id; 3330 3331 /* use default pkind to disable edsa/higig */ 3332 rxpkind = rvu_npc_get_pkind(rvu, pf); 3333 txpkind = NPC_TX_DEF_PKIND; 3334 intf_mode = NPC_INTF_MODE_DEF; 3335 3336 if (mode & OTX2_PRIV_FLAGS_CUSTOM) { 3337 if (pkind == NPC_RX_CUSTOM_PRE_L2_PKIND) { 3338 rc = npc_set_var_len_offset_pkind(rvu, pcifunc, pkind, 3339 var_len_off, 3340 var_len_off_mask, 3341 shift_dir); 3342 if (rc) 3343 return rc; 3344 } 3345 rxpkind = pkind; 3346 txpkind = pkind; 3347 } 3348 3349 if (dir & PKIND_RX) { 3350 /* rx pkind set req valid only for cgx mapped PFs */ 3351 if (!is_cgx_config_permitted(rvu, pcifunc)) 3352 return 0; 3353 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 3354 3355 rc = cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, 3356 rxpkind); 3357 if (rc) 3358 return rc; 3359 } 3360 3361 if (dir & PKIND_TX) { 3362 /* Tx pkind set request valid if PCIFUNC has NIXLF attached */ 3363 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3364 if (rc) 3365 return rc; 3366 3367 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), 3368 txpkind); 3369 } 3370 3371 pfvf->intf_mode = intf_mode; 3372 return 0; 3373 } 3374 3375 int rvu_mbox_handler_npc_set_pkind(struct rvu *rvu, struct npc_set_pkind *req, 3376 struct msg_rsp *rsp) 3377 { 3378 return rvu_npc_set_parse_mode(rvu, req->hdr.pcifunc, req->mode, 3379 req->dir, req->pkind, req->var_len_off, 3380 req->var_len_off_mask, req->shift_dir); 3381 } 3382 3383 int rvu_mbox_handler_npc_read_base_steer_rule(struct rvu *rvu, 3384 struct msg_req *req, 3385 struct npc_mcam_read_base_rule_rsp *rsp) 3386 { 3387 struct npc_mcam *mcam = &rvu->hw->mcam; 3388 int index, blkaddr, nixlf, rc = 0; 3389 u16 pcifunc = req->hdr.pcifunc; 3390 struct rvu_pfvf *pfvf; 3391 u8 intf, enable; 3392 3393 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3394 if (blkaddr < 0) 3395 return NPC_MCAM_INVALID_REQ; 3396 3397 /* Return the channel number in case of PF */ 3398 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) { 3399 pfvf = rvu_get_pfvf(rvu, pcifunc); 3400 rsp->entry.kw[0] = pfvf->rx_chan_base; 3401 rsp->entry.kw_mask[0] = 0xFFFULL; 3402 goto out; 3403 } 3404 3405 /* Find the pkt steering rule installed by PF to this VF */ 3406 mutex_lock(&mcam->lock); 3407 for (index = 0; index < mcam->bmap_entries; index++) { 3408 if (mcam->entry2target_pffunc[index] == pcifunc) 3409 goto read_entry; 3410 } 3411 3412 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 3413 if (rc < 0) { 3414 mutex_unlock(&mcam->lock); 3415 goto out; 3416 } 3417 /* Read the default ucast entry if there is no pkt steering rule */ 3418 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, 3419 NIXLF_UCAST_ENTRY); 3420 read_entry: 3421 /* Read the mcam entry */ 3422 npc_read_mcam_entry(rvu, mcam, blkaddr, index, &rsp->entry, &intf, 3423 &enable); 3424 mutex_unlock(&mcam->lock); 3425 out: 3426 return rc; 3427 } 3428 3429 int rvu_mbox_handler_npc_mcam_entry_stats(struct rvu *rvu, 3430 struct npc_mcam_get_stats_req *req, 3431 struct npc_mcam_get_stats_rsp *rsp) 3432 { 3433 struct npc_mcam *mcam = &rvu->hw->mcam; 3434 u16 index, cntr; 3435 int blkaddr; 3436 u64 regval; 3437 u32 bank; 3438 3439 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 3440 if (blkaddr < 0) 3441 return NPC_MCAM_INVALID_REQ; 3442 3443 mutex_lock(&mcam->lock); 3444 3445 index = req->entry & (mcam->banksize - 1); 3446 bank = npc_get_bank(mcam, req->entry); 3447 3448 /* read MCAM entry STAT_ACT register */ 3449 regval = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank)); 3450 3451 if (!(regval & rvu->hw->npc_stat_ena)) { 3452 rsp->stat_ena = 0; 3453 mutex_unlock(&mcam->lock); 3454 return 0; 3455 } 3456 3457 cntr = regval & 0x1FF; 3458 3459 rsp->stat_ena = 1; 3460 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(cntr)); 3461 rsp->stat &= BIT_ULL(48) - 1; 3462 3463 mutex_unlock(&mcam->lock); 3464 3465 return 0; 3466 } 3467