1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #include <linux/module.h>
9 #include <linux/pci.h>
10 
11 #include "rvu_struct.h"
12 #include "rvu_reg.h"
13 #include "rvu.h"
14 #include "npc.h"
15 #include "cgx.h"
16 #include "lmac_common.h"
17 #include "rvu_npc_hash.h"
18 
19 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc);
20 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
21 			    int type, int chan_id);
22 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc,
23 			       int type, bool add);
24 static int nix_setup_ipolicers(struct rvu *rvu,
25 			       struct nix_hw *nix_hw, int blkaddr);
26 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw);
27 static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req,
28 			       struct nix_hw *nix_hw, u16 pcifunc);
29 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc);
30 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw,
31 				     u32 leaf_prof);
32 static const char *nix_get_ctx_name(int ctype);
33 
34 enum mc_tbl_sz {
35 	MC_TBL_SZ_256,
36 	MC_TBL_SZ_512,
37 	MC_TBL_SZ_1K,
38 	MC_TBL_SZ_2K,
39 	MC_TBL_SZ_4K,
40 	MC_TBL_SZ_8K,
41 	MC_TBL_SZ_16K,
42 	MC_TBL_SZ_32K,
43 	MC_TBL_SZ_64K,
44 };
45 
46 enum mc_buf_cnt {
47 	MC_BUF_CNT_8,
48 	MC_BUF_CNT_16,
49 	MC_BUF_CNT_32,
50 	MC_BUF_CNT_64,
51 	MC_BUF_CNT_128,
52 	MC_BUF_CNT_256,
53 	MC_BUF_CNT_512,
54 	MC_BUF_CNT_1024,
55 	MC_BUF_CNT_2048,
56 };
57 
58 enum nix_makr_fmt_indexes {
59 	NIX_MARK_CFG_IP_DSCP_RED,
60 	NIX_MARK_CFG_IP_DSCP_YELLOW,
61 	NIX_MARK_CFG_IP_DSCP_YELLOW_RED,
62 	NIX_MARK_CFG_IP_ECN_RED,
63 	NIX_MARK_CFG_IP_ECN_YELLOW,
64 	NIX_MARK_CFG_IP_ECN_YELLOW_RED,
65 	NIX_MARK_CFG_VLAN_DEI_RED,
66 	NIX_MARK_CFG_VLAN_DEI_YELLOW,
67 	NIX_MARK_CFG_VLAN_DEI_YELLOW_RED,
68 	NIX_MARK_CFG_MAX,
69 };
70 
71 /* For now considering MC resources needed for broadcast
72  * pkt replication only. i.e 256 HWVFs + 12 PFs.
73  */
74 #define MC_TBL_SIZE	MC_TBL_SZ_512
75 #define MC_BUF_CNT	MC_BUF_CNT_128
76 
77 struct mce {
78 	struct hlist_node	node;
79 	u16			pcifunc;
80 };
81 
82 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr)
83 {
84 	int i = 0;
85 
86 	/*If blkaddr is 0, return the first nix block address*/
87 	if (blkaddr == 0)
88 		return rvu->nix_blkaddr[blkaddr];
89 
90 	while (i + 1 < MAX_NIX_BLKS) {
91 		if (rvu->nix_blkaddr[i] == blkaddr)
92 			return rvu->nix_blkaddr[i + 1];
93 		i++;
94 	}
95 
96 	return 0;
97 }
98 
99 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc)
100 {
101 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
102 	int blkaddr;
103 
104 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
105 	if (!pfvf->nixlf || blkaddr < 0)
106 		return false;
107 	return true;
108 }
109 
110 int rvu_get_nixlf_count(struct rvu *rvu)
111 {
112 	int blkaddr = 0, max = 0;
113 	struct rvu_block *block;
114 
115 	blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
116 	while (blkaddr) {
117 		block = &rvu->hw->block[blkaddr];
118 		max += block->lf.max;
119 		blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
120 	}
121 	return max;
122 }
123 
124 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr)
125 {
126 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
127 	struct rvu_hwinfo *hw = rvu->hw;
128 	int blkaddr;
129 
130 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
131 	if (!pfvf->nixlf || blkaddr < 0)
132 		return NIX_AF_ERR_AF_LF_INVALID;
133 
134 	*nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0);
135 	if (*nixlf < 0)
136 		return NIX_AF_ERR_AF_LF_INVALID;
137 
138 	if (nix_blkaddr)
139 		*nix_blkaddr = blkaddr;
140 
141 	return 0;
142 }
143 
144 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
145 			struct nix_hw **nix_hw, int *blkaddr)
146 {
147 	struct rvu_pfvf *pfvf;
148 
149 	pfvf = rvu_get_pfvf(rvu, pcifunc);
150 	*blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
151 	if (!pfvf->nixlf || *blkaddr < 0)
152 		return NIX_AF_ERR_AF_LF_INVALID;
153 
154 	*nix_hw = get_nix_hw(rvu->hw, *blkaddr);
155 	if (!*nix_hw)
156 		return NIX_AF_ERR_INVALID_NIXBLK;
157 	return 0;
158 }
159 
160 static void nix_mce_list_init(struct nix_mce_list *list, int max)
161 {
162 	INIT_HLIST_HEAD(&list->head);
163 	list->count = 0;
164 	list->max = max;
165 }
166 
167 static u16 nix_alloc_mce_list(struct nix_mcast *mcast, int count)
168 {
169 	int idx;
170 
171 	if (!mcast)
172 		return 0;
173 
174 	idx = mcast->next_free_mce;
175 	mcast->next_free_mce += count;
176 	return idx;
177 }
178 
179 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr)
180 {
181 	int nix_blkaddr = 0, i = 0;
182 	struct rvu *rvu = hw->rvu;
183 
184 	nix_blkaddr = rvu_get_next_nix_blkaddr(rvu, nix_blkaddr);
185 	while (nix_blkaddr) {
186 		if (blkaddr == nix_blkaddr && hw->nix)
187 			return &hw->nix[i];
188 		nix_blkaddr = rvu_get_next_nix_blkaddr(rvu, nix_blkaddr);
189 		i++;
190 	}
191 	return NULL;
192 }
193 
194 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu)
195 {
196 	dwrr_mtu &= 0x1FULL;
197 
198 	/* MTU used for DWRR calculation is in power of 2 up until 64K bytes.
199 	 * Value of 4 is reserved for MTU value of 9728 bytes.
200 	 * Value of 5 is reserved for MTU value of 10240 bytes.
201 	 */
202 	switch (dwrr_mtu) {
203 	case 4:
204 		return 9728;
205 	case 5:
206 		return 10240;
207 	default:
208 		return BIT_ULL(dwrr_mtu);
209 	}
210 
211 	return 0;
212 }
213 
214 u32 convert_bytes_to_dwrr_mtu(u32 bytes)
215 {
216 	/* MTU used for DWRR calculation is in power of 2 up until 64K bytes.
217 	 * Value of 4 is reserved for MTU value of 9728 bytes.
218 	 * Value of 5 is reserved for MTU value of 10240 bytes.
219 	 */
220 	if (bytes > BIT_ULL(16))
221 		return 0;
222 
223 	switch (bytes) {
224 	case 9728:
225 		return 4;
226 	case 10240:
227 		return 5;
228 	default:
229 		return ilog2(bytes);
230 	}
231 
232 	return 0;
233 }
234 
235 static void nix_rx_sync(struct rvu *rvu, int blkaddr)
236 {
237 	int err;
238 
239 	/* Sync all in flight RX packets to LLC/DRAM */
240 	rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0));
241 	err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true);
242 	if (err)
243 		dev_err(rvu->dev, "SYNC1: NIX RX software sync failed\n");
244 
245 	/* SW_SYNC ensures all existing transactions are finished and pkts
246 	 * are written to LLC/DRAM, queues should be teared down after
247 	 * successful SW_SYNC. Due to a HW errata, in some rare scenarios
248 	 * an existing transaction might end after SW_SYNC operation. To
249 	 * ensure operation is fully done, do the SW_SYNC twice.
250 	 */
251 	rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0));
252 	err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true);
253 	if (err)
254 		dev_err(rvu->dev, "SYNC2: NIX RX software sync failed\n");
255 }
256 
257 static bool is_valid_txschq(struct rvu *rvu, int blkaddr,
258 			    int lvl, u16 pcifunc, u16 schq)
259 {
260 	struct rvu_hwinfo *hw = rvu->hw;
261 	struct nix_txsch *txsch;
262 	struct nix_hw *nix_hw;
263 	u16 map_func;
264 
265 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
266 	if (!nix_hw)
267 		return false;
268 
269 	txsch = &nix_hw->txsch[lvl];
270 	/* Check out of bounds */
271 	if (schq >= txsch->schq.max)
272 		return false;
273 
274 	mutex_lock(&rvu->rsrc_lock);
275 	map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]);
276 	mutex_unlock(&rvu->rsrc_lock);
277 
278 	/* TLs aggegating traffic are shared across PF and VFs */
279 	if (lvl >= hw->cap.nix_tx_aggr_lvl) {
280 		if (rvu_get_pf(map_func) != rvu_get_pf(pcifunc))
281 			return false;
282 		else
283 			return true;
284 	}
285 
286 	if (map_func != pcifunc)
287 		return false;
288 
289 	return true;
290 }
291 
292 static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf,
293 			      struct nix_lf_alloc_rsp *rsp, bool loop)
294 {
295 	struct rvu_pfvf *parent_pf, *pfvf = rvu_get_pfvf(rvu, pcifunc);
296 	u16 req_chan_base, req_chan_end, req_chan_cnt;
297 	struct rvu_hwinfo *hw = rvu->hw;
298 	struct sdp_node_info *sdp_info;
299 	int pkind, pf, vf, lbkid, vfid;
300 	u8 cgx_id, lmac_id;
301 	bool from_vf;
302 	int err;
303 
304 	pf = rvu_get_pf(pcifunc);
305 	if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK &&
306 	    type != NIX_INTF_TYPE_SDP)
307 		return 0;
308 
309 	switch (type) {
310 	case NIX_INTF_TYPE_CGX:
311 		pfvf->cgx_lmac = rvu->pf2cgxlmac_map[pf];
312 		rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id);
313 
314 		pkind = rvu_npc_get_pkind(rvu, pf);
315 		if (pkind < 0) {
316 			dev_err(rvu->dev,
317 				"PF_Func 0x%x: Invalid pkind\n", pcifunc);
318 			return -EINVAL;
319 		}
320 		pfvf->rx_chan_base = rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0);
321 		pfvf->tx_chan_base = pfvf->rx_chan_base;
322 		pfvf->rx_chan_cnt = 1;
323 		pfvf->tx_chan_cnt = 1;
324 		rsp->tx_link = cgx_id * hw->lmac_per_cgx + lmac_id;
325 
326 		cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, pkind);
327 		rvu_npc_set_pkind(rvu, pkind, pfvf);
328 
329 		break;
330 	case NIX_INTF_TYPE_LBK:
331 		vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
332 
333 		/* If NIX1 block is present on the silicon then NIXes are
334 		 * assigned alternatively for lbk interfaces. NIX0 should
335 		 * send packets on lbk link 1 channels and NIX1 should send
336 		 * on lbk link 0 channels for the communication between
337 		 * NIX0 and NIX1.
338 		 */
339 		lbkid = 0;
340 		if (rvu->hw->lbk_links > 1)
341 			lbkid = vf & 0x1 ? 0 : 1;
342 
343 		/* By default NIX0 is configured to send packet on lbk link 1
344 		 * (which corresponds to LBK1), same packet will receive on
345 		 * NIX1 over lbk link 0. If NIX1 sends packet on lbk link 0
346 		 * (which corresponds to LBK2) packet will receive on NIX0 lbk
347 		 * link 1.
348 		 * But if lbk links for NIX0 and NIX1 are negated, i.e NIX0
349 		 * transmits and receives on lbk link 0, whick corresponds
350 		 * to LBK1 block, back to back connectivity between NIX and
351 		 * LBK can be achieved (which is similar to 96xx)
352 		 *
353 		 *			RX		TX
354 		 * NIX0 lbk link	1 (LBK2)	1 (LBK1)
355 		 * NIX0 lbk link	0 (LBK0)	0 (LBK0)
356 		 * NIX1 lbk link	0 (LBK1)	0 (LBK2)
357 		 * NIX1 lbk link	1 (LBK3)	1 (LBK3)
358 		 */
359 		if (loop)
360 			lbkid = !lbkid;
361 
362 		/* Note that AF's VFs work in pairs and talk over consecutive
363 		 * loopback channels.Therefore if odd number of AF VFs are
364 		 * enabled then the last VF remains with no pair.
365 		 */
366 		pfvf->rx_chan_base = rvu_nix_chan_lbk(rvu, lbkid, vf);
367 		pfvf->tx_chan_base = vf & 0x1 ?
368 					rvu_nix_chan_lbk(rvu, lbkid, vf - 1) :
369 					rvu_nix_chan_lbk(rvu, lbkid, vf + 1);
370 		pfvf->rx_chan_cnt = 1;
371 		pfvf->tx_chan_cnt = 1;
372 		rsp->tx_link = hw->cgx_links + lbkid;
373 		pfvf->lbkid = lbkid;
374 		rvu_npc_set_pkind(rvu, NPC_RX_LBK_PKIND, pfvf);
375 		rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf,
376 					      pfvf->rx_chan_base,
377 					      pfvf->rx_chan_cnt);
378 
379 		break;
380 	case NIX_INTF_TYPE_SDP:
381 		from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK);
382 		parent_pf = &rvu->pf[rvu_get_pf(pcifunc)];
383 		sdp_info = parent_pf->sdp_info;
384 		if (!sdp_info) {
385 			dev_err(rvu->dev, "Invalid sdp_info pointer\n");
386 			return -EINVAL;
387 		}
388 		if (from_vf) {
389 			req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn +
390 				sdp_info->num_pf_rings;
391 			vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
392 			for (vfid = 0; vfid < vf; vfid++)
393 				req_chan_base += sdp_info->vf_rings[vfid];
394 			req_chan_cnt = sdp_info->vf_rings[vf];
395 			req_chan_end = req_chan_base + req_chan_cnt - 1;
396 			if (req_chan_base < rvu_nix_chan_sdp(rvu, 0) ||
397 			    req_chan_end > rvu_nix_chan_sdp(rvu, 255)) {
398 				dev_err(rvu->dev,
399 					"PF_Func 0x%x: Invalid channel base and count\n",
400 					pcifunc);
401 				return -EINVAL;
402 			}
403 		} else {
404 			req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn;
405 			req_chan_cnt = sdp_info->num_pf_rings;
406 		}
407 
408 		pfvf->rx_chan_base = req_chan_base;
409 		pfvf->rx_chan_cnt = req_chan_cnt;
410 		pfvf->tx_chan_base = pfvf->rx_chan_base;
411 		pfvf->tx_chan_cnt = pfvf->rx_chan_cnt;
412 
413 		rsp->tx_link = hw->cgx_links + hw->lbk_links;
414 		rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf,
415 					      pfvf->rx_chan_base,
416 					      pfvf->rx_chan_cnt);
417 		break;
418 	}
419 
420 	/* Add a UCAST forwarding rule in MCAM with this NIXLF attached
421 	 * RVU PF/VF's MAC address.
422 	 */
423 	rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf,
424 				    pfvf->rx_chan_base, pfvf->mac_addr);
425 
426 	/* Add this PF_FUNC to bcast pkt replication list */
427 	err = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, true);
428 	if (err) {
429 		dev_err(rvu->dev,
430 			"Bcast list, failed to enable PF_FUNC 0x%x\n",
431 			pcifunc);
432 		return err;
433 	}
434 	/* Install MCAM rule matching Ethernet broadcast mac address */
435 	rvu_npc_install_bcast_match_entry(rvu, pcifunc,
436 					  nixlf, pfvf->rx_chan_base);
437 
438 	pfvf->maxlen = NIC_HW_MIN_FRS;
439 	pfvf->minlen = NIC_HW_MIN_FRS;
440 
441 	return 0;
442 }
443 
444 static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf)
445 {
446 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
447 	int err;
448 
449 	pfvf->maxlen = 0;
450 	pfvf->minlen = 0;
451 
452 	/* Remove this PF_FUNC from bcast pkt replication list */
453 	err = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, false);
454 	if (err) {
455 		dev_err(rvu->dev,
456 			"Bcast list, failed to disable PF_FUNC 0x%x\n",
457 			pcifunc);
458 	}
459 
460 	/* Free and disable any MCAM entries used by this NIX LF */
461 	rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf);
462 
463 	/* Disable DMAC filters used */
464 	rvu_cgx_disable_dmac_entries(rvu, pcifunc);
465 }
466 
467 int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
468 				    struct nix_bp_cfg_req *req,
469 				    struct msg_rsp *rsp)
470 {
471 	u16 pcifunc = req->hdr.pcifunc;
472 	struct rvu_pfvf *pfvf;
473 	int blkaddr, pf, type;
474 	u16 chan_base, chan;
475 	u64 cfg;
476 
477 	pf = rvu_get_pf(pcifunc);
478 	type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
479 	if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK)
480 		return 0;
481 
482 	pfvf = rvu_get_pfvf(rvu, pcifunc);
483 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
484 
485 	chan_base = pfvf->rx_chan_base + req->chan_base;
486 	for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) {
487 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));
488 		rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
489 			    cfg & ~BIT_ULL(16));
490 	}
491 	return 0;
492 }
493 
494 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
495 			    int type, int chan_id)
496 {
497 	int bpid, blkaddr, lmac_chan_cnt, sdp_chan_cnt;
498 	u16 cgx_bpid_cnt, lbk_bpid_cnt, sdp_bpid_cnt;
499 	struct rvu_hwinfo *hw = rvu->hw;
500 	struct rvu_pfvf *pfvf;
501 	u8 cgx_id, lmac_id;
502 	u64 cfg;
503 
504 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc);
505 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST);
506 	lmac_chan_cnt = cfg & 0xFF;
507 
508 	cgx_bpid_cnt = hw->cgx_links * lmac_chan_cnt;
509 	lbk_bpid_cnt = hw->lbk_links * ((cfg >> 16) & 0xFF);
510 
511 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
512 	sdp_chan_cnt = cfg & 0xFFF;
513 	sdp_bpid_cnt = hw->sdp_links * sdp_chan_cnt;
514 
515 	pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
516 
517 	/* Backpressure IDs range division
518 	 * CGX channles are mapped to (0 - 191) BPIDs
519 	 * LBK channles are mapped to (192 - 255) BPIDs
520 	 * SDP channles are mapped to (256 - 511) BPIDs
521 	 *
522 	 * Lmac channles and bpids mapped as follows
523 	 * cgx(0)_lmac(0)_chan(0 - 15) = bpid(0 - 15)
524 	 * cgx(0)_lmac(1)_chan(0 - 15) = bpid(16 - 31) ....
525 	 * cgx(1)_lmac(0)_chan(0 - 15) = bpid(64 - 79) ....
526 	 */
527 	switch (type) {
528 	case NIX_INTF_TYPE_CGX:
529 		if ((req->chan_base + req->chan_cnt) > 16)
530 			return -EINVAL;
531 		rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id);
532 		/* Assign bpid based on cgx, lmac and chan id */
533 		bpid = (cgx_id * hw->lmac_per_cgx * lmac_chan_cnt) +
534 			(lmac_id * lmac_chan_cnt) + req->chan_base;
535 
536 		if (req->bpid_per_chan)
537 			bpid += chan_id;
538 		if (bpid > cgx_bpid_cnt)
539 			return -EINVAL;
540 		break;
541 
542 	case NIX_INTF_TYPE_LBK:
543 		if ((req->chan_base + req->chan_cnt) > 63)
544 			return -EINVAL;
545 		bpid = cgx_bpid_cnt + req->chan_base;
546 		if (req->bpid_per_chan)
547 			bpid += chan_id;
548 		if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt))
549 			return -EINVAL;
550 		break;
551 	case NIX_INTF_TYPE_SDP:
552 		if ((req->chan_base + req->chan_cnt) > 255)
553 			return -EINVAL;
554 
555 		bpid = sdp_bpid_cnt + req->chan_base;
556 		if (req->bpid_per_chan)
557 			bpid += chan_id;
558 
559 		if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt + sdp_bpid_cnt))
560 			return -EINVAL;
561 		break;
562 	default:
563 		return -EINVAL;
564 	}
565 	return bpid;
566 }
567 
568 int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
569 				   struct nix_bp_cfg_req *req,
570 				   struct nix_bp_cfg_rsp *rsp)
571 {
572 	int blkaddr, pf, type, chan_id = 0;
573 	u16 pcifunc = req->hdr.pcifunc;
574 	struct rvu_pfvf *pfvf;
575 	u16 chan_base, chan;
576 	s16 bpid, bpid_base;
577 	u64 cfg;
578 
579 	pf = rvu_get_pf(pcifunc);
580 	type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
581 	if (is_sdp_pfvf(pcifunc))
582 		type = NIX_INTF_TYPE_SDP;
583 
584 	/* Enable backpressure only for CGX mapped PFs and LBK/SDP interface */
585 	if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK &&
586 	    type != NIX_INTF_TYPE_SDP)
587 		return 0;
588 
589 	pfvf = rvu_get_pfvf(rvu, pcifunc);
590 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
591 
592 	bpid_base = rvu_nix_get_bpid(rvu, req, type, chan_id);
593 	chan_base = pfvf->rx_chan_base + req->chan_base;
594 	bpid = bpid_base;
595 
596 	for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) {
597 		if (bpid < 0) {
598 			dev_warn(rvu->dev, "Fail to enable backpressure\n");
599 			return -EINVAL;
600 		}
601 
602 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));
603 		cfg &= ~GENMASK_ULL(8, 0);
604 		rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
605 			    cfg | (bpid & GENMASK_ULL(8, 0)) | BIT_ULL(16));
606 		chan_id++;
607 		bpid = rvu_nix_get_bpid(rvu, req, type, chan_id);
608 	}
609 
610 	for (chan = 0; chan < req->chan_cnt; chan++) {
611 		/* Map channel and bpid assign to it */
612 		rsp->chan_bpid[chan] = ((req->chan_base + chan) & 0x7F) << 10 |
613 					(bpid_base & 0x3FF);
614 		if (req->bpid_per_chan)
615 			bpid_base++;
616 	}
617 	rsp->chan_cnt = req->chan_cnt;
618 
619 	return 0;
620 }
621 
622 static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr,
623 				 u64 format, bool v4, u64 *fidx)
624 {
625 	struct nix_lso_format field = {0};
626 
627 	/* IP's Length field */
628 	field.layer = NIX_TXLAYER_OL3;
629 	/* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */
630 	field.offset = v4 ? 2 : 4;
631 	field.sizem1 = 1; /* i.e 2 bytes */
632 	field.alg = NIX_LSOALG_ADD_PAYLEN;
633 	rvu_write64(rvu, blkaddr,
634 		    NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++),
635 		    *(u64 *)&field);
636 
637 	/* No ID field in IPv6 header */
638 	if (!v4)
639 		return;
640 
641 	/* IP's ID field */
642 	field.layer = NIX_TXLAYER_OL3;
643 	field.offset = 4;
644 	field.sizem1 = 1; /* i.e 2 bytes */
645 	field.alg = NIX_LSOALG_ADD_SEGNUM;
646 	rvu_write64(rvu, blkaddr,
647 		    NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++),
648 		    *(u64 *)&field);
649 }
650 
651 static void nix_setup_lso_tso_l4(struct rvu *rvu, int blkaddr,
652 				 u64 format, u64 *fidx)
653 {
654 	struct nix_lso_format field = {0};
655 
656 	/* TCP's sequence number field */
657 	field.layer = NIX_TXLAYER_OL4;
658 	field.offset = 4;
659 	field.sizem1 = 3; /* i.e 4 bytes */
660 	field.alg = NIX_LSOALG_ADD_OFFSET;
661 	rvu_write64(rvu, blkaddr,
662 		    NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++),
663 		    *(u64 *)&field);
664 
665 	/* TCP's flags field */
666 	field.layer = NIX_TXLAYER_OL4;
667 	field.offset = 12;
668 	field.sizem1 = 1; /* 2 bytes */
669 	field.alg = NIX_LSOALG_TCP_FLAGS;
670 	rvu_write64(rvu, blkaddr,
671 		    NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++),
672 		    *(u64 *)&field);
673 }
674 
675 static void nix_setup_lso(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)
676 {
677 	u64 cfg, idx, fidx = 0;
678 
679 	/* Get max HW supported format indices */
680 	cfg = (rvu_read64(rvu, blkaddr, NIX_AF_CONST1) >> 48) & 0xFF;
681 	nix_hw->lso.total = cfg;
682 
683 	/* Enable LSO */
684 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_LSO_CFG);
685 	/* For TSO, set first and middle segment flags to
686 	 * mask out PSH, RST & FIN flags in TCP packet
687 	 */
688 	cfg &= ~((0xFFFFULL << 32) | (0xFFFFULL << 16));
689 	cfg |= (0xFFF2ULL << 32) | (0xFFF2ULL << 16);
690 	rvu_write64(rvu, blkaddr, NIX_AF_LSO_CFG, cfg | BIT_ULL(63));
691 
692 	/* Setup default static LSO formats
693 	 *
694 	 * Configure format fields for TCPv4 segmentation offload
695 	 */
696 	idx = NIX_LSO_FORMAT_IDX_TSOV4;
697 	nix_setup_lso_tso_l3(rvu, blkaddr, idx, true, &fidx);
698 	nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx);
699 
700 	/* Set rest of the fields to NOP */
701 	for (; fidx < 8; fidx++) {
702 		rvu_write64(rvu, blkaddr,
703 			    NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL);
704 	}
705 	nix_hw->lso.in_use++;
706 
707 	/* Configure format fields for TCPv6 segmentation offload */
708 	idx = NIX_LSO_FORMAT_IDX_TSOV6;
709 	fidx = 0;
710 	nix_setup_lso_tso_l3(rvu, blkaddr, idx, false, &fidx);
711 	nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx);
712 
713 	/* Set rest of the fields to NOP */
714 	for (; fidx < 8; fidx++) {
715 		rvu_write64(rvu, blkaddr,
716 			    NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL);
717 	}
718 	nix_hw->lso.in_use++;
719 }
720 
721 static void nix_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf)
722 {
723 	kfree(pfvf->rq_bmap);
724 	kfree(pfvf->sq_bmap);
725 	kfree(pfvf->cq_bmap);
726 	if (pfvf->rq_ctx)
727 		qmem_free(rvu->dev, pfvf->rq_ctx);
728 	if (pfvf->sq_ctx)
729 		qmem_free(rvu->dev, pfvf->sq_ctx);
730 	if (pfvf->cq_ctx)
731 		qmem_free(rvu->dev, pfvf->cq_ctx);
732 	if (pfvf->rss_ctx)
733 		qmem_free(rvu->dev, pfvf->rss_ctx);
734 	if (pfvf->nix_qints_ctx)
735 		qmem_free(rvu->dev, pfvf->nix_qints_ctx);
736 	if (pfvf->cq_ints_ctx)
737 		qmem_free(rvu->dev, pfvf->cq_ints_ctx);
738 
739 	pfvf->rq_bmap = NULL;
740 	pfvf->cq_bmap = NULL;
741 	pfvf->sq_bmap = NULL;
742 	pfvf->rq_ctx = NULL;
743 	pfvf->sq_ctx = NULL;
744 	pfvf->cq_ctx = NULL;
745 	pfvf->rss_ctx = NULL;
746 	pfvf->nix_qints_ctx = NULL;
747 	pfvf->cq_ints_ctx = NULL;
748 }
749 
750 static int nixlf_rss_ctx_init(struct rvu *rvu, int blkaddr,
751 			      struct rvu_pfvf *pfvf, int nixlf,
752 			      int rss_sz, int rss_grps, int hwctx_size,
753 			      u64 way_mask, bool tag_lsb_as_adder)
754 {
755 	int err, grp, num_indices;
756 	u64 val;
757 
758 	/* RSS is not requested for this NIXLF */
759 	if (!rss_sz)
760 		return 0;
761 	num_indices = rss_sz * rss_grps;
762 
763 	/* Alloc NIX RSS HW context memory and config the base */
764 	err = qmem_alloc(rvu->dev, &pfvf->rss_ctx, num_indices, hwctx_size);
765 	if (err)
766 		return err;
767 
768 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_BASE(nixlf),
769 		    (u64)pfvf->rss_ctx->iova);
770 
771 	/* Config full RSS table size, enable RSS and caching */
772 	val = BIT_ULL(36) | BIT_ULL(4) | way_mask << 20 |
773 			ilog2(num_indices / MAX_RSS_INDIR_TBL_SIZE);
774 
775 	if (tag_lsb_as_adder)
776 		val |= BIT_ULL(5);
777 
778 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf), val);
779 	/* Config RSS group offset and sizes */
780 	for (grp = 0; grp < rss_grps; grp++)
781 		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_GRPX(nixlf, grp),
782 			    ((ilog2(rss_sz) - 1) << 16) | (rss_sz * grp));
783 	return 0;
784 }
785 
786 static int nix_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block,
787 			       struct nix_aq_inst_s *inst)
788 {
789 	struct admin_queue *aq = block->aq;
790 	struct nix_aq_res_s *result;
791 	int timeout = 1000;
792 	u64 reg, head;
793 	int ret;
794 
795 	result = (struct nix_aq_res_s *)aq->res->base;
796 
797 	/* Get current head pointer where to append this instruction */
798 	reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS);
799 	head = (reg >> 4) & AQ_PTR_MASK;
800 
801 	memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)),
802 	       (void *)inst, aq->inst->entry_sz);
803 	memset(result, 0, sizeof(*result));
804 	/* sync into memory */
805 	wmb();
806 
807 	/* Ring the doorbell and wait for result */
808 	rvu_write64(rvu, block->addr, NIX_AF_AQ_DOOR, 1);
809 	while (result->compcode == NIX_AQ_COMP_NOTDONE) {
810 		cpu_relax();
811 		udelay(1);
812 		timeout--;
813 		if (!timeout)
814 			return -EBUSY;
815 	}
816 
817 	if (result->compcode != NIX_AQ_COMP_GOOD) {
818 		/* TODO: Replace this with some error code */
819 		if (result->compcode == NIX_AQ_COMP_CTX_FAULT ||
820 		    result->compcode == NIX_AQ_COMP_LOCKERR ||
821 		    result->compcode == NIX_AQ_COMP_CTX_POISON) {
822 			ret = rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX0_RX);
823 			ret |= rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX0_TX);
824 			ret |= rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX1_RX);
825 			ret |= rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX1_TX);
826 			if (ret)
827 				dev_err(rvu->dev,
828 					"%s: Not able to unlock cachelines\n", __func__);
829 		}
830 
831 		return -EBUSY;
832 	}
833 
834 	return 0;
835 }
836 
837 static int rvu_nix_blk_aq_enq_inst(struct rvu *rvu, struct nix_hw *nix_hw,
838 				   struct nix_aq_enq_req *req,
839 				   struct nix_aq_enq_rsp *rsp)
840 {
841 	struct rvu_hwinfo *hw = rvu->hw;
842 	u16 pcifunc = req->hdr.pcifunc;
843 	int nixlf, blkaddr, rc = 0;
844 	struct nix_aq_inst_s inst;
845 	struct rvu_block *block;
846 	struct admin_queue *aq;
847 	struct rvu_pfvf *pfvf;
848 	void *ctx, *mask;
849 	bool ena;
850 	u64 cfg;
851 
852 	blkaddr = nix_hw->blkaddr;
853 	block = &hw->block[blkaddr];
854 	aq = block->aq;
855 	if (!aq) {
856 		dev_warn(rvu->dev, "%s: NIX AQ not initialized\n", __func__);
857 		return NIX_AF_ERR_AQ_ENQUEUE;
858 	}
859 
860 	pfvf = rvu_get_pfvf(rvu, pcifunc);
861 	nixlf = rvu_get_lf(rvu, block, pcifunc, 0);
862 
863 	/* Skip NIXLF check for broadcast MCE entry and bandwidth profile
864 	 * operations done by AF itself.
865 	 */
866 	if (!((!rsp && req->ctype == NIX_AQ_CTYPE_MCE) ||
867 	      (req->ctype == NIX_AQ_CTYPE_BANDPROF && !pcifunc))) {
868 		if (!pfvf->nixlf || nixlf < 0)
869 			return NIX_AF_ERR_AF_LF_INVALID;
870 	}
871 
872 	switch (req->ctype) {
873 	case NIX_AQ_CTYPE_RQ:
874 		/* Check if index exceeds max no of queues */
875 		if (!pfvf->rq_ctx || req->qidx >= pfvf->rq_ctx->qsize)
876 			rc = NIX_AF_ERR_AQ_ENQUEUE;
877 		break;
878 	case NIX_AQ_CTYPE_SQ:
879 		if (!pfvf->sq_ctx || req->qidx >= pfvf->sq_ctx->qsize)
880 			rc = NIX_AF_ERR_AQ_ENQUEUE;
881 		break;
882 	case NIX_AQ_CTYPE_CQ:
883 		if (!pfvf->cq_ctx || req->qidx >= pfvf->cq_ctx->qsize)
884 			rc = NIX_AF_ERR_AQ_ENQUEUE;
885 		break;
886 	case NIX_AQ_CTYPE_RSS:
887 		/* Check if RSS is enabled and qidx is within range */
888 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf));
889 		if (!(cfg & BIT_ULL(4)) || !pfvf->rss_ctx ||
890 		    (req->qidx >= (256UL << (cfg & 0xF))))
891 			rc = NIX_AF_ERR_AQ_ENQUEUE;
892 		break;
893 	case NIX_AQ_CTYPE_MCE:
894 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG);
895 
896 		/* Check if index exceeds MCE list length */
897 		if (!nix_hw->mcast.mce_ctx ||
898 		    (req->qidx >= (256UL << (cfg & 0xF))))
899 			rc = NIX_AF_ERR_AQ_ENQUEUE;
900 
901 		/* Adding multicast lists for requests from PF/VFs is not
902 		 * yet supported, so ignore this.
903 		 */
904 		if (rsp)
905 			rc = NIX_AF_ERR_AQ_ENQUEUE;
906 		break;
907 	case NIX_AQ_CTYPE_BANDPROF:
908 		if (nix_verify_bandprof((struct nix_cn10k_aq_enq_req *)req,
909 					nix_hw, pcifunc))
910 			rc = NIX_AF_ERR_INVALID_BANDPROF;
911 		break;
912 	default:
913 		rc = NIX_AF_ERR_AQ_ENQUEUE;
914 	}
915 
916 	if (rc)
917 		return rc;
918 
919 	/* Check if SQ pointed SMQ belongs to this PF/VF or not */
920 	if (req->ctype == NIX_AQ_CTYPE_SQ &&
921 	    ((req->op == NIX_AQ_INSTOP_INIT && req->sq.ena) ||
922 	     (req->op == NIX_AQ_INSTOP_WRITE &&
923 	      req->sq_mask.ena && req->sq_mask.smq && req->sq.ena))) {
924 		if (!is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_SMQ,
925 				     pcifunc, req->sq.smq))
926 			return NIX_AF_ERR_AQ_ENQUEUE;
927 	}
928 
929 	memset(&inst, 0, sizeof(struct nix_aq_inst_s));
930 	inst.lf = nixlf;
931 	inst.cindex = req->qidx;
932 	inst.ctype = req->ctype;
933 	inst.op = req->op;
934 	/* Currently we are not supporting enqueuing multiple instructions,
935 	 * so always choose first entry in result memory.
936 	 */
937 	inst.res_addr = (u64)aq->res->iova;
938 
939 	/* Hardware uses same aq->res->base for updating result of
940 	 * previous instruction hence wait here till it is done.
941 	 */
942 	spin_lock(&aq->lock);
943 
944 	/* Clean result + context memory */
945 	memset(aq->res->base, 0, aq->res->entry_sz);
946 	/* Context needs to be written at RES_ADDR + 128 */
947 	ctx = aq->res->base + 128;
948 	/* Mask needs to be written at RES_ADDR + 256 */
949 	mask = aq->res->base + 256;
950 
951 	switch (req->op) {
952 	case NIX_AQ_INSTOP_WRITE:
953 		if (req->ctype == NIX_AQ_CTYPE_RQ)
954 			memcpy(mask, &req->rq_mask,
955 			       sizeof(struct nix_rq_ctx_s));
956 		else if (req->ctype == NIX_AQ_CTYPE_SQ)
957 			memcpy(mask, &req->sq_mask,
958 			       sizeof(struct nix_sq_ctx_s));
959 		else if (req->ctype == NIX_AQ_CTYPE_CQ)
960 			memcpy(mask, &req->cq_mask,
961 			       sizeof(struct nix_cq_ctx_s));
962 		else if (req->ctype == NIX_AQ_CTYPE_RSS)
963 			memcpy(mask, &req->rss_mask,
964 			       sizeof(struct nix_rsse_s));
965 		else if (req->ctype == NIX_AQ_CTYPE_MCE)
966 			memcpy(mask, &req->mce_mask,
967 			       sizeof(struct nix_rx_mce_s));
968 		else if (req->ctype == NIX_AQ_CTYPE_BANDPROF)
969 			memcpy(mask, &req->prof_mask,
970 			       sizeof(struct nix_bandprof_s));
971 		fallthrough;
972 	case NIX_AQ_INSTOP_INIT:
973 		if (req->ctype == NIX_AQ_CTYPE_RQ)
974 			memcpy(ctx, &req->rq, sizeof(struct nix_rq_ctx_s));
975 		else if (req->ctype == NIX_AQ_CTYPE_SQ)
976 			memcpy(ctx, &req->sq, sizeof(struct nix_sq_ctx_s));
977 		else if (req->ctype == NIX_AQ_CTYPE_CQ)
978 			memcpy(ctx, &req->cq, sizeof(struct nix_cq_ctx_s));
979 		else if (req->ctype == NIX_AQ_CTYPE_RSS)
980 			memcpy(ctx, &req->rss, sizeof(struct nix_rsse_s));
981 		else if (req->ctype == NIX_AQ_CTYPE_MCE)
982 			memcpy(ctx, &req->mce, sizeof(struct nix_rx_mce_s));
983 		else if (req->ctype == NIX_AQ_CTYPE_BANDPROF)
984 			memcpy(ctx, &req->prof, sizeof(struct nix_bandprof_s));
985 		break;
986 	case NIX_AQ_INSTOP_NOP:
987 	case NIX_AQ_INSTOP_READ:
988 	case NIX_AQ_INSTOP_LOCK:
989 	case NIX_AQ_INSTOP_UNLOCK:
990 		break;
991 	default:
992 		rc = NIX_AF_ERR_AQ_ENQUEUE;
993 		spin_unlock(&aq->lock);
994 		return rc;
995 	}
996 
997 	/* Submit the instruction to AQ */
998 	rc = nix_aq_enqueue_wait(rvu, block, &inst);
999 	if (rc) {
1000 		spin_unlock(&aq->lock);
1001 		return rc;
1002 	}
1003 
1004 	/* Set RQ/SQ/CQ bitmap if respective queue hw context is enabled */
1005 	if (req->op == NIX_AQ_INSTOP_INIT) {
1006 		if (req->ctype == NIX_AQ_CTYPE_RQ && req->rq.ena)
1007 			__set_bit(req->qidx, pfvf->rq_bmap);
1008 		if (req->ctype == NIX_AQ_CTYPE_SQ && req->sq.ena)
1009 			__set_bit(req->qidx, pfvf->sq_bmap);
1010 		if (req->ctype == NIX_AQ_CTYPE_CQ && req->cq.ena)
1011 			__set_bit(req->qidx, pfvf->cq_bmap);
1012 	}
1013 
1014 	if (req->op == NIX_AQ_INSTOP_WRITE) {
1015 		if (req->ctype == NIX_AQ_CTYPE_RQ) {
1016 			ena = (req->rq.ena & req->rq_mask.ena) |
1017 				(test_bit(req->qidx, pfvf->rq_bmap) &
1018 				~req->rq_mask.ena);
1019 			if (ena)
1020 				__set_bit(req->qidx, pfvf->rq_bmap);
1021 			else
1022 				__clear_bit(req->qidx, pfvf->rq_bmap);
1023 		}
1024 		if (req->ctype == NIX_AQ_CTYPE_SQ) {
1025 			ena = (req->rq.ena & req->sq_mask.ena) |
1026 				(test_bit(req->qidx, pfvf->sq_bmap) &
1027 				~req->sq_mask.ena);
1028 			if (ena)
1029 				__set_bit(req->qidx, pfvf->sq_bmap);
1030 			else
1031 				__clear_bit(req->qidx, pfvf->sq_bmap);
1032 		}
1033 		if (req->ctype == NIX_AQ_CTYPE_CQ) {
1034 			ena = (req->rq.ena & req->cq_mask.ena) |
1035 				(test_bit(req->qidx, pfvf->cq_bmap) &
1036 				~req->cq_mask.ena);
1037 			if (ena)
1038 				__set_bit(req->qidx, pfvf->cq_bmap);
1039 			else
1040 				__clear_bit(req->qidx, pfvf->cq_bmap);
1041 		}
1042 	}
1043 
1044 	if (rsp) {
1045 		/* Copy read context into mailbox */
1046 		if (req->op == NIX_AQ_INSTOP_READ) {
1047 			if (req->ctype == NIX_AQ_CTYPE_RQ)
1048 				memcpy(&rsp->rq, ctx,
1049 				       sizeof(struct nix_rq_ctx_s));
1050 			else if (req->ctype == NIX_AQ_CTYPE_SQ)
1051 				memcpy(&rsp->sq, ctx,
1052 				       sizeof(struct nix_sq_ctx_s));
1053 			else if (req->ctype == NIX_AQ_CTYPE_CQ)
1054 				memcpy(&rsp->cq, ctx,
1055 				       sizeof(struct nix_cq_ctx_s));
1056 			else if (req->ctype == NIX_AQ_CTYPE_RSS)
1057 				memcpy(&rsp->rss, ctx,
1058 				       sizeof(struct nix_rsse_s));
1059 			else if (req->ctype == NIX_AQ_CTYPE_MCE)
1060 				memcpy(&rsp->mce, ctx,
1061 				       sizeof(struct nix_rx_mce_s));
1062 			else if (req->ctype == NIX_AQ_CTYPE_BANDPROF)
1063 				memcpy(&rsp->prof, ctx,
1064 				       sizeof(struct nix_bandprof_s));
1065 		}
1066 	}
1067 
1068 	spin_unlock(&aq->lock);
1069 	return 0;
1070 }
1071 
1072 static int rvu_nix_verify_aq_ctx(struct rvu *rvu, struct nix_hw *nix_hw,
1073 				 struct nix_aq_enq_req *req, u8 ctype)
1074 {
1075 	struct nix_cn10k_aq_enq_req aq_req;
1076 	struct nix_cn10k_aq_enq_rsp aq_rsp;
1077 	int rc, word;
1078 
1079 	if (req->ctype != NIX_AQ_CTYPE_CQ)
1080 		return 0;
1081 
1082 	rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp,
1083 				 req->hdr.pcifunc, ctype, req->qidx);
1084 	if (rc) {
1085 		dev_err(rvu->dev,
1086 			"%s: Failed to fetch %s%d context of PFFUNC 0x%x\n",
1087 			__func__, nix_get_ctx_name(ctype), req->qidx,
1088 			req->hdr.pcifunc);
1089 		return rc;
1090 	}
1091 
1092 	/* Make copy of original context & mask which are required
1093 	 * for resubmission
1094 	 */
1095 	memcpy(&aq_req.cq_mask, &req->cq_mask, sizeof(struct nix_cq_ctx_s));
1096 	memcpy(&aq_req.cq, &req->cq, sizeof(struct nix_cq_ctx_s));
1097 
1098 	/* exclude fields which HW can update */
1099 	aq_req.cq_mask.cq_err       = 0;
1100 	aq_req.cq_mask.wrptr        = 0;
1101 	aq_req.cq_mask.tail         = 0;
1102 	aq_req.cq_mask.head	    = 0;
1103 	aq_req.cq_mask.avg_level    = 0;
1104 	aq_req.cq_mask.update_time  = 0;
1105 	aq_req.cq_mask.substream    = 0;
1106 
1107 	/* Context mask (cq_mask) holds mask value of fields which
1108 	 * are changed in AQ WRITE operation.
1109 	 * for example cq.drop = 0xa;
1110 	 *	       cq_mask.drop = 0xff;
1111 	 * Below logic performs '&' between cq and cq_mask so that non
1112 	 * updated fields are masked out for request and response
1113 	 * comparison
1114 	 */
1115 	for (word = 0; word < sizeof(struct nix_cq_ctx_s) / sizeof(u64);
1116 	     word++) {
1117 		*(u64 *)((u8 *)&aq_rsp.cq + word * 8) &=
1118 			(*(u64 *)((u8 *)&aq_req.cq_mask + word * 8));
1119 		*(u64 *)((u8 *)&aq_req.cq + word * 8) &=
1120 			(*(u64 *)((u8 *)&aq_req.cq_mask + word * 8));
1121 	}
1122 
1123 	if (memcmp(&aq_req.cq, &aq_rsp.cq, sizeof(struct nix_cq_ctx_s)))
1124 		return NIX_AF_ERR_AQ_CTX_RETRY_WRITE;
1125 
1126 	return 0;
1127 }
1128 
1129 static int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req,
1130 			       struct nix_aq_enq_rsp *rsp)
1131 {
1132 	struct nix_hw *nix_hw;
1133 	int err, retries = 5;
1134 	int blkaddr;
1135 
1136 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc);
1137 	if (blkaddr < 0)
1138 		return NIX_AF_ERR_AF_LF_INVALID;
1139 
1140 	nix_hw =  get_nix_hw(rvu->hw, blkaddr);
1141 	if (!nix_hw)
1142 		return NIX_AF_ERR_INVALID_NIXBLK;
1143 
1144 retry:
1145 	err = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, req, rsp);
1146 
1147 	/* HW errata 'AQ Modification to CQ could be discarded on heavy traffic'
1148 	 * As a work around perfrom CQ context read after each AQ write. If AQ
1149 	 * read shows AQ write is not updated perform AQ write again.
1150 	 */
1151 	if (!err && req->op == NIX_AQ_INSTOP_WRITE) {
1152 		err = rvu_nix_verify_aq_ctx(rvu, nix_hw, req, NIX_AQ_CTYPE_CQ);
1153 		if (err == NIX_AF_ERR_AQ_CTX_RETRY_WRITE) {
1154 			if (retries--)
1155 				goto retry;
1156 			else
1157 				return NIX_AF_ERR_CQ_CTX_WRITE_ERR;
1158 		}
1159 	}
1160 
1161 	return err;
1162 }
1163 
1164 static const char *nix_get_ctx_name(int ctype)
1165 {
1166 	switch (ctype) {
1167 	case NIX_AQ_CTYPE_CQ:
1168 		return "CQ";
1169 	case NIX_AQ_CTYPE_SQ:
1170 		return "SQ";
1171 	case NIX_AQ_CTYPE_RQ:
1172 		return "RQ";
1173 	case NIX_AQ_CTYPE_RSS:
1174 		return "RSS";
1175 	}
1176 	return "";
1177 }
1178 
1179 static int nix_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req *req)
1180 {
1181 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
1182 	struct nix_aq_enq_req aq_req;
1183 	unsigned long *bmap;
1184 	int qidx, q_cnt = 0;
1185 	int err = 0, rc;
1186 
1187 	if (!pfvf->cq_ctx || !pfvf->sq_ctx || !pfvf->rq_ctx)
1188 		return NIX_AF_ERR_AQ_ENQUEUE;
1189 
1190 	memset(&aq_req, 0, sizeof(struct nix_aq_enq_req));
1191 	aq_req.hdr.pcifunc = req->hdr.pcifunc;
1192 
1193 	if (req->ctype == NIX_AQ_CTYPE_CQ) {
1194 		aq_req.cq.ena = 0;
1195 		aq_req.cq_mask.ena = 1;
1196 		aq_req.cq.bp_ena = 0;
1197 		aq_req.cq_mask.bp_ena = 1;
1198 		q_cnt = pfvf->cq_ctx->qsize;
1199 		bmap = pfvf->cq_bmap;
1200 	}
1201 	if (req->ctype == NIX_AQ_CTYPE_SQ) {
1202 		aq_req.sq.ena = 0;
1203 		aq_req.sq_mask.ena = 1;
1204 		q_cnt = pfvf->sq_ctx->qsize;
1205 		bmap = pfvf->sq_bmap;
1206 	}
1207 	if (req->ctype == NIX_AQ_CTYPE_RQ) {
1208 		aq_req.rq.ena = 0;
1209 		aq_req.rq_mask.ena = 1;
1210 		q_cnt = pfvf->rq_ctx->qsize;
1211 		bmap = pfvf->rq_bmap;
1212 	}
1213 
1214 	aq_req.ctype = req->ctype;
1215 	aq_req.op = NIX_AQ_INSTOP_WRITE;
1216 
1217 	for (qidx = 0; qidx < q_cnt; qidx++) {
1218 		if (!test_bit(qidx, bmap))
1219 			continue;
1220 		aq_req.qidx = qidx;
1221 		rc = rvu_nix_aq_enq_inst(rvu, &aq_req, NULL);
1222 		if (rc) {
1223 			err = rc;
1224 			dev_err(rvu->dev, "Failed to disable %s:%d context\n",
1225 				nix_get_ctx_name(req->ctype), qidx);
1226 		}
1227 	}
1228 
1229 	return err;
1230 }
1231 
1232 #ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING
1233 static int nix_lf_hwctx_lockdown(struct rvu *rvu, struct nix_aq_enq_req *req)
1234 {
1235 	struct nix_aq_enq_req lock_ctx_req;
1236 	int err;
1237 
1238 	if (req->op != NIX_AQ_INSTOP_INIT)
1239 		return 0;
1240 
1241 	if (req->ctype == NIX_AQ_CTYPE_MCE ||
1242 	    req->ctype == NIX_AQ_CTYPE_DYNO)
1243 		return 0;
1244 
1245 	memset(&lock_ctx_req, 0, sizeof(struct nix_aq_enq_req));
1246 	lock_ctx_req.hdr.pcifunc = req->hdr.pcifunc;
1247 	lock_ctx_req.ctype = req->ctype;
1248 	lock_ctx_req.op = NIX_AQ_INSTOP_LOCK;
1249 	lock_ctx_req.qidx = req->qidx;
1250 	err = rvu_nix_aq_enq_inst(rvu, &lock_ctx_req, NULL);
1251 	if (err)
1252 		dev_err(rvu->dev,
1253 			"PFUNC 0x%x: Failed to lock NIX %s:%d context\n",
1254 			req->hdr.pcifunc,
1255 			nix_get_ctx_name(req->ctype), req->qidx);
1256 	return err;
1257 }
1258 
1259 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu,
1260 				struct nix_aq_enq_req *req,
1261 				struct nix_aq_enq_rsp *rsp)
1262 {
1263 	int err;
1264 
1265 	err = rvu_nix_aq_enq_inst(rvu, req, rsp);
1266 	if (!err)
1267 		err = nix_lf_hwctx_lockdown(rvu, req);
1268 	return err;
1269 }
1270 #else
1271 
1272 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu,
1273 				struct nix_aq_enq_req *req,
1274 				struct nix_aq_enq_rsp *rsp)
1275 {
1276 	return rvu_nix_aq_enq_inst(rvu, req, rsp);
1277 }
1278 #endif
1279 /* CN10K mbox handler */
1280 int rvu_mbox_handler_nix_cn10k_aq_enq(struct rvu *rvu,
1281 				      struct nix_cn10k_aq_enq_req *req,
1282 				      struct nix_cn10k_aq_enq_rsp *rsp)
1283 {
1284 	return rvu_nix_aq_enq_inst(rvu, (struct nix_aq_enq_req *)req,
1285 				  (struct nix_aq_enq_rsp *)rsp);
1286 }
1287 
1288 int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu,
1289 				       struct hwctx_disable_req *req,
1290 				       struct msg_rsp *rsp)
1291 {
1292 	return nix_lf_hwctx_disable(rvu, req);
1293 }
1294 
1295 int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,
1296 				  struct nix_lf_alloc_req *req,
1297 				  struct nix_lf_alloc_rsp *rsp)
1298 {
1299 	int nixlf, qints, hwctx_size, intf, err, rc = 0;
1300 	struct rvu_hwinfo *hw = rvu->hw;
1301 	u16 pcifunc = req->hdr.pcifunc;
1302 	struct rvu_block *block;
1303 	struct rvu_pfvf *pfvf;
1304 	u64 cfg, ctx_cfg;
1305 	int blkaddr;
1306 
1307 	if (!req->rq_cnt || !req->sq_cnt || !req->cq_cnt)
1308 		return NIX_AF_ERR_PARAM;
1309 
1310 	if (req->way_mask)
1311 		req->way_mask &= 0xFFFF;
1312 
1313 	pfvf = rvu_get_pfvf(rvu, pcifunc);
1314 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1315 	if (!pfvf->nixlf || blkaddr < 0)
1316 		return NIX_AF_ERR_AF_LF_INVALID;
1317 
1318 	block = &hw->block[blkaddr];
1319 	nixlf = rvu_get_lf(rvu, block, pcifunc, 0);
1320 	if (nixlf < 0)
1321 		return NIX_AF_ERR_AF_LF_INVALID;
1322 
1323 	/* Check if requested 'NIXLF <=> NPALF' mapping is valid */
1324 	if (req->npa_func) {
1325 		/* If default, use 'this' NIXLF's PFFUNC */
1326 		if (req->npa_func == RVU_DEFAULT_PF_FUNC)
1327 			req->npa_func = pcifunc;
1328 		if (!is_pffunc_map_valid(rvu, req->npa_func, BLKTYPE_NPA))
1329 			return NIX_AF_INVAL_NPA_PF_FUNC;
1330 	}
1331 
1332 	/* Check if requested 'NIXLF <=> SSOLF' mapping is valid */
1333 	if (req->sso_func) {
1334 		/* If default, use 'this' NIXLF's PFFUNC */
1335 		if (req->sso_func == RVU_DEFAULT_PF_FUNC)
1336 			req->sso_func = pcifunc;
1337 		if (!is_pffunc_map_valid(rvu, req->sso_func, BLKTYPE_SSO))
1338 			return NIX_AF_INVAL_SSO_PF_FUNC;
1339 	}
1340 
1341 	/* If RSS is being enabled, check if requested config is valid.
1342 	 * RSS table size should be power of two, otherwise
1343 	 * RSS_GRP::OFFSET + adder might go beyond that group or
1344 	 * won't be able to use entire table.
1345 	 */
1346 	if (req->rss_sz && (req->rss_sz > MAX_RSS_INDIR_TBL_SIZE ||
1347 			    !is_power_of_2(req->rss_sz)))
1348 		return NIX_AF_ERR_RSS_SIZE_INVALID;
1349 
1350 	if (req->rss_sz &&
1351 	    (!req->rss_grps || req->rss_grps > MAX_RSS_GROUPS))
1352 		return NIX_AF_ERR_RSS_GRPS_INVALID;
1353 
1354 	/* Reset this NIX LF */
1355 	err = rvu_lf_reset(rvu, block, nixlf);
1356 	if (err) {
1357 		dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n",
1358 			block->addr - BLKADDR_NIX0, nixlf);
1359 		return NIX_AF_ERR_LF_RESET;
1360 	}
1361 
1362 	ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3);
1363 
1364 	/* Alloc NIX RQ HW context memory and config the base */
1365 	hwctx_size = 1UL << ((ctx_cfg >> 4) & 0xF);
1366 	err = qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size);
1367 	if (err)
1368 		goto free_mem;
1369 
1370 	pfvf->rq_bmap = kcalloc(req->rq_cnt, sizeof(long), GFP_KERNEL);
1371 	if (!pfvf->rq_bmap)
1372 		goto free_mem;
1373 
1374 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_BASE(nixlf),
1375 		    (u64)pfvf->rq_ctx->iova);
1376 
1377 	/* Set caching and queue count in HW */
1378 	cfg = BIT_ULL(36) | (req->rq_cnt - 1) | req->way_mask << 20;
1379 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_CFG(nixlf), cfg);
1380 
1381 	/* Alloc NIX SQ HW context memory and config the base */
1382 	hwctx_size = 1UL << (ctx_cfg & 0xF);
1383 	err = qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size);
1384 	if (err)
1385 		goto free_mem;
1386 
1387 	pfvf->sq_bmap = kcalloc(req->sq_cnt, sizeof(long), GFP_KERNEL);
1388 	if (!pfvf->sq_bmap)
1389 		goto free_mem;
1390 
1391 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_BASE(nixlf),
1392 		    (u64)pfvf->sq_ctx->iova);
1393 
1394 	cfg = BIT_ULL(36) | (req->sq_cnt - 1) | req->way_mask << 20;
1395 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_CFG(nixlf), cfg);
1396 
1397 	/* Alloc NIX CQ HW context memory and config the base */
1398 	hwctx_size = 1UL << ((ctx_cfg >> 8) & 0xF);
1399 	err = qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size);
1400 	if (err)
1401 		goto free_mem;
1402 
1403 	pfvf->cq_bmap = kcalloc(req->cq_cnt, sizeof(long), GFP_KERNEL);
1404 	if (!pfvf->cq_bmap)
1405 		goto free_mem;
1406 
1407 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_BASE(nixlf),
1408 		    (u64)pfvf->cq_ctx->iova);
1409 
1410 	cfg = BIT_ULL(36) | (req->cq_cnt - 1) | req->way_mask << 20;
1411 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_CFG(nixlf), cfg);
1412 
1413 	/* Initialize receive side scaling (RSS) */
1414 	hwctx_size = 1UL << ((ctx_cfg >> 12) & 0xF);
1415 	err = nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, req->rss_sz,
1416 				 req->rss_grps, hwctx_size, req->way_mask,
1417 				 !!(req->flags & NIX_LF_RSS_TAG_LSB_AS_ADDER));
1418 	if (err)
1419 		goto free_mem;
1420 
1421 	/* Alloc memory for CQINT's HW contexts */
1422 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
1423 	qints = (cfg >> 24) & 0xFFF;
1424 	hwctx_size = 1UL << ((ctx_cfg >> 24) & 0xF);
1425 	err = qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size);
1426 	if (err)
1427 		goto free_mem;
1428 
1429 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_BASE(nixlf),
1430 		    (u64)pfvf->cq_ints_ctx->iova);
1431 
1432 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_CFG(nixlf),
1433 		    BIT_ULL(36) | req->way_mask << 20);
1434 
1435 	/* Alloc memory for QINT's HW contexts */
1436 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
1437 	qints = (cfg >> 12) & 0xFFF;
1438 	hwctx_size = 1UL << ((ctx_cfg >> 20) & 0xF);
1439 	err = qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size);
1440 	if (err)
1441 		goto free_mem;
1442 
1443 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_BASE(nixlf),
1444 		    (u64)pfvf->nix_qints_ctx->iova);
1445 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_CFG(nixlf),
1446 		    BIT_ULL(36) | req->way_mask << 20);
1447 
1448 	/* Setup VLANX TPID's.
1449 	 * Use VLAN1 for 802.1Q
1450 	 * and VLAN0 for 802.1AD.
1451 	 */
1452 	cfg = (0x8100ULL << 16) | 0x88A8ULL;
1453 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg);
1454 
1455 	/* Enable LMTST for this NIX LF */
1456 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG2(nixlf), BIT_ULL(0));
1457 
1458 	/* Set CQE/WQE size, NPA_PF_FUNC for SQBs and also SSO_PF_FUNC */
1459 	if (req->npa_func)
1460 		cfg = req->npa_func;
1461 	if (req->sso_func)
1462 		cfg |= (u64)req->sso_func << 16;
1463 
1464 	cfg |= (u64)req->xqe_sz << 33;
1465 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf), cfg);
1466 
1467 	/* Config Rx pkt length, csum checks and apad  enable / disable */
1468 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), req->rx_cfg);
1469 
1470 	/* Configure pkind for TX parse config */
1471 	cfg = NPC_TX_DEF_PKIND;
1472 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg);
1473 
1474 	intf = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
1475 	if (is_sdp_pfvf(pcifunc))
1476 		intf = NIX_INTF_TYPE_SDP;
1477 
1478 	err = nix_interface_init(rvu, pcifunc, intf, nixlf, rsp,
1479 				 !!(req->flags & NIX_LF_LBK_BLK_SEL));
1480 	if (err)
1481 		goto free_mem;
1482 
1483 	/* Disable NPC entries as NIXLF's contexts are not initialized yet */
1484 	rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
1485 
1486 	/* Configure RX VTAG Type 7 (strip) for vf vlan */
1487 	rvu_write64(rvu, blkaddr,
1488 		    NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, NIX_AF_LFX_RX_VTAG_TYPE7),
1489 		    VTAGSIZE_T4 | VTAG_STRIP);
1490 
1491 	goto exit;
1492 
1493 free_mem:
1494 	nix_ctx_free(rvu, pfvf);
1495 	rc = -ENOMEM;
1496 
1497 exit:
1498 	/* Set macaddr of this PF/VF */
1499 	ether_addr_copy(rsp->mac_addr, pfvf->mac_addr);
1500 
1501 	/* set SQB size info */
1502 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQ_CONST);
1503 	rsp->sqb_size = (cfg >> 34) & 0xFFFF;
1504 	rsp->rx_chan_base = pfvf->rx_chan_base;
1505 	rsp->tx_chan_base = pfvf->tx_chan_base;
1506 	rsp->rx_chan_cnt = pfvf->rx_chan_cnt;
1507 	rsp->tx_chan_cnt = pfvf->tx_chan_cnt;
1508 	rsp->lso_tsov4_idx = NIX_LSO_FORMAT_IDX_TSOV4;
1509 	rsp->lso_tsov6_idx = NIX_LSO_FORMAT_IDX_TSOV6;
1510 	/* Get HW supported stat count */
1511 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
1512 	rsp->lf_rx_stats = ((cfg >> 32) & 0xFF);
1513 	rsp->lf_tx_stats = ((cfg >> 24) & 0xFF);
1514 	/* Get count of CQ IRQs and error IRQs supported per LF */
1515 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
1516 	rsp->qints = ((cfg >> 12) & 0xFFF);
1517 	rsp->cints = ((cfg >> 24) & 0xFFF);
1518 	rsp->cgx_links = hw->cgx_links;
1519 	rsp->lbk_links = hw->lbk_links;
1520 	rsp->sdp_links = hw->sdp_links;
1521 
1522 	return rc;
1523 }
1524 
1525 int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct nix_lf_free_req *req,
1526 				 struct msg_rsp *rsp)
1527 {
1528 	struct rvu_hwinfo *hw = rvu->hw;
1529 	u16 pcifunc = req->hdr.pcifunc;
1530 	struct rvu_block *block;
1531 	int blkaddr, nixlf, err;
1532 	struct rvu_pfvf *pfvf;
1533 
1534 	pfvf = rvu_get_pfvf(rvu, pcifunc);
1535 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1536 	if (!pfvf->nixlf || blkaddr < 0)
1537 		return NIX_AF_ERR_AF_LF_INVALID;
1538 
1539 	block = &hw->block[blkaddr];
1540 	nixlf = rvu_get_lf(rvu, block, pcifunc, 0);
1541 	if (nixlf < 0)
1542 		return NIX_AF_ERR_AF_LF_INVALID;
1543 
1544 	if (req->flags & NIX_LF_DISABLE_FLOWS)
1545 		rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf);
1546 	else
1547 		rvu_npc_free_mcam_entries(rvu, pcifunc, nixlf);
1548 
1549 	/* Free any tx vtag def entries used by this NIX LF */
1550 	if (!(req->flags & NIX_LF_DONT_FREE_TX_VTAG))
1551 		nix_free_tx_vtag_entries(rvu, pcifunc);
1552 
1553 	nix_interface_deinit(rvu, pcifunc, nixlf);
1554 
1555 	/* Reset this NIX LF */
1556 	err = rvu_lf_reset(rvu, block, nixlf);
1557 	if (err) {
1558 		dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n",
1559 			block->addr - BLKADDR_NIX0, nixlf);
1560 		return NIX_AF_ERR_LF_RESET;
1561 	}
1562 
1563 	nix_ctx_free(rvu, pfvf);
1564 
1565 	return 0;
1566 }
1567 
1568 int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu,
1569 					 struct nix_mark_format_cfg  *req,
1570 					 struct nix_mark_format_cfg_rsp *rsp)
1571 {
1572 	u16 pcifunc = req->hdr.pcifunc;
1573 	struct nix_hw *nix_hw;
1574 	struct rvu_pfvf *pfvf;
1575 	int blkaddr, rc;
1576 	u32 cfg;
1577 
1578 	pfvf = rvu_get_pfvf(rvu, pcifunc);
1579 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1580 	if (!pfvf->nixlf || blkaddr < 0)
1581 		return NIX_AF_ERR_AF_LF_INVALID;
1582 
1583 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
1584 	if (!nix_hw)
1585 		return NIX_AF_ERR_INVALID_NIXBLK;
1586 
1587 	cfg = (((u32)req->offset & 0x7) << 16) |
1588 	      (((u32)req->y_mask & 0xF) << 12) |
1589 	      (((u32)req->y_val & 0xF) << 8) |
1590 	      (((u32)req->r_mask & 0xF) << 4) | ((u32)req->r_val & 0xF);
1591 
1592 	rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfg);
1593 	if (rc < 0) {
1594 		dev_err(rvu->dev, "No mark_format_ctl for (pf:%d, vf:%d)",
1595 			rvu_get_pf(pcifunc), pcifunc & RVU_PFVF_FUNC_MASK);
1596 		return NIX_AF_ERR_MARK_CFG_FAIL;
1597 	}
1598 
1599 	rsp->mark_format_idx = rc;
1600 	return 0;
1601 }
1602 
1603 /* Handle shaper update specially for few revisions */
1604 static bool
1605 handle_txschq_shaper_update(struct rvu *rvu, int blkaddr, int nixlf,
1606 			    int lvl, u64 reg, u64 regval)
1607 {
1608 	u64 regbase, oldval, sw_xoff = 0;
1609 	u64 dbgval, md_debug0 = 0;
1610 	unsigned long poll_tmo;
1611 	bool rate_reg = 0;
1612 	u32 schq;
1613 
1614 	regbase = reg & 0xFFFF;
1615 	schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT);
1616 
1617 	/* Check for rate register */
1618 	switch (lvl) {
1619 	case NIX_TXSCH_LVL_TL1:
1620 		md_debug0 = NIX_AF_TL1X_MD_DEBUG0(schq);
1621 		sw_xoff = NIX_AF_TL1X_SW_XOFF(schq);
1622 
1623 		rate_reg = !!(regbase == NIX_AF_TL1X_CIR(0));
1624 		break;
1625 	case NIX_TXSCH_LVL_TL2:
1626 		md_debug0 = NIX_AF_TL2X_MD_DEBUG0(schq);
1627 		sw_xoff = NIX_AF_TL2X_SW_XOFF(schq);
1628 
1629 		rate_reg = (regbase == NIX_AF_TL2X_CIR(0) ||
1630 			    regbase == NIX_AF_TL2X_PIR(0));
1631 		break;
1632 	case NIX_TXSCH_LVL_TL3:
1633 		md_debug0 = NIX_AF_TL3X_MD_DEBUG0(schq);
1634 		sw_xoff = NIX_AF_TL3X_SW_XOFF(schq);
1635 
1636 		rate_reg = (regbase == NIX_AF_TL3X_CIR(0) ||
1637 			    regbase == NIX_AF_TL3X_PIR(0));
1638 		break;
1639 	case NIX_TXSCH_LVL_TL4:
1640 		md_debug0 = NIX_AF_TL4X_MD_DEBUG0(schq);
1641 		sw_xoff = NIX_AF_TL4X_SW_XOFF(schq);
1642 
1643 		rate_reg = (regbase == NIX_AF_TL4X_CIR(0) ||
1644 			    regbase == NIX_AF_TL4X_PIR(0));
1645 		break;
1646 	case NIX_TXSCH_LVL_MDQ:
1647 		sw_xoff = NIX_AF_MDQX_SW_XOFF(schq);
1648 		rate_reg = (regbase == NIX_AF_MDQX_CIR(0) ||
1649 			    regbase == NIX_AF_MDQX_PIR(0));
1650 		break;
1651 	}
1652 
1653 	if (!rate_reg)
1654 		return false;
1655 
1656 	/* Nothing special to do when state is not toggled */
1657 	oldval = rvu_read64(rvu, blkaddr, reg);
1658 	if ((oldval & 0x1) == (regval & 0x1)) {
1659 		rvu_write64(rvu, blkaddr, reg, regval);
1660 		return true;
1661 	}
1662 
1663 	/* PIR/CIR disable */
1664 	if (!(regval & 0x1)) {
1665 		rvu_write64(rvu, blkaddr, sw_xoff, 1);
1666 		rvu_write64(rvu, blkaddr, reg, 0);
1667 		udelay(4);
1668 		rvu_write64(rvu, blkaddr, sw_xoff, 0);
1669 		return true;
1670 	}
1671 
1672 	/* PIR/CIR enable */
1673 	rvu_write64(rvu, blkaddr, sw_xoff, 1);
1674 	if (md_debug0) {
1675 		poll_tmo = jiffies + usecs_to_jiffies(10000);
1676 		/* Wait until VLD(bit32) == 1 or C_CON(bit48) == 0 */
1677 		do {
1678 			if (time_after(jiffies, poll_tmo)) {
1679 				dev_err(rvu->dev,
1680 					"NIXLF%d: TLX%u(lvl %u) CIR/PIR enable failed\n",
1681 					nixlf, schq, lvl);
1682 				goto exit;
1683 			}
1684 			usleep_range(1, 5);
1685 			dbgval = rvu_read64(rvu, blkaddr, md_debug0);
1686 		} while (!(dbgval & BIT_ULL(32)) && (dbgval & BIT_ULL(48)));
1687 	}
1688 	rvu_write64(rvu, blkaddr, reg, regval);
1689 exit:
1690 	rvu_write64(rvu, blkaddr, sw_xoff, 0);
1691 	return true;
1692 }
1693 
1694 /* Disable shaping of pkts by a scheduler queue
1695  * at a given scheduler level.
1696  */
1697 static void nix_reset_tx_shaping(struct rvu *rvu, int blkaddr,
1698 				 int nixlf, int lvl, int schq)
1699 {
1700 	struct rvu_hwinfo *hw = rvu->hw;
1701 	u64  cir_reg = 0, pir_reg = 0;
1702 	u64  cfg;
1703 
1704 	switch (lvl) {
1705 	case NIX_TXSCH_LVL_TL1:
1706 		cir_reg = NIX_AF_TL1X_CIR(schq);
1707 		pir_reg = 0; /* PIR not available at TL1 */
1708 		break;
1709 	case NIX_TXSCH_LVL_TL2:
1710 		cir_reg = NIX_AF_TL2X_CIR(schq);
1711 		pir_reg = NIX_AF_TL2X_PIR(schq);
1712 		break;
1713 	case NIX_TXSCH_LVL_TL3:
1714 		cir_reg = NIX_AF_TL3X_CIR(schq);
1715 		pir_reg = NIX_AF_TL3X_PIR(schq);
1716 		break;
1717 	case NIX_TXSCH_LVL_TL4:
1718 		cir_reg = NIX_AF_TL4X_CIR(schq);
1719 		pir_reg = NIX_AF_TL4X_PIR(schq);
1720 		break;
1721 	case NIX_TXSCH_LVL_MDQ:
1722 		cir_reg = NIX_AF_MDQX_CIR(schq);
1723 		pir_reg = NIX_AF_MDQX_PIR(schq);
1724 		break;
1725 	}
1726 
1727 	/* Shaper state toggle needs wait/poll */
1728 	if (hw->cap.nix_shaper_toggle_wait) {
1729 		if (cir_reg)
1730 			handle_txschq_shaper_update(rvu, blkaddr, nixlf,
1731 						    lvl, cir_reg, 0);
1732 		if (pir_reg)
1733 			handle_txschq_shaper_update(rvu, blkaddr, nixlf,
1734 						    lvl, pir_reg, 0);
1735 		return;
1736 	}
1737 
1738 	if (!cir_reg)
1739 		return;
1740 	cfg = rvu_read64(rvu, blkaddr, cir_reg);
1741 	rvu_write64(rvu, blkaddr, cir_reg, cfg & ~BIT_ULL(0));
1742 
1743 	if (!pir_reg)
1744 		return;
1745 	cfg = rvu_read64(rvu, blkaddr, pir_reg);
1746 	rvu_write64(rvu, blkaddr, pir_reg, cfg & ~BIT_ULL(0));
1747 }
1748 
1749 static void nix_reset_tx_linkcfg(struct rvu *rvu, int blkaddr,
1750 				 int lvl, int schq)
1751 {
1752 	struct rvu_hwinfo *hw = rvu->hw;
1753 	int link_level;
1754 	int link;
1755 
1756 	if (lvl >= hw->cap.nix_tx_aggr_lvl)
1757 		return;
1758 
1759 	/* Reset TL4's SDP link config */
1760 	if (lvl == NIX_TXSCH_LVL_TL4)
1761 		rvu_write64(rvu, blkaddr, NIX_AF_TL4X_SDP_LINK_CFG(schq), 0x00);
1762 
1763 	link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ?
1764 			NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2;
1765 	if (lvl != link_level)
1766 		return;
1767 
1768 	/* Reset TL2's CGX or LBK link config */
1769 	for (link = 0; link < (hw->cgx_links + hw->lbk_links); link++)
1770 		rvu_write64(rvu, blkaddr,
1771 			    NIX_AF_TL3_TL2X_LINKX_CFG(schq, link), 0x00);
1772 }
1773 
1774 static void nix_clear_tx_xoff(struct rvu *rvu, int blkaddr,
1775 			      int lvl, int schq)
1776 {
1777 	struct rvu_hwinfo *hw = rvu->hw;
1778 	u64 reg;
1779 
1780 	/* Skip this if shaping is not supported */
1781 	if (!hw->cap.nix_shaping)
1782 		return;
1783 
1784 	/* Clear level specific SW_XOFF */
1785 	switch (lvl) {
1786 	case NIX_TXSCH_LVL_TL1:
1787 		reg = NIX_AF_TL1X_SW_XOFF(schq);
1788 		break;
1789 	case NIX_TXSCH_LVL_TL2:
1790 		reg = NIX_AF_TL2X_SW_XOFF(schq);
1791 		break;
1792 	case NIX_TXSCH_LVL_TL3:
1793 		reg = NIX_AF_TL3X_SW_XOFF(schq);
1794 		break;
1795 	case NIX_TXSCH_LVL_TL4:
1796 		reg = NIX_AF_TL4X_SW_XOFF(schq);
1797 		break;
1798 	case NIX_TXSCH_LVL_MDQ:
1799 		reg = NIX_AF_MDQX_SW_XOFF(schq);
1800 		break;
1801 	default:
1802 		return;
1803 	}
1804 
1805 	rvu_write64(rvu, blkaddr, reg, 0x0);
1806 }
1807 
1808 static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc)
1809 {
1810 	struct rvu_hwinfo *hw = rvu->hw;
1811 	int pf = rvu_get_pf(pcifunc);
1812 	u8 cgx_id = 0, lmac_id = 0;
1813 
1814 	if (is_afvf(pcifunc)) {/* LBK links */
1815 		return hw->cgx_links;
1816 	} else if (is_pf_cgxmapped(rvu, pf)) {
1817 		rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1818 		return (cgx_id * hw->lmac_per_cgx) + lmac_id;
1819 	}
1820 
1821 	/* SDP link */
1822 	return hw->cgx_links + hw->lbk_links;
1823 }
1824 
1825 static void nix_get_txschq_range(struct rvu *rvu, u16 pcifunc,
1826 				 int link, int *start, int *end)
1827 {
1828 	struct rvu_hwinfo *hw = rvu->hw;
1829 	int pf = rvu_get_pf(pcifunc);
1830 
1831 	if (is_afvf(pcifunc)) { /* LBK links */
1832 		*start = hw->cap.nix_txsch_per_cgx_lmac * link;
1833 		*end = *start + hw->cap.nix_txsch_per_lbk_lmac;
1834 	} else if (is_pf_cgxmapped(rvu, pf)) { /* CGX links */
1835 		*start = hw->cap.nix_txsch_per_cgx_lmac * link;
1836 		*end = *start + hw->cap.nix_txsch_per_cgx_lmac;
1837 	} else { /* SDP link */
1838 		*start = (hw->cap.nix_txsch_per_cgx_lmac * hw->cgx_links) +
1839 			(hw->cap.nix_txsch_per_lbk_lmac * hw->lbk_links);
1840 		*end = *start + hw->cap.nix_txsch_per_sdp_lmac;
1841 	}
1842 }
1843 
1844 static int nix_check_txschq_alloc_req(struct rvu *rvu, int lvl, u16 pcifunc,
1845 				      struct nix_hw *nix_hw,
1846 				      struct nix_txsch_alloc_req *req)
1847 {
1848 	struct rvu_hwinfo *hw = rvu->hw;
1849 	int schq, req_schq, free_cnt;
1850 	struct nix_txsch *txsch;
1851 	int link, start, end;
1852 
1853 	txsch = &nix_hw->txsch[lvl];
1854 	req_schq = req->schq_contig[lvl] + req->schq[lvl];
1855 
1856 	if (!req_schq)
1857 		return 0;
1858 
1859 	link = nix_get_tx_link(rvu, pcifunc);
1860 
1861 	/* For traffic aggregating scheduler level, one queue is enough */
1862 	if (lvl >= hw->cap.nix_tx_aggr_lvl) {
1863 		if (req_schq != 1)
1864 			return NIX_AF_ERR_TLX_ALLOC_FAIL;
1865 		return 0;
1866 	}
1867 
1868 	/* Get free SCHQ count and check if request can be accomodated */
1869 	if (hw->cap.nix_fixed_txschq_mapping) {
1870 		nix_get_txschq_range(rvu, pcifunc, link, &start, &end);
1871 		schq = start + (pcifunc & RVU_PFVF_FUNC_MASK);
1872 		if (end <= txsch->schq.max && schq < end &&
1873 		    !test_bit(schq, txsch->schq.bmap))
1874 			free_cnt = 1;
1875 		else
1876 			free_cnt = 0;
1877 	} else {
1878 		free_cnt = rvu_rsrc_free_count(&txsch->schq);
1879 	}
1880 
1881 	if (free_cnt < req_schq || req->schq[lvl] > MAX_TXSCHQ_PER_FUNC ||
1882 	    req->schq_contig[lvl] > MAX_TXSCHQ_PER_FUNC)
1883 		return NIX_AF_ERR_TLX_ALLOC_FAIL;
1884 
1885 	/* If contiguous queues are needed, check for availability */
1886 	if (!hw->cap.nix_fixed_txschq_mapping && req->schq_contig[lvl] &&
1887 	    !rvu_rsrc_check_contig(&txsch->schq, req->schq_contig[lvl]))
1888 		return NIX_AF_ERR_TLX_ALLOC_FAIL;
1889 
1890 	return 0;
1891 }
1892 
1893 static void nix_txsch_alloc(struct rvu *rvu, struct nix_txsch *txsch,
1894 			    struct nix_txsch_alloc_rsp *rsp,
1895 			    int lvl, int start, int end)
1896 {
1897 	struct rvu_hwinfo *hw = rvu->hw;
1898 	u16 pcifunc = rsp->hdr.pcifunc;
1899 	int idx, schq;
1900 
1901 	/* For traffic aggregating levels, queue alloc is based
1902 	 * on transmit link to which PF_FUNC is mapped to.
1903 	 */
1904 	if (lvl >= hw->cap.nix_tx_aggr_lvl) {
1905 		/* A single TL queue is allocated */
1906 		if (rsp->schq_contig[lvl]) {
1907 			rsp->schq_contig[lvl] = 1;
1908 			rsp->schq_contig_list[lvl][0] = start;
1909 		}
1910 
1911 		/* Both contig and non-contig reqs doesn't make sense here */
1912 		if (rsp->schq_contig[lvl])
1913 			rsp->schq[lvl] = 0;
1914 
1915 		if (rsp->schq[lvl]) {
1916 			rsp->schq[lvl] = 1;
1917 			rsp->schq_list[lvl][0] = start;
1918 		}
1919 		return;
1920 	}
1921 
1922 	/* Adjust the queue request count if HW supports
1923 	 * only one queue per level configuration.
1924 	 */
1925 	if (hw->cap.nix_fixed_txschq_mapping) {
1926 		idx = pcifunc & RVU_PFVF_FUNC_MASK;
1927 		schq = start + idx;
1928 		if (idx >= (end - start) || test_bit(schq, txsch->schq.bmap)) {
1929 			rsp->schq_contig[lvl] = 0;
1930 			rsp->schq[lvl] = 0;
1931 			return;
1932 		}
1933 
1934 		if (rsp->schq_contig[lvl]) {
1935 			rsp->schq_contig[lvl] = 1;
1936 			set_bit(schq, txsch->schq.bmap);
1937 			rsp->schq_contig_list[lvl][0] = schq;
1938 			rsp->schq[lvl] = 0;
1939 		} else if (rsp->schq[lvl]) {
1940 			rsp->schq[lvl] = 1;
1941 			set_bit(schq, txsch->schq.bmap);
1942 			rsp->schq_list[lvl][0] = schq;
1943 		}
1944 		return;
1945 	}
1946 
1947 	/* Allocate contiguous queue indices requesty first */
1948 	if (rsp->schq_contig[lvl]) {
1949 		schq = bitmap_find_next_zero_area(txsch->schq.bmap,
1950 						  txsch->schq.max, start,
1951 						  rsp->schq_contig[lvl], 0);
1952 		if (schq >= end)
1953 			rsp->schq_contig[lvl] = 0;
1954 		for (idx = 0; idx < rsp->schq_contig[lvl]; idx++) {
1955 			set_bit(schq, txsch->schq.bmap);
1956 			rsp->schq_contig_list[lvl][idx] = schq;
1957 			schq++;
1958 		}
1959 	}
1960 
1961 	/* Allocate non-contiguous queue indices */
1962 	if (rsp->schq[lvl]) {
1963 		idx = 0;
1964 		for (schq = start; schq < end; schq++) {
1965 			if (!test_bit(schq, txsch->schq.bmap)) {
1966 				set_bit(schq, txsch->schq.bmap);
1967 				rsp->schq_list[lvl][idx++] = schq;
1968 			}
1969 			if (idx == rsp->schq[lvl])
1970 				break;
1971 		}
1972 		/* Update how many were allocated */
1973 		rsp->schq[lvl] = idx;
1974 	}
1975 }
1976 
1977 int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu,
1978 				     struct nix_txsch_alloc_req *req,
1979 				     struct nix_txsch_alloc_rsp *rsp)
1980 {
1981 	struct rvu_hwinfo *hw = rvu->hw;
1982 	u16 pcifunc = req->hdr.pcifunc;
1983 	int link, blkaddr, rc = 0;
1984 	int lvl, idx, start, end;
1985 	struct nix_txsch *txsch;
1986 	struct nix_hw *nix_hw;
1987 	u32 *pfvf_map;
1988 	int nixlf;
1989 	u16 schq;
1990 
1991 	rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
1992 	if (rc)
1993 		return rc;
1994 
1995 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
1996 	if (!nix_hw)
1997 		return NIX_AF_ERR_INVALID_NIXBLK;
1998 
1999 	mutex_lock(&rvu->rsrc_lock);
2000 
2001 	/* Check if request is valid as per HW capabilities
2002 	 * and can be accomodated.
2003 	 */
2004 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
2005 		rc = nix_check_txschq_alloc_req(rvu, lvl, pcifunc, nix_hw, req);
2006 		if (rc)
2007 			goto err;
2008 	}
2009 
2010 	/* Allocate requested Tx scheduler queues */
2011 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
2012 		txsch = &nix_hw->txsch[lvl];
2013 		pfvf_map = txsch->pfvf_map;
2014 
2015 		if (!req->schq[lvl] && !req->schq_contig[lvl])
2016 			continue;
2017 
2018 		rsp->schq[lvl] = req->schq[lvl];
2019 		rsp->schq_contig[lvl] = req->schq_contig[lvl];
2020 
2021 		link = nix_get_tx_link(rvu, pcifunc);
2022 
2023 		if (lvl >= hw->cap.nix_tx_aggr_lvl) {
2024 			start = link;
2025 			end = link;
2026 		} else if (hw->cap.nix_fixed_txschq_mapping) {
2027 			nix_get_txschq_range(rvu, pcifunc, link, &start, &end);
2028 		} else {
2029 			start = 0;
2030 			end = txsch->schq.max;
2031 		}
2032 
2033 		nix_txsch_alloc(rvu, txsch, rsp, lvl, start, end);
2034 
2035 		/* Reset queue config */
2036 		for (idx = 0; idx < req->schq_contig[lvl]; idx++) {
2037 			schq = rsp->schq_contig_list[lvl][idx];
2038 			if (!(TXSCH_MAP_FLAGS(pfvf_map[schq]) &
2039 			    NIX_TXSCHQ_CFG_DONE))
2040 				pfvf_map[schq] = TXSCH_MAP(pcifunc, 0);
2041 			nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq);
2042 			nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq);
2043 		}
2044 
2045 		for (idx = 0; idx < req->schq[lvl]; idx++) {
2046 			schq = rsp->schq_list[lvl][idx];
2047 			if (!(TXSCH_MAP_FLAGS(pfvf_map[schq]) &
2048 			    NIX_TXSCHQ_CFG_DONE))
2049 				pfvf_map[schq] = TXSCH_MAP(pcifunc, 0);
2050 			nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq);
2051 			nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq);
2052 		}
2053 	}
2054 
2055 	rsp->aggr_level = hw->cap.nix_tx_aggr_lvl;
2056 	rsp->aggr_lvl_rr_prio = TXSCH_TL1_DFLT_RR_PRIO;
2057 	rsp->link_cfg_lvl = rvu_read64(rvu, blkaddr,
2058 				       NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ?
2059 				       NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2;
2060 	goto exit;
2061 err:
2062 	rc = NIX_AF_ERR_TLX_ALLOC_FAIL;
2063 exit:
2064 	mutex_unlock(&rvu->rsrc_lock);
2065 	return rc;
2066 }
2067 
2068 static int nix_smq_flush(struct rvu *rvu, int blkaddr,
2069 			 int smq, u16 pcifunc, int nixlf)
2070 {
2071 	int pf = rvu_get_pf(pcifunc);
2072 	u8 cgx_id = 0, lmac_id = 0;
2073 	int err, restore_tx_en = 0;
2074 	u64 cfg;
2075 
2076 	if (!is_rvu_otx2(rvu)) {
2077 		/* Skip SMQ flush if pkt count is zero */
2078 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_MDQX_IN_MD_COUNT(smq));
2079 		if (!cfg)
2080 			return 0;
2081 	}
2082 
2083 	/* enable cgx tx if disabled */
2084 	if (is_pf_cgxmapped(rvu, pf)) {
2085 		rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
2086 		restore_tx_en = !rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu),
2087 						   lmac_id, true);
2088 	}
2089 
2090 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq));
2091 	/* Do SMQ flush and set enqueue xoff */
2092 	cfg |= BIT_ULL(50) | BIT_ULL(49);
2093 	rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg);
2094 
2095 	/* Disable backpressure from physical link,
2096 	 * otherwise SMQ flush may stall.
2097 	 */
2098 	rvu_cgx_enadis_rx_bp(rvu, pf, false);
2099 
2100 	/* Wait for flush to complete */
2101 	err = rvu_poll_reg(rvu, blkaddr,
2102 			   NIX_AF_SMQX_CFG(smq), BIT_ULL(49), true);
2103 	if (err)
2104 		dev_err(rvu->dev,
2105 			"NIXLF%d: SMQ%d flush failed\n", nixlf, smq);
2106 
2107 	rvu_cgx_enadis_rx_bp(rvu, pf, true);
2108 	/* restore cgx tx state */
2109 	if (restore_tx_en)
2110 		rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false);
2111 	return err;
2112 }
2113 
2114 static int nix_txschq_free(struct rvu *rvu, u16 pcifunc)
2115 {
2116 	int blkaddr, nixlf, lvl, schq, err;
2117 	struct rvu_hwinfo *hw = rvu->hw;
2118 	struct nix_txsch *txsch;
2119 	struct nix_hw *nix_hw;
2120 	u16 map_func;
2121 
2122 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
2123 	if (blkaddr < 0)
2124 		return NIX_AF_ERR_AF_LF_INVALID;
2125 
2126 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
2127 	if (!nix_hw)
2128 		return NIX_AF_ERR_INVALID_NIXBLK;
2129 
2130 	nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0);
2131 	if (nixlf < 0)
2132 		return NIX_AF_ERR_AF_LF_INVALID;
2133 
2134 	/* Disable TL2/3 queue links and all XOFF's before SMQ flush*/
2135 	mutex_lock(&rvu->rsrc_lock);
2136 	for (lvl = NIX_TXSCH_LVL_MDQ; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
2137 		txsch = &nix_hw->txsch[lvl];
2138 
2139 		if (lvl >= hw->cap.nix_tx_aggr_lvl)
2140 			continue;
2141 
2142 		for (schq = 0; schq < txsch->schq.max; schq++) {
2143 			if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc)
2144 				continue;
2145 			nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq);
2146 			nix_clear_tx_xoff(rvu, blkaddr, lvl, schq);
2147 		}
2148 	}
2149 	nix_clear_tx_xoff(rvu, blkaddr, NIX_TXSCH_LVL_TL1,
2150 			  nix_get_tx_link(rvu, pcifunc));
2151 
2152 	/* On PF cleanup, clear cfg done flag as
2153 	 * PF would have changed default config.
2154 	 */
2155 	if (!(pcifunc & RVU_PFVF_FUNC_MASK)) {
2156 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL1];
2157 		schq = nix_get_tx_link(rvu, pcifunc);
2158 		/* Do not clear pcifunc in txsch->pfvf_map[schq] because
2159 		 * VF might be using this TL1 queue
2160 		 */
2161 		map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]);
2162 		txsch->pfvf_map[schq] = TXSCH_SET_FLAG(map_func, 0x0);
2163 	}
2164 
2165 	/* Flush SMQs */
2166 	txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
2167 	for (schq = 0; schq < txsch->schq.max; schq++) {
2168 		if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc)
2169 			continue;
2170 		nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf);
2171 	}
2172 
2173 	/* Now free scheduler queues to free pool */
2174 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
2175 		 /* TLs above aggregation level are shared across all PF
2176 		  * and it's VFs, hence skip freeing them.
2177 		  */
2178 		if (lvl >= hw->cap.nix_tx_aggr_lvl)
2179 			continue;
2180 
2181 		txsch = &nix_hw->txsch[lvl];
2182 		for (schq = 0; schq < txsch->schq.max; schq++) {
2183 			if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc)
2184 				continue;
2185 			rvu_free_rsrc(&txsch->schq, schq);
2186 			txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE);
2187 		}
2188 	}
2189 	mutex_unlock(&rvu->rsrc_lock);
2190 
2191 	/* Sync cached info for this LF in NDC-TX to LLC/DRAM */
2192 	rvu_write64(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12) | nixlf);
2193 	err = rvu_poll_reg(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12), true);
2194 	if (err)
2195 		dev_err(rvu->dev, "NDC-TX sync failed for NIXLF %d\n", nixlf);
2196 
2197 	return 0;
2198 }
2199 
2200 static int nix_txschq_free_one(struct rvu *rvu,
2201 			       struct nix_txsch_free_req *req)
2202 {
2203 	struct rvu_hwinfo *hw = rvu->hw;
2204 	u16 pcifunc = req->hdr.pcifunc;
2205 	int lvl, schq, nixlf, blkaddr;
2206 	struct nix_txsch *txsch;
2207 	struct nix_hw *nix_hw;
2208 	u32 *pfvf_map;
2209 	int rc;
2210 
2211 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
2212 	if (blkaddr < 0)
2213 		return NIX_AF_ERR_AF_LF_INVALID;
2214 
2215 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
2216 	if (!nix_hw)
2217 		return NIX_AF_ERR_INVALID_NIXBLK;
2218 
2219 	nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0);
2220 	if (nixlf < 0)
2221 		return NIX_AF_ERR_AF_LF_INVALID;
2222 
2223 	lvl = req->schq_lvl;
2224 	schq = req->schq;
2225 	txsch = &nix_hw->txsch[lvl];
2226 
2227 	if (lvl >= hw->cap.nix_tx_aggr_lvl || schq >= txsch->schq.max)
2228 		return 0;
2229 
2230 	pfvf_map = txsch->pfvf_map;
2231 	mutex_lock(&rvu->rsrc_lock);
2232 
2233 	if (TXSCH_MAP_FUNC(pfvf_map[schq]) != pcifunc) {
2234 		rc = NIX_AF_ERR_TLX_INVALID;
2235 		goto err;
2236 	}
2237 
2238 	/* Clear SW_XOFF of this resource only.
2239 	 * For SMQ level, all path XOFF's
2240 	 * need to be made clear by user
2241 	 */
2242 	nix_clear_tx_xoff(rvu, blkaddr, lvl, schq);
2243 
2244 	/* Flush if it is a SMQ. Onus of disabling
2245 	 * TL2/3 queue links before SMQ flush is on user
2246 	 */
2247 	if (lvl == NIX_TXSCH_LVL_SMQ &&
2248 	    nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf)) {
2249 		rc = NIX_AF_SMQ_FLUSH_FAILED;
2250 		goto err;
2251 	}
2252 
2253 	/* Free the resource */
2254 	rvu_free_rsrc(&txsch->schq, schq);
2255 	txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE);
2256 	mutex_unlock(&rvu->rsrc_lock);
2257 	return 0;
2258 err:
2259 	mutex_unlock(&rvu->rsrc_lock);
2260 	return rc;
2261 }
2262 
2263 int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu,
2264 				    struct nix_txsch_free_req *req,
2265 				    struct msg_rsp *rsp)
2266 {
2267 	if (req->flags & TXSCHQ_FREE_ALL)
2268 		return nix_txschq_free(rvu, req->hdr.pcifunc);
2269 	else
2270 		return nix_txschq_free_one(rvu, req);
2271 }
2272 
2273 static bool is_txschq_hierarchy_valid(struct rvu *rvu, u16 pcifunc, int blkaddr,
2274 				      int lvl, u64 reg, u64 regval)
2275 {
2276 	u64 regbase = reg & 0xFFFF;
2277 	u16 schq, parent;
2278 
2279 	if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, lvl, reg))
2280 		return false;
2281 
2282 	schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT);
2283 	/* Check if this schq belongs to this PF/VF or not */
2284 	if (!is_valid_txschq(rvu, blkaddr, lvl, pcifunc, schq))
2285 		return false;
2286 
2287 	parent = (regval >> 16) & 0x1FF;
2288 	/* Validate MDQ's TL4 parent */
2289 	if (regbase == NIX_AF_MDQX_PARENT(0) &&
2290 	    !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL4, pcifunc, parent))
2291 		return false;
2292 
2293 	/* Validate TL4's TL3 parent */
2294 	if (regbase == NIX_AF_TL4X_PARENT(0) &&
2295 	    !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL3, pcifunc, parent))
2296 		return false;
2297 
2298 	/* Validate TL3's TL2 parent */
2299 	if (regbase == NIX_AF_TL3X_PARENT(0) &&
2300 	    !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL2, pcifunc, parent))
2301 		return false;
2302 
2303 	/* Validate TL2's TL1 parent */
2304 	if (regbase == NIX_AF_TL2X_PARENT(0) &&
2305 	    !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL1, pcifunc, parent))
2306 		return false;
2307 
2308 	return true;
2309 }
2310 
2311 static bool is_txschq_shaping_valid(struct rvu_hwinfo *hw, int lvl, u64 reg)
2312 {
2313 	u64 regbase;
2314 
2315 	if (hw->cap.nix_shaping)
2316 		return true;
2317 
2318 	/* If shaping and coloring is not supported, then
2319 	 * *_CIR and *_PIR registers should not be configured.
2320 	 */
2321 	regbase = reg & 0xFFFF;
2322 
2323 	switch (lvl) {
2324 	case NIX_TXSCH_LVL_TL1:
2325 		if (regbase == NIX_AF_TL1X_CIR(0))
2326 			return false;
2327 		break;
2328 	case NIX_TXSCH_LVL_TL2:
2329 		if (regbase == NIX_AF_TL2X_CIR(0) ||
2330 		    regbase == NIX_AF_TL2X_PIR(0))
2331 			return false;
2332 		break;
2333 	case NIX_TXSCH_LVL_TL3:
2334 		if (regbase == NIX_AF_TL3X_CIR(0) ||
2335 		    regbase == NIX_AF_TL3X_PIR(0))
2336 			return false;
2337 		break;
2338 	case NIX_TXSCH_LVL_TL4:
2339 		if (regbase == NIX_AF_TL4X_CIR(0) ||
2340 		    regbase == NIX_AF_TL4X_PIR(0))
2341 			return false;
2342 		break;
2343 	case NIX_TXSCH_LVL_MDQ:
2344 		if (regbase == NIX_AF_MDQX_CIR(0) ||
2345 		    regbase == NIX_AF_MDQX_PIR(0))
2346 			return false;
2347 		break;
2348 	}
2349 	return true;
2350 }
2351 
2352 static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw,
2353 				u16 pcifunc, int blkaddr)
2354 {
2355 	u32 *pfvf_map;
2356 	int schq;
2357 
2358 	schq = nix_get_tx_link(rvu, pcifunc);
2359 	pfvf_map = nix_hw->txsch[NIX_TXSCH_LVL_TL1].pfvf_map;
2360 	/* Skip if PF has already done the config */
2361 	if (TXSCH_MAP_FLAGS(pfvf_map[schq]) & NIX_TXSCHQ_CFG_DONE)
2362 		return;
2363 	rvu_write64(rvu, blkaddr, NIX_AF_TL1X_TOPOLOGY(schq),
2364 		    (TXSCH_TL1_DFLT_RR_PRIO << 1));
2365 
2366 	/* On OcteonTx2 the config was in bytes and newer silcons
2367 	 * it's changed to weight.
2368 	 */
2369 	if (!rvu->hw->cap.nix_common_dwrr_mtu)
2370 		rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq),
2371 			    TXSCH_TL1_DFLT_RR_QTM);
2372 	else
2373 		rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq),
2374 			    CN10K_MAX_DWRR_WEIGHT);
2375 
2376 	rvu_write64(rvu, blkaddr, NIX_AF_TL1X_CIR(schq), 0x00);
2377 	pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], NIX_TXSCHQ_CFG_DONE);
2378 }
2379 
2380 /* Register offset - [15:0]
2381  * Scheduler Queue number - [25:16]
2382  */
2383 #define NIX_TX_SCHQ_MASK	GENMASK_ULL(25, 0)
2384 
2385 static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw,
2386 			       int blkaddr, struct nix_txschq_config *req,
2387 			       struct nix_txschq_config *rsp)
2388 {
2389 	u16 pcifunc = req->hdr.pcifunc;
2390 	int idx, schq;
2391 	u64 reg;
2392 
2393 	for (idx = 0; idx < req->num_regs; idx++) {
2394 		reg = req->reg[idx];
2395 		reg &= NIX_TX_SCHQ_MASK;
2396 		schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT);
2397 		if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, req->lvl, reg) ||
2398 		    !is_valid_txschq(rvu, blkaddr, req->lvl, pcifunc, schq))
2399 			return NIX_AF_INVAL_TXSCHQ_CFG;
2400 		rsp->regval[idx] = rvu_read64(rvu, blkaddr, reg);
2401 	}
2402 	rsp->lvl = req->lvl;
2403 	rsp->num_regs = req->num_regs;
2404 	return 0;
2405 }
2406 
2407 static void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr,
2408 			       u16 pcifunc, struct nix_txsch *txsch)
2409 {
2410 	struct rvu_hwinfo *hw = rvu->hw;
2411 	int lbk_link_start, lbk_links;
2412 	u8 pf = rvu_get_pf(pcifunc);
2413 	int schq;
2414 
2415 	if (!is_pf_cgxmapped(rvu, pf))
2416 		return;
2417 
2418 	lbk_link_start = hw->cgx_links;
2419 
2420 	for (schq = 0; schq < txsch->schq.max; schq++) {
2421 		if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc)
2422 			continue;
2423 		/* Enable all LBK links with channel 63 by default so that
2424 		 * packets can be sent to LBK with a NPC TX MCAM rule
2425 		 */
2426 		lbk_links = hw->lbk_links;
2427 		while (lbk_links--)
2428 			rvu_write64(rvu, blkaddr,
2429 				    NIX_AF_TL3_TL2X_LINKX_CFG(schq,
2430 							      lbk_link_start +
2431 							      lbk_links),
2432 				    BIT_ULL(12) | RVU_SWITCH_LBK_CHAN);
2433 	}
2434 }
2435 
2436 int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
2437 				    struct nix_txschq_config *req,
2438 				    struct nix_txschq_config *rsp)
2439 {
2440 	u64 reg, val, regval, schq_regbase, val_mask;
2441 	struct rvu_hwinfo *hw = rvu->hw;
2442 	u16 pcifunc = req->hdr.pcifunc;
2443 	struct nix_txsch *txsch;
2444 	struct nix_hw *nix_hw;
2445 	int blkaddr, idx, err;
2446 	int nixlf, schq;
2447 	u32 *pfvf_map;
2448 
2449 	if (req->lvl >= NIX_TXSCH_LVL_CNT ||
2450 	    req->num_regs > MAX_REGS_PER_MBOX_MSG)
2451 		return NIX_AF_INVAL_TXSCHQ_CFG;
2452 
2453 	err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
2454 	if (err)
2455 		return err;
2456 
2457 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
2458 	if (!nix_hw)
2459 		return NIX_AF_ERR_INVALID_NIXBLK;
2460 
2461 	if (req->read)
2462 		return nix_txschq_cfg_read(rvu, nix_hw, blkaddr, req, rsp);
2463 
2464 	txsch = &nix_hw->txsch[req->lvl];
2465 	pfvf_map = txsch->pfvf_map;
2466 
2467 	if (req->lvl >= hw->cap.nix_tx_aggr_lvl &&
2468 	    pcifunc & RVU_PFVF_FUNC_MASK) {
2469 		mutex_lock(&rvu->rsrc_lock);
2470 		if (req->lvl == NIX_TXSCH_LVL_TL1)
2471 			nix_tl1_default_cfg(rvu, nix_hw, pcifunc, blkaddr);
2472 		mutex_unlock(&rvu->rsrc_lock);
2473 		return 0;
2474 	}
2475 
2476 	for (idx = 0; idx < req->num_regs; idx++) {
2477 		reg = req->reg[idx];
2478 		reg &= NIX_TX_SCHQ_MASK;
2479 		regval = req->regval[idx];
2480 		schq_regbase = reg & 0xFFFF;
2481 		val_mask = req->regval_mask[idx];
2482 
2483 		if (!is_txschq_hierarchy_valid(rvu, pcifunc, blkaddr,
2484 					       txsch->lvl, reg, regval))
2485 			return NIX_AF_INVAL_TXSCHQ_CFG;
2486 
2487 		/* Check if shaping and coloring is supported */
2488 		if (!is_txschq_shaping_valid(hw, req->lvl, reg))
2489 			continue;
2490 
2491 		val = rvu_read64(rvu, blkaddr, reg);
2492 		regval = (val & val_mask) | (regval & ~val_mask);
2493 
2494 		/* Handle shaping state toggle specially */
2495 		if (hw->cap.nix_shaper_toggle_wait &&
2496 		    handle_txschq_shaper_update(rvu, blkaddr, nixlf,
2497 						req->lvl, reg, regval))
2498 			continue;
2499 
2500 		/* Replace PF/VF visible NIXLF slot with HW NIXLF id */
2501 		if (schq_regbase == NIX_AF_SMQX_CFG(0)) {
2502 			nixlf = rvu_get_lf(rvu, &hw->block[blkaddr],
2503 					   pcifunc, 0);
2504 			regval &= ~(0x7FULL << 24);
2505 			regval |= ((u64)nixlf << 24);
2506 		}
2507 
2508 		/* Clear 'BP_ENA' config, if it's not allowed */
2509 		if (!hw->cap.nix_tx_link_bp) {
2510 			if (schq_regbase == NIX_AF_TL4X_SDP_LINK_CFG(0) ||
2511 			    (schq_regbase & 0xFF00) ==
2512 			    NIX_AF_TL3_TL2X_LINKX_CFG(0, 0))
2513 				regval &= ~BIT_ULL(13);
2514 		}
2515 
2516 		/* Mark config as done for TL1 by PF */
2517 		if (schq_regbase >= NIX_AF_TL1X_SCHEDULE(0) &&
2518 		    schq_regbase <= NIX_AF_TL1X_GREEN_BYTES(0)) {
2519 			schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT);
2520 			mutex_lock(&rvu->rsrc_lock);
2521 			pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq],
2522 							NIX_TXSCHQ_CFG_DONE);
2523 			mutex_unlock(&rvu->rsrc_lock);
2524 		}
2525 
2526 		/* SMQ flush is special hence split register writes such
2527 		 * that flush first and write rest of the bits later.
2528 		 */
2529 		if (schq_regbase == NIX_AF_SMQX_CFG(0) &&
2530 		    (regval & BIT_ULL(49))) {
2531 			schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT);
2532 			nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf);
2533 			regval &= ~BIT_ULL(49);
2534 		}
2535 		rvu_write64(rvu, blkaddr, reg, regval);
2536 	}
2537 
2538 	rvu_nix_tx_tl2_cfg(rvu, blkaddr, pcifunc,
2539 			   &nix_hw->txsch[NIX_TXSCH_LVL_TL2]);
2540 	return 0;
2541 }
2542 
2543 static int nix_rx_vtag_cfg(struct rvu *rvu, int nixlf, int blkaddr,
2544 			   struct nix_vtag_config *req)
2545 {
2546 	u64 regval = req->vtag_size;
2547 
2548 	if (req->rx.vtag_type > NIX_AF_LFX_RX_VTAG_TYPE7 ||
2549 	    req->vtag_size > VTAGSIZE_T8)
2550 		return -EINVAL;
2551 
2552 	/* RX VTAG Type 7 reserved for vf vlan */
2553 	if (req->rx.vtag_type == NIX_AF_LFX_RX_VTAG_TYPE7)
2554 		return NIX_AF_ERR_RX_VTAG_INUSE;
2555 
2556 	if (req->rx.capture_vtag)
2557 		regval |= BIT_ULL(5);
2558 	if (req->rx.strip_vtag)
2559 		regval |= BIT_ULL(4);
2560 
2561 	rvu_write64(rvu, blkaddr,
2562 		    NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, req->rx.vtag_type), regval);
2563 	return 0;
2564 }
2565 
2566 static int nix_tx_vtag_free(struct rvu *rvu, int blkaddr,
2567 			    u16 pcifunc, int index)
2568 {
2569 	struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr);
2570 	struct nix_txvlan *vlan;
2571 
2572 	if (!nix_hw)
2573 		return NIX_AF_ERR_INVALID_NIXBLK;
2574 
2575 	vlan = &nix_hw->txvlan;
2576 	if (vlan->entry2pfvf_map[index] != pcifunc)
2577 		return NIX_AF_ERR_PARAM;
2578 
2579 	rvu_write64(rvu, blkaddr,
2580 		    NIX_AF_TX_VTAG_DEFX_DATA(index), 0x0ull);
2581 	rvu_write64(rvu, blkaddr,
2582 		    NIX_AF_TX_VTAG_DEFX_CTL(index), 0x0ull);
2583 
2584 	vlan->entry2pfvf_map[index] = 0;
2585 	rvu_free_rsrc(&vlan->rsrc, index);
2586 
2587 	return 0;
2588 }
2589 
2590 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc)
2591 {
2592 	struct nix_txvlan *vlan;
2593 	struct nix_hw *nix_hw;
2594 	int index, blkaddr;
2595 
2596 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
2597 	if (blkaddr < 0)
2598 		return;
2599 
2600 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
2601 	if (!nix_hw)
2602 		return;
2603 
2604 	vlan = &nix_hw->txvlan;
2605 
2606 	mutex_lock(&vlan->rsrc_lock);
2607 	/* Scan all the entries and free the ones mapped to 'pcifunc' */
2608 	for (index = 0; index < vlan->rsrc.max; index++) {
2609 		if (vlan->entry2pfvf_map[index] == pcifunc)
2610 			nix_tx_vtag_free(rvu, blkaddr, pcifunc, index);
2611 	}
2612 	mutex_unlock(&vlan->rsrc_lock);
2613 }
2614 
2615 static int nix_tx_vtag_alloc(struct rvu *rvu, int blkaddr,
2616 			     u64 vtag, u8 size)
2617 {
2618 	struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr);
2619 	struct nix_txvlan *vlan;
2620 	u64 regval;
2621 	int index;
2622 
2623 	if (!nix_hw)
2624 		return NIX_AF_ERR_INVALID_NIXBLK;
2625 
2626 	vlan = &nix_hw->txvlan;
2627 
2628 	mutex_lock(&vlan->rsrc_lock);
2629 
2630 	index = rvu_alloc_rsrc(&vlan->rsrc);
2631 	if (index < 0) {
2632 		mutex_unlock(&vlan->rsrc_lock);
2633 		return index;
2634 	}
2635 
2636 	mutex_unlock(&vlan->rsrc_lock);
2637 
2638 	regval = size ? vtag : vtag << 32;
2639 
2640 	rvu_write64(rvu, blkaddr,
2641 		    NIX_AF_TX_VTAG_DEFX_DATA(index), regval);
2642 	rvu_write64(rvu, blkaddr,
2643 		    NIX_AF_TX_VTAG_DEFX_CTL(index), size);
2644 
2645 	return index;
2646 }
2647 
2648 static int nix_tx_vtag_decfg(struct rvu *rvu, int blkaddr,
2649 			     struct nix_vtag_config *req)
2650 {
2651 	struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr);
2652 	u16 pcifunc = req->hdr.pcifunc;
2653 	int idx0 = req->tx.vtag0_idx;
2654 	int idx1 = req->tx.vtag1_idx;
2655 	struct nix_txvlan *vlan;
2656 	int err = 0;
2657 
2658 	if (!nix_hw)
2659 		return NIX_AF_ERR_INVALID_NIXBLK;
2660 
2661 	vlan = &nix_hw->txvlan;
2662 	if (req->tx.free_vtag0 && req->tx.free_vtag1)
2663 		if (vlan->entry2pfvf_map[idx0] != pcifunc ||
2664 		    vlan->entry2pfvf_map[idx1] != pcifunc)
2665 			return NIX_AF_ERR_PARAM;
2666 
2667 	mutex_lock(&vlan->rsrc_lock);
2668 
2669 	if (req->tx.free_vtag0) {
2670 		err = nix_tx_vtag_free(rvu, blkaddr, pcifunc, idx0);
2671 		if (err)
2672 			goto exit;
2673 	}
2674 
2675 	if (req->tx.free_vtag1)
2676 		err = nix_tx_vtag_free(rvu, blkaddr, pcifunc, idx1);
2677 
2678 exit:
2679 	mutex_unlock(&vlan->rsrc_lock);
2680 	return err;
2681 }
2682 
2683 static int nix_tx_vtag_cfg(struct rvu *rvu, int blkaddr,
2684 			   struct nix_vtag_config *req,
2685 			   struct nix_vtag_config_rsp *rsp)
2686 {
2687 	struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr);
2688 	struct nix_txvlan *vlan;
2689 	u16 pcifunc = req->hdr.pcifunc;
2690 
2691 	if (!nix_hw)
2692 		return NIX_AF_ERR_INVALID_NIXBLK;
2693 
2694 	vlan = &nix_hw->txvlan;
2695 	if (req->tx.cfg_vtag0) {
2696 		rsp->vtag0_idx =
2697 			nix_tx_vtag_alloc(rvu, blkaddr,
2698 					  req->tx.vtag0, req->vtag_size);
2699 
2700 		if (rsp->vtag0_idx < 0)
2701 			return NIX_AF_ERR_TX_VTAG_NOSPC;
2702 
2703 		vlan->entry2pfvf_map[rsp->vtag0_idx] = pcifunc;
2704 	}
2705 
2706 	if (req->tx.cfg_vtag1) {
2707 		rsp->vtag1_idx =
2708 			nix_tx_vtag_alloc(rvu, blkaddr,
2709 					  req->tx.vtag1, req->vtag_size);
2710 
2711 		if (rsp->vtag1_idx < 0)
2712 			goto err_free;
2713 
2714 		vlan->entry2pfvf_map[rsp->vtag1_idx] = pcifunc;
2715 	}
2716 
2717 	return 0;
2718 
2719 err_free:
2720 	if (req->tx.cfg_vtag0)
2721 		nix_tx_vtag_free(rvu, blkaddr, pcifunc, rsp->vtag0_idx);
2722 
2723 	return NIX_AF_ERR_TX_VTAG_NOSPC;
2724 }
2725 
2726 int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu,
2727 				  struct nix_vtag_config *req,
2728 				  struct nix_vtag_config_rsp *rsp)
2729 {
2730 	u16 pcifunc = req->hdr.pcifunc;
2731 	int blkaddr, nixlf, err;
2732 
2733 	err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
2734 	if (err)
2735 		return err;
2736 
2737 	if (req->cfg_type) {
2738 		/* rx vtag configuration */
2739 		err = nix_rx_vtag_cfg(rvu, nixlf, blkaddr, req);
2740 		if (err)
2741 			return NIX_AF_ERR_PARAM;
2742 	} else {
2743 		/* tx vtag configuration */
2744 		if ((req->tx.cfg_vtag0 || req->tx.cfg_vtag1) &&
2745 		    (req->tx.free_vtag0 || req->tx.free_vtag1))
2746 			return NIX_AF_ERR_PARAM;
2747 
2748 		if (req->tx.cfg_vtag0 || req->tx.cfg_vtag1)
2749 			return nix_tx_vtag_cfg(rvu, blkaddr, req, rsp);
2750 
2751 		if (req->tx.free_vtag0 || req->tx.free_vtag1)
2752 			return nix_tx_vtag_decfg(rvu, blkaddr, req);
2753 	}
2754 
2755 	return 0;
2756 }
2757 
2758 static int nix_blk_setup_mce(struct rvu *rvu, struct nix_hw *nix_hw,
2759 			     int mce, u8 op, u16 pcifunc, int next, bool eol)
2760 {
2761 	struct nix_aq_enq_req aq_req;
2762 	int err;
2763 
2764 	aq_req.hdr.pcifunc = 0;
2765 	aq_req.ctype = NIX_AQ_CTYPE_MCE;
2766 	aq_req.op = op;
2767 	aq_req.qidx = mce;
2768 
2769 	/* Use RSS with RSS index 0 */
2770 	aq_req.mce.op = 1;
2771 	aq_req.mce.index = 0;
2772 	aq_req.mce.eol = eol;
2773 	aq_req.mce.pf_func = pcifunc;
2774 	aq_req.mce.next = next;
2775 
2776 	/* All fields valid */
2777 	*(u64 *)(&aq_req.mce_mask) = ~0ULL;
2778 
2779 	err = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, &aq_req, NULL);
2780 	if (err) {
2781 		dev_err(rvu->dev, "Failed to setup Bcast MCE for PF%d:VF%d\n",
2782 			rvu_get_pf(pcifunc), pcifunc & RVU_PFVF_FUNC_MASK);
2783 		return err;
2784 	}
2785 	return 0;
2786 }
2787 
2788 static int nix_update_mce_list_entry(struct nix_mce_list *mce_list,
2789 				     u16 pcifunc, bool add)
2790 {
2791 	struct mce *mce, *tail = NULL;
2792 	bool delete = false;
2793 
2794 	/* Scan through the current list */
2795 	hlist_for_each_entry(mce, &mce_list->head, node) {
2796 		/* If already exists, then delete */
2797 		if (mce->pcifunc == pcifunc && !add) {
2798 			delete = true;
2799 			break;
2800 		} else if (mce->pcifunc == pcifunc && add) {
2801 			/* entry already exists */
2802 			return 0;
2803 		}
2804 		tail = mce;
2805 	}
2806 
2807 	if (delete) {
2808 		hlist_del(&mce->node);
2809 		kfree(mce);
2810 		mce_list->count--;
2811 		return 0;
2812 	}
2813 
2814 	if (!add)
2815 		return 0;
2816 
2817 	/* Add a new one to the list, at the tail */
2818 	mce = kzalloc(sizeof(*mce), GFP_KERNEL);
2819 	if (!mce)
2820 		return -ENOMEM;
2821 	mce->pcifunc = pcifunc;
2822 	if (!tail)
2823 		hlist_add_head(&mce->node, &mce_list->head);
2824 	else
2825 		hlist_add_behind(&mce->node, &tail->node);
2826 	mce_list->count++;
2827 	return 0;
2828 }
2829 
2830 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
2831 			struct nix_mce_list *mce_list,
2832 			int mce_idx, int mcam_index, bool add)
2833 {
2834 	int err = 0, idx, next_idx, last_idx, blkaddr, npc_blkaddr;
2835 	struct npc_mcam *mcam = &rvu->hw->mcam;
2836 	struct nix_mcast *mcast;
2837 	struct nix_hw *nix_hw;
2838 	struct mce *mce;
2839 
2840 	if (!mce_list)
2841 		return -EINVAL;
2842 
2843 	/* Get this PF/VF func's MCE index */
2844 	idx = mce_idx + (pcifunc & RVU_PFVF_FUNC_MASK);
2845 
2846 	if (idx > (mce_idx + mce_list->max)) {
2847 		dev_err(rvu->dev,
2848 			"%s: Idx %d > max MCE idx %d, for PF%d bcast list\n",
2849 			__func__, idx, mce_list->max,
2850 			pcifunc >> RVU_PFVF_PF_SHIFT);
2851 		return -EINVAL;
2852 	}
2853 
2854 	err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);
2855 	if (err)
2856 		return err;
2857 
2858 	mcast = &nix_hw->mcast;
2859 	mutex_lock(&mcast->mce_lock);
2860 
2861 	err = nix_update_mce_list_entry(mce_list, pcifunc, add);
2862 	if (err)
2863 		goto end;
2864 
2865 	/* Disable MCAM entry in NPC */
2866 	if (!mce_list->count) {
2867 		npc_blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2868 		npc_enable_mcam_entry(rvu, mcam, npc_blkaddr, mcam_index, false);
2869 		goto end;
2870 	}
2871 
2872 	/* Dump the updated list to HW */
2873 	idx = mce_idx;
2874 	last_idx = idx + mce_list->count - 1;
2875 	hlist_for_each_entry(mce, &mce_list->head, node) {
2876 		if (idx > last_idx)
2877 			break;
2878 
2879 		next_idx = idx + 1;
2880 		/* EOL should be set in last MCE */
2881 		err = nix_blk_setup_mce(rvu, nix_hw, idx, NIX_AQ_INSTOP_WRITE,
2882 					mce->pcifunc, next_idx,
2883 					(next_idx > last_idx) ? true : false);
2884 		if (err)
2885 			goto end;
2886 		idx++;
2887 	}
2888 
2889 end:
2890 	mutex_unlock(&mcast->mce_lock);
2891 	return err;
2892 }
2893 
2894 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
2895 		      struct nix_mce_list **mce_list, int *mce_idx)
2896 {
2897 	struct rvu_hwinfo *hw = rvu->hw;
2898 	struct rvu_pfvf *pfvf;
2899 
2900 	if (!hw->cap.nix_rx_multicast ||
2901 	    !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc & ~RVU_PFVF_FUNC_MASK))) {
2902 		*mce_list = NULL;
2903 		*mce_idx = 0;
2904 		return;
2905 	}
2906 
2907 	/* Get this PF/VF func's MCE index */
2908 	pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
2909 
2910 	if (type == NIXLF_BCAST_ENTRY) {
2911 		*mce_list = &pfvf->bcast_mce_list;
2912 		*mce_idx = pfvf->bcast_mce_idx;
2913 	} else if (type == NIXLF_ALLMULTI_ENTRY) {
2914 		*mce_list = &pfvf->mcast_mce_list;
2915 		*mce_idx = pfvf->mcast_mce_idx;
2916 	} else if (type == NIXLF_PROMISC_ENTRY) {
2917 		*mce_list = &pfvf->promisc_mce_list;
2918 		*mce_idx = pfvf->promisc_mce_idx;
2919 	}  else {
2920 		*mce_list = NULL;
2921 		*mce_idx = 0;
2922 	}
2923 }
2924 
2925 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc,
2926 			       int type, bool add)
2927 {
2928 	int err = 0, nixlf, blkaddr, mcam_index, mce_idx;
2929 	struct npc_mcam *mcam = &rvu->hw->mcam;
2930 	struct rvu_hwinfo *hw = rvu->hw;
2931 	struct nix_mce_list *mce_list;
2932 	int pf;
2933 
2934 	/* skip multicast pkt replication for AF's VFs & SDP links */
2935 	if (is_afvf(pcifunc) || is_sdp_pfvf(pcifunc))
2936 		return 0;
2937 
2938 	if (!hw->cap.nix_rx_multicast)
2939 		return 0;
2940 
2941 	pf = rvu_get_pf(pcifunc);
2942 	if (!is_pf_cgxmapped(rvu, pf))
2943 		return 0;
2944 
2945 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
2946 	if (blkaddr < 0)
2947 		return -EINVAL;
2948 
2949 	nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0);
2950 	if (nixlf < 0)
2951 		return -EINVAL;
2952 
2953 	nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx);
2954 
2955 	mcam_index = npc_get_nixlf_mcam_index(mcam,
2956 					      pcifunc & ~RVU_PFVF_FUNC_MASK,
2957 					      nixlf, type);
2958 	err = nix_update_mce_list(rvu, pcifunc, mce_list,
2959 				  mce_idx, mcam_index, add);
2960 	return err;
2961 }
2962 
2963 static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw)
2964 {
2965 	struct nix_mcast *mcast = &nix_hw->mcast;
2966 	int err, pf, numvfs, idx;
2967 	struct rvu_pfvf *pfvf;
2968 	u16 pcifunc;
2969 	u64 cfg;
2970 
2971 	/* Skip PF0 (i.e AF) */
2972 	for (pf = 1; pf < (rvu->cgx_mapped_pfs + 1); pf++) {
2973 		cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2974 		/* If PF is not enabled, nothing to do */
2975 		if (!((cfg >> 20) & 0x01))
2976 			continue;
2977 		/* Get numVFs attached to this PF */
2978 		numvfs = (cfg >> 12) & 0xFF;
2979 
2980 		pfvf = &rvu->pf[pf];
2981 
2982 		/* This NIX0/1 block mapped to PF ? */
2983 		if (pfvf->nix_blkaddr != nix_hw->blkaddr)
2984 			continue;
2985 
2986 		/* save start idx of broadcast mce list */
2987 		pfvf->bcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1);
2988 		nix_mce_list_init(&pfvf->bcast_mce_list, numvfs + 1);
2989 
2990 		/* save start idx of multicast mce list */
2991 		pfvf->mcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1);
2992 		nix_mce_list_init(&pfvf->mcast_mce_list, numvfs + 1);
2993 
2994 		/* save the start idx of promisc mce list */
2995 		pfvf->promisc_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1);
2996 		nix_mce_list_init(&pfvf->promisc_mce_list, numvfs + 1);
2997 
2998 		for (idx = 0; idx < (numvfs + 1); idx++) {
2999 			/* idx-0 is for PF, followed by VFs */
3000 			pcifunc = (pf << RVU_PFVF_PF_SHIFT);
3001 			pcifunc |= idx;
3002 			/* Add dummy entries now, so that we don't have to check
3003 			 * for whether AQ_OP should be INIT/WRITE later on.
3004 			 * Will be updated when a NIXLF is attached/detached to
3005 			 * these PF/VFs.
3006 			 */
3007 			err = nix_blk_setup_mce(rvu, nix_hw,
3008 						pfvf->bcast_mce_idx + idx,
3009 						NIX_AQ_INSTOP_INIT,
3010 						pcifunc, 0, true);
3011 			if (err)
3012 				return err;
3013 
3014 			/* add dummy entries to multicast mce list */
3015 			err = nix_blk_setup_mce(rvu, nix_hw,
3016 						pfvf->mcast_mce_idx + idx,
3017 						NIX_AQ_INSTOP_INIT,
3018 						pcifunc, 0, true);
3019 			if (err)
3020 				return err;
3021 
3022 			/* add dummy entries to promisc mce list */
3023 			err = nix_blk_setup_mce(rvu, nix_hw,
3024 						pfvf->promisc_mce_idx + idx,
3025 						NIX_AQ_INSTOP_INIT,
3026 						pcifunc, 0, true);
3027 			if (err)
3028 				return err;
3029 		}
3030 	}
3031 	return 0;
3032 }
3033 
3034 static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)
3035 {
3036 	struct nix_mcast *mcast = &nix_hw->mcast;
3037 	struct rvu_hwinfo *hw = rvu->hw;
3038 	int err, size;
3039 
3040 	size = (rvu_read64(rvu, blkaddr, NIX_AF_CONST3) >> 16) & 0x0F;
3041 	size = (1ULL << size);
3042 
3043 	/* Alloc memory for multicast/mirror replication entries */
3044 	err = qmem_alloc(rvu->dev, &mcast->mce_ctx,
3045 			 (256UL << MC_TBL_SIZE), size);
3046 	if (err)
3047 		return -ENOMEM;
3048 
3049 	rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BASE,
3050 		    (u64)mcast->mce_ctx->iova);
3051 
3052 	/* Set max list length equal to max no of VFs per PF  + PF itself */
3053 	rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG,
3054 		    BIT_ULL(36) | (hw->max_vfs_per_pf << 4) | MC_TBL_SIZE);
3055 
3056 	/* Alloc memory for multicast replication buffers */
3057 	size = rvu_read64(rvu, blkaddr, NIX_AF_MC_MIRROR_CONST) & 0xFFFF;
3058 	err = qmem_alloc(rvu->dev, &mcast->mcast_buf,
3059 			 (8UL << MC_BUF_CNT), size);
3060 	if (err)
3061 		return -ENOMEM;
3062 
3063 	rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_BASE,
3064 		    (u64)mcast->mcast_buf->iova);
3065 
3066 	/* Alloc pkind for NIX internal RX multicast/mirror replay */
3067 	mcast->replay_pkind = rvu_alloc_rsrc(&hw->pkind.rsrc);
3068 
3069 	rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_CFG,
3070 		    BIT_ULL(63) | (mcast->replay_pkind << 24) |
3071 		    BIT_ULL(20) | MC_BUF_CNT);
3072 
3073 	mutex_init(&mcast->mce_lock);
3074 
3075 	return nix_setup_mce_tables(rvu, nix_hw);
3076 }
3077 
3078 static int nix_setup_txvlan(struct rvu *rvu, struct nix_hw *nix_hw)
3079 {
3080 	struct nix_txvlan *vlan = &nix_hw->txvlan;
3081 	int err;
3082 
3083 	/* Allocate resource bimap for tx vtag def registers*/
3084 	vlan->rsrc.max = NIX_TX_VTAG_DEF_MAX;
3085 	err = rvu_alloc_bitmap(&vlan->rsrc);
3086 	if (err)
3087 		return -ENOMEM;
3088 
3089 	/* Alloc memory for saving entry to RVU PFFUNC allocation mapping */
3090 	vlan->entry2pfvf_map = devm_kcalloc(rvu->dev, vlan->rsrc.max,
3091 					    sizeof(u16), GFP_KERNEL);
3092 	if (!vlan->entry2pfvf_map)
3093 		goto free_mem;
3094 
3095 	mutex_init(&vlan->rsrc_lock);
3096 	return 0;
3097 
3098 free_mem:
3099 	kfree(vlan->rsrc.bmap);
3100 	return -ENOMEM;
3101 }
3102 
3103 static int nix_setup_txschq(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)
3104 {
3105 	struct nix_txsch *txsch;
3106 	int err, lvl, schq;
3107 	u64 cfg, reg;
3108 
3109 	/* Get scheduler queue count of each type and alloc
3110 	 * bitmap for each for alloc/free/attach operations.
3111 	 */
3112 	for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
3113 		txsch = &nix_hw->txsch[lvl];
3114 		txsch->lvl = lvl;
3115 		switch (lvl) {
3116 		case NIX_TXSCH_LVL_SMQ:
3117 			reg = NIX_AF_MDQ_CONST;
3118 			break;
3119 		case NIX_TXSCH_LVL_TL4:
3120 			reg = NIX_AF_TL4_CONST;
3121 			break;
3122 		case NIX_TXSCH_LVL_TL3:
3123 			reg = NIX_AF_TL3_CONST;
3124 			break;
3125 		case NIX_TXSCH_LVL_TL2:
3126 			reg = NIX_AF_TL2_CONST;
3127 			break;
3128 		case NIX_TXSCH_LVL_TL1:
3129 			reg = NIX_AF_TL1_CONST;
3130 			break;
3131 		}
3132 		cfg = rvu_read64(rvu, blkaddr, reg);
3133 		txsch->schq.max = cfg & 0xFFFF;
3134 		err = rvu_alloc_bitmap(&txsch->schq);
3135 		if (err)
3136 			return err;
3137 
3138 		/* Allocate memory for scheduler queues to
3139 		 * PF/VF pcifunc mapping info.
3140 		 */
3141 		txsch->pfvf_map = devm_kcalloc(rvu->dev, txsch->schq.max,
3142 					       sizeof(u32), GFP_KERNEL);
3143 		if (!txsch->pfvf_map)
3144 			return -ENOMEM;
3145 		for (schq = 0; schq < txsch->schq.max; schq++)
3146 			txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE);
3147 	}
3148 
3149 	/* Setup a default value of 8192 as DWRR MTU */
3150 	if (rvu->hw->cap.nix_common_dwrr_mtu) {
3151 		rvu_write64(rvu, blkaddr, NIX_AF_DWRR_RPM_MTU,
3152 			    convert_bytes_to_dwrr_mtu(8192));
3153 		rvu_write64(rvu, blkaddr, NIX_AF_DWRR_SDP_MTU,
3154 			    convert_bytes_to_dwrr_mtu(8192));
3155 	}
3156 
3157 	return 0;
3158 }
3159 
3160 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
3161 				int blkaddr, u32 cfg)
3162 {
3163 	int fmt_idx;
3164 
3165 	for (fmt_idx = 0; fmt_idx < nix_hw->mark_format.in_use; fmt_idx++) {
3166 		if (nix_hw->mark_format.cfg[fmt_idx] == cfg)
3167 			return fmt_idx;
3168 	}
3169 	if (fmt_idx >= nix_hw->mark_format.total)
3170 		return -ERANGE;
3171 
3172 	rvu_write64(rvu, blkaddr, NIX_AF_MARK_FORMATX_CTL(fmt_idx), cfg);
3173 	nix_hw->mark_format.cfg[fmt_idx] = cfg;
3174 	nix_hw->mark_format.in_use++;
3175 	return fmt_idx;
3176 }
3177 
3178 static int nix_af_mark_format_setup(struct rvu *rvu, struct nix_hw *nix_hw,
3179 				    int blkaddr)
3180 {
3181 	u64 cfgs[] = {
3182 		[NIX_MARK_CFG_IP_DSCP_RED]         = 0x10003,
3183 		[NIX_MARK_CFG_IP_DSCP_YELLOW]      = 0x11200,
3184 		[NIX_MARK_CFG_IP_DSCP_YELLOW_RED]  = 0x11203,
3185 		[NIX_MARK_CFG_IP_ECN_RED]          = 0x6000c,
3186 		[NIX_MARK_CFG_IP_ECN_YELLOW]       = 0x60c00,
3187 		[NIX_MARK_CFG_IP_ECN_YELLOW_RED]   = 0x60c0c,
3188 		[NIX_MARK_CFG_VLAN_DEI_RED]        = 0x30008,
3189 		[NIX_MARK_CFG_VLAN_DEI_YELLOW]     = 0x30800,
3190 		[NIX_MARK_CFG_VLAN_DEI_YELLOW_RED] = 0x30808,
3191 	};
3192 	int i, rc;
3193 	u64 total;
3194 
3195 	total = (rvu_read64(rvu, blkaddr, NIX_AF_PSE_CONST) & 0xFF00) >> 8;
3196 	nix_hw->mark_format.total = (u8)total;
3197 	nix_hw->mark_format.cfg = devm_kcalloc(rvu->dev, total, sizeof(u32),
3198 					       GFP_KERNEL);
3199 	if (!nix_hw->mark_format.cfg)
3200 		return -ENOMEM;
3201 	for (i = 0; i < NIX_MARK_CFG_MAX; i++) {
3202 		rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfgs[i]);
3203 		if (rc < 0)
3204 			dev_err(rvu->dev, "Err %d in setup mark format %d\n",
3205 				i, rc);
3206 	}
3207 
3208 	return 0;
3209 }
3210 
3211 static void rvu_get_lbk_link_max_frs(struct rvu *rvu,  u16 *max_mtu)
3212 {
3213 	/* CN10K supports LBK FIFO size 72 KB */
3214 	if (rvu->hw->lbk_bufsize == 0x12000)
3215 		*max_mtu = CN10K_LBK_LINK_MAX_FRS;
3216 	else
3217 		*max_mtu = NIC_HW_MAX_FRS;
3218 }
3219 
3220 static void rvu_get_lmac_link_max_frs(struct rvu *rvu, u16 *max_mtu)
3221 {
3222 	int fifo_size = rvu_cgx_get_fifolen(rvu);
3223 
3224 	/* RPM supports FIFO len 128 KB and RPM2 supports double the
3225 	 * FIFO len to accommodate 8 LMACS
3226 	 */
3227 	if (fifo_size == 0x20000 || fifo_size == 0x40000)
3228 		*max_mtu = CN10K_LMAC_LINK_MAX_FRS;
3229 	else
3230 		*max_mtu = NIC_HW_MAX_FRS;
3231 }
3232 
3233 int rvu_mbox_handler_nix_get_hw_info(struct rvu *rvu, struct msg_req *req,
3234 				     struct nix_hw_info *rsp)
3235 {
3236 	u16 pcifunc = req->hdr.pcifunc;
3237 	u64 dwrr_mtu;
3238 	int blkaddr;
3239 
3240 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
3241 	if (blkaddr < 0)
3242 		return NIX_AF_ERR_AF_LF_INVALID;
3243 
3244 	if (is_afvf(pcifunc))
3245 		rvu_get_lbk_link_max_frs(rvu, &rsp->max_mtu);
3246 	else
3247 		rvu_get_lmac_link_max_frs(rvu, &rsp->max_mtu);
3248 
3249 	rsp->min_mtu = NIC_HW_MIN_FRS;
3250 
3251 	if (!rvu->hw->cap.nix_common_dwrr_mtu) {
3252 		/* Return '1' on OTx2 */
3253 		rsp->rpm_dwrr_mtu = 1;
3254 		rsp->sdp_dwrr_mtu = 1;
3255 		return 0;
3256 	}
3257 
3258 	dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_RPM_MTU);
3259 	rsp->rpm_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu);
3260 
3261 	dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_SDP_MTU);
3262 	rsp->sdp_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu);
3263 
3264 	return 0;
3265 }
3266 
3267 int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req,
3268 				   struct msg_rsp *rsp)
3269 {
3270 	u16 pcifunc = req->hdr.pcifunc;
3271 	int i, nixlf, blkaddr, err;
3272 	u64 stats;
3273 
3274 	err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
3275 	if (err)
3276 		return err;
3277 
3278 	/* Get stats count supported by HW */
3279 	stats = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
3280 
3281 	/* Reset tx stats */
3282 	for (i = 0; i < ((stats >> 24) & 0xFF); i++)
3283 		rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_STATX(nixlf, i), 0);
3284 
3285 	/* Reset rx stats */
3286 	for (i = 0; i < ((stats >> 32) & 0xFF); i++)
3287 		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, i), 0);
3288 
3289 	return 0;
3290 }
3291 
3292 /* Returns the ALG index to be set into NPC_RX_ACTION */
3293 static int get_flowkey_alg_idx(struct nix_hw *nix_hw, u32 flow_cfg)
3294 {
3295 	int i;
3296 
3297 	/* Scan over exiting algo entries to find a match */
3298 	for (i = 0; i < nix_hw->flowkey.in_use; i++)
3299 		if (nix_hw->flowkey.flowkey[i] == flow_cfg)
3300 			return i;
3301 
3302 	return -ERANGE;
3303 }
3304 
3305 static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg)
3306 {
3307 	int idx, nr_field, key_off, field_marker, keyoff_marker;
3308 	int max_key_off, max_bit_pos, group_member;
3309 	struct nix_rx_flowkey_alg *field;
3310 	struct nix_rx_flowkey_alg tmp;
3311 	u32 key_type, valid_key;
3312 	int l4_key_offset = 0;
3313 
3314 	if (!alg)
3315 		return -EINVAL;
3316 
3317 #define FIELDS_PER_ALG  5
3318 #define MAX_KEY_OFF	40
3319 	/* Clear all fields */
3320 	memset(alg, 0, sizeof(uint64_t) * FIELDS_PER_ALG);
3321 
3322 	/* Each of the 32 possible flow key algorithm definitions should
3323 	 * fall into above incremental config (except ALG0). Otherwise a
3324 	 * single NPC MCAM entry is not sufficient for supporting RSS.
3325 	 *
3326 	 * If a different definition or combination needed then NPC MCAM
3327 	 * has to be programmed to filter such pkts and it's action should
3328 	 * point to this definition to calculate flowtag or hash.
3329 	 *
3330 	 * The `for loop` goes over _all_ protocol field and the following
3331 	 * variables depicts the state machine forward progress logic.
3332 	 *
3333 	 * keyoff_marker - Enabled when hash byte length needs to be accounted
3334 	 * in field->key_offset update.
3335 	 * field_marker - Enabled when a new field needs to be selected.
3336 	 * group_member - Enabled when protocol is part of a group.
3337 	 */
3338 
3339 	keyoff_marker = 0; max_key_off = 0; group_member = 0;
3340 	nr_field = 0; key_off = 0; field_marker = 1;
3341 	field = &tmp; max_bit_pos = fls(flow_cfg);
3342 	for (idx = 0;
3343 	     idx < max_bit_pos && nr_field < FIELDS_PER_ALG &&
3344 	     key_off < MAX_KEY_OFF; idx++) {
3345 		key_type = BIT(idx);
3346 		valid_key = flow_cfg & key_type;
3347 		/* Found a field marker, reset the field values */
3348 		if (field_marker)
3349 			memset(&tmp, 0, sizeof(tmp));
3350 
3351 		field_marker = true;
3352 		keyoff_marker = true;
3353 		switch (key_type) {
3354 		case NIX_FLOW_KEY_TYPE_PORT:
3355 			field->sel_chan = true;
3356 			/* This should be set to 1, when SEL_CHAN is set */
3357 			field->bytesm1 = 1;
3358 			break;
3359 		case NIX_FLOW_KEY_TYPE_IPV4_PROTO:
3360 			field->lid = NPC_LID_LC;
3361 			field->hdr_offset = 9; /* offset */
3362 			field->bytesm1 = 0; /* 1 byte */
3363 			field->ltype_match = NPC_LT_LC_IP;
3364 			field->ltype_mask = 0xF;
3365 			break;
3366 		case NIX_FLOW_KEY_TYPE_IPV4:
3367 		case NIX_FLOW_KEY_TYPE_INNR_IPV4:
3368 			field->lid = NPC_LID_LC;
3369 			field->ltype_match = NPC_LT_LC_IP;
3370 			if (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV4) {
3371 				field->lid = NPC_LID_LG;
3372 				field->ltype_match = NPC_LT_LG_TU_IP;
3373 			}
3374 			field->hdr_offset = 12; /* SIP offset */
3375 			field->bytesm1 = 7; /* SIP + DIP, 8 bytes */
3376 			field->ltype_mask = 0xF; /* Match only IPv4 */
3377 			keyoff_marker = false;
3378 			break;
3379 		case NIX_FLOW_KEY_TYPE_IPV6:
3380 		case NIX_FLOW_KEY_TYPE_INNR_IPV6:
3381 			field->lid = NPC_LID_LC;
3382 			field->ltype_match = NPC_LT_LC_IP6;
3383 			if (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV6) {
3384 				field->lid = NPC_LID_LG;
3385 				field->ltype_match = NPC_LT_LG_TU_IP6;
3386 			}
3387 			field->hdr_offset = 8; /* SIP offset */
3388 			field->bytesm1 = 31; /* SIP + DIP, 32 bytes */
3389 			field->ltype_mask = 0xF; /* Match only IPv6 */
3390 			break;
3391 		case NIX_FLOW_KEY_TYPE_TCP:
3392 		case NIX_FLOW_KEY_TYPE_UDP:
3393 		case NIX_FLOW_KEY_TYPE_SCTP:
3394 		case NIX_FLOW_KEY_TYPE_INNR_TCP:
3395 		case NIX_FLOW_KEY_TYPE_INNR_UDP:
3396 		case NIX_FLOW_KEY_TYPE_INNR_SCTP:
3397 			field->lid = NPC_LID_LD;
3398 			if (key_type == NIX_FLOW_KEY_TYPE_INNR_TCP ||
3399 			    key_type == NIX_FLOW_KEY_TYPE_INNR_UDP ||
3400 			    key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP)
3401 				field->lid = NPC_LID_LH;
3402 			field->bytesm1 = 3; /* Sport + Dport, 4 bytes */
3403 
3404 			/* Enum values for NPC_LID_LD and NPC_LID_LG are same,
3405 			 * so no need to change the ltype_match, just change
3406 			 * the lid for inner protocols
3407 			 */
3408 			BUILD_BUG_ON((int)NPC_LT_LD_TCP !=
3409 				     (int)NPC_LT_LH_TU_TCP);
3410 			BUILD_BUG_ON((int)NPC_LT_LD_UDP !=
3411 				     (int)NPC_LT_LH_TU_UDP);
3412 			BUILD_BUG_ON((int)NPC_LT_LD_SCTP !=
3413 				     (int)NPC_LT_LH_TU_SCTP);
3414 
3415 			if ((key_type == NIX_FLOW_KEY_TYPE_TCP ||
3416 			     key_type == NIX_FLOW_KEY_TYPE_INNR_TCP) &&
3417 			    valid_key) {
3418 				field->ltype_match |= NPC_LT_LD_TCP;
3419 				group_member = true;
3420 			} else if ((key_type == NIX_FLOW_KEY_TYPE_UDP ||
3421 				    key_type == NIX_FLOW_KEY_TYPE_INNR_UDP) &&
3422 				   valid_key) {
3423 				field->ltype_match |= NPC_LT_LD_UDP;
3424 				group_member = true;
3425 			} else if ((key_type == NIX_FLOW_KEY_TYPE_SCTP ||
3426 				    key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) &&
3427 				   valid_key) {
3428 				field->ltype_match |= NPC_LT_LD_SCTP;
3429 				group_member = true;
3430 			}
3431 			field->ltype_mask = ~field->ltype_match;
3432 			if (key_type == NIX_FLOW_KEY_TYPE_SCTP ||
3433 			    key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) {
3434 				/* Handle the case where any of the group item
3435 				 * is enabled in the group but not the final one
3436 				 */
3437 				if (group_member) {
3438 					valid_key = true;
3439 					group_member = false;
3440 				}
3441 			} else {
3442 				field_marker = false;
3443 				keyoff_marker = false;
3444 			}
3445 
3446 			/* TCP/UDP/SCTP and ESP/AH falls at same offset so
3447 			 * remember the TCP key offset of 40 byte hash key.
3448 			 */
3449 			if (key_type == NIX_FLOW_KEY_TYPE_TCP)
3450 				l4_key_offset = key_off;
3451 			break;
3452 		case NIX_FLOW_KEY_TYPE_NVGRE:
3453 			field->lid = NPC_LID_LD;
3454 			field->hdr_offset = 4; /* VSID offset */
3455 			field->bytesm1 = 2;
3456 			field->ltype_match = NPC_LT_LD_NVGRE;
3457 			field->ltype_mask = 0xF;
3458 			break;
3459 		case NIX_FLOW_KEY_TYPE_VXLAN:
3460 		case NIX_FLOW_KEY_TYPE_GENEVE:
3461 			field->lid = NPC_LID_LE;
3462 			field->bytesm1 = 2;
3463 			field->hdr_offset = 4;
3464 			field->ltype_mask = 0xF;
3465 			field_marker = false;
3466 			keyoff_marker = false;
3467 
3468 			if (key_type == NIX_FLOW_KEY_TYPE_VXLAN && valid_key) {
3469 				field->ltype_match |= NPC_LT_LE_VXLAN;
3470 				group_member = true;
3471 			}
3472 
3473 			if (key_type == NIX_FLOW_KEY_TYPE_GENEVE && valid_key) {
3474 				field->ltype_match |= NPC_LT_LE_GENEVE;
3475 				group_member = true;
3476 			}
3477 
3478 			if (key_type == NIX_FLOW_KEY_TYPE_GENEVE) {
3479 				if (group_member) {
3480 					field->ltype_mask = ~field->ltype_match;
3481 					field_marker = true;
3482 					keyoff_marker = true;
3483 					valid_key = true;
3484 					group_member = false;
3485 				}
3486 			}
3487 			break;
3488 		case NIX_FLOW_KEY_TYPE_ETH_DMAC:
3489 		case NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC:
3490 			field->lid = NPC_LID_LA;
3491 			field->ltype_match = NPC_LT_LA_ETHER;
3492 			if (key_type == NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC) {
3493 				field->lid = NPC_LID_LF;
3494 				field->ltype_match = NPC_LT_LF_TU_ETHER;
3495 			}
3496 			field->hdr_offset = 0;
3497 			field->bytesm1 = 5; /* DMAC 6 Byte */
3498 			field->ltype_mask = 0xF;
3499 			break;
3500 		case NIX_FLOW_KEY_TYPE_IPV6_EXT:
3501 			field->lid = NPC_LID_LC;
3502 			field->hdr_offset = 40; /* IPV6 hdr */
3503 			field->bytesm1 = 0; /* 1 Byte ext hdr*/
3504 			field->ltype_match = NPC_LT_LC_IP6_EXT;
3505 			field->ltype_mask = 0xF;
3506 			break;
3507 		case NIX_FLOW_KEY_TYPE_GTPU:
3508 			field->lid = NPC_LID_LE;
3509 			field->hdr_offset = 4;
3510 			field->bytesm1 = 3; /* 4 bytes TID*/
3511 			field->ltype_match = NPC_LT_LE_GTPU;
3512 			field->ltype_mask = 0xF;
3513 			break;
3514 		case NIX_FLOW_KEY_TYPE_VLAN:
3515 			field->lid = NPC_LID_LB;
3516 			field->hdr_offset = 2; /* Skip TPID (2-bytes) */
3517 			field->bytesm1 = 1; /* 2 Bytes (Actually 12 bits) */
3518 			field->ltype_match = NPC_LT_LB_CTAG;
3519 			field->ltype_mask = 0xF;
3520 			field->fn_mask = 1; /* Mask out the first nibble */
3521 			break;
3522 		case NIX_FLOW_KEY_TYPE_AH:
3523 		case NIX_FLOW_KEY_TYPE_ESP:
3524 			field->hdr_offset = 0;
3525 			field->bytesm1 = 7; /* SPI + sequence number */
3526 			field->ltype_mask = 0xF;
3527 			field->lid = NPC_LID_LE;
3528 			field->ltype_match = NPC_LT_LE_ESP;
3529 			if (key_type == NIX_FLOW_KEY_TYPE_AH) {
3530 				field->lid = NPC_LID_LD;
3531 				field->ltype_match = NPC_LT_LD_AH;
3532 				field->hdr_offset = 4;
3533 				keyoff_marker = false;
3534 			}
3535 			break;
3536 		}
3537 		field->ena = 1;
3538 
3539 		/* Found a valid flow key type */
3540 		if (valid_key) {
3541 			/* Use the key offset of TCP/UDP/SCTP fields
3542 			 * for ESP/AH fields.
3543 			 */
3544 			if (key_type == NIX_FLOW_KEY_TYPE_ESP ||
3545 			    key_type == NIX_FLOW_KEY_TYPE_AH)
3546 				key_off = l4_key_offset;
3547 			field->key_offset = key_off;
3548 			memcpy(&alg[nr_field], field, sizeof(*field));
3549 			max_key_off = max(max_key_off, field->bytesm1 + 1);
3550 
3551 			/* Found a field marker, get the next field */
3552 			if (field_marker)
3553 				nr_field++;
3554 		}
3555 
3556 		/* Found a keyoff marker, update the new key_off */
3557 		if (keyoff_marker) {
3558 			key_off += max_key_off;
3559 			max_key_off = 0;
3560 		}
3561 	}
3562 	/* Processed all the flow key types */
3563 	if (idx == max_bit_pos && key_off <= MAX_KEY_OFF)
3564 		return 0;
3565 	else
3566 		return NIX_AF_ERR_RSS_NOSPC_FIELD;
3567 }
3568 
3569 static int reserve_flowkey_alg_idx(struct rvu *rvu, int blkaddr, u32 flow_cfg)
3570 {
3571 	u64 field[FIELDS_PER_ALG];
3572 	struct nix_hw *hw;
3573 	int fid, rc;
3574 
3575 	hw = get_nix_hw(rvu->hw, blkaddr);
3576 	if (!hw)
3577 		return NIX_AF_ERR_INVALID_NIXBLK;
3578 
3579 	/* No room to add new flow hash algoritham */
3580 	if (hw->flowkey.in_use >= NIX_FLOW_KEY_ALG_MAX)
3581 		return NIX_AF_ERR_RSS_NOSPC_ALGO;
3582 
3583 	/* Generate algo fields for the given flow_cfg */
3584 	rc = set_flowkey_fields((struct nix_rx_flowkey_alg *)field, flow_cfg);
3585 	if (rc)
3586 		return rc;
3587 
3588 	/* Update ALGX_FIELDX register with generated fields */
3589 	for (fid = 0; fid < FIELDS_PER_ALG; fid++)
3590 		rvu_write64(rvu, blkaddr,
3591 			    NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(hw->flowkey.in_use,
3592 							   fid), field[fid]);
3593 
3594 	/* Store the flow_cfg for futher lookup */
3595 	rc = hw->flowkey.in_use;
3596 	hw->flowkey.flowkey[rc] = flow_cfg;
3597 	hw->flowkey.in_use++;
3598 
3599 	return rc;
3600 }
3601 
3602 int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu,
3603 					 struct nix_rss_flowkey_cfg *req,
3604 					 struct nix_rss_flowkey_cfg_rsp *rsp)
3605 {
3606 	u16 pcifunc = req->hdr.pcifunc;
3607 	int alg_idx, nixlf, blkaddr;
3608 	struct nix_hw *nix_hw;
3609 	int err;
3610 
3611 	err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
3612 	if (err)
3613 		return err;
3614 
3615 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
3616 	if (!nix_hw)
3617 		return NIX_AF_ERR_INVALID_NIXBLK;
3618 
3619 	alg_idx = get_flowkey_alg_idx(nix_hw, req->flowkey_cfg);
3620 	/* Failed to get algo index from the exiting list, reserve new  */
3621 	if (alg_idx < 0) {
3622 		alg_idx = reserve_flowkey_alg_idx(rvu, blkaddr,
3623 						  req->flowkey_cfg);
3624 		if (alg_idx < 0)
3625 			return alg_idx;
3626 	}
3627 	rsp->alg_idx = alg_idx;
3628 	rvu_npc_update_flowkey_alg_idx(rvu, pcifunc, nixlf, req->group,
3629 				       alg_idx, req->mcam_index);
3630 	return 0;
3631 }
3632 
3633 static int nix_rx_flowkey_alg_cfg(struct rvu *rvu, int blkaddr)
3634 {
3635 	u32 flowkey_cfg, minkey_cfg;
3636 	int alg, fid, rc;
3637 
3638 	/* Disable all flow key algx fieldx */
3639 	for (alg = 0; alg < NIX_FLOW_KEY_ALG_MAX; alg++) {
3640 		for (fid = 0; fid < FIELDS_PER_ALG; fid++)
3641 			rvu_write64(rvu, blkaddr,
3642 				    NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(alg, fid),
3643 				    0);
3644 	}
3645 
3646 	/* IPv4/IPv6 SIP/DIPs */
3647 	flowkey_cfg = NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6;
3648 	rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg);
3649 	if (rc < 0)
3650 		return rc;
3651 
3652 	/* TCPv4/v6 4-tuple, SIP, DIP, Sport, Dport */
3653 	minkey_cfg = flowkey_cfg;
3654 	flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP;
3655 	rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg);
3656 	if (rc < 0)
3657 		return rc;
3658 
3659 	/* UDPv4/v6 4-tuple, SIP, DIP, Sport, Dport */
3660 	flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_UDP;
3661 	rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg);
3662 	if (rc < 0)
3663 		return rc;
3664 
3665 	/* SCTPv4/v6 4-tuple, SIP, DIP, Sport, Dport */
3666 	flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_SCTP;
3667 	rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg);
3668 	if (rc < 0)
3669 		return rc;
3670 
3671 	/* TCP/UDP v4/v6 4-tuple, rest IP pkts 2-tuple */
3672 	flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP |
3673 			NIX_FLOW_KEY_TYPE_UDP;
3674 	rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg);
3675 	if (rc < 0)
3676 		return rc;
3677 
3678 	/* TCP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */
3679 	flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP |
3680 			NIX_FLOW_KEY_TYPE_SCTP;
3681 	rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg);
3682 	if (rc < 0)
3683 		return rc;
3684 
3685 	/* UDP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */
3686 	flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_UDP |
3687 			NIX_FLOW_KEY_TYPE_SCTP;
3688 	rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg);
3689 	if (rc < 0)
3690 		return rc;
3691 
3692 	/* TCP/UDP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */
3693 	flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP |
3694 		      NIX_FLOW_KEY_TYPE_UDP | NIX_FLOW_KEY_TYPE_SCTP;
3695 	rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg);
3696 	if (rc < 0)
3697 		return rc;
3698 
3699 	return 0;
3700 }
3701 
3702 int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu,
3703 				      struct nix_set_mac_addr *req,
3704 				      struct msg_rsp *rsp)
3705 {
3706 	bool from_vf = req->hdr.pcifunc & RVU_PFVF_FUNC_MASK;
3707 	u16 pcifunc = req->hdr.pcifunc;
3708 	int blkaddr, nixlf, err;
3709 	struct rvu_pfvf *pfvf;
3710 
3711 	err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr);
3712 	if (err)
3713 		return err;
3714 
3715 	pfvf = rvu_get_pfvf(rvu, pcifunc);
3716 
3717 	/* untrusted VF can't overwrite admin(PF) changes */
3718 	if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) &&
3719 	    (from_vf && test_bit(PF_SET_VF_MAC, &pfvf->flags))) {
3720 		dev_warn(rvu->dev,
3721 			 "MAC address set by admin(PF) cannot be overwritten by untrusted VF");
3722 		return -EPERM;
3723 	}
3724 
3725 	ether_addr_copy(pfvf->mac_addr, req->mac_addr);
3726 
3727 	rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf,
3728 				    pfvf->rx_chan_base, req->mac_addr);
3729 
3730 	if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && from_vf)
3731 		ether_addr_copy(pfvf->default_mac, req->mac_addr);
3732 
3733 	rvu_switch_update_rules(rvu, pcifunc);
3734 
3735 	return 0;
3736 }
3737 
3738 int rvu_mbox_handler_nix_get_mac_addr(struct rvu *rvu,
3739 				      struct msg_req *req,
3740 				      struct nix_get_mac_addr_rsp *rsp)
3741 {
3742 	u16 pcifunc = req->hdr.pcifunc;
3743 	struct rvu_pfvf *pfvf;
3744 
3745 	if (!is_nixlf_attached(rvu, pcifunc))
3746 		return NIX_AF_ERR_AF_LF_INVALID;
3747 
3748 	pfvf = rvu_get_pfvf(rvu, pcifunc);
3749 
3750 	ether_addr_copy(rsp->mac_addr, pfvf->mac_addr);
3751 
3752 	return 0;
3753 }
3754 
3755 int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req,
3756 				     struct msg_rsp *rsp)
3757 {
3758 	bool allmulti, promisc, nix_rx_multicast;
3759 	u16 pcifunc = req->hdr.pcifunc;
3760 	struct rvu_pfvf *pfvf;
3761 	int nixlf, err;
3762 
3763 	pfvf = rvu_get_pfvf(rvu, pcifunc);
3764 	promisc = req->mode & NIX_RX_MODE_PROMISC ? true : false;
3765 	allmulti = req->mode & NIX_RX_MODE_ALLMULTI ? true : false;
3766 	pfvf->use_mce_list = req->mode & NIX_RX_MODE_USE_MCE ? true : false;
3767 
3768 	nix_rx_multicast = rvu->hw->cap.nix_rx_multicast & pfvf->use_mce_list;
3769 
3770 	if (is_vf(pcifunc) && !nix_rx_multicast &&
3771 	    (promisc || allmulti)) {
3772 		dev_warn_ratelimited(rvu->dev,
3773 				     "VF promisc/multicast not supported\n");
3774 		return 0;
3775 	}
3776 
3777 	/* untrusted VF can't configure promisc/allmulti */
3778 	if (is_vf(pcifunc) && !test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) &&
3779 	    (promisc || allmulti))
3780 		return 0;
3781 
3782 	err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL);
3783 	if (err)
3784 		return err;
3785 
3786 	if (nix_rx_multicast) {
3787 		/* add/del this PF_FUNC to/from mcast pkt replication list */
3788 		err = nix_update_mce_rule(rvu, pcifunc, NIXLF_ALLMULTI_ENTRY,
3789 					  allmulti);
3790 		if (err) {
3791 			dev_err(rvu->dev,
3792 				"Failed to update pcifunc 0x%x to multicast list\n",
3793 				pcifunc);
3794 			return err;
3795 		}
3796 
3797 		/* add/del this PF_FUNC to/from promisc pkt replication list */
3798 		err = nix_update_mce_rule(rvu, pcifunc, NIXLF_PROMISC_ENTRY,
3799 					  promisc);
3800 		if (err) {
3801 			dev_err(rvu->dev,
3802 				"Failed to update pcifunc 0x%x to promisc list\n",
3803 				pcifunc);
3804 			return err;
3805 		}
3806 	}
3807 
3808 	/* install/uninstall allmulti entry */
3809 	if (allmulti) {
3810 		rvu_npc_install_allmulti_entry(rvu, pcifunc, nixlf,
3811 					       pfvf->rx_chan_base);
3812 	} else {
3813 		if (!nix_rx_multicast)
3814 			rvu_npc_enable_allmulti_entry(rvu, pcifunc, nixlf, false);
3815 	}
3816 
3817 	/* install/uninstall promisc entry */
3818 	if (promisc) {
3819 		rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf,
3820 					      pfvf->rx_chan_base,
3821 					      pfvf->rx_chan_cnt);
3822 
3823 		if (rvu_npc_exact_has_match_table(rvu))
3824 			rvu_npc_exact_promisc_enable(rvu, pcifunc);
3825 	} else {
3826 		if (!nix_rx_multicast)
3827 			rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf, false);
3828 
3829 		if (rvu_npc_exact_has_match_table(rvu))
3830 			rvu_npc_exact_promisc_disable(rvu, pcifunc);
3831 	}
3832 
3833 	return 0;
3834 }
3835 
3836 static void nix_find_link_frs(struct rvu *rvu,
3837 			      struct nix_frs_cfg *req, u16 pcifunc)
3838 {
3839 	int pf = rvu_get_pf(pcifunc);
3840 	struct rvu_pfvf *pfvf;
3841 	int maxlen, minlen;
3842 	int numvfs, hwvf;
3843 	int vf;
3844 
3845 	/* Update with requester's min/max lengths */
3846 	pfvf = rvu_get_pfvf(rvu, pcifunc);
3847 	pfvf->maxlen = req->maxlen;
3848 	if (req->update_minlen)
3849 		pfvf->minlen = req->minlen;
3850 
3851 	maxlen = req->maxlen;
3852 	minlen = req->update_minlen ? req->minlen : 0;
3853 
3854 	/* Get this PF's numVFs and starting hwvf */
3855 	rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
3856 
3857 	/* For each VF, compare requested max/minlen */
3858 	for (vf = 0; vf < numvfs; vf++) {
3859 		pfvf =  &rvu->hwvf[hwvf + vf];
3860 		if (pfvf->maxlen > maxlen)
3861 			maxlen = pfvf->maxlen;
3862 		if (req->update_minlen &&
3863 		    pfvf->minlen && pfvf->minlen < minlen)
3864 			minlen = pfvf->minlen;
3865 	}
3866 
3867 	/* Compare requested max/minlen with PF's max/minlen */
3868 	pfvf = &rvu->pf[pf];
3869 	if (pfvf->maxlen > maxlen)
3870 		maxlen = pfvf->maxlen;
3871 	if (req->update_minlen &&
3872 	    pfvf->minlen && pfvf->minlen < minlen)
3873 		minlen = pfvf->minlen;
3874 
3875 	/* Update the request with max/min PF's and it's VF's max/min */
3876 	req->maxlen = maxlen;
3877 	if (req->update_minlen)
3878 		req->minlen = minlen;
3879 }
3880 
3881 static int
3882 nix_config_link_credits(struct rvu *rvu, int blkaddr, int link,
3883 			u16 pcifunc, u64 tx_credits)
3884 {
3885 	struct rvu_hwinfo *hw = rvu->hw;
3886 	int pf = rvu_get_pf(pcifunc);
3887 	u8 cgx_id = 0, lmac_id = 0;
3888 	unsigned long poll_tmo;
3889 	bool restore_tx_en = 0;
3890 	struct nix_hw *nix_hw;
3891 	u64 cfg, sw_xoff = 0;
3892 	u32 schq = 0;
3893 	u32 credits;
3894 	int rc;
3895 
3896 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
3897 	if (!nix_hw)
3898 		return NIX_AF_ERR_INVALID_NIXBLK;
3899 
3900 	if (tx_credits == nix_hw->tx_credits[link])
3901 		return 0;
3902 
3903 	/* Enable cgx tx if disabled for credits to be back */
3904 	if (is_pf_cgxmapped(rvu, pf)) {
3905 		rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
3906 		restore_tx_en = !rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu),
3907 						    lmac_id, true);
3908 	}
3909 
3910 	mutex_lock(&rvu->rsrc_lock);
3911 	/* Disable new traffic to link */
3912 	if (hw->cap.nix_shaping) {
3913 		schq = nix_get_tx_link(rvu, pcifunc);
3914 		sw_xoff = rvu_read64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq));
3915 		rvu_write64(rvu, blkaddr,
3916 			    NIX_AF_TL1X_SW_XOFF(schq), BIT_ULL(0));
3917 	}
3918 
3919 	rc = NIX_AF_ERR_LINK_CREDITS;
3920 	poll_tmo = jiffies + usecs_to_jiffies(200000);
3921 	/* Wait for credits to return */
3922 	do {
3923 		if (time_after(jiffies, poll_tmo))
3924 			goto exit;
3925 		usleep_range(100, 200);
3926 
3927 		cfg = rvu_read64(rvu, blkaddr,
3928 				 NIX_AF_TX_LINKX_NORM_CREDIT(link));
3929 		credits = (cfg >> 12) & 0xFFFFFULL;
3930 	} while (credits != nix_hw->tx_credits[link]);
3931 
3932 	cfg &= ~(0xFFFFFULL << 12);
3933 	cfg |= (tx_credits << 12);
3934 	rvu_write64(rvu, blkaddr, NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg);
3935 	rc = 0;
3936 
3937 	nix_hw->tx_credits[link] = tx_credits;
3938 
3939 exit:
3940 	/* Enable traffic back */
3941 	if (hw->cap.nix_shaping && !sw_xoff)
3942 		rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq), 0);
3943 
3944 	/* Restore state of cgx tx */
3945 	if (restore_tx_en)
3946 		rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false);
3947 
3948 	mutex_unlock(&rvu->rsrc_lock);
3949 	return rc;
3950 }
3951 
3952 int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req,
3953 				    struct msg_rsp *rsp)
3954 {
3955 	struct rvu_hwinfo *hw = rvu->hw;
3956 	u16 pcifunc = req->hdr.pcifunc;
3957 	int pf = rvu_get_pf(pcifunc);
3958 	int blkaddr, schq, link = -1;
3959 	struct nix_txsch *txsch;
3960 	u64 cfg, lmac_fifo_len;
3961 	struct nix_hw *nix_hw;
3962 	struct rvu_pfvf *pfvf;
3963 	u8 cgx = 0, lmac = 0;
3964 	u16 max_mtu;
3965 
3966 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
3967 	if (blkaddr < 0)
3968 		return NIX_AF_ERR_AF_LF_INVALID;
3969 
3970 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
3971 	if (!nix_hw)
3972 		return NIX_AF_ERR_INVALID_NIXBLK;
3973 
3974 	if (is_afvf(pcifunc))
3975 		rvu_get_lbk_link_max_frs(rvu, &max_mtu);
3976 	else
3977 		rvu_get_lmac_link_max_frs(rvu, &max_mtu);
3978 
3979 	if (!req->sdp_link && req->maxlen > max_mtu)
3980 		return NIX_AF_ERR_FRS_INVALID;
3981 
3982 	if (req->update_minlen && req->minlen < NIC_HW_MIN_FRS)
3983 		return NIX_AF_ERR_FRS_INVALID;
3984 
3985 	/* Check if requester wants to update SMQ's */
3986 	if (!req->update_smq)
3987 		goto rx_frscfg;
3988 
3989 	/* Update min/maxlen in each of the SMQ attached to this PF/VF */
3990 	txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
3991 	mutex_lock(&rvu->rsrc_lock);
3992 	for (schq = 0; schq < txsch->schq.max; schq++) {
3993 		if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc)
3994 			continue;
3995 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq));
3996 		cfg = (cfg & ~(0xFFFFULL << 8)) | ((u64)req->maxlen << 8);
3997 		if (req->update_minlen)
3998 			cfg = (cfg & ~0x7FULL) | ((u64)req->minlen & 0x7F);
3999 		rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq), cfg);
4000 	}
4001 	mutex_unlock(&rvu->rsrc_lock);
4002 
4003 rx_frscfg:
4004 	/* Check if config is for SDP link */
4005 	if (req->sdp_link) {
4006 		if (!hw->sdp_links)
4007 			return NIX_AF_ERR_RX_LINK_INVALID;
4008 		link = hw->cgx_links + hw->lbk_links;
4009 		goto linkcfg;
4010 	}
4011 
4012 	/* Check if the request is from CGX mapped RVU PF */
4013 	if (is_pf_cgxmapped(rvu, pf)) {
4014 		/* Get CGX and LMAC to which this PF is mapped and find link */
4015 		rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac);
4016 		link = (cgx * hw->lmac_per_cgx) + lmac;
4017 	} else if (pf == 0) {
4018 		/* For VFs of PF0 ingress is LBK port, so config LBK link */
4019 		pfvf = rvu_get_pfvf(rvu, pcifunc);
4020 		link = hw->cgx_links + pfvf->lbkid;
4021 	}
4022 
4023 	if (link < 0)
4024 		return NIX_AF_ERR_RX_LINK_INVALID;
4025 
4026 	nix_find_link_frs(rvu, req, pcifunc);
4027 
4028 linkcfg:
4029 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link));
4030 	cfg = (cfg & ~(0xFFFFULL << 16)) | ((u64)req->maxlen << 16);
4031 	if (req->update_minlen)
4032 		cfg = (cfg & ~0xFFFFULL) | req->minlen;
4033 	rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), cfg);
4034 
4035 	if (req->sdp_link || pf == 0)
4036 		return 0;
4037 
4038 	/* Update transmit credits for CGX links */
4039 	lmac_fifo_len = rvu_cgx_get_lmac_fifolen(rvu, cgx, lmac);
4040 	if (!lmac_fifo_len) {
4041 		dev_err(rvu->dev,
4042 			"%s: Failed to get CGX/RPM%d:LMAC%d FIFO size\n",
4043 			__func__, cgx, lmac);
4044 		return 0;
4045 	}
4046 	return nix_config_link_credits(rvu, blkaddr, link, pcifunc,
4047 				       (lmac_fifo_len - req->maxlen) / 16);
4048 }
4049 
4050 int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req,
4051 				    struct msg_rsp *rsp)
4052 {
4053 	int nixlf, blkaddr, err;
4054 	u64 cfg;
4055 
4056 	err = nix_get_nixlf(rvu, req->hdr.pcifunc, &nixlf, &blkaddr);
4057 	if (err)
4058 		return err;
4059 
4060 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf));
4061 	/* Set the interface configuration */
4062 	if (req->len_verify & BIT(0))
4063 		cfg |= BIT_ULL(41);
4064 	else
4065 		cfg &= ~BIT_ULL(41);
4066 
4067 	if (req->len_verify & BIT(1))
4068 		cfg |= BIT_ULL(40);
4069 	else
4070 		cfg &= ~BIT_ULL(40);
4071 
4072 	if (req->csum_verify & BIT(0))
4073 		cfg |= BIT_ULL(37);
4074 	else
4075 		cfg &= ~BIT_ULL(37);
4076 
4077 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), cfg);
4078 
4079 	return 0;
4080 }
4081 
4082 static u64 rvu_get_lbk_link_credits(struct rvu *rvu, u16 lbk_max_frs)
4083 {
4084 	return 1600; /* 16 * max LBK datarate = 16 * 100Gbps */
4085 }
4086 
4087 static void nix_link_config(struct rvu *rvu, int blkaddr,
4088 			    struct nix_hw *nix_hw)
4089 {
4090 	struct rvu_hwinfo *hw = rvu->hw;
4091 	int cgx, lmac_cnt, slink, link;
4092 	u16 lbk_max_frs, lmac_max_frs;
4093 	unsigned long lmac_bmap;
4094 	u64 tx_credits, cfg;
4095 	u64 lmac_fifo_len;
4096 	int iter;
4097 
4098 	rvu_get_lbk_link_max_frs(rvu, &lbk_max_frs);
4099 	rvu_get_lmac_link_max_frs(rvu, &lmac_max_frs);
4100 
4101 	/* Set default min/max packet lengths allowed on NIX Rx links.
4102 	 *
4103 	 * With HW reset minlen value of 60byte, HW will treat ARP pkts
4104 	 * as undersize and report them to SW as error pkts, hence
4105 	 * setting it to 40 bytes.
4106 	 */
4107 	for (link = 0; link < hw->cgx_links; link++) {
4108 		rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link),
4109 				((u64)lmac_max_frs << 16) | NIC_HW_MIN_FRS);
4110 	}
4111 
4112 	for (link = hw->cgx_links; link < hw->lbk_links; link++) {
4113 		rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link),
4114 			    ((u64)lbk_max_frs << 16) | NIC_HW_MIN_FRS);
4115 	}
4116 	if (hw->sdp_links) {
4117 		link = hw->cgx_links + hw->lbk_links;
4118 		rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link),
4119 			    SDP_HW_MAX_FRS << 16 | NIC_HW_MIN_FRS);
4120 	}
4121 
4122 	/* Set credits for Tx links assuming max packet length allowed.
4123 	 * This will be reconfigured based on MTU set for PF/VF.
4124 	 */
4125 	for (cgx = 0; cgx < hw->cgx; cgx++) {
4126 		lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu));
4127 		/* Skip when cgx is not available or lmac cnt is zero */
4128 		if (lmac_cnt <= 0)
4129 			continue;
4130 		slink = cgx * hw->lmac_per_cgx;
4131 
4132 		/* Get LMAC id's from bitmap */
4133 		lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu));
4134 		for_each_set_bit(iter, &lmac_bmap, rvu->hw->lmac_per_cgx) {
4135 			lmac_fifo_len = rvu_cgx_get_lmac_fifolen(rvu, cgx, iter);
4136 			if (!lmac_fifo_len) {
4137 				dev_err(rvu->dev,
4138 					"%s: Failed to get CGX/RPM%d:LMAC%d FIFO size\n",
4139 					__func__, cgx, iter);
4140 				continue;
4141 			}
4142 			tx_credits = (lmac_fifo_len - lmac_max_frs) / 16;
4143 			/* Enable credits and set credit pkt count to max allowed */
4144 			cfg =  (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1);
4145 
4146 			link = iter + slink;
4147 			nix_hw->tx_credits[link] = tx_credits;
4148 			rvu_write64(rvu, blkaddr,
4149 				    NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg);
4150 		}
4151 	}
4152 
4153 	/* Set Tx credits for LBK link */
4154 	slink = hw->cgx_links;
4155 	for (link = slink; link < (slink + hw->lbk_links); link++) {
4156 		tx_credits = rvu_get_lbk_link_credits(rvu, lbk_max_frs);
4157 		nix_hw->tx_credits[link] = tx_credits;
4158 		/* Enable credits and set credit pkt count to max allowed */
4159 		tx_credits =  (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1);
4160 		rvu_write64(rvu, blkaddr,
4161 			    NIX_AF_TX_LINKX_NORM_CREDIT(link), tx_credits);
4162 	}
4163 }
4164 
4165 static int nix_calibrate_x2p(struct rvu *rvu, int blkaddr)
4166 {
4167 	int idx, err;
4168 	u64 status;
4169 
4170 	/* Start X2P bus calibration */
4171 	rvu_write64(rvu, blkaddr, NIX_AF_CFG,
4172 		    rvu_read64(rvu, blkaddr, NIX_AF_CFG) | BIT_ULL(9));
4173 	/* Wait for calibration to complete */
4174 	err = rvu_poll_reg(rvu, blkaddr,
4175 			   NIX_AF_STATUS, BIT_ULL(10), false);
4176 	if (err) {
4177 		dev_err(rvu->dev, "NIX X2P bus calibration failed\n");
4178 		return err;
4179 	}
4180 
4181 	status = rvu_read64(rvu, blkaddr, NIX_AF_STATUS);
4182 	/* Check if CGX devices are ready */
4183 	for (idx = 0; idx < rvu->cgx_cnt_max; idx++) {
4184 		/* Skip when cgx port is not available */
4185 		if (!rvu_cgx_pdata(idx, rvu) ||
4186 		    (status & (BIT_ULL(16 + idx))))
4187 			continue;
4188 		dev_err(rvu->dev,
4189 			"CGX%d didn't respond to NIX X2P calibration\n", idx);
4190 		err = -EBUSY;
4191 	}
4192 
4193 	/* Check if LBK is ready */
4194 	if (!(status & BIT_ULL(19))) {
4195 		dev_err(rvu->dev,
4196 			"LBK didn't respond to NIX X2P calibration\n");
4197 		err = -EBUSY;
4198 	}
4199 
4200 	/* Clear 'calibrate_x2p' bit */
4201 	rvu_write64(rvu, blkaddr, NIX_AF_CFG,
4202 		    rvu_read64(rvu, blkaddr, NIX_AF_CFG) & ~BIT_ULL(9));
4203 	if (err || (status & 0x3FFULL))
4204 		dev_err(rvu->dev,
4205 			"NIX X2P calibration failed, status 0x%llx\n", status);
4206 	if (err)
4207 		return err;
4208 	return 0;
4209 }
4210 
4211 static int nix_aq_init(struct rvu *rvu, struct rvu_block *block)
4212 {
4213 	u64 cfg;
4214 	int err;
4215 
4216 	/* Set admin queue endianness */
4217 	cfg = rvu_read64(rvu, block->addr, NIX_AF_CFG);
4218 #ifdef __BIG_ENDIAN
4219 	cfg |= BIT_ULL(8);
4220 	rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg);
4221 #else
4222 	cfg &= ~BIT_ULL(8);
4223 	rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg);
4224 #endif
4225 
4226 	/* Do not bypass NDC cache */
4227 	cfg = rvu_read64(rvu, block->addr, NIX_AF_NDC_CFG);
4228 	cfg &= ~0x3FFEULL;
4229 #ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING
4230 	/* Disable caching of SQB aka SQEs */
4231 	cfg |= 0x04ULL;
4232 #endif
4233 	rvu_write64(rvu, block->addr, NIX_AF_NDC_CFG, cfg);
4234 
4235 	/* Result structure can be followed by RQ/SQ/CQ context at
4236 	 * RES + 128bytes and a write mask at RES + 256 bytes, depending on
4237 	 * operation type. Alloc sufficient result memory for all operations.
4238 	 */
4239 	err = rvu_aq_alloc(rvu, &block->aq,
4240 			   Q_COUNT(AQ_SIZE), sizeof(struct nix_aq_inst_s),
4241 			   ALIGN(sizeof(struct nix_aq_res_s), 128) + 256);
4242 	if (err)
4243 		return err;
4244 
4245 	rvu_write64(rvu, block->addr, NIX_AF_AQ_CFG, AQ_SIZE);
4246 	rvu_write64(rvu, block->addr,
4247 		    NIX_AF_AQ_BASE, (u64)block->aq->inst->iova);
4248 	return 0;
4249 }
4250 
4251 static void rvu_nix_setup_capabilities(struct rvu *rvu, int blkaddr)
4252 {
4253 	struct rvu_hwinfo *hw = rvu->hw;
4254 	u64 hw_const;
4255 
4256 	hw_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
4257 
4258 	/* On OcteonTx2 DWRR quantum is directly configured into each of
4259 	 * the transmit scheduler queues. And PF/VF drivers were free to
4260 	 * config any value upto 2^24.
4261 	 * On CN10K, HW is modified, the quantum configuration at scheduler
4262 	 * queues is in terms of weight. And SW needs to setup a base DWRR MTU
4263 	 * at NIX_AF_DWRR_RPM_MTU / NIX_AF_DWRR_SDP_MTU. HW will do
4264 	 * 'DWRR MTU * weight' to get the quantum.
4265 	 *
4266 	 * Check if HW uses a common MTU for all DWRR quantum configs.
4267 	 * On OcteonTx2 this register field is '0'.
4268 	 */
4269 	if (((hw_const >> 56) & 0x10) == 0x10)
4270 		hw->cap.nix_common_dwrr_mtu = true;
4271 }
4272 
4273 static int rvu_nix_block_init(struct rvu *rvu, struct nix_hw *nix_hw)
4274 {
4275 	const struct npc_lt_def_cfg *ltdefs;
4276 	struct rvu_hwinfo *hw = rvu->hw;
4277 	int blkaddr = nix_hw->blkaddr;
4278 	struct rvu_block *block;
4279 	int err;
4280 	u64 cfg;
4281 
4282 	block = &hw->block[blkaddr];
4283 
4284 	if (is_rvu_96xx_B0(rvu)) {
4285 		/* As per a HW errata in 96xx A0/B0 silicon, NIX may corrupt
4286 		 * internal state when conditional clocks are turned off.
4287 		 * Hence enable them.
4288 		 */
4289 		rvu_write64(rvu, blkaddr, NIX_AF_CFG,
4290 			    rvu_read64(rvu, blkaddr, NIX_AF_CFG) | 0x40ULL);
4291 
4292 		/* Set chan/link to backpressure TL3 instead of TL2 */
4293 		rvu_write64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL, 0x01);
4294 
4295 		/* Disable SQ manager's sticky mode operation (set TM6 = 0)
4296 		 * This sticky mode is known to cause SQ stalls when multiple
4297 		 * SQs are mapped to same SMQ and transmitting pkts at a time.
4298 		 */
4299 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS);
4300 		cfg &= ~BIT_ULL(15);
4301 		rvu_write64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS, cfg);
4302 	}
4303 
4304 	ltdefs = rvu->kpu.lt_def;
4305 	/* Calibrate X2P bus to check if CGX/LBK links are fine */
4306 	err = nix_calibrate_x2p(rvu, blkaddr);
4307 	if (err)
4308 		return err;
4309 
4310 	/* Setup capabilities of the NIX block */
4311 	rvu_nix_setup_capabilities(rvu, blkaddr);
4312 
4313 	/* Initialize admin queue */
4314 	err = nix_aq_init(rvu, block);
4315 	if (err)
4316 		return err;
4317 
4318 	/* Restore CINT timer delay to HW reset values */
4319 	rvu_write64(rvu, blkaddr, NIX_AF_CINT_DELAY, 0x0ULL);
4320 
4321 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_SEB_CFG);
4322 
4323 	/* For better performance use NDC TX instead of NDC RX for SQ's SQEs" */
4324 	cfg |= 1ULL;
4325 	if (!is_rvu_otx2(rvu))
4326 		cfg |= NIX_PTP_1STEP_EN;
4327 
4328 	rvu_write64(rvu, blkaddr, NIX_AF_SEB_CFG, cfg);
4329 
4330 	if (!is_rvu_otx2(rvu))
4331 		rvu_nix_block_cn10k_init(rvu, nix_hw);
4332 
4333 	if (is_block_implemented(hw, blkaddr)) {
4334 		err = nix_setup_txschq(rvu, nix_hw, blkaddr);
4335 		if (err)
4336 			return err;
4337 
4338 		err = nix_setup_ipolicers(rvu, nix_hw, blkaddr);
4339 		if (err)
4340 			return err;
4341 
4342 		err = nix_af_mark_format_setup(rvu, nix_hw, blkaddr);
4343 		if (err)
4344 			return err;
4345 
4346 		err = nix_setup_mcast(rvu, nix_hw, blkaddr);
4347 		if (err)
4348 			return err;
4349 
4350 		err = nix_setup_txvlan(rvu, nix_hw);
4351 		if (err)
4352 			return err;
4353 
4354 		/* Configure segmentation offload formats */
4355 		nix_setup_lso(rvu, nix_hw, blkaddr);
4356 
4357 		/* Config Outer/Inner L2, IP, TCP, UDP and SCTP NPC layer info.
4358 		 * This helps HW protocol checker to identify headers
4359 		 * and validate length and checksums.
4360 		 */
4361 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OL2,
4362 			    (ltdefs->rx_ol2.lid << 8) | (ltdefs->rx_ol2.ltype_match << 4) |
4363 			    ltdefs->rx_ol2.ltype_mask);
4364 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4,
4365 			    (ltdefs->rx_oip4.lid << 8) | (ltdefs->rx_oip4.ltype_match << 4) |
4366 			    ltdefs->rx_oip4.ltype_mask);
4367 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4,
4368 			    (ltdefs->rx_iip4.lid << 8) | (ltdefs->rx_iip4.ltype_match << 4) |
4369 			    ltdefs->rx_iip4.ltype_mask);
4370 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6,
4371 			    (ltdefs->rx_oip6.lid << 8) | (ltdefs->rx_oip6.ltype_match << 4) |
4372 			    ltdefs->rx_oip6.ltype_mask);
4373 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6,
4374 			    (ltdefs->rx_iip6.lid << 8) | (ltdefs->rx_iip6.ltype_match << 4) |
4375 			    ltdefs->rx_iip6.ltype_mask);
4376 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OTCP,
4377 			    (ltdefs->rx_otcp.lid << 8) | (ltdefs->rx_otcp.ltype_match << 4) |
4378 			    ltdefs->rx_otcp.ltype_mask);
4379 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ITCP,
4380 			    (ltdefs->rx_itcp.lid << 8) | (ltdefs->rx_itcp.ltype_match << 4) |
4381 			    ltdefs->rx_itcp.ltype_mask);
4382 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OUDP,
4383 			    (ltdefs->rx_oudp.lid << 8) | (ltdefs->rx_oudp.ltype_match << 4) |
4384 			    ltdefs->rx_oudp.ltype_mask);
4385 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IUDP,
4386 			    (ltdefs->rx_iudp.lid << 8) | (ltdefs->rx_iudp.ltype_match << 4) |
4387 			    ltdefs->rx_iudp.ltype_mask);
4388 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OSCTP,
4389 			    (ltdefs->rx_osctp.lid << 8) | (ltdefs->rx_osctp.ltype_match << 4) |
4390 			    ltdefs->rx_osctp.ltype_mask);
4391 		rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ISCTP,
4392 			    (ltdefs->rx_isctp.lid << 8) | (ltdefs->rx_isctp.ltype_match << 4) |
4393 			    ltdefs->rx_isctp.ltype_mask);
4394 
4395 		if (!is_rvu_otx2(rvu)) {
4396 			/* Enable APAD calculation for other protocols
4397 			 * matching APAD0 and APAD1 lt def registers.
4398 			 */
4399 			rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_CST_APAD0,
4400 				    (ltdefs->rx_apad0.valid << 11) |
4401 				    (ltdefs->rx_apad0.lid << 8) |
4402 				    (ltdefs->rx_apad0.ltype_match << 4) |
4403 				    ltdefs->rx_apad0.ltype_mask);
4404 			rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_CST_APAD1,
4405 				    (ltdefs->rx_apad1.valid << 11) |
4406 				    (ltdefs->rx_apad1.lid << 8) |
4407 				    (ltdefs->rx_apad1.ltype_match << 4) |
4408 				    ltdefs->rx_apad1.ltype_mask);
4409 
4410 			/* Receive ethertype defination register defines layer
4411 			 * information in NPC_RESULT_S to identify the Ethertype
4412 			 * location in L2 header. Used for Ethertype overwriting
4413 			 * in inline IPsec flow.
4414 			 */
4415 			rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ET(0),
4416 				    (ltdefs->rx_et[0].offset << 12) |
4417 				    (ltdefs->rx_et[0].valid << 11) |
4418 				    (ltdefs->rx_et[0].lid << 8) |
4419 				    (ltdefs->rx_et[0].ltype_match << 4) |
4420 				    ltdefs->rx_et[0].ltype_mask);
4421 			rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ET(1),
4422 				    (ltdefs->rx_et[1].offset << 12) |
4423 				    (ltdefs->rx_et[1].valid << 11) |
4424 				    (ltdefs->rx_et[1].lid << 8) |
4425 				    (ltdefs->rx_et[1].ltype_match << 4) |
4426 				    ltdefs->rx_et[1].ltype_mask);
4427 		}
4428 
4429 		err = nix_rx_flowkey_alg_cfg(rvu, blkaddr);
4430 		if (err)
4431 			return err;
4432 
4433 		nix_hw->tx_credits = kcalloc(hw->cgx_links + hw->lbk_links,
4434 					     sizeof(u64), GFP_KERNEL);
4435 		if (!nix_hw->tx_credits)
4436 			return -ENOMEM;
4437 
4438 		/* Initialize CGX/LBK/SDP link credits, min/max pkt lengths */
4439 		nix_link_config(rvu, blkaddr, nix_hw);
4440 
4441 		/* Enable Channel backpressure */
4442 		rvu_write64(rvu, blkaddr, NIX_AF_RX_CFG, BIT_ULL(0));
4443 	}
4444 	return 0;
4445 }
4446 
4447 int rvu_nix_init(struct rvu *rvu)
4448 {
4449 	struct rvu_hwinfo *hw = rvu->hw;
4450 	struct nix_hw *nix_hw;
4451 	int blkaddr = 0, err;
4452 	int i = 0;
4453 
4454 	hw->nix = devm_kcalloc(rvu->dev, MAX_NIX_BLKS, sizeof(struct nix_hw),
4455 			       GFP_KERNEL);
4456 	if (!hw->nix)
4457 		return -ENOMEM;
4458 
4459 	blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
4460 	while (blkaddr) {
4461 		nix_hw = &hw->nix[i];
4462 		nix_hw->rvu = rvu;
4463 		nix_hw->blkaddr = blkaddr;
4464 		err = rvu_nix_block_init(rvu, nix_hw);
4465 		if (err)
4466 			return err;
4467 		blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
4468 		i++;
4469 	}
4470 
4471 	return 0;
4472 }
4473 
4474 static void rvu_nix_block_freemem(struct rvu *rvu, int blkaddr,
4475 				  struct rvu_block *block)
4476 {
4477 	struct nix_txsch *txsch;
4478 	struct nix_mcast *mcast;
4479 	struct nix_txvlan *vlan;
4480 	struct nix_hw *nix_hw;
4481 	int lvl;
4482 
4483 	rvu_aq_free(rvu, block->aq);
4484 
4485 	if (is_block_implemented(rvu->hw, blkaddr)) {
4486 		nix_hw = get_nix_hw(rvu->hw, blkaddr);
4487 		if (!nix_hw)
4488 			return;
4489 
4490 		for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
4491 			txsch = &nix_hw->txsch[lvl];
4492 			kfree(txsch->schq.bmap);
4493 		}
4494 
4495 		kfree(nix_hw->tx_credits);
4496 
4497 		nix_ipolicer_freemem(rvu, nix_hw);
4498 
4499 		vlan = &nix_hw->txvlan;
4500 		kfree(vlan->rsrc.bmap);
4501 		mutex_destroy(&vlan->rsrc_lock);
4502 
4503 		mcast = &nix_hw->mcast;
4504 		qmem_free(rvu->dev, mcast->mce_ctx);
4505 		qmem_free(rvu->dev, mcast->mcast_buf);
4506 		mutex_destroy(&mcast->mce_lock);
4507 	}
4508 }
4509 
4510 void rvu_nix_freemem(struct rvu *rvu)
4511 {
4512 	struct rvu_hwinfo *hw = rvu->hw;
4513 	struct rvu_block *block;
4514 	int blkaddr = 0;
4515 
4516 	blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
4517 	while (blkaddr) {
4518 		block = &hw->block[blkaddr];
4519 		rvu_nix_block_freemem(rvu, blkaddr, block);
4520 		blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
4521 	}
4522 }
4523 
4524 int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req,
4525 				     struct msg_rsp *rsp)
4526 {
4527 	u16 pcifunc = req->hdr.pcifunc;
4528 	struct rvu_pfvf *pfvf;
4529 	int nixlf, err;
4530 
4531 	err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL);
4532 	if (err)
4533 		return err;
4534 
4535 	rvu_npc_enable_default_entries(rvu, pcifunc, nixlf);
4536 
4537 	npc_mcam_enable_flows(rvu, pcifunc);
4538 
4539 	pfvf = rvu_get_pfvf(rvu, pcifunc);
4540 	set_bit(NIXLF_INITIALIZED, &pfvf->flags);
4541 
4542 	rvu_switch_update_rules(rvu, pcifunc);
4543 
4544 	return rvu_cgx_start_stop_io(rvu, pcifunc, true);
4545 }
4546 
4547 int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req,
4548 				    struct msg_rsp *rsp)
4549 {
4550 	u16 pcifunc = req->hdr.pcifunc;
4551 	struct rvu_pfvf *pfvf;
4552 	int nixlf, err;
4553 
4554 	err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL);
4555 	if (err)
4556 		return err;
4557 
4558 	rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf);
4559 
4560 	pfvf = rvu_get_pfvf(rvu, pcifunc);
4561 	clear_bit(NIXLF_INITIALIZED, &pfvf->flags);
4562 
4563 	return rvu_cgx_start_stop_io(rvu, pcifunc, false);
4564 }
4565 
4566 #define RX_SA_BASE  GENMASK_ULL(52, 7)
4567 
4568 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int nixlf)
4569 {
4570 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
4571 	struct hwctx_disable_req ctx_req;
4572 	int pf = rvu_get_pf(pcifunc);
4573 	struct mac_ops *mac_ops;
4574 	u8 cgx_id, lmac_id;
4575 	u64 sa_base;
4576 	void *cgxd;
4577 	int err;
4578 
4579 	ctx_req.hdr.pcifunc = pcifunc;
4580 
4581 	/* Cleanup NPC MCAM entries, free Tx scheduler queues being used */
4582 	rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf);
4583 	rvu_npc_free_mcam_entries(rvu, pcifunc, nixlf);
4584 	nix_interface_deinit(rvu, pcifunc, nixlf);
4585 	nix_rx_sync(rvu, blkaddr);
4586 	nix_txschq_free(rvu, pcifunc);
4587 
4588 	clear_bit(NIXLF_INITIALIZED, &pfvf->flags);
4589 
4590 	rvu_cgx_start_stop_io(rvu, pcifunc, false);
4591 
4592 	if (pfvf->sq_ctx) {
4593 		ctx_req.ctype = NIX_AQ_CTYPE_SQ;
4594 		err = nix_lf_hwctx_disable(rvu, &ctx_req);
4595 		if (err)
4596 			dev_err(rvu->dev, "SQ ctx disable failed\n");
4597 	}
4598 
4599 	if (pfvf->rq_ctx) {
4600 		ctx_req.ctype = NIX_AQ_CTYPE_RQ;
4601 		err = nix_lf_hwctx_disable(rvu, &ctx_req);
4602 		if (err)
4603 			dev_err(rvu->dev, "RQ ctx disable failed\n");
4604 	}
4605 
4606 	if (pfvf->cq_ctx) {
4607 		ctx_req.ctype = NIX_AQ_CTYPE_CQ;
4608 		err = nix_lf_hwctx_disable(rvu, &ctx_req);
4609 		if (err)
4610 			dev_err(rvu->dev, "CQ ctx disable failed\n");
4611 	}
4612 
4613 	/* reset HW config done for Switch headers */
4614 	rvu_npc_set_parse_mode(rvu, pcifunc, OTX2_PRIV_FLAGS_DEFAULT,
4615 			       (PKIND_TX | PKIND_RX), 0, 0, 0, 0);
4616 
4617 	/* Disabling CGX and NPC config done for PTP */
4618 	if (pfvf->hw_rx_tstamp_en) {
4619 		rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
4620 		cgxd = rvu_cgx_pdata(cgx_id, rvu);
4621 		mac_ops = get_mac_ops(cgxd);
4622 		mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, false);
4623 		/* Undo NPC config done for PTP */
4624 		if (npc_config_ts_kpuaction(rvu, pf, pcifunc, false))
4625 			dev_err(rvu->dev, "NPC config for PTP failed\n");
4626 		pfvf->hw_rx_tstamp_en = false;
4627 	}
4628 
4629 	/* reset priority flow control config */
4630 	rvu_cgx_prio_flow_ctrl_cfg(rvu, pcifunc, 0, 0, 0);
4631 
4632 	/* reset 802.3x flow control config */
4633 	rvu_cgx_cfg_pause_frm(rvu, pcifunc, 0, 0);
4634 
4635 	nix_ctx_free(rvu, pfvf);
4636 
4637 	nix_free_all_bandprof(rvu, pcifunc);
4638 
4639 	sa_base = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(nixlf));
4640 	if (FIELD_GET(RX_SA_BASE, sa_base)) {
4641 		err = rvu_cpt_ctx_flush(rvu, pcifunc);
4642 		if (err)
4643 			dev_err(rvu->dev,
4644 				"CPT ctx flush failed with error: %d\n", err);
4645 	}
4646 }
4647 
4648 #define NIX_AF_LFX_TX_CFG_PTP_EN	BIT_ULL(32)
4649 
4650 static int rvu_nix_lf_ptp_tx_cfg(struct rvu *rvu, u16 pcifunc, bool enable)
4651 {
4652 	struct rvu_hwinfo *hw = rvu->hw;
4653 	struct rvu_block *block;
4654 	int blkaddr, pf;
4655 	int nixlf;
4656 	u64 cfg;
4657 
4658 	pf = rvu_get_pf(pcifunc);
4659 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP))
4660 		return 0;
4661 
4662 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
4663 	if (blkaddr < 0)
4664 		return NIX_AF_ERR_AF_LF_INVALID;
4665 
4666 	block = &hw->block[blkaddr];
4667 	nixlf = rvu_get_lf(rvu, block, pcifunc, 0);
4668 	if (nixlf < 0)
4669 		return NIX_AF_ERR_AF_LF_INVALID;
4670 
4671 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf));
4672 
4673 	if (enable)
4674 		cfg |= NIX_AF_LFX_TX_CFG_PTP_EN;
4675 	else
4676 		cfg &= ~NIX_AF_LFX_TX_CFG_PTP_EN;
4677 
4678 	rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg);
4679 
4680 	return 0;
4681 }
4682 
4683 int rvu_mbox_handler_nix_lf_ptp_tx_enable(struct rvu *rvu, struct msg_req *req,
4684 					  struct msg_rsp *rsp)
4685 {
4686 	return rvu_nix_lf_ptp_tx_cfg(rvu, req->hdr.pcifunc, true);
4687 }
4688 
4689 int rvu_mbox_handler_nix_lf_ptp_tx_disable(struct rvu *rvu, struct msg_req *req,
4690 					   struct msg_rsp *rsp)
4691 {
4692 	return rvu_nix_lf_ptp_tx_cfg(rvu, req->hdr.pcifunc, false);
4693 }
4694 
4695 int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu,
4696 					struct nix_lso_format_cfg *req,
4697 					struct nix_lso_format_cfg_rsp *rsp)
4698 {
4699 	u16 pcifunc = req->hdr.pcifunc;
4700 	struct nix_hw *nix_hw;
4701 	struct rvu_pfvf *pfvf;
4702 	int blkaddr, idx, f;
4703 	u64 reg;
4704 
4705 	pfvf = rvu_get_pfvf(rvu, pcifunc);
4706 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
4707 	if (!pfvf->nixlf || blkaddr < 0)
4708 		return NIX_AF_ERR_AF_LF_INVALID;
4709 
4710 	nix_hw = get_nix_hw(rvu->hw, blkaddr);
4711 	if (!nix_hw)
4712 		return NIX_AF_ERR_INVALID_NIXBLK;
4713 
4714 	/* Find existing matching LSO format, if any */
4715 	for (idx = 0; idx < nix_hw->lso.in_use; idx++) {
4716 		for (f = 0; f < NIX_LSO_FIELD_MAX; f++) {
4717 			reg = rvu_read64(rvu, blkaddr,
4718 					 NIX_AF_LSO_FORMATX_FIELDX(idx, f));
4719 			if (req->fields[f] != (reg & req->field_mask))
4720 				break;
4721 		}
4722 
4723 		if (f == NIX_LSO_FIELD_MAX)
4724 			break;
4725 	}
4726 
4727 	if (idx < nix_hw->lso.in_use) {
4728 		/* Match found */
4729 		rsp->lso_format_idx = idx;
4730 		return 0;
4731 	}
4732 
4733 	if (nix_hw->lso.in_use == nix_hw->lso.total)
4734 		return NIX_AF_ERR_LSO_CFG_FAIL;
4735 
4736 	rsp->lso_format_idx = nix_hw->lso.in_use++;
4737 
4738 	for (f = 0; f < NIX_LSO_FIELD_MAX; f++)
4739 		rvu_write64(rvu, blkaddr,
4740 			    NIX_AF_LSO_FORMATX_FIELDX(rsp->lso_format_idx, f),
4741 			    req->fields[f]);
4742 
4743 	return 0;
4744 }
4745 
4746 #define IPSEC_GEN_CFG_EGRP    GENMASK_ULL(50, 48)
4747 #define IPSEC_GEN_CFG_OPCODE  GENMASK_ULL(47, 32)
4748 #define IPSEC_GEN_CFG_PARAM1  GENMASK_ULL(31, 16)
4749 #define IPSEC_GEN_CFG_PARAM2  GENMASK_ULL(15, 0)
4750 
4751 #define CPT_INST_QSEL_BLOCK   GENMASK_ULL(28, 24)
4752 #define CPT_INST_QSEL_PF_FUNC GENMASK_ULL(23, 8)
4753 #define CPT_INST_QSEL_SLOT    GENMASK_ULL(7, 0)
4754 
4755 #define CPT_INST_CREDIT_TH    GENMASK_ULL(53, 32)
4756 #define CPT_INST_CREDIT_BPID  GENMASK_ULL(30, 22)
4757 #define CPT_INST_CREDIT_CNT   GENMASK_ULL(21, 0)
4758 
4759 static void nix_inline_ipsec_cfg(struct rvu *rvu, struct nix_inline_ipsec_cfg *req,
4760 				 int blkaddr)
4761 {
4762 	u8 cpt_idx, cpt_blkaddr;
4763 	u64 val;
4764 
4765 	cpt_idx = (blkaddr == BLKADDR_NIX0) ? 0 : 1;
4766 	if (req->enable) {
4767 		val = 0;
4768 		/* Enable context prefetching */
4769 		if (!is_rvu_otx2(rvu))
4770 			val |= BIT_ULL(51);
4771 
4772 		/* Set OPCODE and EGRP */
4773 		val |= FIELD_PREP(IPSEC_GEN_CFG_EGRP, req->gen_cfg.egrp);
4774 		val |= FIELD_PREP(IPSEC_GEN_CFG_OPCODE, req->gen_cfg.opcode);
4775 		val |= FIELD_PREP(IPSEC_GEN_CFG_PARAM1, req->gen_cfg.param1);
4776 		val |= FIELD_PREP(IPSEC_GEN_CFG_PARAM2, req->gen_cfg.param2);
4777 
4778 		rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, val);
4779 
4780 		/* Set CPT queue for inline IPSec */
4781 		val = FIELD_PREP(CPT_INST_QSEL_SLOT, req->inst_qsel.cpt_slot);
4782 		val |= FIELD_PREP(CPT_INST_QSEL_PF_FUNC,
4783 				  req->inst_qsel.cpt_pf_func);
4784 
4785 		if (!is_rvu_otx2(rvu)) {
4786 			cpt_blkaddr = (cpt_idx == 0) ? BLKADDR_CPT0 :
4787 						       BLKADDR_CPT1;
4788 			val |= FIELD_PREP(CPT_INST_QSEL_BLOCK, cpt_blkaddr);
4789 		}
4790 
4791 		rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx),
4792 			    val);
4793 
4794 		/* Set CPT credit */
4795 		val = rvu_read64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx));
4796 		if ((val & 0x3FFFFF) != 0x3FFFFF)
4797 			rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx),
4798 				    0x3FFFFF - val);
4799 
4800 		val = FIELD_PREP(CPT_INST_CREDIT_CNT, req->cpt_credit);
4801 		val |= FIELD_PREP(CPT_INST_CREDIT_BPID, req->bpid);
4802 		val |= FIELD_PREP(CPT_INST_CREDIT_TH, req->credit_th);
4803 		rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), val);
4804 	} else {
4805 		rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, 0x0);
4806 		rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx),
4807 			    0x0);
4808 		val = rvu_read64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx));
4809 		if ((val & 0x3FFFFF) != 0x3FFFFF)
4810 			rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx),
4811 				    0x3FFFFF - val);
4812 	}
4813 }
4814 
4815 int rvu_mbox_handler_nix_inline_ipsec_cfg(struct rvu *rvu,
4816 					  struct nix_inline_ipsec_cfg *req,
4817 					  struct msg_rsp *rsp)
4818 {
4819 	if (!is_block_implemented(rvu->hw, BLKADDR_CPT0))
4820 		return 0;
4821 
4822 	nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX0);
4823 	if (is_block_implemented(rvu->hw, BLKADDR_CPT1))
4824 		nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX1);
4825 
4826 	return 0;
4827 }
4828 
4829 int rvu_mbox_handler_nix_read_inline_ipsec_cfg(struct rvu *rvu,
4830 					       struct msg_req *req,
4831 					       struct nix_inline_ipsec_cfg *rsp)
4832 
4833 {
4834 	u64 val;
4835 
4836 	if (!is_block_implemented(rvu->hw, BLKADDR_CPT0))
4837 		return 0;
4838 
4839 	val = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_RX_IPSEC_GEN_CFG);
4840 	rsp->gen_cfg.egrp = FIELD_GET(IPSEC_GEN_CFG_EGRP, val);
4841 	rsp->gen_cfg.opcode = FIELD_GET(IPSEC_GEN_CFG_OPCODE, val);
4842 	rsp->gen_cfg.param1 = FIELD_GET(IPSEC_GEN_CFG_PARAM1, val);
4843 	rsp->gen_cfg.param2 = FIELD_GET(IPSEC_GEN_CFG_PARAM2, val);
4844 
4845 	val = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_RX_CPTX_CREDIT(0));
4846 	rsp->cpt_credit = FIELD_GET(CPT_INST_CREDIT_CNT, val);
4847 	rsp->credit_th = FIELD_GET(CPT_INST_CREDIT_TH, val);
4848 	rsp->bpid = FIELD_GET(CPT_INST_CREDIT_BPID, val);
4849 
4850 	return 0;
4851 }
4852 
4853 int rvu_mbox_handler_nix_inline_ipsec_lf_cfg(struct rvu *rvu,
4854 					     struct nix_inline_ipsec_lf_cfg *req,
4855 					     struct msg_rsp *rsp)
4856 {
4857 	int lf, blkaddr, err;
4858 	u64 val;
4859 
4860 	if (!is_block_implemented(rvu->hw, BLKADDR_CPT0))
4861 		return 0;
4862 
4863 	err = nix_get_nixlf(rvu, req->hdr.pcifunc, &lf, &blkaddr);
4864 	if (err)
4865 		return err;
4866 
4867 	if (req->enable) {
4868 		/* Set TT, TAG_CONST, SA_POW2_SIZE and LENM1_MAX */
4869 		val = (u64)req->ipsec_cfg0.tt << 44 |
4870 		      (u64)req->ipsec_cfg0.tag_const << 20 |
4871 		      (u64)req->ipsec_cfg0.sa_pow2_size << 16 |
4872 		      req->ipsec_cfg0.lenm1_max;
4873 
4874 		if (blkaddr == BLKADDR_NIX1)
4875 			val |= BIT_ULL(46);
4876 
4877 		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG0(lf), val);
4878 
4879 		/* Set SA_IDX_W and SA_IDX_MAX */
4880 		val = (u64)req->ipsec_cfg1.sa_idx_w << 32 |
4881 		      req->ipsec_cfg1.sa_idx_max;
4882 		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(lf), val);
4883 
4884 		/* Set SA base address */
4885 		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(lf),
4886 			    req->sa_base_addr);
4887 	} else {
4888 		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG0(lf), 0x0);
4889 		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(lf), 0x0);
4890 		rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(lf),
4891 			    0x0);
4892 	}
4893 
4894 	return 0;
4895 }
4896 
4897 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc)
4898 {
4899 	bool from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK);
4900 
4901 	/* overwrite vf mac address with default_mac */
4902 	if (from_vf)
4903 		ether_addr_copy(pfvf->mac_addr, pfvf->default_mac);
4904 }
4905 
4906 /* NIX ingress policers or bandwidth profiles APIs */
4907 static void nix_config_rx_pkt_policer_precolor(struct rvu *rvu, int blkaddr)
4908 {
4909 	struct npc_lt_def_cfg defs, *ltdefs;
4910 
4911 	ltdefs = &defs;
4912 	memcpy(ltdefs, rvu->kpu.lt_def, sizeof(struct npc_lt_def_cfg));
4913 
4914 	/* Extract PCP and DEI fields from outer VLAN from byte offset
4915 	 * 2 from the start of LB_PTR (ie TAG).
4916 	 * VLAN0 is Outer VLAN and VLAN1 is Inner VLAN. Inner VLAN
4917 	 * fields are considered when 'Tunnel enable' is set in profile.
4918 	 */
4919 	rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN0_PCP_DEI,
4920 		    (2UL << 12) | (ltdefs->ovlan.lid << 8) |
4921 		    (ltdefs->ovlan.ltype_match << 4) |
4922 		    ltdefs->ovlan.ltype_mask);
4923 	rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN1_PCP_DEI,
4924 		    (2UL << 12) | (ltdefs->ivlan.lid << 8) |
4925 		    (ltdefs->ivlan.ltype_match << 4) |
4926 		    ltdefs->ivlan.ltype_mask);
4927 
4928 	/* DSCP field in outer and tunneled IPv4 packets */
4929 	rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4_DSCP,
4930 		    (1UL << 12) | (ltdefs->rx_oip4.lid << 8) |
4931 		    (ltdefs->rx_oip4.ltype_match << 4) |
4932 		    ltdefs->rx_oip4.ltype_mask);
4933 	rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4_DSCP,
4934 		    (1UL << 12) | (ltdefs->rx_iip4.lid << 8) |
4935 		    (ltdefs->rx_iip4.ltype_match << 4) |
4936 		    ltdefs->rx_iip4.ltype_mask);
4937 
4938 	/* DSCP field (traffic class) in outer and tunneled IPv6 packets */
4939 	rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6_DSCP,
4940 		    (1UL << 11) | (ltdefs->rx_oip6.lid << 8) |
4941 		    (ltdefs->rx_oip6.ltype_match << 4) |
4942 		    ltdefs->rx_oip6.ltype_mask);
4943 	rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6_DSCP,
4944 		    (1UL << 11) | (ltdefs->rx_iip6.lid << 8) |
4945 		    (ltdefs->rx_iip6.ltype_match << 4) |
4946 		    ltdefs->rx_iip6.ltype_mask);
4947 }
4948 
4949 static int nix_init_policer_context(struct rvu *rvu, struct nix_hw *nix_hw,
4950 				    int layer, int prof_idx)
4951 {
4952 	struct nix_cn10k_aq_enq_req aq_req;
4953 	int rc;
4954 
4955 	memset(&aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req));
4956 
4957 	aq_req.qidx = (prof_idx & 0x3FFF) | (layer << 14);
4958 	aq_req.ctype = NIX_AQ_CTYPE_BANDPROF;
4959 	aq_req.op = NIX_AQ_INSTOP_INIT;
4960 
4961 	/* Context is all zeros, submit to AQ */
4962 	rc = rvu_nix_blk_aq_enq_inst(rvu, nix_hw,
4963 				     (struct nix_aq_enq_req *)&aq_req, NULL);
4964 	if (rc)
4965 		dev_err(rvu->dev, "Failed to INIT bandwidth profile layer %d profile %d\n",
4966 			layer, prof_idx);
4967 	return rc;
4968 }
4969 
4970 static int nix_setup_ipolicers(struct rvu *rvu,
4971 			       struct nix_hw *nix_hw, int blkaddr)
4972 {
4973 	struct rvu_hwinfo *hw = rvu->hw;
4974 	struct nix_ipolicer *ipolicer;
4975 	int err, layer, prof_idx;
4976 	u64 cfg;
4977 
4978 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST);
4979 	if (!(cfg & BIT_ULL(61))) {
4980 		hw->cap.ipolicer = false;
4981 		return 0;
4982 	}
4983 
4984 	hw->cap.ipolicer = true;
4985 	nix_hw->ipolicer = devm_kcalloc(rvu->dev, BAND_PROF_NUM_LAYERS,
4986 					sizeof(*ipolicer), GFP_KERNEL);
4987 	if (!nix_hw->ipolicer)
4988 		return -ENOMEM;
4989 
4990 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_PL_CONST);
4991 
4992 	for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) {
4993 		ipolicer = &nix_hw->ipolicer[layer];
4994 		switch (layer) {
4995 		case BAND_PROF_LEAF_LAYER:
4996 			ipolicer->band_prof.max = cfg & 0XFFFF;
4997 			break;
4998 		case BAND_PROF_MID_LAYER:
4999 			ipolicer->band_prof.max = (cfg >> 16) & 0XFFFF;
5000 			break;
5001 		case BAND_PROF_TOP_LAYER:
5002 			ipolicer->band_prof.max = (cfg >> 32) & 0XFFFF;
5003 			break;
5004 		}
5005 
5006 		if (!ipolicer->band_prof.max)
5007 			continue;
5008 
5009 		err = rvu_alloc_bitmap(&ipolicer->band_prof);
5010 		if (err)
5011 			return err;
5012 
5013 		ipolicer->pfvf_map = devm_kcalloc(rvu->dev,
5014 						  ipolicer->band_prof.max,
5015 						  sizeof(u16), GFP_KERNEL);
5016 		if (!ipolicer->pfvf_map)
5017 			return -ENOMEM;
5018 
5019 		ipolicer->match_id = devm_kcalloc(rvu->dev,
5020 						  ipolicer->band_prof.max,
5021 						  sizeof(u16), GFP_KERNEL);
5022 		if (!ipolicer->match_id)
5023 			return -ENOMEM;
5024 
5025 		for (prof_idx = 0;
5026 		     prof_idx < ipolicer->band_prof.max; prof_idx++) {
5027 			/* Set AF as current owner for INIT ops to succeed */
5028 			ipolicer->pfvf_map[prof_idx] = 0x00;
5029 
5030 			/* There is no enable bit in the profile context,
5031 			 * so no context disable. So let's INIT them here
5032 			 * so that PF/VF later on have to just do WRITE to
5033 			 * setup policer rates and config.
5034 			 */
5035 			err = nix_init_policer_context(rvu, nix_hw,
5036 						       layer, prof_idx);
5037 			if (err)
5038 				return err;
5039 		}
5040 
5041 		/* Allocate memory for maintaining ref_counts for MID level
5042 		 * profiles, this will be needed for leaf layer profiles'
5043 		 * aggregation.
5044 		 */
5045 		if (layer != BAND_PROF_MID_LAYER)
5046 			continue;
5047 
5048 		ipolicer->ref_count = devm_kcalloc(rvu->dev,
5049 						   ipolicer->band_prof.max,
5050 						   sizeof(u16), GFP_KERNEL);
5051 		if (!ipolicer->ref_count)
5052 			return -ENOMEM;
5053 	}
5054 
5055 	/* Set policer timeunit to 2us ie  (19 + 1) * 100 nsec = 2us */
5056 	rvu_write64(rvu, blkaddr, NIX_AF_PL_TS, 19);
5057 
5058 	nix_config_rx_pkt_policer_precolor(rvu, blkaddr);
5059 
5060 	return 0;
5061 }
5062 
5063 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw)
5064 {
5065 	struct nix_ipolicer *ipolicer;
5066 	int layer;
5067 
5068 	if (!rvu->hw->cap.ipolicer)
5069 		return;
5070 
5071 	for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) {
5072 		ipolicer = &nix_hw->ipolicer[layer];
5073 
5074 		if (!ipolicer->band_prof.max)
5075 			continue;
5076 
5077 		kfree(ipolicer->band_prof.bmap);
5078 	}
5079 }
5080 
5081 static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req,
5082 			       struct nix_hw *nix_hw, u16 pcifunc)
5083 {
5084 	struct nix_ipolicer *ipolicer;
5085 	int layer, hi_layer, prof_idx;
5086 
5087 	/* Bits [15:14] in profile index represent layer */
5088 	layer = (req->qidx >> 14) & 0x03;
5089 	prof_idx = req->qidx & 0x3FFF;
5090 
5091 	ipolicer = &nix_hw->ipolicer[layer];
5092 	if (prof_idx >= ipolicer->band_prof.max)
5093 		return -EINVAL;
5094 
5095 	/* Check if the profile is allocated to the requesting PCIFUNC or not
5096 	 * with the exception of AF. AF is allowed to read and update contexts.
5097 	 */
5098 	if (pcifunc && ipolicer->pfvf_map[prof_idx] != pcifunc)
5099 		return -EINVAL;
5100 
5101 	/* If this profile is linked to higher layer profile then check
5102 	 * if that profile is also allocated to the requesting PCIFUNC
5103 	 * or not.
5104 	 */
5105 	if (!req->prof.hl_en)
5106 		return 0;
5107 
5108 	/* Leaf layer profile can link only to mid layer and
5109 	 * mid layer to top layer.
5110 	 */
5111 	if (layer == BAND_PROF_LEAF_LAYER)
5112 		hi_layer = BAND_PROF_MID_LAYER;
5113 	else if (layer == BAND_PROF_MID_LAYER)
5114 		hi_layer = BAND_PROF_TOP_LAYER;
5115 	else
5116 		return -EINVAL;
5117 
5118 	ipolicer = &nix_hw->ipolicer[hi_layer];
5119 	prof_idx = req->prof.band_prof_id;
5120 	if (prof_idx >= ipolicer->band_prof.max ||
5121 	    ipolicer->pfvf_map[prof_idx] != pcifunc)
5122 		return -EINVAL;
5123 
5124 	return 0;
5125 }
5126 
5127 int rvu_mbox_handler_nix_bandprof_alloc(struct rvu *rvu,
5128 					struct nix_bandprof_alloc_req *req,
5129 					struct nix_bandprof_alloc_rsp *rsp)
5130 {
5131 	int blkaddr, layer, prof, idx, err;
5132 	u16 pcifunc = req->hdr.pcifunc;
5133 	struct nix_ipolicer *ipolicer;
5134 	struct nix_hw *nix_hw;
5135 
5136 	if (!rvu->hw->cap.ipolicer)
5137 		return NIX_AF_ERR_IPOLICER_NOTSUPP;
5138 
5139 	err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);
5140 	if (err)
5141 		return err;
5142 
5143 	mutex_lock(&rvu->rsrc_lock);
5144 	for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) {
5145 		if (layer == BAND_PROF_INVAL_LAYER)
5146 			continue;
5147 		if (!req->prof_count[layer])
5148 			continue;
5149 
5150 		ipolicer = &nix_hw->ipolicer[layer];
5151 		for (idx = 0; idx < req->prof_count[layer]; idx++) {
5152 			/* Allocate a max of 'MAX_BANDPROF_PER_PFFUNC' profiles */
5153 			if (idx == MAX_BANDPROF_PER_PFFUNC)
5154 				break;
5155 
5156 			prof = rvu_alloc_rsrc(&ipolicer->band_prof);
5157 			if (prof < 0)
5158 				break;
5159 			rsp->prof_count[layer]++;
5160 			rsp->prof_idx[layer][idx] = prof;
5161 			ipolicer->pfvf_map[prof] = pcifunc;
5162 		}
5163 	}
5164 	mutex_unlock(&rvu->rsrc_lock);
5165 	return 0;
5166 }
5167 
5168 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc)
5169 {
5170 	int blkaddr, layer, prof_idx, err;
5171 	struct nix_ipolicer *ipolicer;
5172 	struct nix_hw *nix_hw;
5173 
5174 	if (!rvu->hw->cap.ipolicer)
5175 		return NIX_AF_ERR_IPOLICER_NOTSUPP;
5176 
5177 	err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);
5178 	if (err)
5179 		return err;
5180 
5181 	mutex_lock(&rvu->rsrc_lock);
5182 	/* Free all the profiles allocated to the PCIFUNC */
5183 	for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) {
5184 		if (layer == BAND_PROF_INVAL_LAYER)
5185 			continue;
5186 		ipolicer = &nix_hw->ipolicer[layer];
5187 
5188 		for (prof_idx = 0; prof_idx < ipolicer->band_prof.max; prof_idx++) {
5189 			if (ipolicer->pfvf_map[prof_idx] != pcifunc)
5190 				continue;
5191 
5192 			/* Clear ratelimit aggregation, if any */
5193 			if (layer == BAND_PROF_LEAF_LAYER &&
5194 			    ipolicer->match_id[prof_idx])
5195 				nix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx);
5196 
5197 			ipolicer->pfvf_map[prof_idx] = 0x00;
5198 			ipolicer->match_id[prof_idx] = 0;
5199 			rvu_free_rsrc(&ipolicer->band_prof, prof_idx);
5200 		}
5201 	}
5202 	mutex_unlock(&rvu->rsrc_lock);
5203 	return 0;
5204 }
5205 
5206 int rvu_mbox_handler_nix_bandprof_free(struct rvu *rvu,
5207 				       struct nix_bandprof_free_req *req,
5208 				       struct msg_rsp *rsp)
5209 {
5210 	int blkaddr, layer, prof_idx, idx, err;
5211 	u16 pcifunc = req->hdr.pcifunc;
5212 	struct nix_ipolicer *ipolicer;
5213 	struct nix_hw *nix_hw;
5214 
5215 	if (req->free_all)
5216 		return nix_free_all_bandprof(rvu, pcifunc);
5217 
5218 	if (!rvu->hw->cap.ipolicer)
5219 		return NIX_AF_ERR_IPOLICER_NOTSUPP;
5220 
5221 	err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);
5222 	if (err)
5223 		return err;
5224 
5225 	mutex_lock(&rvu->rsrc_lock);
5226 	/* Free the requested profile indices */
5227 	for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) {
5228 		if (layer == BAND_PROF_INVAL_LAYER)
5229 			continue;
5230 		if (!req->prof_count[layer])
5231 			continue;
5232 
5233 		ipolicer = &nix_hw->ipolicer[layer];
5234 		for (idx = 0; idx < req->prof_count[layer]; idx++) {
5235 			prof_idx = req->prof_idx[layer][idx];
5236 			if (prof_idx >= ipolicer->band_prof.max ||
5237 			    ipolicer->pfvf_map[prof_idx] != pcifunc)
5238 				continue;
5239 
5240 			/* Clear ratelimit aggregation, if any */
5241 			if (layer == BAND_PROF_LEAF_LAYER &&
5242 			    ipolicer->match_id[prof_idx])
5243 				nix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx);
5244 
5245 			ipolicer->pfvf_map[prof_idx] = 0x00;
5246 			ipolicer->match_id[prof_idx] = 0;
5247 			rvu_free_rsrc(&ipolicer->band_prof, prof_idx);
5248 			if (idx == MAX_BANDPROF_PER_PFFUNC)
5249 				break;
5250 		}
5251 	}
5252 	mutex_unlock(&rvu->rsrc_lock);
5253 	return 0;
5254 }
5255 
5256 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
5257 			struct nix_cn10k_aq_enq_req *aq_req,
5258 			struct nix_cn10k_aq_enq_rsp *aq_rsp,
5259 			u16 pcifunc, u8 ctype, u32 qidx)
5260 {
5261 	memset(aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req));
5262 	aq_req->hdr.pcifunc = pcifunc;
5263 	aq_req->ctype = ctype;
5264 	aq_req->op = NIX_AQ_INSTOP_READ;
5265 	aq_req->qidx = qidx;
5266 
5267 	return rvu_nix_blk_aq_enq_inst(rvu, nix_hw,
5268 				       (struct nix_aq_enq_req *)aq_req,
5269 				       (struct nix_aq_enq_rsp *)aq_rsp);
5270 }
5271 
5272 static int nix_ipolicer_map_leaf_midprofs(struct rvu *rvu,
5273 					  struct nix_hw *nix_hw,
5274 					  struct nix_cn10k_aq_enq_req *aq_req,
5275 					  struct nix_cn10k_aq_enq_rsp *aq_rsp,
5276 					  u32 leaf_prof, u16 mid_prof)
5277 {
5278 	memset(aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req));
5279 	aq_req->hdr.pcifunc = 0x00;
5280 	aq_req->ctype = NIX_AQ_CTYPE_BANDPROF;
5281 	aq_req->op = NIX_AQ_INSTOP_WRITE;
5282 	aq_req->qidx = leaf_prof;
5283 
5284 	aq_req->prof.band_prof_id = mid_prof;
5285 	aq_req->prof_mask.band_prof_id = GENMASK(6, 0);
5286 	aq_req->prof.hl_en = 1;
5287 	aq_req->prof_mask.hl_en = 1;
5288 
5289 	return rvu_nix_blk_aq_enq_inst(rvu, nix_hw,
5290 				       (struct nix_aq_enq_req *)aq_req,
5291 				       (struct nix_aq_enq_rsp *)aq_rsp);
5292 }
5293 
5294 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
5295 				 u16 rq_idx, u16 match_id)
5296 {
5297 	int leaf_prof, mid_prof, leaf_match;
5298 	struct nix_cn10k_aq_enq_req aq_req;
5299 	struct nix_cn10k_aq_enq_rsp aq_rsp;
5300 	struct nix_ipolicer *ipolicer;
5301 	struct nix_hw *nix_hw;
5302 	int blkaddr, idx, rc;
5303 
5304 	if (!rvu->hw->cap.ipolicer)
5305 		return 0;
5306 
5307 	rc = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr);
5308 	if (rc)
5309 		return rc;
5310 
5311 	/* Fetch the RQ's context to see if policing is enabled */
5312 	rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, pcifunc,
5313 				 NIX_AQ_CTYPE_RQ, rq_idx);
5314 	if (rc) {
5315 		dev_err(rvu->dev,
5316 			"%s: Failed to fetch RQ%d context of PFFUNC 0x%x\n",
5317 			__func__, rq_idx, pcifunc);
5318 		return rc;
5319 	}
5320 
5321 	if (!aq_rsp.rq.policer_ena)
5322 		return 0;
5323 
5324 	/* Get the bandwidth profile ID mapped to this RQ */
5325 	leaf_prof = aq_rsp.rq.band_prof_id;
5326 
5327 	ipolicer = &nix_hw->ipolicer[BAND_PROF_LEAF_LAYER];
5328 	ipolicer->match_id[leaf_prof] = match_id;
5329 
5330 	/* Check if any other leaf profile is marked with same match_id */
5331 	for (idx = 0; idx < ipolicer->band_prof.max; idx++) {
5332 		if (idx == leaf_prof)
5333 			continue;
5334 		if (ipolicer->match_id[idx] != match_id)
5335 			continue;
5336 
5337 		leaf_match = idx;
5338 		break;
5339 	}
5340 
5341 	if (idx == ipolicer->band_prof.max)
5342 		return 0;
5343 
5344 	/* Fetch the matching profile's context to check if it's already
5345 	 * mapped to a mid level profile.
5346 	 */
5347 	rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00,
5348 				 NIX_AQ_CTYPE_BANDPROF, leaf_match);
5349 	if (rc) {
5350 		dev_err(rvu->dev,
5351 			"%s: Failed to fetch context of leaf profile %d\n",
5352 			__func__, leaf_match);
5353 		return rc;
5354 	}
5355 
5356 	ipolicer = &nix_hw->ipolicer[BAND_PROF_MID_LAYER];
5357 	if (aq_rsp.prof.hl_en) {
5358 		/* Get Mid layer prof index and map leaf_prof index
5359 		 * also such that flows that are being steered
5360 		 * to different RQs and marked with same match_id
5361 		 * are rate limited in a aggregate fashion
5362 		 */
5363 		mid_prof = aq_rsp.prof.band_prof_id;
5364 		rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw,
5365 						    &aq_req, &aq_rsp,
5366 						    leaf_prof, mid_prof);
5367 		if (rc) {
5368 			dev_err(rvu->dev,
5369 				"%s: Failed to map leaf(%d) and mid(%d) profiles\n",
5370 				__func__, leaf_prof, mid_prof);
5371 			goto exit;
5372 		}
5373 
5374 		mutex_lock(&rvu->rsrc_lock);
5375 		ipolicer->ref_count[mid_prof]++;
5376 		mutex_unlock(&rvu->rsrc_lock);
5377 		goto exit;
5378 	}
5379 
5380 	/* Allocate a mid layer profile and
5381 	 * map both 'leaf_prof' and 'leaf_match' profiles to it.
5382 	 */
5383 	mutex_lock(&rvu->rsrc_lock);
5384 	mid_prof = rvu_alloc_rsrc(&ipolicer->band_prof);
5385 	if (mid_prof < 0) {
5386 		dev_err(rvu->dev,
5387 			"%s: Unable to allocate mid layer profile\n", __func__);
5388 		mutex_unlock(&rvu->rsrc_lock);
5389 		goto exit;
5390 	}
5391 	mutex_unlock(&rvu->rsrc_lock);
5392 	ipolicer->pfvf_map[mid_prof] = 0x00;
5393 	ipolicer->ref_count[mid_prof] = 0;
5394 
5395 	/* Initialize mid layer profile same as 'leaf_prof' */
5396 	rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00,
5397 				 NIX_AQ_CTYPE_BANDPROF, leaf_prof);
5398 	if (rc) {
5399 		dev_err(rvu->dev,
5400 			"%s: Failed to fetch context of leaf profile %d\n",
5401 			__func__, leaf_prof);
5402 		goto exit;
5403 	}
5404 
5405 	memset(&aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req));
5406 	aq_req.hdr.pcifunc = 0x00;
5407 	aq_req.qidx = (mid_prof & 0x3FFF) | (BAND_PROF_MID_LAYER << 14);
5408 	aq_req.ctype = NIX_AQ_CTYPE_BANDPROF;
5409 	aq_req.op = NIX_AQ_INSTOP_WRITE;
5410 	memcpy(&aq_req.prof, &aq_rsp.prof, sizeof(struct nix_bandprof_s));
5411 	memset((char *)&aq_req.prof_mask, 0xff, sizeof(struct nix_bandprof_s));
5412 	/* Clear higher layer enable bit in the mid profile, just in case */
5413 	aq_req.prof.hl_en = 0;
5414 	aq_req.prof_mask.hl_en = 1;
5415 
5416 	rc = rvu_nix_blk_aq_enq_inst(rvu, nix_hw,
5417 				     (struct nix_aq_enq_req *)&aq_req, NULL);
5418 	if (rc) {
5419 		dev_err(rvu->dev,
5420 			"%s: Failed to INIT context of mid layer profile %d\n",
5421 			__func__, mid_prof);
5422 		goto exit;
5423 	}
5424 
5425 	/* Map both leaf profiles to this mid layer profile */
5426 	rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw,
5427 					    &aq_req, &aq_rsp,
5428 					    leaf_prof, mid_prof);
5429 	if (rc) {
5430 		dev_err(rvu->dev,
5431 			"%s: Failed to map leaf(%d) and mid(%d) profiles\n",
5432 			__func__, leaf_prof, mid_prof);
5433 		goto exit;
5434 	}
5435 
5436 	mutex_lock(&rvu->rsrc_lock);
5437 	ipolicer->ref_count[mid_prof]++;
5438 	mutex_unlock(&rvu->rsrc_lock);
5439 
5440 	rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw,
5441 					    &aq_req, &aq_rsp,
5442 					    leaf_match, mid_prof);
5443 	if (rc) {
5444 		dev_err(rvu->dev,
5445 			"%s: Failed to map leaf(%d) and mid(%d) profiles\n",
5446 			__func__, leaf_match, mid_prof);
5447 		ipolicer->ref_count[mid_prof]--;
5448 		goto exit;
5449 	}
5450 
5451 	mutex_lock(&rvu->rsrc_lock);
5452 	ipolicer->ref_count[mid_prof]++;
5453 	mutex_unlock(&rvu->rsrc_lock);
5454 
5455 exit:
5456 	return rc;
5457 }
5458 
5459 /* Called with mutex rsrc_lock */
5460 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw,
5461 				     u32 leaf_prof)
5462 {
5463 	struct nix_cn10k_aq_enq_req aq_req;
5464 	struct nix_cn10k_aq_enq_rsp aq_rsp;
5465 	struct nix_ipolicer *ipolicer;
5466 	u16 mid_prof;
5467 	int rc;
5468 
5469 	mutex_unlock(&rvu->rsrc_lock);
5470 
5471 	rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00,
5472 				 NIX_AQ_CTYPE_BANDPROF, leaf_prof);
5473 
5474 	mutex_lock(&rvu->rsrc_lock);
5475 	if (rc) {
5476 		dev_err(rvu->dev,
5477 			"%s: Failed to fetch context of leaf profile %d\n",
5478 			__func__, leaf_prof);
5479 		return;
5480 	}
5481 
5482 	if (!aq_rsp.prof.hl_en)
5483 		return;
5484 
5485 	mid_prof = aq_rsp.prof.band_prof_id;
5486 	ipolicer = &nix_hw->ipolicer[BAND_PROF_MID_LAYER];
5487 	ipolicer->ref_count[mid_prof]--;
5488 	/* If ref_count is zero, free mid layer profile */
5489 	if (!ipolicer->ref_count[mid_prof]) {
5490 		ipolicer->pfvf_map[mid_prof] = 0x00;
5491 		rvu_free_rsrc(&ipolicer->band_prof, mid_prof);
5492 	}
5493 }
5494 
5495 int rvu_mbox_handler_nix_bandprof_get_hwinfo(struct rvu *rvu, struct msg_req *req,
5496 					     struct nix_bandprof_get_hwinfo_rsp *rsp)
5497 {
5498 	struct nix_ipolicer *ipolicer;
5499 	int blkaddr, layer, err;
5500 	struct nix_hw *nix_hw;
5501 	u64 tu;
5502 
5503 	if (!rvu->hw->cap.ipolicer)
5504 		return NIX_AF_ERR_IPOLICER_NOTSUPP;
5505 
5506 	err = nix_get_struct_ptrs(rvu, req->hdr.pcifunc, &nix_hw, &blkaddr);
5507 	if (err)
5508 		return err;
5509 
5510 	/* Return number of bandwidth profiles free at each layer */
5511 	mutex_lock(&rvu->rsrc_lock);
5512 	for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) {
5513 		if (layer == BAND_PROF_INVAL_LAYER)
5514 			continue;
5515 
5516 		ipolicer = &nix_hw->ipolicer[layer];
5517 		rsp->prof_count[layer] = rvu_rsrc_free_count(&ipolicer->band_prof);
5518 	}
5519 	mutex_unlock(&rvu->rsrc_lock);
5520 
5521 	/* Set the policer timeunit in nanosec */
5522 	tu = rvu_read64(rvu, blkaddr, NIX_AF_PL_TS) & GENMASK_ULL(9, 0);
5523 	rsp->policer_timeunit = (tu + 1) * 100;
5524 
5525 	return 0;
5526 }
5527