1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/pci.h> 10 11 #include "rvu_struct.h" 12 #include "rvu_reg.h" 13 #include "rvu.h" 14 #include "npc.h" 15 #include "cgx.h" 16 #include "lmac_common.h" 17 #include "rvu_npc_hash.h" 18 19 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc); 20 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, 21 int type, int chan_id); 22 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc, 23 int type, bool add); 24 static int nix_setup_ipolicers(struct rvu *rvu, 25 struct nix_hw *nix_hw, int blkaddr); 26 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw); 27 static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req, 28 struct nix_hw *nix_hw, u16 pcifunc); 29 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc); 30 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw, 31 u32 leaf_prof); 32 static const char *nix_get_ctx_name(int ctype); 33 34 enum mc_tbl_sz { 35 MC_TBL_SZ_256, 36 MC_TBL_SZ_512, 37 MC_TBL_SZ_1K, 38 MC_TBL_SZ_2K, 39 MC_TBL_SZ_4K, 40 MC_TBL_SZ_8K, 41 MC_TBL_SZ_16K, 42 MC_TBL_SZ_32K, 43 MC_TBL_SZ_64K, 44 }; 45 46 enum mc_buf_cnt { 47 MC_BUF_CNT_8, 48 MC_BUF_CNT_16, 49 MC_BUF_CNT_32, 50 MC_BUF_CNT_64, 51 MC_BUF_CNT_128, 52 MC_BUF_CNT_256, 53 MC_BUF_CNT_512, 54 MC_BUF_CNT_1024, 55 MC_BUF_CNT_2048, 56 }; 57 58 enum nix_makr_fmt_indexes { 59 NIX_MARK_CFG_IP_DSCP_RED, 60 NIX_MARK_CFG_IP_DSCP_YELLOW, 61 NIX_MARK_CFG_IP_DSCP_YELLOW_RED, 62 NIX_MARK_CFG_IP_ECN_RED, 63 NIX_MARK_CFG_IP_ECN_YELLOW, 64 NIX_MARK_CFG_IP_ECN_YELLOW_RED, 65 NIX_MARK_CFG_VLAN_DEI_RED, 66 NIX_MARK_CFG_VLAN_DEI_YELLOW, 67 NIX_MARK_CFG_VLAN_DEI_YELLOW_RED, 68 NIX_MARK_CFG_MAX, 69 }; 70 71 /* For now considering MC resources needed for broadcast 72 * pkt replication only. i.e 256 HWVFs + 12 PFs. 73 */ 74 #define MC_TBL_SIZE MC_TBL_SZ_512 75 #define MC_BUF_CNT MC_BUF_CNT_128 76 77 struct mce { 78 struct hlist_node node; 79 u16 pcifunc; 80 }; 81 82 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr) 83 { 84 int i = 0; 85 86 /*If blkaddr is 0, return the first nix block address*/ 87 if (blkaddr == 0) 88 return rvu->nix_blkaddr[blkaddr]; 89 90 while (i + 1 < MAX_NIX_BLKS) { 91 if (rvu->nix_blkaddr[i] == blkaddr) 92 return rvu->nix_blkaddr[i + 1]; 93 i++; 94 } 95 96 return 0; 97 } 98 99 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc) 100 { 101 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 102 int blkaddr; 103 104 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 105 if (!pfvf->nixlf || blkaddr < 0) 106 return false; 107 return true; 108 } 109 110 int rvu_get_nixlf_count(struct rvu *rvu) 111 { 112 int blkaddr = 0, max = 0; 113 struct rvu_block *block; 114 115 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 116 while (blkaddr) { 117 block = &rvu->hw->block[blkaddr]; 118 max += block->lf.max; 119 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 120 } 121 return max; 122 } 123 124 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr) 125 { 126 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 127 struct rvu_hwinfo *hw = rvu->hw; 128 int blkaddr; 129 130 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 131 if (!pfvf->nixlf || blkaddr < 0) 132 return NIX_AF_ERR_AF_LF_INVALID; 133 134 *nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 135 if (*nixlf < 0) 136 return NIX_AF_ERR_AF_LF_INVALID; 137 138 if (nix_blkaddr) 139 *nix_blkaddr = blkaddr; 140 141 return 0; 142 } 143 144 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 145 struct nix_hw **nix_hw, int *blkaddr) 146 { 147 struct rvu_pfvf *pfvf; 148 149 pfvf = rvu_get_pfvf(rvu, pcifunc); 150 *blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 151 if (!pfvf->nixlf || *blkaddr < 0) 152 return NIX_AF_ERR_AF_LF_INVALID; 153 154 *nix_hw = get_nix_hw(rvu->hw, *blkaddr); 155 if (!*nix_hw) 156 return NIX_AF_ERR_INVALID_NIXBLK; 157 return 0; 158 } 159 160 static void nix_mce_list_init(struct nix_mce_list *list, int max) 161 { 162 INIT_HLIST_HEAD(&list->head); 163 list->count = 0; 164 list->max = max; 165 } 166 167 static u16 nix_alloc_mce_list(struct nix_mcast *mcast, int count) 168 { 169 int idx; 170 171 if (!mcast) 172 return 0; 173 174 idx = mcast->next_free_mce; 175 mcast->next_free_mce += count; 176 return idx; 177 } 178 179 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr) 180 { 181 int nix_blkaddr = 0, i = 0; 182 struct rvu *rvu = hw->rvu; 183 184 nix_blkaddr = rvu_get_next_nix_blkaddr(rvu, nix_blkaddr); 185 while (nix_blkaddr) { 186 if (blkaddr == nix_blkaddr && hw->nix) 187 return &hw->nix[i]; 188 nix_blkaddr = rvu_get_next_nix_blkaddr(rvu, nix_blkaddr); 189 i++; 190 } 191 return NULL; 192 } 193 194 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu) 195 { 196 dwrr_mtu &= 0x1FULL; 197 198 /* MTU used for DWRR calculation is in power of 2 up until 64K bytes. 199 * Value of 4 is reserved for MTU value of 9728 bytes. 200 * Value of 5 is reserved for MTU value of 10240 bytes. 201 */ 202 switch (dwrr_mtu) { 203 case 4: 204 return 9728; 205 case 5: 206 return 10240; 207 default: 208 return BIT_ULL(dwrr_mtu); 209 } 210 211 return 0; 212 } 213 214 u32 convert_bytes_to_dwrr_mtu(u32 bytes) 215 { 216 /* MTU used for DWRR calculation is in power of 2 up until 64K bytes. 217 * Value of 4 is reserved for MTU value of 9728 bytes. 218 * Value of 5 is reserved for MTU value of 10240 bytes. 219 */ 220 if (bytes > BIT_ULL(16)) 221 return 0; 222 223 switch (bytes) { 224 case 9728: 225 return 4; 226 case 10240: 227 return 5; 228 default: 229 return ilog2(bytes); 230 } 231 232 return 0; 233 } 234 235 static void nix_rx_sync(struct rvu *rvu, int blkaddr) 236 { 237 int err; 238 239 /* Sync all in flight RX packets to LLC/DRAM */ 240 rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); 241 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true); 242 if (err) 243 dev_err(rvu->dev, "SYNC1: NIX RX software sync failed\n"); 244 245 /* SW_SYNC ensures all existing transactions are finished and pkts 246 * are written to LLC/DRAM, queues should be teared down after 247 * successful SW_SYNC. Due to a HW errata, in some rare scenarios 248 * an existing transaction might end after SW_SYNC operation. To 249 * ensure operation is fully done, do the SW_SYNC twice. 250 */ 251 rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); 252 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true); 253 if (err) 254 dev_err(rvu->dev, "SYNC2: NIX RX software sync failed\n"); 255 } 256 257 static bool is_valid_txschq(struct rvu *rvu, int blkaddr, 258 int lvl, u16 pcifunc, u16 schq) 259 { 260 struct rvu_hwinfo *hw = rvu->hw; 261 struct nix_txsch *txsch; 262 struct nix_hw *nix_hw; 263 u16 map_func; 264 265 nix_hw = get_nix_hw(rvu->hw, blkaddr); 266 if (!nix_hw) 267 return false; 268 269 txsch = &nix_hw->txsch[lvl]; 270 /* Check out of bounds */ 271 if (schq >= txsch->schq.max) 272 return false; 273 274 mutex_lock(&rvu->rsrc_lock); 275 map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]); 276 mutex_unlock(&rvu->rsrc_lock); 277 278 /* TLs aggegating traffic are shared across PF and VFs */ 279 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 280 if (rvu_get_pf(map_func) != rvu_get_pf(pcifunc)) 281 return false; 282 else 283 return true; 284 } 285 286 if (map_func != pcifunc) 287 return false; 288 289 return true; 290 } 291 292 static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf, 293 struct nix_lf_alloc_rsp *rsp, bool loop) 294 { 295 struct rvu_pfvf *parent_pf, *pfvf = rvu_get_pfvf(rvu, pcifunc); 296 u16 req_chan_base, req_chan_end, req_chan_cnt; 297 struct rvu_hwinfo *hw = rvu->hw; 298 struct sdp_node_info *sdp_info; 299 int pkind, pf, vf, lbkid, vfid; 300 u8 cgx_id, lmac_id; 301 bool from_vf; 302 int err; 303 304 pf = rvu_get_pf(pcifunc); 305 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK && 306 type != NIX_INTF_TYPE_SDP) 307 return 0; 308 309 switch (type) { 310 case NIX_INTF_TYPE_CGX: 311 pfvf->cgx_lmac = rvu->pf2cgxlmac_map[pf]; 312 rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id); 313 314 pkind = rvu_npc_get_pkind(rvu, pf); 315 if (pkind < 0) { 316 dev_err(rvu->dev, 317 "PF_Func 0x%x: Invalid pkind\n", pcifunc); 318 return -EINVAL; 319 } 320 pfvf->rx_chan_base = rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0); 321 pfvf->tx_chan_base = pfvf->rx_chan_base; 322 pfvf->rx_chan_cnt = 1; 323 pfvf->tx_chan_cnt = 1; 324 rsp->tx_link = cgx_id * hw->lmac_per_cgx + lmac_id; 325 326 cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, pkind); 327 rvu_npc_set_pkind(rvu, pkind, pfvf); 328 329 break; 330 case NIX_INTF_TYPE_LBK: 331 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 332 333 /* If NIX1 block is present on the silicon then NIXes are 334 * assigned alternatively for lbk interfaces. NIX0 should 335 * send packets on lbk link 1 channels and NIX1 should send 336 * on lbk link 0 channels for the communication between 337 * NIX0 and NIX1. 338 */ 339 lbkid = 0; 340 if (rvu->hw->lbk_links > 1) 341 lbkid = vf & 0x1 ? 0 : 1; 342 343 /* By default NIX0 is configured to send packet on lbk link 1 344 * (which corresponds to LBK1), same packet will receive on 345 * NIX1 over lbk link 0. If NIX1 sends packet on lbk link 0 346 * (which corresponds to LBK2) packet will receive on NIX0 lbk 347 * link 1. 348 * But if lbk links for NIX0 and NIX1 are negated, i.e NIX0 349 * transmits and receives on lbk link 0, whick corresponds 350 * to LBK1 block, back to back connectivity between NIX and 351 * LBK can be achieved (which is similar to 96xx) 352 * 353 * RX TX 354 * NIX0 lbk link 1 (LBK2) 1 (LBK1) 355 * NIX0 lbk link 0 (LBK0) 0 (LBK0) 356 * NIX1 lbk link 0 (LBK1) 0 (LBK2) 357 * NIX1 lbk link 1 (LBK3) 1 (LBK3) 358 */ 359 if (loop) 360 lbkid = !lbkid; 361 362 /* Note that AF's VFs work in pairs and talk over consecutive 363 * loopback channels.Therefore if odd number of AF VFs are 364 * enabled then the last VF remains with no pair. 365 */ 366 pfvf->rx_chan_base = rvu_nix_chan_lbk(rvu, lbkid, vf); 367 pfvf->tx_chan_base = vf & 0x1 ? 368 rvu_nix_chan_lbk(rvu, lbkid, vf - 1) : 369 rvu_nix_chan_lbk(rvu, lbkid, vf + 1); 370 pfvf->rx_chan_cnt = 1; 371 pfvf->tx_chan_cnt = 1; 372 rsp->tx_link = hw->cgx_links + lbkid; 373 pfvf->lbkid = lbkid; 374 rvu_npc_set_pkind(rvu, NPC_RX_LBK_PKIND, pfvf); 375 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 376 pfvf->rx_chan_base, 377 pfvf->rx_chan_cnt); 378 379 break; 380 case NIX_INTF_TYPE_SDP: 381 from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK); 382 parent_pf = &rvu->pf[rvu_get_pf(pcifunc)]; 383 sdp_info = parent_pf->sdp_info; 384 if (!sdp_info) { 385 dev_err(rvu->dev, "Invalid sdp_info pointer\n"); 386 return -EINVAL; 387 } 388 if (from_vf) { 389 req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn + 390 sdp_info->num_pf_rings; 391 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 392 for (vfid = 0; vfid < vf; vfid++) 393 req_chan_base += sdp_info->vf_rings[vfid]; 394 req_chan_cnt = sdp_info->vf_rings[vf]; 395 req_chan_end = req_chan_base + req_chan_cnt - 1; 396 if (req_chan_base < rvu_nix_chan_sdp(rvu, 0) || 397 req_chan_end > rvu_nix_chan_sdp(rvu, 255)) { 398 dev_err(rvu->dev, 399 "PF_Func 0x%x: Invalid channel base and count\n", 400 pcifunc); 401 return -EINVAL; 402 } 403 } else { 404 req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn; 405 req_chan_cnt = sdp_info->num_pf_rings; 406 } 407 408 pfvf->rx_chan_base = req_chan_base; 409 pfvf->rx_chan_cnt = req_chan_cnt; 410 pfvf->tx_chan_base = pfvf->rx_chan_base; 411 pfvf->tx_chan_cnt = pfvf->rx_chan_cnt; 412 413 rsp->tx_link = hw->cgx_links + hw->lbk_links; 414 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 415 pfvf->rx_chan_base, 416 pfvf->rx_chan_cnt); 417 break; 418 } 419 420 /* Add a UCAST forwarding rule in MCAM with this NIXLF attached 421 * RVU PF/VF's MAC address. 422 */ 423 rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, 424 pfvf->rx_chan_base, pfvf->mac_addr); 425 426 /* Add this PF_FUNC to bcast pkt replication list */ 427 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, true); 428 if (err) { 429 dev_err(rvu->dev, 430 "Bcast list, failed to enable PF_FUNC 0x%x\n", 431 pcifunc); 432 return err; 433 } 434 /* Install MCAM rule matching Ethernet broadcast mac address */ 435 rvu_npc_install_bcast_match_entry(rvu, pcifunc, 436 nixlf, pfvf->rx_chan_base); 437 438 pfvf->maxlen = NIC_HW_MIN_FRS; 439 pfvf->minlen = NIC_HW_MIN_FRS; 440 441 return 0; 442 } 443 444 static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf) 445 { 446 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 447 int err; 448 449 pfvf->maxlen = 0; 450 pfvf->minlen = 0; 451 452 /* Remove this PF_FUNC from bcast pkt replication list */ 453 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, false); 454 if (err) { 455 dev_err(rvu->dev, 456 "Bcast list, failed to disable PF_FUNC 0x%x\n", 457 pcifunc); 458 } 459 460 /* Free and disable any MCAM entries used by this NIX LF */ 461 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 462 463 /* Disable DMAC filters used */ 464 rvu_cgx_disable_dmac_entries(rvu, pcifunc); 465 } 466 467 int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu, 468 struct nix_bp_cfg_req *req, 469 struct msg_rsp *rsp) 470 { 471 u16 pcifunc = req->hdr.pcifunc; 472 struct rvu_pfvf *pfvf; 473 int blkaddr, pf, type; 474 u16 chan_base, chan; 475 u64 cfg; 476 477 pf = rvu_get_pf(pcifunc); 478 type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 479 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK) 480 return 0; 481 482 pfvf = rvu_get_pfvf(rvu, pcifunc); 483 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 484 485 chan_base = pfvf->rx_chan_base + req->chan_base; 486 for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) { 487 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan)); 488 rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan), 489 cfg & ~BIT_ULL(16)); 490 } 491 return 0; 492 } 493 494 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, 495 int type, int chan_id) 496 { 497 int bpid, blkaddr, lmac_chan_cnt, sdp_chan_cnt; 498 u16 cgx_bpid_cnt, lbk_bpid_cnt, sdp_bpid_cnt; 499 struct rvu_hwinfo *hw = rvu->hw; 500 struct rvu_pfvf *pfvf; 501 u8 cgx_id, lmac_id; 502 u64 cfg; 503 504 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc); 505 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST); 506 lmac_chan_cnt = cfg & 0xFF; 507 508 cgx_bpid_cnt = hw->cgx_links * lmac_chan_cnt; 509 lbk_bpid_cnt = hw->lbk_links * ((cfg >> 16) & 0xFF); 510 511 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 512 sdp_chan_cnt = cfg & 0xFFF; 513 sdp_bpid_cnt = hw->sdp_links * sdp_chan_cnt; 514 515 pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 516 517 /* Backpressure IDs range division 518 * CGX channles are mapped to (0 - 191) BPIDs 519 * LBK channles are mapped to (192 - 255) BPIDs 520 * SDP channles are mapped to (256 - 511) BPIDs 521 * 522 * Lmac channles and bpids mapped as follows 523 * cgx(0)_lmac(0)_chan(0 - 15) = bpid(0 - 15) 524 * cgx(0)_lmac(1)_chan(0 - 15) = bpid(16 - 31) .... 525 * cgx(1)_lmac(0)_chan(0 - 15) = bpid(64 - 79) .... 526 */ 527 switch (type) { 528 case NIX_INTF_TYPE_CGX: 529 if ((req->chan_base + req->chan_cnt) > 16) 530 return -EINVAL; 531 rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id); 532 /* Assign bpid based on cgx, lmac and chan id */ 533 bpid = (cgx_id * hw->lmac_per_cgx * lmac_chan_cnt) + 534 (lmac_id * lmac_chan_cnt) + req->chan_base; 535 536 if (req->bpid_per_chan) 537 bpid += chan_id; 538 if (bpid > cgx_bpid_cnt) 539 return -EINVAL; 540 break; 541 542 case NIX_INTF_TYPE_LBK: 543 if ((req->chan_base + req->chan_cnt) > 63) 544 return -EINVAL; 545 bpid = cgx_bpid_cnt + req->chan_base; 546 if (req->bpid_per_chan) 547 bpid += chan_id; 548 if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt)) 549 return -EINVAL; 550 break; 551 case NIX_INTF_TYPE_SDP: 552 if ((req->chan_base + req->chan_cnt) > 255) 553 return -EINVAL; 554 555 bpid = sdp_bpid_cnt + req->chan_base; 556 if (req->bpid_per_chan) 557 bpid += chan_id; 558 559 if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt + sdp_bpid_cnt)) 560 return -EINVAL; 561 break; 562 default: 563 return -EINVAL; 564 } 565 return bpid; 566 } 567 568 int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu, 569 struct nix_bp_cfg_req *req, 570 struct nix_bp_cfg_rsp *rsp) 571 { 572 int blkaddr, pf, type, chan_id = 0; 573 u16 pcifunc = req->hdr.pcifunc; 574 struct rvu_pfvf *pfvf; 575 u16 chan_base, chan; 576 s16 bpid, bpid_base; 577 u64 cfg; 578 579 pf = rvu_get_pf(pcifunc); 580 type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 581 if (is_sdp_pfvf(pcifunc)) 582 type = NIX_INTF_TYPE_SDP; 583 584 /* Enable backpressure only for CGX mapped PFs and LBK/SDP interface */ 585 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK && 586 type != NIX_INTF_TYPE_SDP) 587 return 0; 588 589 pfvf = rvu_get_pfvf(rvu, pcifunc); 590 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 591 592 bpid_base = rvu_nix_get_bpid(rvu, req, type, chan_id); 593 chan_base = pfvf->rx_chan_base + req->chan_base; 594 bpid = bpid_base; 595 596 for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) { 597 if (bpid < 0) { 598 dev_warn(rvu->dev, "Fail to enable backpressure\n"); 599 return -EINVAL; 600 } 601 602 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan)); 603 cfg &= ~GENMASK_ULL(8, 0); 604 rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan), 605 cfg | (bpid & GENMASK_ULL(8, 0)) | BIT_ULL(16)); 606 chan_id++; 607 bpid = rvu_nix_get_bpid(rvu, req, type, chan_id); 608 } 609 610 for (chan = 0; chan < req->chan_cnt; chan++) { 611 /* Map channel and bpid assign to it */ 612 rsp->chan_bpid[chan] = ((req->chan_base + chan) & 0x7F) << 10 | 613 (bpid_base & 0x3FF); 614 if (req->bpid_per_chan) 615 bpid_base++; 616 } 617 rsp->chan_cnt = req->chan_cnt; 618 619 return 0; 620 } 621 622 static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr, 623 u64 format, bool v4, u64 *fidx) 624 { 625 struct nix_lso_format field = {0}; 626 627 /* IP's Length field */ 628 field.layer = NIX_TXLAYER_OL3; 629 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 630 field.offset = v4 ? 2 : 4; 631 field.sizem1 = 1; /* i.e 2 bytes */ 632 field.alg = NIX_LSOALG_ADD_PAYLEN; 633 rvu_write64(rvu, blkaddr, 634 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 635 *(u64 *)&field); 636 637 /* No ID field in IPv6 header */ 638 if (!v4) 639 return; 640 641 /* IP's ID field */ 642 field.layer = NIX_TXLAYER_OL3; 643 field.offset = 4; 644 field.sizem1 = 1; /* i.e 2 bytes */ 645 field.alg = NIX_LSOALG_ADD_SEGNUM; 646 rvu_write64(rvu, blkaddr, 647 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 648 *(u64 *)&field); 649 } 650 651 static void nix_setup_lso_tso_l4(struct rvu *rvu, int blkaddr, 652 u64 format, u64 *fidx) 653 { 654 struct nix_lso_format field = {0}; 655 656 /* TCP's sequence number field */ 657 field.layer = NIX_TXLAYER_OL4; 658 field.offset = 4; 659 field.sizem1 = 3; /* i.e 4 bytes */ 660 field.alg = NIX_LSOALG_ADD_OFFSET; 661 rvu_write64(rvu, blkaddr, 662 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 663 *(u64 *)&field); 664 665 /* TCP's flags field */ 666 field.layer = NIX_TXLAYER_OL4; 667 field.offset = 12; 668 field.sizem1 = 1; /* 2 bytes */ 669 field.alg = NIX_LSOALG_TCP_FLAGS; 670 rvu_write64(rvu, blkaddr, 671 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 672 *(u64 *)&field); 673 } 674 675 static void nix_setup_lso(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 676 { 677 u64 cfg, idx, fidx = 0; 678 679 /* Get max HW supported format indices */ 680 cfg = (rvu_read64(rvu, blkaddr, NIX_AF_CONST1) >> 48) & 0xFF; 681 nix_hw->lso.total = cfg; 682 683 /* Enable LSO */ 684 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LSO_CFG); 685 /* For TSO, set first and middle segment flags to 686 * mask out PSH, RST & FIN flags in TCP packet 687 */ 688 cfg &= ~((0xFFFFULL << 32) | (0xFFFFULL << 16)); 689 cfg |= (0xFFF2ULL << 32) | (0xFFF2ULL << 16); 690 rvu_write64(rvu, blkaddr, NIX_AF_LSO_CFG, cfg | BIT_ULL(63)); 691 692 /* Setup default static LSO formats 693 * 694 * Configure format fields for TCPv4 segmentation offload 695 */ 696 idx = NIX_LSO_FORMAT_IDX_TSOV4; 697 nix_setup_lso_tso_l3(rvu, blkaddr, idx, true, &fidx); 698 nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx); 699 700 /* Set rest of the fields to NOP */ 701 for (; fidx < 8; fidx++) { 702 rvu_write64(rvu, blkaddr, 703 NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL); 704 } 705 nix_hw->lso.in_use++; 706 707 /* Configure format fields for TCPv6 segmentation offload */ 708 idx = NIX_LSO_FORMAT_IDX_TSOV6; 709 fidx = 0; 710 nix_setup_lso_tso_l3(rvu, blkaddr, idx, false, &fidx); 711 nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx); 712 713 /* Set rest of the fields to NOP */ 714 for (; fidx < 8; fidx++) { 715 rvu_write64(rvu, blkaddr, 716 NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL); 717 } 718 nix_hw->lso.in_use++; 719 } 720 721 static void nix_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf) 722 { 723 kfree(pfvf->rq_bmap); 724 kfree(pfvf->sq_bmap); 725 kfree(pfvf->cq_bmap); 726 if (pfvf->rq_ctx) 727 qmem_free(rvu->dev, pfvf->rq_ctx); 728 if (pfvf->sq_ctx) 729 qmem_free(rvu->dev, pfvf->sq_ctx); 730 if (pfvf->cq_ctx) 731 qmem_free(rvu->dev, pfvf->cq_ctx); 732 if (pfvf->rss_ctx) 733 qmem_free(rvu->dev, pfvf->rss_ctx); 734 if (pfvf->nix_qints_ctx) 735 qmem_free(rvu->dev, pfvf->nix_qints_ctx); 736 if (pfvf->cq_ints_ctx) 737 qmem_free(rvu->dev, pfvf->cq_ints_ctx); 738 739 pfvf->rq_bmap = NULL; 740 pfvf->cq_bmap = NULL; 741 pfvf->sq_bmap = NULL; 742 pfvf->rq_ctx = NULL; 743 pfvf->sq_ctx = NULL; 744 pfvf->cq_ctx = NULL; 745 pfvf->rss_ctx = NULL; 746 pfvf->nix_qints_ctx = NULL; 747 pfvf->cq_ints_ctx = NULL; 748 } 749 750 static int nixlf_rss_ctx_init(struct rvu *rvu, int blkaddr, 751 struct rvu_pfvf *pfvf, int nixlf, 752 int rss_sz, int rss_grps, int hwctx_size, 753 u64 way_mask, bool tag_lsb_as_adder) 754 { 755 int err, grp, num_indices; 756 u64 val; 757 758 /* RSS is not requested for this NIXLF */ 759 if (!rss_sz) 760 return 0; 761 num_indices = rss_sz * rss_grps; 762 763 /* Alloc NIX RSS HW context memory and config the base */ 764 err = qmem_alloc(rvu->dev, &pfvf->rss_ctx, num_indices, hwctx_size); 765 if (err) 766 return err; 767 768 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_BASE(nixlf), 769 (u64)pfvf->rss_ctx->iova); 770 771 /* Config full RSS table size, enable RSS and caching */ 772 val = BIT_ULL(36) | BIT_ULL(4) | way_mask << 20 | 773 ilog2(num_indices / MAX_RSS_INDIR_TBL_SIZE); 774 775 if (tag_lsb_as_adder) 776 val |= BIT_ULL(5); 777 778 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf), val); 779 /* Config RSS group offset and sizes */ 780 for (grp = 0; grp < rss_grps; grp++) 781 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_GRPX(nixlf, grp), 782 ((ilog2(rss_sz) - 1) << 16) | (rss_sz * grp)); 783 return 0; 784 } 785 786 static int nix_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block, 787 struct nix_aq_inst_s *inst) 788 { 789 struct admin_queue *aq = block->aq; 790 struct nix_aq_res_s *result; 791 int timeout = 1000; 792 u64 reg, head; 793 794 result = (struct nix_aq_res_s *)aq->res->base; 795 796 /* Get current head pointer where to append this instruction */ 797 reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS); 798 head = (reg >> 4) & AQ_PTR_MASK; 799 800 memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)), 801 (void *)inst, aq->inst->entry_sz); 802 memset(result, 0, sizeof(*result)); 803 /* sync into memory */ 804 wmb(); 805 806 /* Ring the doorbell and wait for result */ 807 rvu_write64(rvu, block->addr, NIX_AF_AQ_DOOR, 1); 808 while (result->compcode == NIX_AQ_COMP_NOTDONE) { 809 cpu_relax(); 810 udelay(1); 811 timeout--; 812 if (!timeout) 813 return -EBUSY; 814 } 815 816 if (result->compcode != NIX_AQ_COMP_GOOD) 817 /* TODO: Replace this with some error code */ 818 return -EBUSY; 819 820 return 0; 821 } 822 823 static int rvu_nix_blk_aq_enq_inst(struct rvu *rvu, struct nix_hw *nix_hw, 824 struct nix_aq_enq_req *req, 825 struct nix_aq_enq_rsp *rsp) 826 { 827 struct rvu_hwinfo *hw = rvu->hw; 828 u16 pcifunc = req->hdr.pcifunc; 829 int nixlf, blkaddr, rc = 0; 830 struct nix_aq_inst_s inst; 831 struct rvu_block *block; 832 struct admin_queue *aq; 833 struct rvu_pfvf *pfvf; 834 void *ctx, *mask; 835 bool ena; 836 u64 cfg; 837 838 blkaddr = nix_hw->blkaddr; 839 block = &hw->block[blkaddr]; 840 aq = block->aq; 841 if (!aq) { 842 dev_warn(rvu->dev, "%s: NIX AQ not initialized\n", __func__); 843 return NIX_AF_ERR_AQ_ENQUEUE; 844 } 845 846 pfvf = rvu_get_pfvf(rvu, pcifunc); 847 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 848 849 /* Skip NIXLF check for broadcast MCE entry and bandwidth profile 850 * operations done by AF itself. 851 */ 852 if (!((!rsp && req->ctype == NIX_AQ_CTYPE_MCE) || 853 (req->ctype == NIX_AQ_CTYPE_BANDPROF && !pcifunc))) { 854 if (!pfvf->nixlf || nixlf < 0) 855 return NIX_AF_ERR_AF_LF_INVALID; 856 } 857 858 switch (req->ctype) { 859 case NIX_AQ_CTYPE_RQ: 860 /* Check if index exceeds max no of queues */ 861 if (!pfvf->rq_ctx || req->qidx >= pfvf->rq_ctx->qsize) 862 rc = NIX_AF_ERR_AQ_ENQUEUE; 863 break; 864 case NIX_AQ_CTYPE_SQ: 865 if (!pfvf->sq_ctx || req->qidx >= pfvf->sq_ctx->qsize) 866 rc = NIX_AF_ERR_AQ_ENQUEUE; 867 break; 868 case NIX_AQ_CTYPE_CQ: 869 if (!pfvf->cq_ctx || req->qidx >= pfvf->cq_ctx->qsize) 870 rc = NIX_AF_ERR_AQ_ENQUEUE; 871 break; 872 case NIX_AQ_CTYPE_RSS: 873 /* Check if RSS is enabled and qidx is within range */ 874 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf)); 875 if (!(cfg & BIT_ULL(4)) || !pfvf->rss_ctx || 876 (req->qidx >= (256UL << (cfg & 0xF)))) 877 rc = NIX_AF_ERR_AQ_ENQUEUE; 878 break; 879 case NIX_AQ_CTYPE_MCE: 880 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG); 881 882 /* Check if index exceeds MCE list length */ 883 if (!nix_hw->mcast.mce_ctx || 884 (req->qidx >= (256UL << (cfg & 0xF)))) 885 rc = NIX_AF_ERR_AQ_ENQUEUE; 886 887 /* Adding multicast lists for requests from PF/VFs is not 888 * yet supported, so ignore this. 889 */ 890 if (rsp) 891 rc = NIX_AF_ERR_AQ_ENQUEUE; 892 break; 893 case NIX_AQ_CTYPE_BANDPROF: 894 if (nix_verify_bandprof((struct nix_cn10k_aq_enq_req *)req, 895 nix_hw, pcifunc)) 896 rc = NIX_AF_ERR_INVALID_BANDPROF; 897 break; 898 default: 899 rc = NIX_AF_ERR_AQ_ENQUEUE; 900 } 901 902 if (rc) 903 return rc; 904 905 /* Check if SQ pointed SMQ belongs to this PF/VF or not */ 906 if (req->ctype == NIX_AQ_CTYPE_SQ && 907 ((req->op == NIX_AQ_INSTOP_INIT && req->sq.ena) || 908 (req->op == NIX_AQ_INSTOP_WRITE && 909 req->sq_mask.ena && req->sq_mask.smq && req->sq.ena))) { 910 if (!is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_SMQ, 911 pcifunc, req->sq.smq)) 912 return NIX_AF_ERR_AQ_ENQUEUE; 913 } 914 915 memset(&inst, 0, sizeof(struct nix_aq_inst_s)); 916 inst.lf = nixlf; 917 inst.cindex = req->qidx; 918 inst.ctype = req->ctype; 919 inst.op = req->op; 920 /* Currently we are not supporting enqueuing multiple instructions, 921 * so always choose first entry in result memory. 922 */ 923 inst.res_addr = (u64)aq->res->iova; 924 925 /* Hardware uses same aq->res->base for updating result of 926 * previous instruction hence wait here till it is done. 927 */ 928 spin_lock(&aq->lock); 929 930 /* Clean result + context memory */ 931 memset(aq->res->base, 0, aq->res->entry_sz); 932 /* Context needs to be written at RES_ADDR + 128 */ 933 ctx = aq->res->base + 128; 934 /* Mask needs to be written at RES_ADDR + 256 */ 935 mask = aq->res->base + 256; 936 937 switch (req->op) { 938 case NIX_AQ_INSTOP_WRITE: 939 if (req->ctype == NIX_AQ_CTYPE_RQ) 940 memcpy(mask, &req->rq_mask, 941 sizeof(struct nix_rq_ctx_s)); 942 else if (req->ctype == NIX_AQ_CTYPE_SQ) 943 memcpy(mask, &req->sq_mask, 944 sizeof(struct nix_sq_ctx_s)); 945 else if (req->ctype == NIX_AQ_CTYPE_CQ) 946 memcpy(mask, &req->cq_mask, 947 sizeof(struct nix_cq_ctx_s)); 948 else if (req->ctype == NIX_AQ_CTYPE_RSS) 949 memcpy(mask, &req->rss_mask, 950 sizeof(struct nix_rsse_s)); 951 else if (req->ctype == NIX_AQ_CTYPE_MCE) 952 memcpy(mask, &req->mce_mask, 953 sizeof(struct nix_rx_mce_s)); 954 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 955 memcpy(mask, &req->prof_mask, 956 sizeof(struct nix_bandprof_s)); 957 fallthrough; 958 case NIX_AQ_INSTOP_INIT: 959 if (req->ctype == NIX_AQ_CTYPE_RQ) 960 memcpy(ctx, &req->rq, sizeof(struct nix_rq_ctx_s)); 961 else if (req->ctype == NIX_AQ_CTYPE_SQ) 962 memcpy(ctx, &req->sq, sizeof(struct nix_sq_ctx_s)); 963 else if (req->ctype == NIX_AQ_CTYPE_CQ) 964 memcpy(ctx, &req->cq, sizeof(struct nix_cq_ctx_s)); 965 else if (req->ctype == NIX_AQ_CTYPE_RSS) 966 memcpy(ctx, &req->rss, sizeof(struct nix_rsse_s)); 967 else if (req->ctype == NIX_AQ_CTYPE_MCE) 968 memcpy(ctx, &req->mce, sizeof(struct nix_rx_mce_s)); 969 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 970 memcpy(ctx, &req->prof, sizeof(struct nix_bandprof_s)); 971 break; 972 case NIX_AQ_INSTOP_NOP: 973 case NIX_AQ_INSTOP_READ: 974 case NIX_AQ_INSTOP_LOCK: 975 case NIX_AQ_INSTOP_UNLOCK: 976 break; 977 default: 978 rc = NIX_AF_ERR_AQ_ENQUEUE; 979 spin_unlock(&aq->lock); 980 return rc; 981 } 982 983 /* Submit the instruction to AQ */ 984 rc = nix_aq_enqueue_wait(rvu, block, &inst); 985 if (rc) { 986 spin_unlock(&aq->lock); 987 return rc; 988 } 989 990 /* Set RQ/SQ/CQ bitmap if respective queue hw context is enabled */ 991 if (req->op == NIX_AQ_INSTOP_INIT) { 992 if (req->ctype == NIX_AQ_CTYPE_RQ && req->rq.ena) 993 __set_bit(req->qidx, pfvf->rq_bmap); 994 if (req->ctype == NIX_AQ_CTYPE_SQ && req->sq.ena) 995 __set_bit(req->qidx, pfvf->sq_bmap); 996 if (req->ctype == NIX_AQ_CTYPE_CQ && req->cq.ena) 997 __set_bit(req->qidx, pfvf->cq_bmap); 998 } 999 1000 if (req->op == NIX_AQ_INSTOP_WRITE) { 1001 if (req->ctype == NIX_AQ_CTYPE_RQ) { 1002 ena = (req->rq.ena & req->rq_mask.ena) | 1003 (test_bit(req->qidx, pfvf->rq_bmap) & 1004 ~req->rq_mask.ena); 1005 if (ena) 1006 __set_bit(req->qidx, pfvf->rq_bmap); 1007 else 1008 __clear_bit(req->qidx, pfvf->rq_bmap); 1009 } 1010 if (req->ctype == NIX_AQ_CTYPE_SQ) { 1011 ena = (req->rq.ena & req->sq_mask.ena) | 1012 (test_bit(req->qidx, pfvf->sq_bmap) & 1013 ~req->sq_mask.ena); 1014 if (ena) 1015 __set_bit(req->qidx, pfvf->sq_bmap); 1016 else 1017 __clear_bit(req->qidx, pfvf->sq_bmap); 1018 } 1019 if (req->ctype == NIX_AQ_CTYPE_CQ) { 1020 ena = (req->rq.ena & req->cq_mask.ena) | 1021 (test_bit(req->qidx, pfvf->cq_bmap) & 1022 ~req->cq_mask.ena); 1023 if (ena) 1024 __set_bit(req->qidx, pfvf->cq_bmap); 1025 else 1026 __clear_bit(req->qidx, pfvf->cq_bmap); 1027 } 1028 } 1029 1030 if (rsp) { 1031 /* Copy read context into mailbox */ 1032 if (req->op == NIX_AQ_INSTOP_READ) { 1033 if (req->ctype == NIX_AQ_CTYPE_RQ) 1034 memcpy(&rsp->rq, ctx, 1035 sizeof(struct nix_rq_ctx_s)); 1036 else if (req->ctype == NIX_AQ_CTYPE_SQ) 1037 memcpy(&rsp->sq, ctx, 1038 sizeof(struct nix_sq_ctx_s)); 1039 else if (req->ctype == NIX_AQ_CTYPE_CQ) 1040 memcpy(&rsp->cq, ctx, 1041 sizeof(struct nix_cq_ctx_s)); 1042 else if (req->ctype == NIX_AQ_CTYPE_RSS) 1043 memcpy(&rsp->rss, ctx, 1044 sizeof(struct nix_rsse_s)); 1045 else if (req->ctype == NIX_AQ_CTYPE_MCE) 1046 memcpy(&rsp->mce, ctx, 1047 sizeof(struct nix_rx_mce_s)); 1048 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 1049 memcpy(&rsp->prof, ctx, 1050 sizeof(struct nix_bandprof_s)); 1051 } 1052 } 1053 1054 spin_unlock(&aq->lock); 1055 return 0; 1056 } 1057 1058 static int rvu_nix_verify_aq_ctx(struct rvu *rvu, struct nix_hw *nix_hw, 1059 struct nix_aq_enq_req *req, u8 ctype) 1060 { 1061 struct nix_cn10k_aq_enq_req aq_req; 1062 struct nix_cn10k_aq_enq_rsp aq_rsp; 1063 int rc, word; 1064 1065 if (req->ctype != NIX_AQ_CTYPE_CQ) 1066 return 0; 1067 1068 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 1069 req->hdr.pcifunc, ctype, req->qidx); 1070 if (rc) { 1071 dev_err(rvu->dev, 1072 "%s: Failed to fetch %s%d context of PFFUNC 0x%x\n", 1073 __func__, nix_get_ctx_name(ctype), req->qidx, 1074 req->hdr.pcifunc); 1075 return rc; 1076 } 1077 1078 /* Make copy of original context & mask which are required 1079 * for resubmission 1080 */ 1081 memcpy(&aq_req.cq_mask, &req->cq_mask, sizeof(struct nix_cq_ctx_s)); 1082 memcpy(&aq_req.cq, &req->cq, sizeof(struct nix_cq_ctx_s)); 1083 1084 /* exclude fields which HW can update */ 1085 aq_req.cq_mask.cq_err = 0; 1086 aq_req.cq_mask.wrptr = 0; 1087 aq_req.cq_mask.tail = 0; 1088 aq_req.cq_mask.head = 0; 1089 aq_req.cq_mask.avg_level = 0; 1090 aq_req.cq_mask.update_time = 0; 1091 aq_req.cq_mask.substream = 0; 1092 1093 /* Context mask (cq_mask) holds mask value of fields which 1094 * are changed in AQ WRITE operation. 1095 * for example cq.drop = 0xa; 1096 * cq_mask.drop = 0xff; 1097 * Below logic performs '&' between cq and cq_mask so that non 1098 * updated fields are masked out for request and response 1099 * comparison 1100 */ 1101 for (word = 0; word < sizeof(struct nix_cq_ctx_s) / sizeof(u64); 1102 word++) { 1103 *(u64 *)((u8 *)&aq_rsp.cq + word * 8) &= 1104 (*(u64 *)((u8 *)&aq_req.cq_mask + word * 8)); 1105 *(u64 *)((u8 *)&aq_req.cq + word * 8) &= 1106 (*(u64 *)((u8 *)&aq_req.cq_mask + word * 8)); 1107 } 1108 1109 if (memcmp(&aq_req.cq, &aq_rsp.cq, sizeof(struct nix_cq_ctx_s))) 1110 return NIX_AF_ERR_AQ_CTX_RETRY_WRITE; 1111 1112 return 0; 1113 } 1114 1115 static int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req, 1116 struct nix_aq_enq_rsp *rsp) 1117 { 1118 struct nix_hw *nix_hw; 1119 int err, retries = 5; 1120 int blkaddr; 1121 1122 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc); 1123 if (blkaddr < 0) 1124 return NIX_AF_ERR_AF_LF_INVALID; 1125 1126 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1127 if (!nix_hw) 1128 return NIX_AF_ERR_INVALID_NIXBLK; 1129 1130 retry: 1131 err = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, req, rsp); 1132 1133 /* HW errata 'AQ Modification to CQ could be discarded on heavy traffic' 1134 * As a work around perfrom CQ context read after each AQ write. If AQ 1135 * read shows AQ write is not updated perform AQ write again. 1136 */ 1137 if (!err && req->op == NIX_AQ_INSTOP_WRITE) { 1138 err = rvu_nix_verify_aq_ctx(rvu, nix_hw, req, NIX_AQ_CTYPE_CQ); 1139 if (err == NIX_AF_ERR_AQ_CTX_RETRY_WRITE) { 1140 if (retries--) 1141 goto retry; 1142 else 1143 return NIX_AF_ERR_CQ_CTX_WRITE_ERR; 1144 } 1145 } 1146 1147 return err; 1148 } 1149 1150 static const char *nix_get_ctx_name(int ctype) 1151 { 1152 switch (ctype) { 1153 case NIX_AQ_CTYPE_CQ: 1154 return "CQ"; 1155 case NIX_AQ_CTYPE_SQ: 1156 return "SQ"; 1157 case NIX_AQ_CTYPE_RQ: 1158 return "RQ"; 1159 case NIX_AQ_CTYPE_RSS: 1160 return "RSS"; 1161 } 1162 return ""; 1163 } 1164 1165 static int nix_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req *req) 1166 { 1167 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 1168 struct nix_aq_enq_req aq_req; 1169 unsigned long *bmap; 1170 int qidx, q_cnt = 0; 1171 int err = 0, rc; 1172 1173 if (!pfvf->cq_ctx || !pfvf->sq_ctx || !pfvf->rq_ctx) 1174 return NIX_AF_ERR_AQ_ENQUEUE; 1175 1176 memset(&aq_req, 0, sizeof(struct nix_aq_enq_req)); 1177 aq_req.hdr.pcifunc = req->hdr.pcifunc; 1178 1179 if (req->ctype == NIX_AQ_CTYPE_CQ) { 1180 aq_req.cq.ena = 0; 1181 aq_req.cq_mask.ena = 1; 1182 aq_req.cq.bp_ena = 0; 1183 aq_req.cq_mask.bp_ena = 1; 1184 q_cnt = pfvf->cq_ctx->qsize; 1185 bmap = pfvf->cq_bmap; 1186 } 1187 if (req->ctype == NIX_AQ_CTYPE_SQ) { 1188 aq_req.sq.ena = 0; 1189 aq_req.sq_mask.ena = 1; 1190 q_cnt = pfvf->sq_ctx->qsize; 1191 bmap = pfvf->sq_bmap; 1192 } 1193 if (req->ctype == NIX_AQ_CTYPE_RQ) { 1194 aq_req.rq.ena = 0; 1195 aq_req.rq_mask.ena = 1; 1196 q_cnt = pfvf->rq_ctx->qsize; 1197 bmap = pfvf->rq_bmap; 1198 } 1199 1200 aq_req.ctype = req->ctype; 1201 aq_req.op = NIX_AQ_INSTOP_WRITE; 1202 1203 for (qidx = 0; qidx < q_cnt; qidx++) { 1204 if (!test_bit(qidx, bmap)) 1205 continue; 1206 aq_req.qidx = qidx; 1207 rc = rvu_nix_aq_enq_inst(rvu, &aq_req, NULL); 1208 if (rc) { 1209 err = rc; 1210 dev_err(rvu->dev, "Failed to disable %s:%d context\n", 1211 nix_get_ctx_name(req->ctype), qidx); 1212 } 1213 } 1214 1215 return err; 1216 } 1217 1218 #ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING 1219 static int nix_lf_hwctx_lockdown(struct rvu *rvu, struct nix_aq_enq_req *req) 1220 { 1221 struct nix_aq_enq_req lock_ctx_req; 1222 int err; 1223 1224 if (req->op != NIX_AQ_INSTOP_INIT) 1225 return 0; 1226 1227 if (req->ctype == NIX_AQ_CTYPE_MCE || 1228 req->ctype == NIX_AQ_CTYPE_DYNO) 1229 return 0; 1230 1231 memset(&lock_ctx_req, 0, sizeof(struct nix_aq_enq_req)); 1232 lock_ctx_req.hdr.pcifunc = req->hdr.pcifunc; 1233 lock_ctx_req.ctype = req->ctype; 1234 lock_ctx_req.op = NIX_AQ_INSTOP_LOCK; 1235 lock_ctx_req.qidx = req->qidx; 1236 err = rvu_nix_aq_enq_inst(rvu, &lock_ctx_req, NULL); 1237 if (err) 1238 dev_err(rvu->dev, 1239 "PFUNC 0x%x: Failed to lock NIX %s:%d context\n", 1240 req->hdr.pcifunc, 1241 nix_get_ctx_name(req->ctype), req->qidx); 1242 return err; 1243 } 1244 1245 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, 1246 struct nix_aq_enq_req *req, 1247 struct nix_aq_enq_rsp *rsp) 1248 { 1249 int err; 1250 1251 err = rvu_nix_aq_enq_inst(rvu, req, rsp); 1252 if (!err) 1253 err = nix_lf_hwctx_lockdown(rvu, req); 1254 return err; 1255 } 1256 #else 1257 1258 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, 1259 struct nix_aq_enq_req *req, 1260 struct nix_aq_enq_rsp *rsp) 1261 { 1262 return rvu_nix_aq_enq_inst(rvu, req, rsp); 1263 } 1264 #endif 1265 /* CN10K mbox handler */ 1266 int rvu_mbox_handler_nix_cn10k_aq_enq(struct rvu *rvu, 1267 struct nix_cn10k_aq_enq_req *req, 1268 struct nix_cn10k_aq_enq_rsp *rsp) 1269 { 1270 return rvu_nix_aq_enq_inst(rvu, (struct nix_aq_enq_req *)req, 1271 (struct nix_aq_enq_rsp *)rsp); 1272 } 1273 1274 int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu, 1275 struct hwctx_disable_req *req, 1276 struct msg_rsp *rsp) 1277 { 1278 return nix_lf_hwctx_disable(rvu, req); 1279 } 1280 1281 int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, 1282 struct nix_lf_alloc_req *req, 1283 struct nix_lf_alloc_rsp *rsp) 1284 { 1285 int nixlf, qints, hwctx_size, intf, err, rc = 0; 1286 struct rvu_hwinfo *hw = rvu->hw; 1287 u16 pcifunc = req->hdr.pcifunc; 1288 struct rvu_block *block; 1289 struct rvu_pfvf *pfvf; 1290 u64 cfg, ctx_cfg; 1291 int blkaddr; 1292 1293 if (!req->rq_cnt || !req->sq_cnt || !req->cq_cnt) 1294 return NIX_AF_ERR_PARAM; 1295 1296 if (req->way_mask) 1297 req->way_mask &= 0xFFFF; 1298 1299 pfvf = rvu_get_pfvf(rvu, pcifunc); 1300 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1301 if (!pfvf->nixlf || blkaddr < 0) 1302 return NIX_AF_ERR_AF_LF_INVALID; 1303 1304 block = &hw->block[blkaddr]; 1305 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 1306 if (nixlf < 0) 1307 return NIX_AF_ERR_AF_LF_INVALID; 1308 1309 /* Check if requested 'NIXLF <=> NPALF' mapping is valid */ 1310 if (req->npa_func) { 1311 /* If default, use 'this' NIXLF's PFFUNC */ 1312 if (req->npa_func == RVU_DEFAULT_PF_FUNC) 1313 req->npa_func = pcifunc; 1314 if (!is_pffunc_map_valid(rvu, req->npa_func, BLKTYPE_NPA)) 1315 return NIX_AF_INVAL_NPA_PF_FUNC; 1316 } 1317 1318 /* Check if requested 'NIXLF <=> SSOLF' mapping is valid */ 1319 if (req->sso_func) { 1320 /* If default, use 'this' NIXLF's PFFUNC */ 1321 if (req->sso_func == RVU_DEFAULT_PF_FUNC) 1322 req->sso_func = pcifunc; 1323 if (!is_pffunc_map_valid(rvu, req->sso_func, BLKTYPE_SSO)) 1324 return NIX_AF_INVAL_SSO_PF_FUNC; 1325 } 1326 1327 /* If RSS is being enabled, check if requested config is valid. 1328 * RSS table size should be power of two, otherwise 1329 * RSS_GRP::OFFSET + adder might go beyond that group or 1330 * won't be able to use entire table. 1331 */ 1332 if (req->rss_sz && (req->rss_sz > MAX_RSS_INDIR_TBL_SIZE || 1333 !is_power_of_2(req->rss_sz))) 1334 return NIX_AF_ERR_RSS_SIZE_INVALID; 1335 1336 if (req->rss_sz && 1337 (!req->rss_grps || req->rss_grps > MAX_RSS_GROUPS)) 1338 return NIX_AF_ERR_RSS_GRPS_INVALID; 1339 1340 /* Reset this NIX LF */ 1341 err = rvu_lf_reset(rvu, block, nixlf); 1342 if (err) { 1343 dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", 1344 block->addr - BLKADDR_NIX0, nixlf); 1345 return NIX_AF_ERR_LF_RESET; 1346 } 1347 1348 ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3); 1349 1350 /* Alloc NIX RQ HW context memory and config the base */ 1351 hwctx_size = 1UL << ((ctx_cfg >> 4) & 0xF); 1352 err = qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size); 1353 if (err) 1354 goto free_mem; 1355 1356 pfvf->rq_bmap = kcalloc(req->rq_cnt, sizeof(long), GFP_KERNEL); 1357 if (!pfvf->rq_bmap) 1358 goto free_mem; 1359 1360 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_BASE(nixlf), 1361 (u64)pfvf->rq_ctx->iova); 1362 1363 /* Set caching and queue count in HW */ 1364 cfg = BIT_ULL(36) | (req->rq_cnt - 1) | req->way_mask << 20; 1365 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_CFG(nixlf), cfg); 1366 1367 /* Alloc NIX SQ HW context memory and config the base */ 1368 hwctx_size = 1UL << (ctx_cfg & 0xF); 1369 err = qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size); 1370 if (err) 1371 goto free_mem; 1372 1373 pfvf->sq_bmap = kcalloc(req->sq_cnt, sizeof(long), GFP_KERNEL); 1374 if (!pfvf->sq_bmap) 1375 goto free_mem; 1376 1377 rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_BASE(nixlf), 1378 (u64)pfvf->sq_ctx->iova); 1379 1380 cfg = BIT_ULL(36) | (req->sq_cnt - 1) | req->way_mask << 20; 1381 rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_CFG(nixlf), cfg); 1382 1383 /* Alloc NIX CQ HW context memory and config the base */ 1384 hwctx_size = 1UL << ((ctx_cfg >> 8) & 0xF); 1385 err = qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size); 1386 if (err) 1387 goto free_mem; 1388 1389 pfvf->cq_bmap = kcalloc(req->cq_cnt, sizeof(long), GFP_KERNEL); 1390 if (!pfvf->cq_bmap) 1391 goto free_mem; 1392 1393 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_BASE(nixlf), 1394 (u64)pfvf->cq_ctx->iova); 1395 1396 cfg = BIT_ULL(36) | (req->cq_cnt - 1) | req->way_mask << 20; 1397 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_CFG(nixlf), cfg); 1398 1399 /* Initialize receive side scaling (RSS) */ 1400 hwctx_size = 1UL << ((ctx_cfg >> 12) & 0xF); 1401 err = nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, req->rss_sz, 1402 req->rss_grps, hwctx_size, req->way_mask, 1403 !!(req->flags & NIX_LF_RSS_TAG_LSB_AS_ADDER)); 1404 if (err) 1405 goto free_mem; 1406 1407 /* Alloc memory for CQINT's HW contexts */ 1408 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1409 qints = (cfg >> 24) & 0xFFF; 1410 hwctx_size = 1UL << ((ctx_cfg >> 24) & 0xF); 1411 err = qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size); 1412 if (err) 1413 goto free_mem; 1414 1415 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_BASE(nixlf), 1416 (u64)pfvf->cq_ints_ctx->iova); 1417 1418 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_CFG(nixlf), 1419 BIT_ULL(36) | req->way_mask << 20); 1420 1421 /* Alloc memory for QINT's HW contexts */ 1422 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1423 qints = (cfg >> 12) & 0xFFF; 1424 hwctx_size = 1UL << ((ctx_cfg >> 20) & 0xF); 1425 err = qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size); 1426 if (err) 1427 goto free_mem; 1428 1429 rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_BASE(nixlf), 1430 (u64)pfvf->nix_qints_ctx->iova); 1431 rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_CFG(nixlf), 1432 BIT_ULL(36) | req->way_mask << 20); 1433 1434 /* Setup VLANX TPID's. 1435 * Use VLAN1 for 802.1Q 1436 * and VLAN0 for 802.1AD. 1437 */ 1438 cfg = (0x8100ULL << 16) | 0x88A8ULL; 1439 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg); 1440 1441 /* Enable LMTST for this NIX LF */ 1442 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG2(nixlf), BIT_ULL(0)); 1443 1444 /* Set CQE/WQE size, NPA_PF_FUNC for SQBs and also SSO_PF_FUNC */ 1445 if (req->npa_func) 1446 cfg = req->npa_func; 1447 if (req->sso_func) 1448 cfg |= (u64)req->sso_func << 16; 1449 1450 cfg |= (u64)req->xqe_sz << 33; 1451 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf), cfg); 1452 1453 /* Config Rx pkt length, csum checks and apad enable / disable */ 1454 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), req->rx_cfg); 1455 1456 /* Configure pkind for TX parse config */ 1457 cfg = NPC_TX_DEF_PKIND; 1458 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg); 1459 1460 intf = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 1461 if (is_sdp_pfvf(pcifunc)) 1462 intf = NIX_INTF_TYPE_SDP; 1463 1464 err = nix_interface_init(rvu, pcifunc, intf, nixlf, rsp, 1465 !!(req->flags & NIX_LF_LBK_BLK_SEL)); 1466 if (err) 1467 goto free_mem; 1468 1469 /* Disable NPC entries as NIXLF's contexts are not initialized yet */ 1470 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 1471 1472 /* Configure RX VTAG Type 7 (strip) for vf vlan */ 1473 rvu_write64(rvu, blkaddr, 1474 NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, NIX_AF_LFX_RX_VTAG_TYPE7), 1475 VTAGSIZE_T4 | VTAG_STRIP); 1476 1477 goto exit; 1478 1479 free_mem: 1480 nix_ctx_free(rvu, pfvf); 1481 rc = -ENOMEM; 1482 1483 exit: 1484 /* Set macaddr of this PF/VF */ 1485 ether_addr_copy(rsp->mac_addr, pfvf->mac_addr); 1486 1487 /* set SQB size info */ 1488 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQ_CONST); 1489 rsp->sqb_size = (cfg >> 34) & 0xFFFF; 1490 rsp->rx_chan_base = pfvf->rx_chan_base; 1491 rsp->tx_chan_base = pfvf->tx_chan_base; 1492 rsp->rx_chan_cnt = pfvf->rx_chan_cnt; 1493 rsp->tx_chan_cnt = pfvf->tx_chan_cnt; 1494 rsp->lso_tsov4_idx = NIX_LSO_FORMAT_IDX_TSOV4; 1495 rsp->lso_tsov6_idx = NIX_LSO_FORMAT_IDX_TSOV6; 1496 /* Get HW supported stat count */ 1497 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 1498 rsp->lf_rx_stats = ((cfg >> 32) & 0xFF); 1499 rsp->lf_tx_stats = ((cfg >> 24) & 0xFF); 1500 /* Get count of CQ IRQs and error IRQs supported per LF */ 1501 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1502 rsp->qints = ((cfg >> 12) & 0xFFF); 1503 rsp->cints = ((cfg >> 24) & 0xFFF); 1504 rsp->cgx_links = hw->cgx_links; 1505 rsp->lbk_links = hw->lbk_links; 1506 rsp->sdp_links = hw->sdp_links; 1507 1508 return rc; 1509 } 1510 1511 int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct nix_lf_free_req *req, 1512 struct msg_rsp *rsp) 1513 { 1514 struct rvu_hwinfo *hw = rvu->hw; 1515 u16 pcifunc = req->hdr.pcifunc; 1516 struct rvu_block *block; 1517 int blkaddr, nixlf, err; 1518 struct rvu_pfvf *pfvf; 1519 1520 pfvf = rvu_get_pfvf(rvu, pcifunc); 1521 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1522 if (!pfvf->nixlf || blkaddr < 0) 1523 return NIX_AF_ERR_AF_LF_INVALID; 1524 1525 block = &hw->block[blkaddr]; 1526 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 1527 if (nixlf < 0) 1528 return NIX_AF_ERR_AF_LF_INVALID; 1529 1530 if (req->flags & NIX_LF_DISABLE_FLOWS) 1531 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 1532 else 1533 rvu_npc_free_mcam_entries(rvu, pcifunc, nixlf); 1534 1535 /* Free any tx vtag def entries used by this NIX LF */ 1536 if (!(req->flags & NIX_LF_DONT_FREE_TX_VTAG)) 1537 nix_free_tx_vtag_entries(rvu, pcifunc); 1538 1539 nix_interface_deinit(rvu, pcifunc, nixlf); 1540 1541 /* Reset this NIX LF */ 1542 err = rvu_lf_reset(rvu, block, nixlf); 1543 if (err) { 1544 dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", 1545 block->addr - BLKADDR_NIX0, nixlf); 1546 return NIX_AF_ERR_LF_RESET; 1547 } 1548 1549 nix_ctx_free(rvu, pfvf); 1550 1551 return 0; 1552 } 1553 1554 int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu, 1555 struct nix_mark_format_cfg *req, 1556 struct nix_mark_format_cfg_rsp *rsp) 1557 { 1558 u16 pcifunc = req->hdr.pcifunc; 1559 struct nix_hw *nix_hw; 1560 struct rvu_pfvf *pfvf; 1561 int blkaddr, rc; 1562 u32 cfg; 1563 1564 pfvf = rvu_get_pfvf(rvu, pcifunc); 1565 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1566 if (!pfvf->nixlf || blkaddr < 0) 1567 return NIX_AF_ERR_AF_LF_INVALID; 1568 1569 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1570 if (!nix_hw) 1571 return NIX_AF_ERR_INVALID_NIXBLK; 1572 1573 cfg = (((u32)req->offset & 0x7) << 16) | 1574 (((u32)req->y_mask & 0xF) << 12) | 1575 (((u32)req->y_val & 0xF) << 8) | 1576 (((u32)req->r_mask & 0xF) << 4) | ((u32)req->r_val & 0xF); 1577 1578 rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfg); 1579 if (rc < 0) { 1580 dev_err(rvu->dev, "No mark_format_ctl for (pf:%d, vf:%d)", 1581 rvu_get_pf(pcifunc), pcifunc & RVU_PFVF_FUNC_MASK); 1582 return NIX_AF_ERR_MARK_CFG_FAIL; 1583 } 1584 1585 rsp->mark_format_idx = rc; 1586 return 0; 1587 } 1588 1589 /* Handle shaper update specially for few revisions */ 1590 static bool 1591 handle_txschq_shaper_update(struct rvu *rvu, int blkaddr, int nixlf, 1592 int lvl, u64 reg, u64 regval) 1593 { 1594 u64 regbase, oldval, sw_xoff = 0; 1595 u64 dbgval, md_debug0 = 0; 1596 unsigned long poll_tmo; 1597 bool rate_reg = 0; 1598 u32 schq; 1599 1600 regbase = reg & 0xFFFF; 1601 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 1602 1603 /* Check for rate register */ 1604 switch (lvl) { 1605 case NIX_TXSCH_LVL_TL1: 1606 md_debug0 = NIX_AF_TL1X_MD_DEBUG0(schq); 1607 sw_xoff = NIX_AF_TL1X_SW_XOFF(schq); 1608 1609 rate_reg = !!(regbase == NIX_AF_TL1X_CIR(0)); 1610 break; 1611 case NIX_TXSCH_LVL_TL2: 1612 md_debug0 = NIX_AF_TL2X_MD_DEBUG0(schq); 1613 sw_xoff = NIX_AF_TL2X_SW_XOFF(schq); 1614 1615 rate_reg = (regbase == NIX_AF_TL2X_CIR(0) || 1616 regbase == NIX_AF_TL2X_PIR(0)); 1617 break; 1618 case NIX_TXSCH_LVL_TL3: 1619 md_debug0 = NIX_AF_TL3X_MD_DEBUG0(schq); 1620 sw_xoff = NIX_AF_TL3X_SW_XOFF(schq); 1621 1622 rate_reg = (regbase == NIX_AF_TL3X_CIR(0) || 1623 regbase == NIX_AF_TL3X_PIR(0)); 1624 break; 1625 case NIX_TXSCH_LVL_TL4: 1626 md_debug0 = NIX_AF_TL4X_MD_DEBUG0(schq); 1627 sw_xoff = NIX_AF_TL4X_SW_XOFF(schq); 1628 1629 rate_reg = (regbase == NIX_AF_TL4X_CIR(0) || 1630 regbase == NIX_AF_TL4X_PIR(0)); 1631 break; 1632 case NIX_TXSCH_LVL_MDQ: 1633 sw_xoff = NIX_AF_MDQX_SW_XOFF(schq); 1634 rate_reg = (regbase == NIX_AF_MDQX_CIR(0) || 1635 regbase == NIX_AF_MDQX_PIR(0)); 1636 break; 1637 } 1638 1639 if (!rate_reg) 1640 return false; 1641 1642 /* Nothing special to do when state is not toggled */ 1643 oldval = rvu_read64(rvu, blkaddr, reg); 1644 if ((oldval & 0x1) == (regval & 0x1)) { 1645 rvu_write64(rvu, blkaddr, reg, regval); 1646 return true; 1647 } 1648 1649 /* PIR/CIR disable */ 1650 if (!(regval & 0x1)) { 1651 rvu_write64(rvu, blkaddr, sw_xoff, 1); 1652 rvu_write64(rvu, blkaddr, reg, 0); 1653 udelay(4); 1654 rvu_write64(rvu, blkaddr, sw_xoff, 0); 1655 return true; 1656 } 1657 1658 /* PIR/CIR enable */ 1659 rvu_write64(rvu, blkaddr, sw_xoff, 1); 1660 if (md_debug0) { 1661 poll_tmo = jiffies + usecs_to_jiffies(10000); 1662 /* Wait until VLD(bit32) == 1 or C_CON(bit48) == 0 */ 1663 do { 1664 if (time_after(jiffies, poll_tmo)) { 1665 dev_err(rvu->dev, 1666 "NIXLF%d: TLX%u(lvl %u) CIR/PIR enable failed\n", 1667 nixlf, schq, lvl); 1668 goto exit; 1669 } 1670 usleep_range(1, 5); 1671 dbgval = rvu_read64(rvu, blkaddr, md_debug0); 1672 } while (!(dbgval & BIT_ULL(32)) && (dbgval & BIT_ULL(48))); 1673 } 1674 rvu_write64(rvu, blkaddr, reg, regval); 1675 exit: 1676 rvu_write64(rvu, blkaddr, sw_xoff, 0); 1677 return true; 1678 } 1679 1680 /* Disable shaping of pkts by a scheduler queue 1681 * at a given scheduler level. 1682 */ 1683 static void nix_reset_tx_shaping(struct rvu *rvu, int blkaddr, 1684 int nixlf, int lvl, int schq) 1685 { 1686 struct rvu_hwinfo *hw = rvu->hw; 1687 u64 cir_reg = 0, pir_reg = 0; 1688 u64 cfg; 1689 1690 switch (lvl) { 1691 case NIX_TXSCH_LVL_TL1: 1692 cir_reg = NIX_AF_TL1X_CIR(schq); 1693 pir_reg = 0; /* PIR not available at TL1 */ 1694 break; 1695 case NIX_TXSCH_LVL_TL2: 1696 cir_reg = NIX_AF_TL2X_CIR(schq); 1697 pir_reg = NIX_AF_TL2X_PIR(schq); 1698 break; 1699 case NIX_TXSCH_LVL_TL3: 1700 cir_reg = NIX_AF_TL3X_CIR(schq); 1701 pir_reg = NIX_AF_TL3X_PIR(schq); 1702 break; 1703 case NIX_TXSCH_LVL_TL4: 1704 cir_reg = NIX_AF_TL4X_CIR(schq); 1705 pir_reg = NIX_AF_TL4X_PIR(schq); 1706 break; 1707 case NIX_TXSCH_LVL_MDQ: 1708 cir_reg = NIX_AF_MDQX_CIR(schq); 1709 pir_reg = NIX_AF_MDQX_PIR(schq); 1710 break; 1711 } 1712 1713 /* Shaper state toggle needs wait/poll */ 1714 if (hw->cap.nix_shaper_toggle_wait) { 1715 if (cir_reg) 1716 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 1717 lvl, cir_reg, 0); 1718 if (pir_reg) 1719 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 1720 lvl, pir_reg, 0); 1721 return; 1722 } 1723 1724 if (!cir_reg) 1725 return; 1726 cfg = rvu_read64(rvu, blkaddr, cir_reg); 1727 rvu_write64(rvu, blkaddr, cir_reg, cfg & ~BIT_ULL(0)); 1728 1729 if (!pir_reg) 1730 return; 1731 cfg = rvu_read64(rvu, blkaddr, pir_reg); 1732 rvu_write64(rvu, blkaddr, pir_reg, cfg & ~BIT_ULL(0)); 1733 } 1734 1735 static void nix_reset_tx_linkcfg(struct rvu *rvu, int blkaddr, 1736 int lvl, int schq) 1737 { 1738 struct rvu_hwinfo *hw = rvu->hw; 1739 int link_level; 1740 int link; 1741 1742 if (lvl >= hw->cap.nix_tx_aggr_lvl) 1743 return; 1744 1745 /* Reset TL4's SDP link config */ 1746 if (lvl == NIX_TXSCH_LVL_TL4) 1747 rvu_write64(rvu, blkaddr, NIX_AF_TL4X_SDP_LINK_CFG(schq), 0x00); 1748 1749 link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ? 1750 NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2; 1751 if (lvl != link_level) 1752 return; 1753 1754 /* Reset TL2's CGX or LBK link config */ 1755 for (link = 0; link < (hw->cgx_links + hw->lbk_links); link++) 1756 rvu_write64(rvu, blkaddr, 1757 NIX_AF_TL3_TL2X_LINKX_CFG(schq, link), 0x00); 1758 } 1759 1760 static void nix_clear_tx_xoff(struct rvu *rvu, int blkaddr, 1761 int lvl, int schq) 1762 { 1763 struct rvu_hwinfo *hw = rvu->hw; 1764 u64 reg; 1765 1766 /* Skip this if shaping is not supported */ 1767 if (!hw->cap.nix_shaping) 1768 return; 1769 1770 /* Clear level specific SW_XOFF */ 1771 switch (lvl) { 1772 case NIX_TXSCH_LVL_TL1: 1773 reg = NIX_AF_TL1X_SW_XOFF(schq); 1774 break; 1775 case NIX_TXSCH_LVL_TL2: 1776 reg = NIX_AF_TL2X_SW_XOFF(schq); 1777 break; 1778 case NIX_TXSCH_LVL_TL3: 1779 reg = NIX_AF_TL3X_SW_XOFF(schq); 1780 break; 1781 case NIX_TXSCH_LVL_TL4: 1782 reg = NIX_AF_TL4X_SW_XOFF(schq); 1783 break; 1784 case NIX_TXSCH_LVL_MDQ: 1785 reg = NIX_AF_MDQX_SW_XOFF(schq); 1786 break; 1787 default: 1788 return; 1789 } 1790 1791 rvu_write64(rvu, blkaddr, reg, 0x0); 1792 } 1793 1794 static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc) 1795 { 1796 struct rvu_hwinfo *hw = rvu->hw; 1797 int pf = rvu_get_pf(pcifunc); 1798 u8 cgx_id = 0, lmac_id = 0; 1799 1800 if (is_afvf(pcifunc)) {/* LBK links */ 1801 return hw->cgx_links; 1802 } else if (is_pf_cgxmapped(rvu, pf)) { 1803 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1804 return (cgx_id * hw->lmac_per_cgx) + lmac_id; 1805 } 1806 1807 /* SDP link */ 1808 return hw->cgx_links + hw->lbk_links; 1809 } 1810 1811 static void nix_get_txschq_range(struct rvu *rvu, u16 pcifunc, 1812 int link, int *start, int *end) 1813 { 1814 struct rvu_hwinfo *hw = rvu->hw; 1815 int pf = rvu_get_pf(pcifunc); 1816 1817 if (is_afvf(pcifunc)) { /* LBK links */ 1818 *start = hw->cap.nix_txsch_per_cgx_lmac * link; 1819 *end = *start + hw->cap.nix_txsch_per_lbk_lmac; 1820 } else if (is_pf_cgxmapped(rvu, pf)) { /* CGX links */ 1821 *start = hw->cap.nix_txsch_per_cgx_lmac * link; 1822 *end = *start + hw->cap.nix_txsch_per_cgx_lmac; 1823 } else { /* SDP link */ 1824 *start = (hw->cap.nix_txsch_per_cgx_lmac * hw->cgx_links) + 1825 (hw->cap.nix_txsch_per_lbk_lmac * hw->lbk_links); 1826 *end = *start + hw->cap.nix_txsch_per_sdp_lmac; 1827 } 1828 } 1829 1830 static int nix_check_txschq_alloc_req(struct rvu *rvu, int lvl, u16 pcifunc, 1831 struct nix_hw *nix_hw, 1832 struct nix_txsch_alloc_req *req) 1833 { 1834 struct rvu_hwinfo *hw = rvu->hw; 1835 int schq, req_schq, free_cnt; 1836 struct nix_txsch *txsch; 1837 int link, start, end; 1838 1839 txsch = &nix_hw->txsch[lvl]; 1840 req_schq = req->schq_contig[lvl] + req->schq[lvl]; 1841 1842 if (!req_schq) 1843 return 0; 1844 1845 link = nix_get_tx_link(rvu, pcifunc); 1846 1847 /* For traffic aggregating scheduler level, one queue is enough */ 1848 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 1849 if (req_schq != 1) 1850 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1851 return 0; 1852 } 1853 1854 /* Get free SCHQ count and check if request can be accomodated */ 1855 if (hw->cap.nix_fixed_txschq_mapping) { 1856 nix_get_txschq_range(rvu, pcifunc, link, &start, &end); 1857 schq = start + (pcifunc & RVU_PFVF_FUNC_MASK); 1858 if (end <= txsch->schq.max && schq < end && 1859 !test_bit(schq, txsch->schq.bmap)) 1860 free_cnt = 1; 1861 else 1862 free_cnt = 0; 1863 } else { 1864 free_cnt = rvu_rsrc_free_count(&txsch->schq); 1865 } 1866 1867 if (free_cnt < req_schq || req_schq > MAX_TXSCHQ_PER_FUNC) 1868 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1869 1870 /* If contiguous queues are needed, check for availability */ 1871 if (!hw->cap.nix_fixed_txschq_mapping && req->schq_contig[lvl] && 1872 !rvu_rsrc_check_contig(&txsch->schq, req->schq_contig[lvl])) 1873 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1874 1875 return 0; 1876 } 1877 1878 static void nix_txsch_alloc(struct rvu *rvu, struct nix_txsch *txsch, 1879 struct nix_txsch_alloc_rsp *rsp, 1880 int lvl, int start, int end) 1881 { 1882 struct rvu_hwinfo *hw = rvu->hw; 1883 u16 pcifunc = rsp->hdr.pcifunc; 1884 int idx, schq; 1885 1886 /* For traffic aggregating levels, queue alloc is based 1887 * on transmit link to which PF_FUNC is mapped to. 1888 */ 1889 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 1890 /* A single TL queue is allocated */ 1891 if (rsp->schq_contig[lvl]) { 1892 rsp->schq_contig[lvl] = 1; 1893 rsp->schq_contig_list[lvl][0] = start; 1894 } 1895 1896 /* Both contig and non-contig reqs doesn't make sense here */ 1897 if (rsp->schq_contig[lvl]) 1898 rsp->schq[lvl] = 0; 1899 1900 if (rsp->schq[lvl]) { 1901 rsp->schq[lvl] = 1; 1902 rsp->schq_list[lvl][0] = start; 1903 } 1904 return; 1905 } 1906 1907 /* Adjust the queue request count if HW supports 1908 * only one queue per level configuration. 1909 */ 1910 if (hw->cap.nix_fixed_txschq_mapping) { 1911 idx = pcifunc & RVU_PFVF_FUNC_MASK; 1912 schq = start + idx; 1913 if (idx >= (end - start) || test_bit(schq, txsch->schq.bmap)) { 1914 rsp->schq_contig[lvl] = 0; 1915 rsp->schq[lvl] = 0; 1916 return; 1917 } 1918 1919 if (rsp->schq_contig[lvl]) { 1920 rsp->schq_contig[lvl] = 1; 1921 set_bit(schq, txsch->schq.bmap); 1922 rsp->schq_contig_list[lvl][0] = schq; 1923 rsp->schq[lvl] = 0; 1924 } else if (rsp->schq[lvl]) { 1925 rsp->schq[lvl] = 1; 1926 set_bit(schq, txsch->schq.bmap); 1927 rsp->schq_list[lvl][0] = schq; 1928 } 1929 return; 1930 } 1931 1932 /* Allocate contiguous queue indices requesty first */ 1933 if (rsp->schq_contig[lvl]) { 1934 schq = bitmap_find_next_zero_area(txsch->schq.bmap, 1935 txsch->schq.max, start, 1936 rsp->schq_contig[lvl], 0); 1937 if (schq >= end) 1938 rsp->schq_contig[lvl] = 0; 1939 for (idx = 0; idx < rsp->schq_contig[lvl]; idx++) { 1940 set_bit(schq, txsch->schq.bmap); 1941 rsp->schq_contig_list[lvl][idx] = schq; 1942 schq++; 1943 } 1944 } 1945 1946 /* Allocate non-contiguous queue indices */ 1947 if (rsp->schq[lvl]) { 1948 idx = 0; 1949 for (schq = start; schq < end; schq++) { 1950 if (!test_bit(schq, txsch->schq.bmap)) { 1951 set_bit(schq, txsch->schq.bmap); 1952 rsp->schq_list[lvl][idx++] = schq; 1953 } 1954 if (idx == rsp->schq[lvl]) 1955 break; 1956 } 1957 /* Update how many were allocated */ 1958 rsp->schq[lvl] = idx; 1959 } 1960 } 1961 1962 int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu, 1963 struct nix_txsch_alloc_req *req, 1964 struct nix_txsch_alloc_rsp *rsp) 1965 { 1966 struct rvu_hwinfo *hw = rvu->hw; 1967 u16 pcifunc = req->hdr.pcifunc; 1968 int link, blkaddr, rc = 0; 1969 int lvl, idx, start, end; 1970 struct nix_txsch *txsch; 1971 struct nix_hw *nix_hw; 1972 u32 *pfvf_map; 1973 int nixlf; 1974 u16 schq; 1975 1976 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 1977 if (rc) 1978 return rc; 1979 1980 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1981 if (!nix_hw) 1982 return NIX_AF_ERR_INVALID_NIXBLK; 1983 1984 mutex_lock(&rvu->rsrc_lock); 1985 1986 /* Check if request is valid as per HW capabilities 1987 * and can be accomodated. 1988 */ 1989 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1990 rc = nix_check_txschq_alloc_req(rvu, lvl, pcifunc, nix_hw, req); 1991 if (rc) 1992 goto err; 1993 } 1994 1995 /* Allocate requested Tx scheduler queues */ 1996 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1997 txsch = &nix_hw->txsch[lvl]; 1998 pfvf_map = txsch->pfvf_map; 1999 2000 if (!req->schq[lvl] && !req->schq_contig[lvl]) 2001 continue; 2002 2003 rsp->schq[lvl] = req->schq[lvl]; 2004 rsp->schq_contig[lvl] = req->schq_contig[lvl]; 2005 2006 link = nix_get_tx_link(rvu, pcifunc); 2007 2008 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 2009 start = link; 2010 end = link; 2011 } else if (hw->cap.nix_fixed_txschq_mapping) { 2012 nix_get_txschq_range(rvu, pcifunc, link, &start, &end); 2013 } else { 2014 start = 0; 2015 end = txsch->schq.max; 2016 } 2017 2018 nix_txsch_alloc(rvu, txsch, rsp, lvl, start, end); 2019 2020 /* Reset queue config */ 2021 for (idx = 0; idx < req->schq_contig[lvl]; idx++) { 2022 schq = rsp->schq_contig_list[lvl][idx]; 2023 if (!(TXSCH_MAP_FLAGS(pfvf_map[schq]) & 2024 NIX_TXSCHQ_CFG_DONE)) 2025 pfvf_map[schq] = TXSCH_MAP(pcifunc, 0); 2026 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2027 nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq); 2028 } 2029 2030 for (idx = 0; idx < req->schq[lvl]; idx++) { 2031 schq = rsp->schq_list[lvl][idx]; 2032 if (!(TXSCH_MAP_FLAGS(pfvf_map[schq]) & 2033 NIX_TXSCHQ_CFG_DONE)) 2034 pfvf_map[schq] = TXSCH_MAP(pcifunc, 0); 2035 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2036 nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq); 2037 } 2038 } 2039 2040 rsp->aggr_level = hw->cap.nix_tx_aggr_lvl; 2041 rsp->aggr_lvl_rr_prio = TXSCH_TL1_DFLT_RR_PRIO; 2042 rsp->link_cfg_lvl = rvu_read64(rvu, blkaddr, 2043 NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ? 2044 NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2; 2045 goto exit; 2046 err: 2047 rc = NIX_AF_ERR_TLX_ALLOC_FAIL; 2048 exit: 2049 mutex_unlock(&rvu->rsrc_lock); 2050 return rc; 2051 } 2052 2053 static int nix_smq_flush(struct rvu *rvu, int blkaddr, 2054 int smq, u16 pcifunc, int nixlf) 2055 { 2056 int pf = rvu_get_pf(pcifunc); 2057 u8 cgx_id = 0, lmac_id = 0; 2058 int err, restore_tx_en = 0; 2059 u64 cfg; 2060 2061 if (!is_rvu_otx2(rvu)) { 2062 /* Skip SMQ flush if pkt count is zero */ 2063 cfg = rvu_read64(rvu, blkaddr, NIX_AF_MDQX_IN_MD_COUNT(smq)); 2064 if (!cfg) 2065 return 0; 2066 } 2067 2068 /* enable cgx tx if disabled */ 2069 if (is_pf_cgxmapped(rvu, pf)) { 2070 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 2071 restore_tx_en = !rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), 2072 lmac_id, true); 2073 } 2074 2075 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq)); 2076 /* Do SMQ flush and set enqueue xoff */ 2077 cfg |= BIT_ULL(50) | BIT_ULL(49); 2078 rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg); 2079 2080 /* Disable backpressure from physical link, 2081 * otherwise SMQ flush may stall. 2082 */ 2083 rvu_cgx_enadis_rx_bp(rvu, pf, false); 2084 2085 /* Wait for flush to complete */ 2086 err = rvu_poll_reg(rvu, blkaddr, 2087 NIX_AF_SMQX_CFG(smq), BIT_ULL(49), true); 2088 if (err) 2089 dev_err(rvu->dev, 2090 "NIXLF%d: SMQ%d flush failed\n", nixlf, smq); 2091 2092 rvu_cgx_enadis_rx_bp(rvu, pf, true); 2093 /* restore cgx tx state */ 2094 if (restore_tx_en) 2095 rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false); 2096 return err; 2097 } 2098 2099 static int nix_txschq_free(struct rvu *rvu, u16 pcifunc) 2100 { 2101 int blkaddr, nixlf, lvl, schq, err; 2102 struct rvu_hwinfo *hw = rvu->hw; 2103 struct nix_txsch *txsch; 2104 struct nix_hw *nix_hw; 2105 u16 map_func; 2106 2107 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2108 if (blkaddr < 0) 2109 return NIX_AF_ERR_AF_LF_INVALID; 2110 2111 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2112 if (!nix_hw) 2113 return NIX_AF_ERR_INVALID_NIXBLK; 2114 2115 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2116 if (nixlf < 0) 2117 return NIX_AF_ERR_AF_LF_INVALID; 2118 2119 /* Disable TL2/3 queue links and all XOFF's before SMQ flush*/ 2120 mutex_lock(&rvu->rsrc_lock); 2121 for (lvl = NIX_TXSCH_LVL_MDQ; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2122 txsch = &nix_hw->txsch[lvl]; 2123 2124 if (lvl >= hw->cap.nix_tx_aggr_lvl) 2125 continue; 2126 2127 for (schq = 0; schq < txsch->schq.max; schq++) { 2128 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2129 continue; 2130 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2131 nix_clear_tx_xoff(rvu, blkaddr, lvl, schq); 2132 } 2133 } 2134 nix_clear_tx_xoff(rvu, blkaddr, NIX_TXSCH_LVL_TL1, 2135 nix_get_tx_link(rvu, pcifunc)); 2136 2137 /* On PF cleanup, clear cfg done flag as 2138 * PF would have changed default config. 2139 */ 2140 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) { 2141 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL1]; 2142 schq = nix_get_tx_link(rvu, pcifunc); 2143 /* Do not clear pcifunc in txsch->pfvf_map[schq] because 2144 * VF might be using this TL1 queue 2145 */ 2146 map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]); 2147 txsch->pfvf_map[schq] = TXSCH_SET_FLAG(map_func, 0x0); 2148 } 2149 2150 /* Flush SMQs */ 2151 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 2152 for (schq = 0; schq < txsch->schq.max; schq++) { 2153 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2154 continue; 2155 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf); 2156 } 2157 2158 /* Now free scheduler queues to free pool */ 2159 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2160 /* TLs above aggregation level are shared across all PF 2161 * and it's VFs, hence skip freeing them. 2162 */ 2163 if (lvl >= hw->cap.nix_tx_aggr_lvl) 2164 continue; 2165 2166 txsch = &nix_hw->txsch[lvl]; 2167 for (schq = 0; schq < txsch->schq.max; schq++) { 2168 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2169 continue; 2170 rvu_free_rsrc(&txsch->schq, schq); 2171 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 2172 } 2173 } 2174 mutex_unlock(&rvu->rsrc_lock); 2175 2176 /* Sync cached info for this LF in NDC-TX to LLC/DRAM */ 2177 rvu_write64(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12) | nixlf); 2178 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12), true); 2179 if (err) 2180 dev_err(rvu->dev, "NDC-TX sync failed for NIXLF %d\n", nixlf); 2181 2182 return 0; 2183 } 2184 2185 static int nix_txschq_free_one(struct rvu *rvu, 2186 struct nix_txsch_free_req *req) 2187 { 2188 struct rvu_hwinfo *hw = rvu->hw; 2189 u16 pcifunc = req->hdr.pcifunc; 2190 int lvl, schq, nixlf, blkaddr; 2191 struct nix_txsch *txsch; 2192 struct nix_hw *nix_hw; 2193 u32 *pfvf_map; 2194 int rc; 2195 2196 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2197 if (blkaddr < 0) 2198 return NIX_AF_ERR_AF_LF_INVALID; 2199 2200 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2201 if (!nix_hw) 2202 return NIX_AF_ERR_INVALID_NIXBLK; 2203 2204 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2205 if (nixlf < 0) 2206 return NIX_AF_ERR_AF_LF_INVALID; 2207 2208 lvl = req->schq_lvl; 2209 schq = req->schq; 2210 txsch = &nix_hw->txsch[lvl]; 2211 2212 if (lvl >= hw->cap.nix_tx_aggr_lvl || schq >= txsch->schq.max) 2213 return 0; 2214 2215 pfvf_map = txsch->pfvf_map; 2216 mutex_lock(&rvu->rsrc_lock); 2217 2218 if (TXSCH_MAP_FUNC(pfvf_map[schq]) != pcifunc) { 2219 rc = NIX_AF_ERR_TLX_INVALID; 2220 goto err; 2221 } 2222 2223 /* Clear SW_XOFF of this resource only. 2224 * For SMQ level, all path XOFF's 2225 * need to be made clear by user 2226 */ 2227 nix_clear_tx_xoff(rvu, blkaddr, lvl, schq); 2228 2229 /* Flush if it is a SMQ. Onus of disabling 2230 * TL2/3 queue links before SMQ flush is on user 2231 */ 2232 if (lvl == NIX_TXSCH_LVL_SMQ && 2233 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf)) { 2234 rc = NIX_AF_SMQ_FLUSH_FAILED; 2235 goto err; 2236 } 2237 2238 /* Free the resource */ 2239 rvu_free_rsrc(&txsch->schq, schq); 2240 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 2241 mutex_unlock(&rvu->rsrc_lock); 2242 return 0; 2243 err: 2244 mutex_unlock(&rvu->rsrc_lock); 2245 return rc; 2246 } 2247 2248 int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu, 2249 struct nix_txsch_free_req *req, 2250 struct msg_rsp *rsp) 2251 { 2252 if (req->flags & TXSCHQ_FREE_ALL) 2253 return nix_txschq_free(rvu, req->hdr.pcifunc); 2254 else 2255 return nix_txschq_free_one(rvu, req); 2256 } 2257 2258 static bool is_txschq_hierarchy_valid(struct rvu *rvu, u16 pcifunc, int blkaddr, 2259 int lvl, u64 reg, u64 regval) 2260 { 2261 u64 regbase = reg & 0xFFFF; 2262 u16 schq, parent; 2263 2264 if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, lvl, reg)) 2265 return false; 2266 2267 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2268 /* Check if this schq belongs to this PF/VF or not */ 2269 if (!is_valid_txschq(rvu, blkaddr, lvl, pcifunc, schq)) 2270 return false; 2271 2272 parent = (regval >> 16) & 0x1FF; 2273 /* Validate MDQ's TL4 parent */ 2274 if (regbase == NIX_AF_MDQX_PARENT(0) && 2275 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL4, pcifunc, parent)) 2276 return false; 2277 2278 /* Validate TL4's TL3 parent */ 2279 if (regbase == NIX_AF_TL4X_PARENT(0) && 2280 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL3, pcifunc, parent)) 2281 return false; 2282 2283 /* Validate TL3's TL2 parent */ 2284 if (regbase == NIX_AF_TL3X_PARENT(0) && 2285 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL2, pcifunc, parent)) 2286 return false; 2287 2288 /* Validate TL2's TL1 parent */ 2289 if (regbase == NIX_AF_TL2X_PARENT(0) && 2290 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL1, pcifunc, parent)) 2291 return false; 2292 2293 return true; 2294 } 2295 2296 static bool is_txschq_shaping_valid(struct rvu_hwinfo *hw, int lvl, u64 reg) 2297 { 2298 u64 regbase; 2299 2300 if (hw->cap.nix_shaping) 2301 return true; 2302 2303 /* If shaping and coloring is not supported, then 2304 * *_CIR and *_PIR registers should not be configured. 2305 */ 2306 regbase = reg & 0xFFFF; 2307 2308 switch (lvl) { 2309 case NIX_TXSCH_LVL_TL1: 2310 if (regbase == NIX_AF_TL1X_CIR(0)) 2311 return false; 2312 break; 2313 case NIX_TXSCH_LVL_TL2: 2314 if (regbase == NIX_AF_TL2X_CIR(0) || 2315 regbase == NIX_AF_TL2X_PIR(0)) 2316 return false; 2317 break; 2318 case NIX_TXSCH_LVL_TL3: 2319 if (regbase == NIX_AF_TL3X_CIR(0) || 2320 regbase == NIX_AF_TL3X_PIR(0)) 2321 return false; 2322 break; 2323 case NIX_TXSCH_LVL_TL4: 2324 if (regbase == NIX_AF_TL4X_CIR(0) || 2325 regbase == NIX_AF_TL4X_PIR(0)) 2326 return false; 2327 break; 2328 case NIX_TXSCH_LVL_MDQ: 2329 if (regbase == NIX_AF_MDQX_CIR(0) || 2330 regbase == NIX_AF_MDQX_PIR(0)) 2331 return false; 2332 break; 2333 } 2334 return true; 2335 } 2336 2337 static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw, 2338 u16 pcifunc, int blkaddr) 2339 { 2340 u32 *pfvf_map; 2341 int schq; 2342 2343 schq = nix_get_tx_link(rvu, pcifunc); 2344 pfvf_map = nix_hw->txsch[NIX_TXSCH_LVL_TL1].pfvf_map; 2345 /* Skip if PF has already done the config */ 2346 if (TXSCH_MAP_FLAGS(pfvf_map[schq]) & NIX_TXSCHQ_CFG_DONE) 2347 return; 2348 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_TOPOLOGY(schq), 2349 (TXSCH_TL1_DFLT_RR_PRIO << 1)); 2350 2351 /* On OcteonTx2 the config was in bytes and newer silcons 2352 * it's changed to weight. 2353 */ 2354 if (!rvu->hw->cap.nix_common_dwrr_mtu) 2355 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq), 2356 TXSCH_TL1_DFLT_RR_QTM); 2357 else 2358 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq), 2359 CN10K_MAX_DWRR_WEIGHT); 2360 2361 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_CIR(schq), 0x00); 2362 pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], NIX_TXSCHQ_CFG_DONE); 2363 } 2364 2365 /* Register offset - [15:0] 2366 * Scheduler Queue number - [25:16] 2367 */ 2368 #define NIX_TX_SCHQ_MASK GENMASK_ULL(25, 0) 2369 2370 static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw, 2371 int blkaddr, struct nix_txschq_config *req, 2372 struct nix_txschq_config *rsp) 2373 { 2374 u16 pcifunc = req->hdr.pcifunc; 2375 int idx, schq; 2376 u64 reg; 2377 2378 for (idx = 0; idx < req->num_regs; idx++) { 2379 reg = req->reg[idx]; 2380 reg &= NIX_TX_SCHQ_MASK; 2381 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2382 if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, req->lvl, reg) || 2383 !is_valid_txschq(rvu, blkaddr, req->lvl, pcifunc, schq)) 2384 return NIX_AF_INVAL_TXSCHQ_CFG; 2385 rsp->regval[idx] = rvu_read64(rvu, blkaddr, reg); 2386 } 2387 rsp->lvl = req->lvl; 2388 rsp->num_regs = req->num_regs; 2389 return 0; 2390 } 2391 2392 static void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, 2393 u16 pcifunc, struct nix_txsch *txsch) 2394 { 2395 struct rvu_hwinfo *hw = rvu->hw; 2396 int lbk_link_start, lbk_links; 2397 u8 pf = rvu_get_pf(pcifunc); 2398 int schq; 2399 2400 if (!is_pf_cgxmapped(rvu, pf)) 2401 return; 2402 2403 lbk_link_start = hw->cgx_links; 2404 2405 for (schq = 0; schq < txsch->schq.max; schq++) { 2406 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2407 continue; 2408 /* Enable all LBK links with channel 63 by default so that 2409 * packets can be sent to LBK with a NPC TX MCAM rule 2410 */ 2411 lbk_links = hw->lbk_links; 2412 while (lbk_links--) 2413 rvu_write64(rvu, blkaddr, 2414 NIX_AF_TL3_TL2X_LINKX_CFG(schq, 2415 lbk_link_start + 2416 lbk_links), 2417 BIT_ULL(12) | RVU_SWITCH_LBK_CHAN); 2418 } 2419 } 2420 2421 int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu, 2422 struct nix_txschq_config *req, 2423 struct nix_txschq_config *rsp) 2424 { 2425 u64 reg, val, regval, schq_regbase, val_mask; 2426 struct rvu_hwinfo *hw = rvu->hw; 2427 u16 pcifunc = req->hdr.pcifunc; 2428 struct nix_txsch *txsch; 2429 struct nix_hw *nix_hw; 2430 int blkaddr, idx, err; 2431 int nixlf, schq; 2432 u32 *pfvf_map; 2433 2434 if (req->lvl >= NIX_TXSCH_LVL_CNT || 2435 req->num_regs > MAX_REGS_PER_MBOX_MSG) 2436 return NIX_AF_INVAL_TXSCHQ_CFG; 2437 2438 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 2439 if (err) 2440 return err; 2441 2442 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2443 if (!nix_hw) 2444 return NIX_AF_ERR_INVALID_NIXBLK; 2445 2446 if (req->read) 2447 return nix_txschq_cfg_read(rvu, nix_hw, blkaddr, req, rsp); 2448 2449 txsch = &nix_hw->txsch[req->lvl]; 2450 pfvf_map = txsch->pfvf_map; 2451 2452 if (req->lvl >= hw->cap.nix_tx_aggr_lvl && 2453 pcifunc & RVU_PFVF_FUNC_MASK) { 2454 mutex_lock(&rvu->rsrc_lock); 2455 if (req->lvl == NIX_TXSCH_LVL_TL1) 2456 nix_tl1_default_cfg(rvu, nix_hw, pcifunc, blkaddr); 2457 mutex_unlock(&rvu->rsrc_lock); 2458 return 0; 2459 } 2460 2461 for (idx = 0; idx < req->num_regs; idx++) { 2462 reg = req->reg[idx]; 2463 reg &= NIX_TX_SCHQ_MASK; 2464 regval = req->regval[idx]; 2465 schq_regbase = reg & 0xFFFF; 2466 val_mask = req->regval_mask[idx]; 2467 2468 if (!is_txschq_hierarchy_valid(rvu, pcifunc, blkaddr, 2469 txsch->lvl, reg, regval)) 2470 return NIX_AF_INVAL_TXSCHQ_CFG; 2471 2472 /* Check if shaping and coloring is supported */ 2473 if (!is_txschq_shaping_valid(hw, req->lvl, reg)) 2474 continue; 2475 2476 val = rvu_read64(rvu, blkaddr, reg); 2477 regval = (val & val_mask) | (regval & ~val_mask); 2478 2479 /* Handle shaping state toggle specially */ 2480 if (hw->cap.nix_shaper_toggle_wait && 2481 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 2482 req->lvl, reg, regval)) 2483 continue; 2484 2485 /* Replace PF/VF visible NIXLF slot with HW NIXLF id */ 2486 if (schq_regbase == NIX_AF_SMQX_CFG(0)) { 2487 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 2488 pcifunc, 0); 2489 regval &= ~(0x7FULL << 24); 2490 regval |= ((u64)nixlf << 24); 2491 } 2492 2493 /* Clear 'BP_ENA' config, if it's not allowed */ 2494 if (!hw->cap.nix_tx_link_bp) { 2495 if (schq_regbase == NIX_AF_TL4X_SDP_LINK_CFG(0) || 2496 (schq_regbase & 0xFF00) == 2497 NIX_AF_TL3_TL2X_LINKX_CFG(0, 0)) 2498 regval &= ~BIT_ULL(13); 2499 } 2500 2501 /* Mark config as done for TL1 by PF */ 2502 if (schq_regbase >= NIX_AF_TL1X_SCHEDULE(0) && 2503 schq_regbase <= NIX_AF_TL1X_GREEN_BYTES(0)) { 2504 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2505 mutex_lock(&rvu->rsrc_lock); 2506 pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], 2507 NIX_TXSCHQ_CFG_DONE); 2508 mutex_unlock(&rvu->rsrc_lock); 2509 } 2510 2511 /* SMQ flush is special hence split register writes such 2512 * that flush first and write rest of the bits later. 2513 */ 2514 if (schq_regbase == NIX_AF_SMQX_CFG(0) && 2515 (regval & BIT_ULL(49))) { 2516 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2517 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf); 2518 regval &= ~BIT_ULL(49); 2519 } 2520 rvu_write64(rvu, blkaddr, reg, regval); 2521 } 2522 2523 rvu_nix_tx_tl2_cfg(rvu, blkaddr, pcifunc, 2524 &nix_hw->txsch[NIX_TXSCH_LVL_TL2]); 2525 return 0; 2526 } 2527 2528 static int nix_rx_vtag_cfg(struct rvu *rvu, int nixlf, int blkaddr, 2529 struct nix_vtag_config *req) 2530 { 2531 u64 regval = req->vtag_size; 2532 2533 if (req->rx.vtag_type > NIX_AF_LFX_RX_VTAG_TYPE7 || 2534 req->vtag_size > VTAGSIZE_T8) 2535 return -EINVAL; 2536 2537 /* RX VTAG Type 7 reserved for vf vlan */ 2538 if (req->rx.vtag_type == NIX_AF_LFX_RX_VTAG_TYPE7) 2539 return NIX_AF_ERR_RX_VTAG_INUSE; 2540 2541 if (req->rx.capture_vtag) 2542 regval |= BIT_ULL(5); 2543 if (req->rx.strip_vtag) 2544 regval |= BIT_ULL(4); 2545 2546 rvu_write64(rvu, blkaddr, 2547 NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, req->rx.vtag_type), regval); 2548 return 0; 2549 } 2550 2551 static int nix_tx_vtag_free(struct rvu *rvu, int blkaddr, 2552 u16 pcifunc, int index) 2553 { 2554 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2555 struct nix_txvlan *vlan; 2556 2557 if (!nix_hw) 2558 return NIX_AF_ERR_INVALID_NIXBLK; 2559 2560 vlan = &nix_hw->txvlan; 2561 if (vlan->entry2pfvf_map[index] != pcifunc) 2562 return NIX_AF_ERR_PARAM; 2563 2564 rvu_write64(rvu, blkaddr, 2565 NIX_AF_TX_VTAG_DEFX_DATA(index), 0x0ull); 2566 rvu_write64(rvu, blkaddr, 2567 NIX_AF_TX_VTAG_DEFX_CTL(index), 0x0ull); 2568 2569 vlan->entry2pfvf_map[index] = 0; 2570 rvu_free_rsrc(&vlan->rsrc, index); 2571 2572 return 0; 2573 } 2574 2575 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc) 2576 { 2577 struct nix_txvlan *vlan; 2578 struct nix_hw *nix_hw; 2579 int index, blkaddr; 2580 2581 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2582 if (blkaddr < 0) 2583 return; 2584 2585 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2586 if (!nix_hw) 2587 return; 2588 2589 vlan = &nix_hw->txvlan; 2590 2591 mutex_lock(&vlan->rsrc_lock); 2592 /* Scan all the entries and free the ones mapped to 'pcifunc' */ 2593 for (index = 0; index < vlan->rsrc.max; index++) { 2594 if (vlan->entry2pfvf_map[index] == pcifunc) 2595 nix_tx_vtag_free(rvu, blkaddr, pcifunc, index); 2596 } 2597 mutex_unlock(&vlan->rsrc_lock); 2598 } 2599 2600 static int nix_tx_vtag_alloc(struct rvu *rvu, int blkaddr, 2601 u64 vtag, u8 size) 2602 { 2603 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2604 struct nix_txvlan *vlan; 2605 u64 regval; 2606 int index; 2607 2608 if (!nix_hw) 2609 return NIX_AF_ERR_INVALID_NIXBLK; 2610 2611 vlan = &nix_hw->txvlan; 2612 2613 mutex_lock(&vlan->rsrc_lock); 2614 2615 index = rvu_alloc_rsrc(&vlan->rsrc); 2616 if (index < 0) { 2617 mutex_unlock(&vlan->rsrc_lock); 2618 return index; 2619 } 2620 2621 mutex_unlock(&vlan->rsrc_lock); 2622 2623 regval = size ? vtag : vtag << 32; 2624 2625 rvu_write64(rvu, blkaddr, 2626 NIX_AF_TX_VTAG_DEFX_DATA(index), regval); 2627 rvu_write64(rvu, blkaddr, 2628 NIX_AF_TX_VTAG_DEFX_CTL(index), size); 2629 2630 return index; 2631 } 2632 2633 static int nix_tx_vtag_decfg(struct rvu *rvu, int blkaddr, 2634 struct nix_vtag_config *req) 2635 { 2636 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2637 u16 pcifunc = req->hdr.pcifunc; 2638 int idx0 = req->tx.vtag0_idx; 2639 int idx1 = req->tx.vtag1_idx; 2640 struct nix_txvlan *vlan; 2641 int err = 0; 2642 2643 if (!nix_hw) 2644 return NIX_AF_ERR_INVALID_NIXBLK; 2645 2646 vlan = &nix_hw->txvlan; 2647 if (req->tx.free_vtag0 && req->tx.free_vtag1) 2648 if (vlan->entry2pfvf_map[idx0] != pcifunc || 2649 vlan->entry2pfvf_map[idx1] != pcifunc) 2650 return NIX_AF_ERR_PARAM; 2651 2652 mutex_lock(&vlan->rsrc_lock); 2653 2654 if (req->tx.free_vtag0) { 2655 err = nix_tx_vtag_free(rvu, blkaddr, pcifunc, idx0); 2656 if (err) 2657 goto exit; 2658 } 2659 2660 if (req->tx.free_vtag1) 2661 err = nix_tx_vtag_free(rvu, blkaddr, pcifunc, idx1); 2662 2663 exit: 2664 mutex_unlock(&vlan->rsrc_lock); 2665 return err; 2666 } 2667 2668 static int nix_tx_vtag_cfg(struct rvu *rvu, int blkaddr, 2669 struct nix_vtag_config *req, 2670 struct nix_vtag_config_rsp *rsp) 2671 { 2672 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2673 struct nix_txvlan *vlan; 2674 u16 pcifunc = req->hdr.pcifunc; 2675 2676 if (!nix_hw) 2677 return NIX_AF_ERR_INVALID_NIXBLK; 2678 2679 vlan = &nix_hw->txvlan; 2680 if (req->tx.cfg_vtag0) { 2681 rsp->vtag0_idx = 2682 nix_tx_vtag_alloc(rvu, blkaddr, 2683 req->tx.vtag0, req->vtag_size); 2684 2685 if (rsp->vtag0_idx < 0) 2686 return NIX_AF_ERR_TX_VTAG_NOSPC; 2687 2688 vlan->entry2pfvf_map[rsp->vtag0_idx] = pcifunc; 2689 } 2690 2691 if (req->tx.cfg_vtag1) { 2692 rsp->vtag1_idx = 2693 nix_tx_vtag_alloc(rvu, blkaddr, 2694 req->tx.vtag1, req->vtag_size); 2695 2696 if (rsp->vtag1_idx < 0) 2697 goto err_free; 2698 2699 vlan->entry2pfvf_map[rsp->vtag1_idx] = pcifunc; 2700 } 2701 2702 return 0; 2703 2704 err_free: 2705 if (req->tx.cfg_vtag0) 2706 nix_tx_vtag_free(rvu, blkaddr, pcifunc, rsp->vtag0_idx); 2707 2708 return NIX_AF_ERR_TX_VTAG_NOSPC; 2709 } 2710 2711 int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu, 2712 struct nix_vtag_config *req, 2713 struct nix_vtag_config_rsp *rsp) 2714 { 2715 u16 pcifunc = req->hdr.pcifunc; 2716 int blkaddr, nixlf, err; 2717 2718 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 2719 if (err) 2720 return err; 2721 2722 if (req->cfg_type) { 2723 /* rx vtag configuration */ 2724 err = nix_rx_vtag_cfg(rvu, nixlf, blkaddr, req); 2725 if (err) 2726 return NIX_AF_ERR_PARAM; 2727 } else { 2728 /* tx vtag configuration */ 2729 if ((req->tx.cfg_vtag0 || req->tx.cfg_vtag1) && 2730 (req->tx.free_vtag0 || req->tx.free_vtag1)) 2731 return NIX_AF_ERR_PARAM; 2732 2733 if (req->tx.cfg_vtag0 || req->tx.cfg_vtag1) 2734 return nix_tx_vtag_cfg(rvu, blkaddr, req, rsp); 2735 2736 if (req->tx.free_vtag0 || req->tx.free_vtag1) 2737 return nix_tx_vtag_decfg(rvu, blkaddr, req); 2738 } 2739 2740 return 0; 2741 } 2742 2743 static int nix_blk_setup_mce(struct rvu *rvu, struct nix_hw *nix_hw, 2744 int mce, u8 op, u16 pcifunc, int next, bool eol) 2745 { 2746 struct nix_aq_enq_req aq_req; 2747 int err; 2748 2749 aq_req.hdr.pcifunc = 0; 2750 aq_req.ctype = NIX_AQ_CTYPE_MCE; 2751 aq_req.op = op; 2752 aq_req.qidx = mce; 2753 2754 /* Use RSS with RSS index 0 */ 2755 aq_req.mce.op = 1; 2756 aq_req.mce.index = 0; 2757 aq_req.mce.eol = eol; 2758 aq_req.mce.pf_func = pcifunc; 2759 aq_req.mce.next = next; 2760 2761 /* All fields valid */ 2762 *(u64 *)(&aq_req.mce_mask) = ~0ULL; 2763 2764 err = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, &aq_req, NULL); 2765 if (err) { 2766 dev_err(rvu->dev, "Failed to setup Bcast MCE for PF%d:VF%d\n", 2767 rvu_get_pf(pcifunc), pcifunc & RVU_PFVF_FUNC_MASK); 2768 return err; 2769 } 2770 return 0; 2771 } 2772 2773 static int nix_update_mce_list_entry(struct nix_mce_list *mce_list, 2774 u16 pcifunc, bool add) 2775 { 2776 struct mce *mce, *tail = NULL; 2777 bool delete = false; 2778 2779 /* Scan through the current list */ 2780 hlist_for_each_entry(mce, &mce_list->head, node) { 2781 /* If already exists, then delete */ 2782 if (mce->pcifunc == pcifunc && !add) { 2783 delete = true; 2784 break; 2785 } else if (mce->pcifunc == pcifunc && add) { 2786 /* entry already exists */ 2787 return 0; 2788 } 2789 tail = mce; 2790 } 2791 2792 if (delete) { 2793 hlist_del(&mce->node); 2794 kfree(mce); 2795 mce_list->count--; 2796 return 0; 2797 } 2798 2799 if (!add) 2800 return 0; 2801 2802 /* Add a new one to the list, at the tail */ 2803 mce = kzalloc(sizeof(*mce), GFP_KERNEL); 2804 if (!mce) 2805 return -ENOMEM; 2806 mce->pcifunc = pcifunc; 2807 if (!tail) 2808 hlist_add_head(&mce->node, &mce_list->head); 2809 else 2810 hlist_add_behind(&mce->node, &tail->node); 2811 mce_list->count++; 2812 return 0; 2813 } 2814 2815 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 2816 struct nix_mce_list *mce_list, 2817 int mce_idx, int mcam_index, bool add) 2818 { 2819 int err = 0, idx, next_idx, last_idx, blkaddr, npc_blkaddr; 2820 struct npc_mcam *mcam = &rvu->hw->mcam; 2821 struct nix_mcast *mcast; 2822 struct nix_hw *nix_hw; 2823 struct mce *mce; 2824 2825 if (!mce_list) 2826 return -EINVAL; 2827 2828 /* Get this PF/VF func's MCE index */ 2829 idx = mce_idx + (pcifunc & RVU_PFVF_FUNC_MASK); 2830 2831 if (idx > (mce_idx + mce_list->max)) { 2832 dev_err(rvu->dev, 2833 "%s: Idx %d > max MCE idx %d, for PF%d bcast list\n", 2834 __func__, idx, mce_list->max, 2835 pcifunc >> RVU_PFVF_PF_SHIFT); 2836 return -EINVAL; 2837 } 2838 2839 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 2840 if (err) 2841 return err; 2842 2843 mcast = &nix_hw->mcast; 2844 mutex_lock(&mcast->mce_lock); 2845 2846 err = nix_update_mce_list_entry(mce_list, pcifunc, add); 2847 if (err) 2848 goto end; 2849 2850 /* Disable MCAM entry in NPC */ 2851 if (!mce_list->count) { 2852 npc_blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2853 npc_enable_mcam_entry(rvu, mcam, npc_blkaddr, mcam_index, false); 2854 goto end; 2855 } 2856 2857 /* Dump the updated list to HW */ 2858 idx = mce_idx; 2859 last_idx = idx + mce_list->count - 1; 2860 hlist_for_each_entry(mce, &mce_list->head, node) { 2861 if (idx > last_idx) 2862 break; 2863 2864 next_idx = idx + 1; 2865 /* EOL should be set in last MCE */ 2866 err = nix_blk_setup_mce(rvu, nix_hw, idx, NIX_AQ_INSTOP_WRITE, 2867 mce->pcifunc, next_idx, 2868 (next_idx > last_idx) ? true : false); 2869 if (err) 2870 goto end; 2871 idx++; 2872 } 2873 2874 end: 2875 mutex_unlock(&mcast->mce_lock); 2876 return err; 2877 } 2878 2879 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 2880 struct nix_mce_list **mce_list, int *mce_idx) 2881 { 2882 struct rvu_hwinfo *hw = rvu->hw; 2883 struct rvu_pfvf *pfvf; 2884 2885 if (!hw->cap.nix_rx_multicast || 2886 !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc & ~RVU_PFVF_FUNC_MASK))) { 2887 *mce_list = NULL; 2888 *mce_idx = 0; 2889 return; 2890 } 2891 2892 /* Get this PF/VF func's MCE index */ 2893 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 2894 2895 if (type == NIXLF_BCAST_ENTRY) { 2896 *mce_list = &pfvf->bcast_mce_list; 2897 *mce_idx = pfvf->bcast_mce_idx; 2898 } else if (type == NIXLF_ALLMULTI_ENTRY) { 2899 *mce_list = &pfvf->mcast_mce_list; 2900 *mce_idx = pfvf->mcast_mce_idx; 2901 } else if (type == NIXLF_PROMISC_ENTRY) { 2902 *mce_list = &pfvf->promisc_mce_list; 2903 *mce_idx = pfvf->promisc_mce_idx; 2904 } else { 2905 *mce_list = NULL; 2906 *mce_idx = 0; 2907 } 2908 } 2909 2910 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc, 2911 int type, bool add) 2912 { 2913 int err = 0, nixlf, blkaddr, mcam_index, mce_idx; 2914 struct npc_mcam *mcam = &rvu->hw->mcam; 2915 struct rvu_hwinfo *hw = rvu->hw; 2916 struct nix_mce_list *mce_list; 2917 int pf; 2918 2919 /* skip multicast pkt replication for AF's VFs & SDP links */ 2920 if (is_afvf(pcifunc) || is_sdp_pfvf(pcifunc)) 2921 return 0; 2922 2923 if (!hw->cap.nix_rx_multicast) 2924 return 0; 2925 2926 pf = rvu_get_pf(pcifunc); 2927 if (!is_pf_cgxmapped(rvu, pf)) 2928 return 0; 2929 2930 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2931 if (blkaddr < 0) 2932 return -EINVAL; 2933 2934 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2935 if (nixlf < 0) 2936 return -EINVAL; 2937 2938 nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx); 2939 2940 mcam_index = npc_get_nixlf_mcam_index(mcam, 2941 pcifunc & ~RVU_PFVF_FUNC_MASK, 2942 nixlf, type); 2943 err = nix_update_mce_list(rvu, pcifunc, mce_list, 2944 mce_idx, mcam_index, add); 2945 return err; 2946 } 2947 2948 static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw) 2949 { 2950 struct nix_mcast *mcast = &nix_hw->mcast; 2951 int err, pf, numvfs, idx; 2952 struct rvu_pfvf *pfvf; 2953 u16 pcifunc; 2954 u64 cfg; 2955 2956 /* Skip PF0 (i.e AF) */ 2957 for (pf = 1; pf < (rvu->cgx_mapped_pfs + 1); pf++) { 2958 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2959 /* If PF is not enabled, nothing to do */ 2960 if (!((cfg >> 20) & 0x01)) 2961 continue; 2962 /* Get numVFs attached to this PF */ 2963 numvfs = (cfg >> 12) & 0xFF; 2964 2965 pfvf = &rvu->pf[pf]; 2966 2967 /* This NIX0/1 block mapped to PF ? */ 2968 if (pfvf->nix_blkaddr != nix_hw->blkaddr) 2969 continue; 2970 2971 /* save start idx of broadcast mce list */ 2972 pfvf->bcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2973 nix_mce_list_init(&pfvf->bcast_mce_list, numvfs + 1); 2974 2975 /* save start idx of multicast mce list */ 2976 pfvf->mcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2977 nix_mce_list_init(&pfvf->mcast_mce_list, numvfs + 1); 2978 2979 /* save the start idx of promisc mce list */ 2980 pfvf->promisc_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2981 nix_mce_list_init(&pfvf->promisc_mce_list, numvfs + 1); 2982 2983 for (idx = 0; idx < (numvfs + 1); idx++) { 2984 /* idx-0 is for PF, followed by VFs */ 2985 pcifunc = (pf << RVU_PFVF_PF_SHIFT); 2986 pcifunc |= idx; 2987 /* Add dummy entries now, so that we don't have to check 2988 * for whether AQ_OP should be INIT/WRITE later on. 2989 * Will be updated when a NIXLF is attached/detached to 2990 * these PF/VFs. 2991 */ 2992 err = nix_blk_setup_mce(rvu, nix_hw, 2993 pfvf->bcast_mce_idx + idx, 2994 NIX_AQ_INSTOP_INIT, 2995 pcifunc, 0, true); 2996 if (err) 2997 return err; 2998 2999 /* add dummy entries to multicast mce list */ 3000 err = nix_blk_setup_mce(rvu, nix_hw, 3001 pfvf->mcast_mce_idx + idx, 3002 NIX_AQ_INSTOP_INIT, 3003 pcifunc, 0, true); 3004 if (err) 3005 return err; 3006 3007 /* add dummy entries to promisc mce list */ 3008 err = nix_blk_setup_mce(rvu, nix_hw, 3009 pfvf->promisc_mce_idx + idx, 3010 NIX_AQ_INSTOP_INIT, 3011 pcifunc, 0, true); 3012 if (err) 3013 return err; 3014 } 3015 } 3016 return 0; 3017 } 3018 3019 static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 3020 { 3021 struct nix_mcast *mcast = &nix_hw->mcast; 3022 struct rvu_hwinfo *hw = rvu->hw; 3023 int err, size; 3024 3025 size = (rvu_read64(rvu, blkaddr, NIX_AF_CONST3) >> 16) & 0x0F; 3026 size = (1ULL << size); 3027 3028 /* Alloc memory for multicast/mirror replication entries */ 3029 err = qmem_alloc(rvu->dev, &mcast->mce_ctx, 3030 (256UL << MC_TBL_SIZE), size); 3031 if (err) 3032 return -ENOMEM; 3033 3034 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BASE, 3035 (u64)mcast->mce_ctx->iova); 3036 3037 /* Set max list length equal to max no of VFs per PF + PF itself */ 3038 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG, 3039 BIT_ULL(36) | (hw->max_vfs_per_pf << 4) | MC_TBL_SIZE); 3040 3041 /* Alloc memory for multicast replication buffers */ 3042 size = rvu_read64(rvu, blkaddr, NIX_AF_MC_MIRROR_CONST) & 0xFFFF; 3043 err = qmem_alloc(rvu->dev, &mcast->mcast_buf, 3044 (8UL << MC_BUF_CNT), size); 3045 if (err) 3046 return -ENOMEM; 3047 3048 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_BASE, 3049 (u64)mcast->mcast_buf->iova); 3050 3051 /* Alloc pkind for NIX internal RX multicast/mirror replay */ 3052 mcast->replay_pkind = rvu_alloc_rsrc(&hw->pkind.rsrc); 3053 3054 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_CFG, 3055 BIT_ULL(63) | (mcast->replay_pkind << 24) | 3056 BIT_ULL(20) | MC_BUF_CNT); 3057 3058 mutex_init(&mcast->mce_lock); 3059 3060 return nix_setup_mce_tables(rvu, nix_hw); 3061 } 3062 3063 static int nix_setup_txvlan(struct rvu *rvu, struct nix_hw *nix_hw) 3064 { 3065 struct nix_txvlan *vlan = &nix_hw->txvlan; 3066 int err; 3067 3068 /* Allocate resource bimap for tx vtag def registers*/ 3069 vlan->rsrc.max = NIX_TX_VTAG_DEF_MAX; 3070 err = rvu_alloc_bitmap(&vlan->rsrc); 3071 if (err) 3072 return -ENOMEM; 3073 3074 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */ 3075 vlan->entry2pfvf_map = devm_kcalloc(rvu->dev, vlan->rsrc.max, 3076 sizeof(u16), GFP_KERNEL); 3077 if (!vlan->entry2pfvf_map) 3078 goto free_mem; 3079 3080 mutex_init(&vlan->rsrc_lock); 3081 return 0; 3082 3083 free_mem: 3084 kfree(vlan->rsrc.bmap); 3085 return -ENOMEM; 3086 } 3087 3088 static int nix_setup_txschq(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 3089 { 3090 struct nix_txsch *txsch; 3091 int err, lvl, schq; 3092 u64 cfg, reg; 3093 3094 /* Get scheduler queue count of each type and alloc 3095 * bitmap for each for alloc/free/attach operations. 3096 */ 3097 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 3098 txsch = &nix_hw->txsch[lvl]; 3099 txsch->lvl = lvl; 3100 switch (lvl) { 3101 case NIX_TXSCH_LVL_SMQ: 3102 reg = NIX_AF_MDQ_CONST; 3103 break; 3104 case NIX_TXSCH_LVL_TL4: 3105 reg = NIX_AF_TL4_CONST; 3106 break; 3107 case NIX_TXSCH_LVL_TL3: 3108 reg = NIX_AF_TL3_CONST; 3109 break; 3110 case NIX_TXSCH_LVL_TL2: 3111 reg = NIX_AF_TL2_CONST; 3112 break; 3113 case NIX_TXSCH_LVL_TL1: 3114 reg = NIX_AF_TL1_CONST; 3115 break; 3116 } 3117 cfg = rvu_read64(rvu, blkaddr, reg); 3118 txsch->schq.max = cfg & 0xFFFF; 3119 err = rvu_alloc_bitmap(&txsch->schq); 3120 if (err) 3121 return err; 3122 3123 /* Allocate memory for scheduler queues to 3124 * PF/VF pcifunc mapping info. 3125 */ 3126 txsch->pfvf_map = devm_kcalloc(rvu->dev, txsch->schq.max, 3127 sizeof(u32), GFP_KERNEL); 3128 if (!txsch->pfvf_map) 3129 return -ENOMEM; 3130 for (schq = 0; schq < txsch->schq.max; schq++) 3131 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 3132 } 3133 3134 /* Setup a default value of 8192 as DWRR MTU */ 3135 if (rvu->hw->cap.nix_common_dwrr_mtu) { 3136 rvu_write64(rvu, blkaddr, NIX_AF_DWRR_RPM_MTU, 3137 convert_bytes_to_dwrr_mtu(8192)); 3138 rvu_write64(rvu, blkaddr, NIX_AF_DWRR_SDP_MTU, 3139 convert_bytes_to_dwrr_mtu(8192)); 3140 } 3141 3142 return 0; 3143 } 3144 3145 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 3146 int blkaddr, u32 cfg) 3147 { 3148 int fmt_idx; 3149 3150 for (fmt_idx = 0; fmt_idx < nix_hw->mark_format.in_use; fmt_idx++) { 3151 if (nix_hw->mark_format.cfg[fmt_idx] == cfg) 3152 return fmt_idx; 3153 } 3154 if (fmt_idx >= nix_hw->mark_format.total) 3155 return -ERANGE; 3156 3157 rvu_write64(rvu, blkaddr, NIX_AF_MARK_FORMATX_CTL(fmt_idx), cfg); 3158 nix_hw->mark_format.cfg[fmt_idx] = cfg; 3159 nix_hw->mark_format.in_use++; 3160 return fmt_idx; 3161 } 3162 3163 static int nix_af_mark_format_setup(struct rvu *rvu, struct nix_hw *nix_hw, 3164 int blkaddr) 3165 { 3166 u64 cfgs[] = { 3167 [NIX_MARK_CFG_IP_DSCP_RED] = 0x10003, 3168 [NIX_MARK_CFG_IP_DSCP_YELLOW] = 0x11200, 3169 [NIX_MARK_CFG_IP_DSCP_YELLOW_RED] = 0x11203, 3170 [NIX_MARK_CFG_IP_ECN_RED] = 0x6000c, 3171 [NIX_MARK_CFG_IP_ECN_YELLOW] = 0x60c00, 3172 [NIX_MARK_CFG_IP_ECN_YELLOW_RED] = 0x60c0c, 3173 [NIX_MARK_CFG_VLAN_DEI_RED] = 0x30008, 3174 [NIX_MARK_CFG_VLAN_DEI_YELLOW] = 0x30800, 3175 [NIX_MARK_CFG_VLAN_DEI_YELLOW_RED] = 0x30808, 3176 }; 3177 int i, rc; 3178 u64 total; 3179 3180 total = (rvu_read64(rvu, blkaddr, NIX_AF_PSE_CONST) & 0xFF00) >> 8; 3181 nix_hw->mark_format.total = (u8)total; 3182 nix_hw->mark_format.cfg = devm_kcalloc(rvu->dev, total, sizeof(u32), 3183 GFP_KERNEL); 3184 if (!nix_hw->mark_format.cfg) 3185 return -ENOMEM; 3186 for (i = 0; i < NIX_MARK_CFG_MAX; i++) { 3187 rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfgs[i]); 3188 if (rc < 0) 3189 dev_err(rvu->dev, "Err %d in setup mark format %d\n", 3190 i, rc); 3191 } 3192 3193 return 0; 3194 } 3195 3196 static void rvu_get_lbk_link_max_frs(struct rvu *rvu, u16 *max_mtu) 3197 { 3198 /* CN10K supports LBK FIFO size 72 KB */ 3199 if (rvu->hw->lbk_bufsize == 0x12000) 3200 *max_mtu = CN10K_LBK_LINK_MAX_FRS; 3201 else 3202 *max_mtu = NIC_HW_MAX_FRS; 3203 } 3204 3205 static void rvu_get_lmac_link_max_frs(struct rvu *rvu, u16 *max_mtu) 3206 { 3207 int fifo_size = rvu_cgx_get_fifolen(rvu); 3208 3209 /* RPM supports FIFO len 128 KB and RPM2 supports double the 3210 * FIFO len to accommodate 8 LMACS 3211 */ 3212 if (fifo_size == 0x20000 || fifo_size == 0x40000) 3213 *max_mtu = CN10K_LMAC_LINK_MAX_FRS; 3214 else 3215 *max_mtu = NIC_HW_MAX_FRS; 3216 } 3217 3218 int rvu_mbox_handler_nix_get_hw_info(struct rvu *rvu, struct msg_req *req, 3219 struct nix_hw_info *rsp) 3220 { 3221 u16 pcifunc = req->hdr.pcifunc; 3222 u64 dwrr_mtu; 3223 int blkaddr; 3224 3225 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 3226 if (blkaddr < 0) 3227 return NIX_AF_ERR_AF_LF_INVALID; 3228 3229 if (is_afvf(pcifunc)) 3230 rvu_get_lbk_link_max_frs(rvu, &rsp->max_mtu); 3231 else 3232 rvu_get_lmac_link_max_frs(rvu, &rsp->max_mtu); 3233 3234 rsp->min_mtu = NIC_HW_MIN_FRS; 3235 3236 if (!rvu->hw->cap.nix_common_dwrr_mtu) { 3237 /* Return '1' on OTx2 */ 3238 rsp->rpm_dwrr_mtu = 1; 3239 rsp->sdp_dwrr_mtu = 1; 3240 return 0; 3241 } 3242 3243 dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_RPM_MTU); 3244 rsp->rpm_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu); 3245 3246 dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_SDP_MTU); 3247 rsp->sdp_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu); 3248 3249 return 0; 3250 } 3251 3252 int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req, 3253 struct msg_rsp *rsp) 3254 { 3255 u16 pcifunc = req->hdr.pcifunc; 3256 int i, nixlf, blkaddr, err; 3257 u64 stats; 3258 3259 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3260 if (err) 3261 return err; 3262 3263 /* Get stats count supported by HW */ 3264 stats = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 3265 3266 /* Reset tx stats */ 3267 for (i = 0; i < ((stats >> 24) & 0xFF); i++) 3268 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_STATX(nixlf, i), 0); 3269 3270 /* Reset rx stats */ 3271 for (i = 0; i < ((stats >> 32) & 0xFF); i++) 3272 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, i), 0); 3273 3274 return 0; 3275 } 3276 3277 /* Returns the ALG index to be set into NPC_RX_ACTION */ 3278 static int get_flowkey_alg_idx(struct nix_hw *nix_hw, u32 flow_cfg) 3279 { 3280 int i; 3281 3282 /* Scan over exiting algo entries to find a match */ 3283 for (i = 0; i < nix_hw->flowkey.in_use; i++) 3284 if (nix_hw->flowkey.flowkey[i] == flow_cfg) 3285 return i; 3286 3287 return -ERANGE; 3288 } 3289 3290 static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) 3291 { 3292 int idx, nr_field, key_off, field_marker, keyoff_marker; 3293 int max_key_off, max_bit_pos, group_member; 3294 struct nix_rx_flowkey_alg *field; 3295 struct nix_rx_flowkey_alg tmp; 3296 u32 key_type, valid_key; 3297 int l4_key_offset = 0; 3298 3299 if (!alg) 3300 return -EINVAL; 3301 3302 #define FIELDS_PER_ALG 5 3303 #define MAX_KEY_OFF 40 3304 /* Clear all fields */ 3305 memset(alg, 0, sizeof(uint64_t) * FIELDS_PER_ALG); 3306 3307 /* Each of the 32 possible flow key algorithm definitions should 3308 * fall into above incremental config (except ALG0). Otherwise a 3309 * single NPC MCAM entry is not sufficient for supporting RSS. 3310 * 3311 * If a different definition or combination needed then NPC MCAM 3312 * has to be programmed to filter such pkts and it's action should 3313 * point to this definition to calculate flowtag or hash. 3314 * 3315 * The `for loop` goes over _all_ protocol field and the following 3316 * variables depicts the state machine forward progress logic. 3317 * 3318 * keyoff_marker - Enabled when hash byte length needs to be accounted 3319 * in field->key_offset update. 3320 * field_marker - Enabled when a new field needs to be selected. 3321 * group_member - Enabled when protocol is part of a group. 3322 */ 3323 3324 keyoff_marker = 0; max_key_off = 0; group_member = 0; 3325 nr_field = 0; key_off = 0; field_marker = 1; 3326 field = &tmp; max_bit_pos = fls(flow_cfg); 3327 for (idx = 0; 3328 idx < max_bit_pos && nr_field < FIELDS_PER_ALG && 3329 key_off < MAX_KEY_OFF; idx++) { 3330 key_type = BIT(idx); 3331 valid_key = flow_cfg & key_type; 3332 /* Found a field marker, reset the field values */ 3333 if (field_marker) 3334 memset(&tmp, 0, sizeof(tmp)); 3335 3336 field_marker = true; 3337 keyoff_marker = true; 3338 switch (key_type) { 3339 case NIX_FLOW_KEY_TYPE_PORT: 3340 field->sel_chan = true; 3341 /* This should be set to 1, when SEL_CHAN is set */ 3342 field->bytesm1 = 1; 3343 break; 3344 case NIX_FLOW_KEY_TYPE_IPV4_PROTO: 3345 field->lid = NPC_LID_LC; 3346 field->hdr_offset = 9; /* offset */ 3347 field->bytesm1 = 0; /* 1 byte */ 3348 field->ltype_match = NPC_LT_LC_IP; 3349 field->ltype_mask = 0xF; 3350 break; 3351 case NIX_FLOW_KEY_TYPE_IPV4: 3352 case NIX_FLOW_KEY_TYPE_INNR_IPV4: 3353 field->lid = NPC_LID_LC; 3354 field->ltype_match = NPC_LT_LC_IP; 3355 if (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV4) { 3356 field->lid = NPC_LID_LG; 3357 field->ltype_match = NPC_LT_LG_TU_IP; 3358 } 3359 field->hdr_offset = 12; /* SIP offset */ 3360 field->bytesm1 = 7; /* SIP + DIP, 8 bytes */ 3361 field->ltype_mask = 0xF; /* Match only IPv4 */ 3362 keyoff_marker = false; 3363 break; 3364 case NIX_FLOW_KEY_TYPE_IPV6: 3365 case NIX_FLOW_KEY_TYPE_INNR_IPV6: 3366 field->lid = NPC_LID_LC; 3367 field->ltype_match = NPC_LT_LC_IP6; 3368 if (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV6) { 3369 field->lid = NPC_LID_LG; 3370 field->ltype_match = NPC_LT_LG_TU_IP6; 3371 } 3372 field->hdr_offset = 8; /* SIP offset */ 3373 field->bytesm1 = 31; /* SIP + DIP, 32 bytes */ 3374 field->ltype_mask = 0xF; /* Match only IPv6 */ 3375 break; 3376 case NIX_FLOW_KEY_TYPE_TCP: 3377 case NIX_FLOW_KEY_TYPE_UDP: 3378 case NIX_FLOW_KEY_TYPE_SCTP: 3379 case NIX_FLOW_KEY_TYPE_INNR_TCP: 3380 case NIX_FLOW_KEY_TYPE_INNR_UDP: 3381 case NIX_FLOW_KEY_TYPE_INNR_SCTP: 3382 field->lid = NPC_LID_LD; 3383 if (key_type == NIX_FLOW_KEY_TYPE_INNR_TCP || 3384 key_type == NIX_FLOW_KEY_TYPE_INNR_UDP || 3385 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) 3386 field->lid = NPC_LID_LH; 3387 field->bytesm1 = 3; /* Sport + Dport, 4 bytes */ 3388 3389 /* Enum values for NPC_LID_LD and NPC_LID_LG are same, 3390 * so no need to change the ltype_match, just change 3391 * the lid for inner protocols 3392 */ 3393 BUILD_BUG_ON((int)NPC_LT_LD_TCP != 3394 (int)NPC_LT_LH_TU_TCP); 3395 BUILD_BUG_ON((int)NPC_LT_LD_UDP != 3396 (int)NPC_LT_LH_TU_UDP); 3397 BUILD_BUG_ON((int)NPC_LT_LD_SCTP != 3398 (int)NPC_LT_LH_TU_SCTP); 3399 3400 if ((key_type == NIX_FLOW_KEY_TYPE_TCP || 3401 key_type == NIX_FLOW_KEY_TYPE_INNR_TCP) && 3402 valid_key) { 3403 field->ltype_match |= NPC_LT_LD_TCP; 3404 group_member = true; 3405 } else if ((key_type == NIX_FLOW_KEY_TYPE_UDP || 3406 key_type == NIX_FLOW_KEY_TYPE_INNR_UDP) && 3407 valid_key) { 3408 field->ltype_match |= NPC_LT_LD_UDP; 3409 group_member = true; 3410 } else if ((key_type == NIX_FLOW_KEY_TYPE_SCTP || 3411 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) && 3412 valid_key) { 3413 field->ltype_match |= NPC_LT_LD_SCTP; 3414 group_member = true; 3415 } 3416 field->ltype_mask = ~field->ltype_match; 3417 if (key_type == NIX_FLOW_KEY_TYPE_SCTP || 3418 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) { 3419 /* Handle the case where any of the group item 3420 * is enabled in the group but not the final one 3421 */ 3422 if (group_member) { 3423 valid_key = true; 3424 group_member = false; 3425 } 3426 } else { 3427 field_marker = false; 3428 keyoff_marker = false; 3429 } 3430 3431 /* TCP/UDP/SCTP and ESP/AH falls at same offset so 3432 * remember the TCP key offset of 40 byte hash key. 3433 */ 3434 if (key_type == NIX_FLOW_KEY_TYPE_TCP) 3435 l4_key_offset = key_off; 3436 break; 3437 case NIX_FLOW_KEY_TYPE_NVGRE: 3438 field->lid = NPC_LID_LD; 3439 field->hdr_offset = 4; /* VSID offset */ 3440 field->bytesm1 = 2; 3441 field->ltype_match = NPC_LT_LD_NVGRE; 3442 field->ltype_mask = 0xF; 3443 break; 3444 case NIX_FLOW_KEY_TYPE_VXLAN: 3445 case NIX_FLOW_KEY_TYPE_GENEVE: 3446 field->lid = NPC_LID_LE; 3447 field->bytesm1 = 2; 3448 field->hdr_offset = 4; 3449 field->ltype_mask = 0xF; 3450 field_marker = false; 3451 keyoff_marker = false; 3452 3453 if (key_type == NIX_FLOW_KEY_TYPE_VXLAN && valid_key) { 3454 field->ltype_match |= NPC_LT_LE_VXLAN; 3455 group_member = true; 3456 } 3457 3458 if (key_type == NIX_FLOW_KEY_TYPE_GENEVE && valid_key) { 3459 field->ltype_match |= NPC_LT_LE_GENEVE; 3460 group_member = true; 3461 } 3462 3463 if (key_type == NIX_FLOW_KEY_TYPE_GENEVE) { 3464 if (group_member) { 3465 field->ltype_mask = ~field->ltype_match; 3466 field_marker = true; 3467 keyoff_marker = true; 3468 valid_key = true; 3469 group_member = false; 3470 } 3471 } 3472 break; 3473 case NIX_FLOW_KEY_TYPE_ETH_DMAC: 3474 case NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC: 3475 field->lid = NPC_LID_LA; 3476 field->ltype_match = NPC_LT_LA_ETHER; 3477 if (key_type == NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC) { 3478 field->lid = NPC_LID_LF; 3479 field->ltype_match = NPC_LT_LF_TU_ETHER; 3480 } 3481 field->hdr_offset = 0; 3482 field->bytesm1 = 5; /* DMAC 6 Byte */ 3483 field->ltype_mask = 0xF; 3484 break; 3485 case NIX_FLOW_KEY_TYPE_IPV6_EXT: 3486 field->lid = NPC_LID_LC; 3487 field->hdr_offset = 40; /* IPV6 hdr */ 3488 field->bytesm1 = 0; /* 1 Byte ext hdr*/ 3489 field->ltype_match = NPC_LT_LC_IP6_EXT; 3490 field->ltype_mask = 0xF; 3491 break; 3492 case NIX_FLOW_KEY_TYPE_GTPU: 3493 field->lid = NPC_LID_LE; 3494 field->hdr_offset = 4; 3495 field->bytesm1 = 3; /* 4 bytes TID*/ 3496 field->ltype_match = NPC_LT_LE_GTPU; 3497 field->ltype_mask = 0xF; 3498 break; 3499 case NIX_FLOW_KEY_TYPE_VLAN: 3500 field->lid = NPC_LID_LB; 3501 field->hdr_offset = 2; /* Skip TPID (2-bytes) */ 3502 field->bytesm1 = 1; /* 2 Bytes (Actually 12 bits) */ 3503 field->ltype_match = NPC_LT_LB_CTAG; 3504 field->ltype_mask = 0xF; 3505 field->fn_mask = 1; /* Mask out the first nibble */ 3506 break; 3507 case NIX_FLOW_KEY_TYPE_AH: 3508 case NIX_FLOW_KEY_TYPE_ESP: 3509 field->hdr_offset = 0; 3510 field->bytesm1 = 7; /* SPI + sequence number */ 3511 field->ltype_mask = 0xF; 3512 field->lid = NPC_LID_LE; 3513 field->ltype_match = NPC_LT_LE_ESP; 3514 if (key_type == NIX_FLOW_KEY_TYPE_AH) { 3515 field->lid = NPC_LID_LD; 3516 field->ltype_match = NPC_LT_LD_AH; 3517 field->hdr_offset = 4; 3518 keyoff_marker = false; 3519 } 3520 break; 3521 } 3522 field->ena = 1; 3523 3524 /* Found a valid flow key type */ 3525 if (valid_key) { 3526 /* Use the key offset of TCP/UDP/SCTP fields 3527 * for ESP/AH fields. 3528 */ 3529 if (key_type == NIX_FLOW_KEY_TYPE_ESP || 3530 key_type == NIX_FLOW_KEY_TYPE_AH) 3531 key_off = l4_key_offset; 3532 field->key_offset = key_off; 3533 memcpy(&alg[nr_field], field, sizeof(*field)); 3534 max_key_off = max(max_key_off, field->bytesm1 + 1); 3535 3536 /* Found a field marker, get the next field */ 3537 if (field_marker) 3538 nr_field++; 3539 } 3540 3541 /* Found a keyoff marker, update the new key_off */ 3542 if (keyoff_marker) { 3543 key_off += max_key_off; 3544 max_key_off = 0; 3545 } 3546 } 3547 /* Processed all the flow key types */ 3548 if (idx == max_bit_pos && key_off <= MAX_KEY_OFF) 3549 return 0; 3550 else 3551 return NIX_AF_ERR_RSS_NOSPC_FIELD; 3552 } 3553 3554 static int reserve_flowkey_alg_idx(struct rvu *rvu, int blkaddr, u32 flow_cfg) 3555 { 3556 u64 field[FIELDS_PER_ALG]; 3557 struct nix_hw *hw; 3558 int fid, rc; 3559 3560 hw = get_nix_hw(rvu->hw, blkaddr); 3561 if (!hw) 3562 return NIX_AF_ERR_INVALID_NIXBLK; 3563 3564 /* No room to add new flow hash algoritham */ 3565 if (hw->flowkey.in_use >= NIX_FLOW_KEY_ALG_MAX) 3566 return NIX_AF_ERR_RSS_NOSPC_ALGO; 3567 3568 /* Generate algo fields for the given flow_cfg */ 3569 rc = set_flowkey_fields((struct nix_rx_flowkey_alg *)field, flow_cfg); 3570 if (rc) 3571 return rc; 3572 3573 /* Update ALGX_FIELDX register with generated fields */ 3574 for (fid = 0; fid < FIELDS_PER_ALG; fid++) 3575 rvu_write64(rvu, blkaddr, 3576 NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(hw->flowkey.in_use, 3577 fid), field[fid]); 3578 3579 /* Store the flow_cfg for futher lookup */ 3580 rc = hw->flowkey.in_use; 3581 hw->flowkey.flowkey[rc] = flow_cfg; 3582 hw->flowkey.in_use++; 3583 3584 return rc; 3585 } 3586 3587 int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu, 3588 struct nix_rss_flowkey_cfg *req, 3589 struct nix_rss_flowkey_cfg_rsp *rsp) 3590 { 3591 u16 pcifunc = req->hdr.pcifunc; 3592 int alg_idx, nixlf, blkaddr; 3593 struct nix_hw *nix_hw; 3594 int err; 3595 3596 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3597 if (err) 3598 return err; 3599 3600 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3601 if (!nix_hw) 3602 return NIX_AF_ERR_INVALID_NIXBLK; 3603 3604 alg_idx = get_flowkey_alg_idx(nix_hw, req->flowkey_cfg); 3605 /* Failed to get algo index from the exiting list, reserve new */ 3606 if (alg_idx < 0) { 3607 alg_idx = reserve_flowkey_alg_idx(rvu, blkaddr, 3608 req->flowkey_cfg); 3609 if (alg_idx < 0) 3610 return alg_idx; 3611 } 3612 rsp->alg_idx = alg_idx; 3613 rvu_npc_update_flowkey_alg_idx(rvu, pcifunc, nixlf, req->group, 3614 alg_idx, req->mcam_index); 3615 return 0; 3616 } 3617 3618 static int nix_rx_flowkey_alg_cfg(struct rvu *rvu, int blkaddr) 3619 { 3620 u32 flowkey_cfg, minkey_cfg; 3621 int alg, fid, rc; 3622 3623 /* Disable all flow key algx fieldx */ 3624 for (alg = 0; alg < NIX_FLOW_KEY_ALG_MAX; alg++) { 3625 for (fid = 0; fid < FIELDS_PER_ALG; fid++) 3626 rvu_write64(rvu, blkaddr, 3627 NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(alg, fid), 3628 0); 3629 } 3630 3631 /* IPv4/IPv6 SIP/DIPs */ 3632 flowkey_cfg = NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6; 3633 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3634 if (rc < 0) 3635 return rc; 3636 3637 /* TCPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3638 minkey_cfg = flowkey_cfg; 3639 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP; 3640 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3641 if (rc < 0) 3642 return rc; 3643 3644 /* UDPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3645 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_UDP; 3646 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3647 if (rc < 0) 3648 return rc; 3649 3650 /* SCTPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3651 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_SCTP; 3652 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3653 if (rc < 0) 3654 return rc; 3655 3656 /* TCP/UDP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3657 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3658 NIX_FLOW_KEY_TYPE_UDP; 3659 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3660 if (rc < 0) 3661 return rc; 3662 3663 /* TCP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3664 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3665 NIX_FLOW_KEY_TYPE_SCTP; 3666 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3667 if (rc < 0) 3668 return rc; 3669 3670 /* UDP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3671 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_UDP | 3672 NIX_FLOW_KEY_TYPE_SCTP; 3673 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3674 if (rc < 0) 3675 return rc; 3676 3677 /* TCP/UDP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3678 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3679 NIX_FLOW_KEY_TYPE_UDP | NIX_FLOW_KEY_TYPE_SCTP; 3680 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3681 if (rc < 0) 3682 return rc; 3683 3684 return 0; 3685 } 3686 3687 int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu, 3688 struct nix_set_mac_addr *req, 3689 struct msg_rsp *rsp) 3690 { 3691 bool from_vf = req->hdr.pcifunc & RVU_PFVF_FUNC_MASK; 3692 u16 pcifunc = req->hdr.pcifunc; 3693 int blkaddr, nixlf, err; 3694 struct rvu_pfvf *pfvf; 3695 3696 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3697 if (err) 3698 return err; 3699 3700 pfvf = rvu_get_pfvf(rvu, pcifunc); 3701 3702 /* untrusted VF can't overwrite admin(PF) changes */ 3703 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && 3704 (from_vf && test_bit(PF_SET_VF_MAC, &pfvf->flags))) { 3705 dev_warn(rvu->dev, 3706 "MAC address set by admin(PF) cannot be overwritten by untrusted VF"); 3707 return -EPERM; 3708 } 3709 3710 ether_addr_copy(pfvf->mac_addr, req->mac_addr); 3711 3712 rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, 3713 pfvf->rx_chan_base, req->mac_addr); 3714 3715 if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && from_vf) 3716 ether_addr_copy(pfvf->default_mac, req->mac_addr); 3717 3718 rvu_switch_update_rules(rvu, pcifunc); 3719 3720 return 0; 3721 } 3722 3723 int rvu_mbox_handler_nix_get_mac_addr(struct rvu *rvu, 3724 struct msg_req *req, 3725 struct nix_get_mac_addr_rsp *rsp) 3726 { 3727 u16 pcifunc = req->hdr.pcifunc; 3728 struct rvu_pfvf *pfvf; 3729 3730 if (!is_nixlf_attached(rvu, pcifunc)) 3731 return NIX_AF_ERR_AF_LF_INVALID; 3732 3733 pfvf = rvu_get_pfvf(rvu, pcifunc); 3734 3735 ether_addr_copy(rsp->mac_addr, pfvf->mac_addr); 3736 3737 return 0; 3738 } 3739 3740 int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req, 3741 struct msg_rsp *rsp) 3742 { 3743 bool allmulti, promisc, nix_rx_multicast; 3744 u16 pcifunc = req->hdr.pcifunc; 3745 struct rvu_pfvf *pfvf; 3746 int nixlf, err; 3747 3748 pfvf = rvu_get_pfvf(rvu, pcifunc); 3749 promisc = req->mode & NIX_RX_MODE_PROMISC ? true : false; 3750 allmulti = req->mode & NIX_RX_MODE_ALLMULTI ? true : false; 3751 pfvf->use_mce_list = req->mode & NIX_RX_MODE_USE_MCE ? true : false; 3752 3753 nix_rx_multicast = rvu->hw->cap.nix_rx_multicast & pfvf->use_mce_list; 3754 3755 if (is_vf(pcifunc) && !nix_rx_multicast && 3756 (promisc || allmulti)) { 3757 dev_warn_ratelimited(rvu->dev, 3758 "VF promisc/multicast not supported\n"); 3759 return 0; 3760 } 3761 3762 /* untrusted VF can't configure promisc/allmulti */ 3763 if (is_vf(pcifunc) && !test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && 3764 (promisc || allmulti)) 3765 return 0; 3766 3767 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 3768 if (err) 3769 return err; 3770 3771 if (nix_rx_multicast) { 3772 /* add/del this PF_FUNC to/from mcast pkt replication list */ 3773 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_ALLMULTI_ENTRY, 3774 allmulti); 3775 if (err) { 3776 dev_err(rvu->dev, 3777 "Failed to update pcifunc 0x%x to multicast list\n", 3778 pcifunc); 3779 return err; 3780 } 3781 3782 /* add/del this PF_FUNC to/from promisc pkt replication list */ 3783 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_PROMISC_ENTRY, 3784 promisc); 3785 if (err) { 3786 dev_err(rvu->dev, 3787 "Failed to update pcifunc 0x%x to promisc list\n", 3788 pcifunc); 3789 return err; 3790 } 3791 } 3792 3793 /* install/uninstall allmulti entry */ 3794 if (allmulti) { 3795 rvu_npc_install_allmulti_entry(rvu, pcifunc, nixlf, 3796 pfvf->rx_chan_base); 3797 } else { 3798 if (!nix_rx_multicast) 3799 rvu_npc_enable_allmulti_entry(rvu, pcifunc, nixlf, false); 3800 } 3801 3802 /* install/uninstall promisc entry */ 3803 if (promisc) { 3804 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 3805 pfvf->rx_chan_base, 3806 pfvf->rx_chan_cnt); 3807 3808 if (rvu_npc_exact_has_match_table(rvu)) 3809 rvu_npc_exact_promisc_enable(rvu, pcifunc); 3810 } else { 3811 if (!nix_rx_multicast) 3812 rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf, false); 3813 3814 if (rvu_npc_exact_has_match_table(rvu)) 3815 rvu_npc_exact_promisc_disable(rvu, pcifunc); 3816 } 3817 3818 return 0; 3819 } 3820 3821 static void nix_find_link_frs(struct rvu *rvu, 3822 struct nix_frs_cfg *req, u16 pcifunc) 3823 { 3824 int pf = rvu_get_pf(pcifunc); 3825 struct rvu_pfvf *pfvf; 3826 int maxlen, minlen; 3827 int numvfs, hwvf; 3828 int vf; 3829 3830 /* Update with requester's min/max lengths */ 3831 pfvf = rvu_get_pfvf(rvu, pcifunc); 3832 pfvf->maxlen = req->maxlen; 3833 if (req->update_minlen) 3834 pfvf->minlen = req->minlen; 3835 3836 maxlen = req->maxlen; 3837 minlen = req->update_minlen ? req->minlen : 0; 3838 3839 /* Get this PF's numVFs and starting hwvf */ 3840 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 3841 3842 /* For each VF, compare requested max/minlen */ 3843 for (vf = 0; vf < numvfs; vf++) { 3844 pfvf = &rvu->hwvf[hwvf + vf]; 3845 if (pfvf->maxlen > maxlen) 3846 maxlen = pfvf->maxlen; 3847 if (req->update_minlen && 3848 pfvf->minlen && pfvf->minlen < minlen) 3849 minlen = pfvf->minlen; 3850 } 3851 3852 /* Compare requested max/minlen with PF's max/minlen */ 3853 pfvf = &rvu->pf[pf]; 3854 if (pfvf->maxlen > maxlen) 3855 maxlen = pfvf->maxlen; 3856 if (req->update_minlen && 3857 pfvf->minlen && pfvf->minlen < minlen) 3858 minlen = pfvf->minlen; 3859 3860 /* Update the request with max/min PF's and it's VF's max/min */ 3861 req->maxlen = maxlen; 3862 if (req->update_minlen) 3863 req->minlen = minlen; 3864 } 3865 3866 static int 3867 nix_config_link_credits(struct rvu *rvu, int blkaddr, int link, 3868 u16 pcifunc, u64 tx_credits) 3869 { 3870 struct rvu_hwinfo *hw = rvu->hw; 3871 int pf = rvu_get_pf(pcifunc); 3872 u8 cgx_id = 0, lmac_id = 0; 3873 unsigned long poll_tmo; 3874 bool restore_tx_en = 0; 3875 struct nix_hw *nix_hw; 3876 u64 cfg, sw_xoff = 0; 3877 u32 schq = 0; 3878 u32 credits; 3879 int rc; 3880 3881 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3882 if (!nix_hw) 3883 return NIX_AF_ERR_INVALID_NIXBLK; 3884 3885 if (tx_credits == nix_hw->tx_credits[link]) 3886 return 0; 3887 3888 /* Enable cgx tx if disabled for credits to be back */ 3889 if (is_pf_cgxmapped(rvu, pf)) { 3890 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 3891 restore_tx_en = !rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), 3892 lmac_id, true); 3893 } 3894 3895 mutex_lock(&rvu->rsrc_lock); 3896 /* Disable new traffic to link */ 3897 if (hw->cap.nix_shaping) { 3898 schq = nix_get_tx_link(rvu, pcifunc); 3899 sw_xoff = rvu_read64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq)); 3900 rvu_write64(rvu, blkaddr, 3901 NIX_AF_TL1X_SW_XOFF(schq), BIT_ULL(0)); 3902 } 3903 3904 rc = NIX_AF_ERR_LINK_CREDITS; 3905 poll_tmo = jiffies + usecs_to_jiffies(200000); 3906 /* Wait for credits to return */ 3907 do { 3908 if (time_after(jiffies, poll_tmo)) 3909 goto exit; 3910 usleep_range(100, 200); 3911 3912 cfg = rvu_read64(rvu, blkaddr, 3913 NIX_AF_TX_LINKX_NORM_CREDIT(link)); 3914 credits = (cfg >> 12) & 0xFFFFFULL; 3915 } while (credits != nix_hw->tx_credits[link]); 3916 3917 cfg &= ~(0xFFFFFULL << 12); 3918 cfg |= (tx_credits << 12); 3919 rvu_write64(rvu, blkaddr, NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg); 3920 rc = 0; 3921 3922 nix_hw->tx_credits[link] = tx_credits; 3923 3924 exit: 3925 /* Enable traffic back */ 3926 if (hw->cap.nix_shaping && !sw_xoff) 3927 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq), 0); 3928 3929 /* Restore state of cgx tx */ 3930 if (restore_tx_en) 3931 rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false); 3932 3933 mutex_unlock(&rvu->rsrc_lock); 3934 return rc; 3935 } 3936 3937 int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req, 3938 struct msg_rsp *rsp) 3939 { 3940 struct rvu_hwinfo *hw = rvu->hw; 3941 u16 pcifunc = req->hdr.pcifunc; 3942 int pf = rvu_get_pf(pcifunc); 3943 int blkaddr, schq, link = -1; 3944 struct nix_txsch *txsch; 3945 u64 cfg, lmac_fifo_len; 3946 struct nix_hw *nix_hw; 3947 struct rvu_pfvf *pfvf; 3948 u8 cgx = 0, lmac = 0; 3949 u16 max_mtu; 3950 3951 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 3952 if (blkaddr < 0) 3953 return NIX_AF_ERR_AF_LF_INVALID; 3954 3955 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3956 if (!nix_hw) 3957 return NIX_AF_ERR_INVALID_NIXBLK; 3958 3959 if (is_afvf(pcifunc)) 3960 rvu_get_lbk_link_max_frs(rvu, &max_mtu); 3961 else 3962 rvu_get_lmac_link_max_frs(rvu, &max_mtu); 3963 3964 if (!req->sdp_link && req->maxlen > max_mtu) 3965 return NIX_AF_ERR_FRS_INVALID; 3966 3967 if (req->update_minlen && req->minlen < NIC_HW_MIN_FRS) 3968 return NIX_AF_ERR_FRS_INVALID; 3969 3970 /* Check if requester wants to update SMQ's */ 3971 if (!req->update_smq) 3972 goto rx_frscfg; 3973 3974 /* Update min/maxlen in each of the SMQ attached to this PF/VF */ 3975 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 3976 mutex_lock(&rvu->rsrc_lock); 3977 for (schq = 0; schq < txsch->schq.max; schq++) { 3978 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 3979 continue; 3980 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq)); 3981 cfg = (cfg & ~(0xFFFFULL << 8)) | ((u64)req->maxlen << 8); 3982 if (req->update_minlen) 3983 cfg = (cfg & ~0x7FULL) | ((u64)req->minlen & 0x7F); 3984 rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq), cfg); 3985 } 3986 mutex_unlock(&rvu->rsrc_lock); 3987 3988 rx_frscfg: 3989 /* Check if config is for SDP link */ 3990 if (req->sdp_link) { 3991 if (!hw->sdp_links) 3992 return NIX_AF_ERR_RX_LINK_INVALID; 3993 link = hw->cgx_links + hw->lbk_links; 3994 goto linkcfg; 3995 } 3996 3997 /* Check if the request is from CGX mapped RVU PF */ 3998 if (is_pf_cgxmapped(rvu, pf)) { 3999 /* Get CGX and LMAC to which this PF is mapped and find link */ 4000 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac); 4001 link = (cgx * hw->lmac_per_cgx) + lmac; 4002 } else if (pf == 0) { 4003 /* For VFs of PF0 ingress is LBK port, so config LBK link */ 4004 pfvf = rvu_get_pfvf(rvu, pcifunc); 4005 link = hw->cgx_links + pfvf->lbkid; 4006 } 4007 4008 if (link < 0) 4009 return NIX_AF_ERR_RX_LINK_INVALID; 4010 4011 nix_find_link_frs(rvu, req, pcifunc); 4012 4013 linkcfg: 4014 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link)); 4015 cfg = (cfg & ~(0xFFFFULL << 16)) | ((u64)req->maxlen << 16); 4016 if (req->update_minlen) 4017 cfg = (cfg & ~0xFFFFULL) | req->minlen; 4018 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), cfg); 4019 4020 if (req->sdp_link || pf == 0) 4021 return 0; 4022 4023 /* Update transmit credits for CGX links */ 4024 lmac_fifo_len = rvu_cgx_get_lmac_fifolen(rvu, cgx, lmac); 4025 if (!lmac_fifo_len) { 4026 dev_err(rvu->dev, 4027 "%s: Failed to get CGX/RPM%d:LMAC%d FIFO size\n", 4028 __func__, cgx, lmac); 4029 return 0; 4030 } 4031 return nix_config_link_credits(rvu, blkaddr, link, pcifunc, 4032 (lmac_fifo_len - req->maxlen) / 16); 4033 } 4034 4035 int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req, 4036 struct msg_rsp *rsp) 4037 { 4038 int nixlf, blkaddr, err; 4039 u64 cfg; 4040 4041 err = nix_get_nixlf(rvu, req->hdr.pcifunc, &nixlf, &blkaddr); 4042 if (err) 4043 return err; 4044 4045 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf)); 4046 /* Set the interface configuration */ 4047 if (req->len_verify & BIT(0)) 4048 cfg |= BIT_ULL(41); 4049 else 4050 cfg &= ~BIT_ULL(41); 4051 4052 if (req->len_verify & BIT(1)) 4053 cfg |= BIT_ULL(40); 4054 else 4055 cfg &= ~BIT_ULL(40); 4056 4057 if (req->csum_verify & BIT(0)) 4058 cfg |= BIT_ULL(37); 4059 else 4060 cfg &= ~BIT_ULL(37); 4061 4062 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), cfg); 4063 4064 return 0; 4065 } 4066 4067 static u64 rvu_get_lbk_link_credits(struct rvu *rvu, u16 lbk_max_frs) 4068 { 4069 /* CN10k supports 72KB FIFO size and max packet size of 64k */ 4070 if (rvu->hw->lbk_bufsize == 0x12000) 4071 return (rvu->hw->lbk_bufsize - lbk_max_frs) / 16; 4072 4073 return 1600; /* 16 * max LBK datarate = 16 * 100Gbps */ 4074 } 4075 4076 static void nix_link_config(struct rvu *rvu, int blkaddr, 4077 struct nix_hw *nix_hw) 4078 { 4079 struct rvu_hwinfo *hw = rvu->hw; 4080 int cgx, lmac_cnt, slink, link; 4081 u16 lbk_max_frs, lmac_max_frs; 4082 unsigned long lmac_bmap; 4083 u64 tx_credits, cfg; 4084 u64 lmac_fifo_len; 4085 int iter; 4086 4087 rvu_get_lbk_link_max_frs(rvu, &lbk_max_frs); 4088 rvu_get_lmac_link_max_frs(rvu, &lmac_max_frs); 4089 4090 /* Set default min/max packet lengths allowed on NIX Rx links. 4091 * 4092 * With HW reset minlen value of 60byte, HW will treat ARP pkts 4093 * as undersize and report them to SW as error pkts, hence 4094 * setting it to 40 bytes. 4095 */ 4096 for (link = 0; link < hw->cgx_links; link++) { 4097 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4098 ((u64)lmac_max_frs << 16) | NIC_HW_MIN_FRS); 4099 } 4100 4101 for (link = hw->cgx_links; link < hw->lbk_links; link++) { 4102 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4103 ((u64)lbk_max_frs << 16) | NIC_HW_MIN_FRS); 4104 } 4105 if (hw->sdp_links) { 4106 link = hw->cgx_links + hw->lbk_links; 4107 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4108 SDP_HW_MAX_FRS << 16 | NIC_HW_MIN_FRS); 4109 } 4110 4111 /* Set credits for Tx links assuming max packet length allowed. 4112 * This will be reconfigured based on MTU set for PF/VF. 4113 */ 4114 for (cgx = 0; cgx < hw->cgx; cgx++) { 4115 lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); 4116 /* Skip when cgx is not available or lmac cnt is zero */ 4117 if (lmac_cnt <= 0) 4118 continue; 4119 slink = cgx * hw->lmac_per_cgx; 4120 4121 /* Get LMAC id's from bitmap */ 4122 lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu)); 4123 for_each_set_bit(iter, &lmac_bmap, rvu->hw->lmac_per_cgx) { 4124 lmac_fifo_len = rvu_cgx_get_lmac_fifolen(rvu, cgx, iter); 4125 if (!lmac_fifo_len) { 4126 dev_err(rvu->dev, 4127 "%s: Failed to get CGX/RPM%d:LMAC%d FIFO size\n", 4128 __func__, cgx, iter); 4129 continue; 4130 } 4131 tx_credits = (lmac_fifo_len - lmac_max_frs) / 16; 4132 /* Enable credits and set credit pkt count to max allowed */ 4133 cfg = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1); 4134 4135 link = iter + slink; 4136 nix_hw->tx_credits[link] = tx_credits; 4137 rvu_write64(rvu, blkaddr, 4138 NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg); 4139 } 4140 } 4141 4142 /* Set Tx credits for LBK link */ 4143 slink = hw->cgx_links; 4144 for (link = slink; link < (slink + hw->lbk_links); link++) { 4145 tx_credits = rvu_get_lbk_link_credits(rvu, lbk_max_frs); 4146 nix_hw->tx_credits[link] = tx_credits; 4147 /* Enable credits and set credit pkt count to max allowed */ 4148 tx_credits = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1); 4149 rvu_write64(rvu, blkaddr, 4150 NIX_AF_TX_LINKX_NORM_CREDIT(link), tx_credits); 4151 } 4152 } 4153 4154 static int nix_calibrate_x2p(struct rvu *rvu, int blkaddr) 4155 { 4156 int idx, err; 4157 u64 status; 4158 4159 /* Start X2P bus calibration */ 4160 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4161 rvu_read64(rvu, blkaddr, NIX_AF_CFG) | BIT_ULL(9)); 4162 /* Wait for calibration to complete */ 4163 err = rvu_poll_reg(rvu, blkaddr, 4164 NIX_AF_STATUS, BIT_ULL(10), false); 4165 if (err) { 4166 dev_err(rvu->dev, "NIX X2P bus calibration failed\n"); 4167 return err; 4168 } 4169 4170 status = rvu_read64(rvu, blkaddr, NIX_AF_STATUS); 4171 /* Check if CGX devices are ready */ 4172 for (idx = 0; idx < rvu->cgx_cnt_max; idx++) { 4173 /* Skip when cgx port is not available */ 4174 if (!rvu_cgx_pdata(idx, rvu) || 4175 (status & (BIT_ULL(16 + idx)))) 4176 continue; 4177 dev_err(rvu->dev, 4178 "CGX%d didn't respond to NIX X2P calibration\n", idx); 4179 err = -EBUSY; 4180 } 4181 4182 /* Check if LBK is ready */ 4183 if (!(status & BIT_ULL(19))) { 4184 dev_err(rvu->dev, 4185 "LBK didn't respond to NIX X2P calibration\n"); 4186 err = -EBUSY; 4187 } 4188 4189 /* Clear 'calibrate_x2p' bit */ 4190 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4191 rvu_read64(rvu, blkaddr, NIX_AF_CFG) & ~BIT_ULL(9)); 4192 if (err || (status & 0x3FFULL)) 4193 dev_err(rvu->dev, 4194 "NIX X2P calibration failed, status 0x%llx\n", status); 4195 if (err) 4196 return err; 4197 return 0; 4198 } 4199 4200 static int nix_aq_init(struct rvu *rvu, struct rvu_block *block) 4201 { 4202 u64 cfg; 4203 int err; 4204 4205 /* Set admin queue endianness */ 4206 cfg = rvu_read64(rvu, block->addr, NIX_AF_CFG); 4207 #ifdef __BIG_ENDIAN 4208 cfg |= BIT_ULL(8); 4209 rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg); 4210 #else 4211 cfg &= ~BIT_ULL(8); 4212 rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg); 4213 #endif 4214 4215 /* Do not bypass NDC cache */ 4216 cfg = rvu_read64(rvu, block->addr, NIX_AF_NDC_CFG); 4217 cfg &= ~0x3FFEULL; 4218 #ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING 4219 /* Disable caching of SQB aka SQEs */ 4220 cfg |= 0x04ULL; 4221 #endif 4222 rvu_write64(rvu, block->addr, NIX_AF_NDC_CFG, cfg); 4223 4224 /* Result structure can be followed by RQ/SQ/CQ context at 4225 * RES + 128bytes and a write mask at RES + 256 bytes, depending on 4226 * operation type. Alloc sufficient result memory for all operations. 4227 */ 4228 err = rvu_aq_alloc(rvu, &block->aq, 4229 Q_COUNT(AQ_SIZE), sizeof(struct nix_aq_inst_s), 4230 ALIGN(sizeof(struct nix_aq_res_s), 128) + 256); 4231 if (err) 4232 return err; 4233 4234 rvu_write64(rvu, block->addr, NIX_AF_AQ_CFG, AQ_SIZE); 4235 rvu_write64(rvu, block->addr, 4236 NIX_AF_AQ_BASE, (u64)block->aq->inst->iova); 4237 return 0; 4238 } 4239 4240 static void rvu_nix_setup_capabilities(struct rvu *rvu, int blkaddr) 4241 { 4242 struct rvu_hwinfo *hw = rvu->hw; 4243 u64 hw_const; 4244 4245 hw_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 4246 4247 /* On OcteonTx2 DWRR quantum is directly configured into each of 4248 * the transmit scheduler queues. And PF/VF drivers were free to 4249 * config any value upto 2^24. 4250 * On CN10K, HW is modified, the quantum configuration at scheduler 4251 * queues is in terms of weight. And SW needs to setup a base DWRR MTU 4252 * at NIX_AF_DWRR_RPM_MTU / NIX_AF_DWRR_SDP_MTU. HW will do 4253 * 'DWRR MTU * weight' to get the quantum. 4254 * 4255 * Check if HW uses a common MTU for all DWRR quantum configs. 4256 * On OcteonTx2 this register field is '0'. 4257 */ 4258 if (((hw_const >> 56) & 0x10) == 0x10) 4259 hw->cap.nix_common_dwrr_mtu = true; 4260 } 4261 4262 static int rvu_nix_block_init(struct rvu *rvu, struct nix_hw *nix_hw) 4263 { 4264 const struct npc_lt_def_cfg *ltdefs; 4265 struct rvu_hwinfo *hw = rvu->hw; 4266 int blkaddr = nix_hw->blkaddr; 4267 struct rvu_block *block; 4268 int err; 4269 u64 cfg; 4270 4271 block = &hw->block[blkaddr]; 4272 4273 if (is_rvu_96xx_B0(rvu)) { 4274 /* As per a HW errata in 96xx A0/B0 silicon, NIX may corrupt 4275 * internal state when conditional clocks are turned off. 4276 * Hence enable them. 4277 */ 4278 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4279 rvu_read64(rvu, blkaddr, NIX_AF_CFG) | 0x40ULL); 4280 4281 /* Set chan/link to backpressure TL3 instead of TL2 */ 4282 rvu_write64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL, 0x01); 4283 4284 /* Disable SQ manager's sticky mode operation (set TM6 = 0) 4285 * This sticky mode is known to cause SQ stalls when multiple 4286 * SQs are mapped to same SMQ and transmitting pkts at a time. 4287 */ 4288 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS); 4289 cfg &= ~BIT_ULL(15); 4290 rvu_write64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS, cfg); 4291 } 4292 4293 ltdefs = rvu->kpu.lt_def; 4294 /* Calibrate X2P bus to check if CGX/LBK links are fine */ 4295 err = nix_calibrate_x2p(rvu, blkaddr); 4296 if (err) 4297 return err; 4298 4299 /* Setup capabilities of the NIX block */ 4300 rvu_nix_setup_capabilities(rvu, blkaddr); 4301 4302 /* Initialize admin queue */ 4303 err = nix_aq_init(rvu, block); 4304 if (err) 4305 return err; 4306 4307 /* Restore CINT timer delay to HW reset values */ 4308 rvu_write64(rvu, blkaddr, NIX_AF_CINT_DELAY, 0x0ULL); 4309 4310 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SEB_CFG); 4311 4312 /* For better performance use NDC TX instead of NDC RX for SQ's SQEs" */ 4313 cfg |= 1ULL; 4314 if (!is_rvu_otx2(rvu)) 4315 cfg |= NIX_PTP_1STEP_EN; 4316 4317 rvu_write64(rvu, blkaddr, NIX_AF_SEB_CFG, cfg); 4318 4319 if (!is_rvu_otx2(rvu)) 4320 rvu_nix_block_cn10k_init(rvu, nix_hw); 4321 4322 if (is_block_implemented(hw, blkaddr)) { 4323 err = nix_setup_txschq(rvu, nix_hw, blkaddr); 4324 if (err) 4325 return err; 4326 4327 err = nix_setup_ipolicers(rvu, nix_hw, blkaddr); 4328 if (err) 4329 return err; 4330 4331 err = nix_af_mark_format_setup(rvu, nix_hw, blkaddr); 4332 if (err) 4333 return err; 4334 4335 err = nix_setup_mcast(rvu, nix_hw, blkaddr); 4336 if (err) 4337 return err; 4338 4339 err = nix_setup_txvlan(rvu, nix_hw); 4340 if (err) 4341 return err; 4342 4343 /* Configure segmentation offload formats */ 4344 nix_setup_lso(rvu, nix_hw, blkaddr); 4345 4346 /* Config Outer/Inner L2, IP, TCP, UDP and SCTP NPC layer info. 4347 * This helps HW protocol checker to identify headers 4348 * and validate length and checksums. 4349 */ 4350 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OL2, 4351 (ltdefs->rx_ol2.lid << 8) | (ltdefs->rx_ol2.ltype_match << 4) | 4352 ltdefs->rx_ol2.ltype_mask); 4353 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4, 4354 (ltdefs->rx_oip4.lid << 8) | (ltdefs->rx_oip4.ltype_match << 4) | 4355 ltdefs->rx_oip4.ltype_mask); 4356 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4, 4357 (ltdefs->rx_iip4.lid << 8) | (ltdefs->rx_iip4.ltype_match << 4) | 4358 ltdefs->rx_iip4.ltype_mask); 4359 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6, 4360 (ltdefs->rx_oip6.lid << 8) | (ltdefs->rx_oip6.ltype_match << 4) | 4361 ltdefs->rx_oip6.ltype_mask); 4362 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6, 4363 (ltdefs->rx_iip6.lid << 8) | (ltdefs->rx_iip6.ltype_match << 4) | 4364 ltdefs->rx_iip6.ltype_mask); 4365 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OTCP, 4366 (ltdefs->rx_otcp.lid << 8) | (ltdefs->rx_otcp.ltype_match << 4) | 4367 ltdefs->rx_otcp.ltype_mask); 4368 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ITCP, 4369 (ltdefs->rx_itcp.lid << 8) | (ltdefs->rx_itcp.ltype_match << 4) | 4370 ltdefs->rx_itcp.ltype_mask); 4371 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OUDP, 4372 (ltdefs->rx_oudp.lid << 8) | (ltdefs->rx_oudp.ltype_match << 4) | 4373 ltdefs->rx_oudp.ltype_mask); 4374 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IUDP, 4375 (ltdefs->rx_iudp.lid << 8) | (ltdefs->rx_iudp.ltype_match << 4) | 4376 ltdefs->rx_iudp.ltype_mask); 4377 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OSCTP, 4378 (ltdefs->rx_osctp.lid << 8) | (ltdefs->rx_osctp.ltype_match << 4) | 4379 ltdefs->rx_osctp.ltype_mask); 4380 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ISCTP, 4381 (ltdefs->rx_isctp.lid << 8) | (ltdefs->rx_isctp.ltype_match << 4) | 4382 ltdefs->rx_isctp.ltype_mask); 4383 4384 if (!is_rvu_otx2(rvu)) { 4385 /* Enable APAD calculation for other protocols 4386 * matching APAD0 and APAD1 lt def registers. 4387 */ 4388 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_CST_APAD0, 4389 (ltdefs->rx_apad0.valid << 11) | 4390 (ltdefs->rx_apad0.lid << 8) | 4391 (ltdefs->rx_apad0.ltype_match << 4) | 4392 ltdefs->rx_apad0.ltype_mask); 4393 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_CST_APAD1, 4394 (ltdefs->rx_apad1.valid << 11) | 4395 (ltdefs->rx_apad1.lid << 8) | 4396 (ltdefs->rx_apad1.ltype_match << 4) | 4397 ltdefs->rx_apad1.ltype_mask); 4398 4399 /* Receive ethertype defination register defines layer 4400 * information in NPC_RESULT_S to identify the Ethertype 4401 * location in L2 header. Used for Ethertype overwriting 4402 * in inline IPsec flow. 4403 */ 4404 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ET(0), 4405 (ltdefs->rx_et[0].offset << 12) | 4406 (ltdefs->rx_et[0].valid << 11) | 4407 (ltdefs->rx_et[0].lid << 8) | 4408 (ltdefs->rx_et[0].ltype_match << 4) | 4409 ltdefs->rx_et[0].ltype_mask); 4410 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ET(1), 4411 (ltdefs->rx_et[1].offset << 12) | 4412 (ltdefs->rx_et[1].valid << 11) | 4413 (ltdefs->rx_et[1].lid << 8) | 4414 (ltdefs->rx_et[1].ltype_match << 4) | 4415 ltdefs->rx_et[1].ltype_mask); 4416 } 4417 4418 err = nix_rx_flowkey_alg_cfg(rvu, blkaddr); 4419 if (err) 4420 return err; 4421 4422 nix_hw->tx_credits = kcalloc(hw->cgx_links + hw->lbk_links, 4423 sizeof(u64), GFP_KERNEL); 4424 if (!nix_hw->tx_credits) 4425 return -ENOMEM; 4426 4427 /* Initialize CGX/LBK/SDP link credits, min/max pkt lengths */ 4428 nix_link_config(rvu, blkaddr, nix_hw); 4429 4430 /* Enable Channel backpressure */ 4431 rvu_write64(rvu, blkaddr, NIX_AF_RX_CFG, BIT_ULL(0)); 4432 } 4433 return 0; 4434 } 4435 4436 int rvu_nix_init(struct rvu *rvu) 4437 { 4438 struct rvu_hwinfo *hw = rvu->hw; 4439 struct nix_hw *nix_hw; 4440 int blkaddr = 0, err; 4441 int i = 0; 4442 4443 hw->nix = devm_kcalloc(rvu->dev, MAX_NIX_BLKS, sizeof(struct nix_hw), 4444 GFP_KERNEL); 4445 if (!hw->nix) 4446 return -ENOMEM; 4447 4448 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4449 while (blkaddr) { 4450 nix_hw = &hw->nix[i]; 4451 nix_hw->rvu = rvu; 4452 nix_hw->blkaddr = blkaddr; 4453 err = rvu_nix_block_init(rvu, nix_hw); 4454 if (err) 4455 return err; 4456 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4457 i++; 4458 } 4459 4460 return 0; 4461 } 4462 4463 static void rvu_nix_block_freemem(struct rvu *rvu, int blkaddr, 4464 struct rvu_block *block) 4465 { 4466 struct nix_txsch *txsch; 4467 struct nix_mcast *mcast; 4468 struct nix_txvlan *vlan; 4469 struct nix_hw *nix_hw; 4470 int lvl; 4471 4472 rvu_aq_free(rvu, block->aq); 4473 4474 if (is_block_implemented(rvu->hw, blkaddr)) { 4475 nix_hw = get_nix_hw(rvu->hw, blkaddr); 4476 if (!nix_hw) 4477 return; 4478 4479 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 4480 txsch = &nix_hw->txsch[lvl]; 4481 kfree(txsch->schq.bmap); 4482 } 4483 4484 kfree(nix_hw->tx_credits); 4485 4486 nix_ipolicer_freemem(rvu, nix_hw); 4487 4488 vlan = &nix_hw->txvlan; 4489 kfree(vlan->rsrc.bmap); 4490 mutex_destroy(&vlan->rsrc_lock); 4491 4492 mcast = &nix_hw->mcast; 4493 qmem_free(rvu->dev, mcast->mce_ctx); 4494 qmem_free(rvu->dev, mcast->mcast_buf); 4495 mutex_destroy(&mcast->mce_lock); 4496 } 4497 } 4498 4499 void rvu_nix_freemem(struct rvu *rvu) 4500 { 4501 struct rvu_hwinfo *hw = rvu->hw; 4502 struct rvu_block *block; 4503 int blkaddr = 0; 4504 4505 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4506 while (blkaddr) { 4507 block = &hw->block[blkaddr]; 4508 rvu_nix_block_freemem(rvu, blkaddr, block); 4509 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4510 } 4511 } 4512 4513 int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req, 4514 struct msg_rsp *rsp) 4515 { 4516 u16 pcifunc = req->hdr.pcifunc; 4517 struct rvu_pfvf *pfvf; 4518 int nixlf, err; 4519 4520 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 4521 if (err) 4522 return err; 4523 4524 rvu_npc_enable_default_entries(rvu, pcifunc, nixlf); 4525 4526 npc_mcam_enable_flows(rvu, pcifunc); 4527 4528 pfvf = rvu_get_pfvf(rvu, pcifunc); 4529 set_bit(NIXLF_INITIALIZED, &pfvf->flags); 4530 4531 rvu_switch_update_rules(rvu, pcifunc); 4532 4533 return rvu_cgx_start_stop_io(rvu, pcifunc, true); 4534 } 4535 4536 int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req, 4537 struct msg_rsp *rsp) 4538 { 4539 u16 pcifunc = req->hdr.pcifunc; 4540 struct rvu_pfvf *pfvf; 4541 int nixlf, err; 4542 4543 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 4544 if (err) 4545 return err; 4546 4547 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 4548 4549 pfvf = rvu_get_pfvf(rvu, pcifunc); 4550 clear_bit(NIXLF_INITIALIZED, &pfvf->flags); 4551 4552 return rvu_cgx_start_stop_io(rvu, pcifunc, false); 4553 } 4554 4555 #define RX_SA_BASE GENMASK_ULL(52, 7) 4556 4557 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int nixlf) 4558 { 4559 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 4560 struct hwctx_disable_req ctx_req; 4561 int pf = rvu_get_pf(pcifunc); 4562 struct mac_ops *mac_ops; 4563 u8 cgx_id, lmac_id; 4564 u64 sa_base; 4565 void *cgxd; 4566 int err; 4567 4568 ctx_req.hdr.pcifunc = pcifunc; 4569 4570 /* Cleanup NPC MCAM entries, free Tx scheduler queues being used */ 4571 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 4572 rvu_npc_free_mcam_entries(rvu, pcifunc, nixlf); 4573 nix_interface_deinit(rvu, pcifunc, nixlf); 4574 nix_rx_sync(rvu, blkaddr); 4575 nix_txschq_free(rvu, pcifunc); 4576 4577 clear_bit(NIXLF_INITIALIZED, &pfvf->flags); 4578 4579 rvu_cgx_start_stop_io(rvu, pcifunc, false); 4580 4581 if (pfvf->sq_ctx) { 4582 ctx_req.ctype = NIX_AQ_CTYPE_SQ; 4583 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4584 if (err) 4585 dev_err(rvu->dev, "SQ ctx disable failed\n"); 4586 } 4587 4588 if (pfvf->rq_ctx) { 4589 ctx_req.ctype = NIX_AQ_CTYPE_RQ; 4590 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4591 if (err) 4592 dev_err(rvu->dev, "RQ ctx disable failed\n"); 4593 } 4594 4595 if (pfvf->cq_ctx) { 4596 ctx_req.ctype = NIX_AQ_CTYPE_CQ; 4597 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4598 if (err) 4599 dev_err(rvu->dev, "CQ ctx disable failed\n"); 4600 } 4601 4602 /* reset HW config done for Switch headers */ 4603 rvu_npc_set_parse_mode(rvu, pcifunc, OTX2_PRIV_FLAGS_DEFAULT, 4604 (PKIND_TX | PKIND_RX), 0, 0, 0, 0); 4605 4606 /* Disabling CGX and NPC config done for PTP */ 4607 if (pfvf->hw_rx_tstamp_en) { 4608 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 4609 cgxd = rvu_cgx_pdata(cgx_id, rvu); 4610 mac_ops = get_mac_ops(cgxd); 4611 mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, false); 4612 /* Undo NPC config done for PTP */ 4613 if (npc_config_ts_kpuaction(rvu, pf, pcifunc, false)) 4614 dev_err(rvu->dev, "NPC config for PTP failed\n"); 4615 pfvf->hw_rx_tstamp_en = false; 4616 } 4617 4618 /* reset priority flow control config */ 4619 rvu_cgx_prio_flow_ctrl_cfg(rvu, pcifunc, 0, 0, 0); 4620 4621 /* reset 802.3x flow control config */ 4622 rvu_cgx_cfg_pause_frm(rvu, pcifunc, 0, 0); 4623 4624 nix_ctx_free(rvu, pfvf); 4625 4626 nix_free_all_bandprof(rvu, pcifunc); 4627 4628 sa_base = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(nixlf)); 4629 if (FIELD_GET(RX_SA_BASE, sa_base)) { 4630 err = rvu_cpt_ctx_flush(rvu, pcifunc); 4631 if (err) 4632 dev_err(rvu->dev, 4633 "CPT ctx flush failed with error: %d\n", err); 4634 } 4635 } 4636 4637 #define NIX_AF_LFX_TX_CFG_PTP_EN BIT_ULL(32) 4638 4639 static int rvu_nix_lf_ptp_tx_cfg(struct rvu *rvu, u16 pcifunc, bool enable) 4640 { 4641 struct rvu_hwinfo *hw = rvu->hw; 4642 struct rvu_block *block; 4643 int blkaddr, pf; 4644 int nixlf; 4645 u64 cfg; 4646 4647 pf = rvu_get_pf(pcifunc); 4648 if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP)) 4649 return 0; 4650 4651 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 4652 if (blkaddr < 0) 4653 return NIX_AF_ERR_AF_LF_INVALID; 4654 4655 block = &hw->block[blkaddr]; 4656 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 4657 if (nixlf < 0) 4658 return NIX_AF_ERR_AF_LF_INVALID; 4659 4660 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf)); 4661 4662 if (enable) 4663 cfg |= NIX_AF_LFX_TX_CFG_PTP_EN; 4664 else 4665 cfg &= ~NIX_AF_LFX_TX_CFG_PTP_EN; 4666 4667 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg); 4668 4669 return 0; 4670 } 4671 4672 int rvu_mbox_handler_nix_lf_ptp_tx_enable(struct rvu *rvu, struct msg_req *req, 4673 struct msg_rsp *rsp) 4674 { 4675 return rvu_nix_lf_ptp_tx_cfg(rvu, req->hdr.pcifunc, true); 4676 } 4677 4678 int rvu_mbox_handler_nix_lf_ptp_tx_disable(struct rvu *rvu, struct msg_req *req, 4679 struct msg_rsp *rsp) 4680 { 4681 return rvu_nix_lf_ptp_tx_cfg(rvu, req->hdr.pcifunc, false); 4682 } 4683 4684 int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu, 4685 struct nix_lso_format_cfg *req, 4686 struct nix_lso_format_cfg_rsp *rsp) 4687 { 4688 u16 pcifunc = req->hdr.pcifunc; 4689 struct nix_hw *nix_hw; 4690 struct rvu_pfvf *pfvf; 4691 int blkaddr, idx, f; 4692 u64 reg; 4693 4694 pfvf = rvu_get_pfvf(rvu, pcifunc); 4695 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 4696 if (!pfvf->nixlf || blkaddr < 0) 4697 return NIX_AF_ERR_AF_LF_INVALID; 4698 4699 nix_hw = get_nix_hw(rvu->hw, blkaddr); 4700 if (!nix_hw) 4701 return NIX_AF_ERR_INVALID_NIXBLK; 4702 4703 /* Find existing matching LSO format, if any */ 4704 for (idx = 0; idx < nix_hw->lso.in_use; idx++) { 4705 for (f = 0; f < NIX_LSO_FIELD_MAX; f++) { 4706 reg = rvu_read64(rvu, blkaddr, 4707 NIX_AF_LSO_FORMATX_FIELDX(idx, f)); 4708 if (req->fields[f] != (reg & req->field_mask)) 4709 break; 4710 } 4711 4712 if (f == NIX_LSO_FIELD_MAX) 4713 break; 4714 } 4715 4716 if (idx < nix_hw->lso.in_use) { 4717 /* Match found */ 4718 rsp->lso_format_idx = idx; 4719 return 0; 4720 } 4721 4722 if (nix_hw->lso.in_use == nix_hw->lso.total) 4723 return NIX_AF_ERR_LSO_CFG_FAIL; 4724 4725 rsp->lso_format_idx = nix_hw->lso.in_use++; 4726 4727 for (f = 0; f < NIX_LSO_FIELD_MAX; f++) 4728 rvu_write64(rvu, blkaddr, 4729 NIX_AF_LSO_FORMATX_FIELDX(rsp->lso_format_idx, f), 4730 req->fields[f]); 4731 4732 return 0; 4733 } 4734 4735 #define IPSEC_GEN_CFG_EGRP GENMASK_ULL(50, 48) 4736 #define IPSEC_GEN_CFG_OPCODE GENMASK_ULL(47, 32) 4737 #define IPSEC_GEN_CFG_PARAM1 GENMASK_ULL(31, 16) 4738 #define IPSEC_GEN_CFG_PARAM2 GENMASK_ULL(15, 0) 4739 4740 #define CPT_INST_QSEL_BLOCK GENMASK_ULL(28, 24) 4741 #define CPT_INST_QSEL_PF_FUNC GENMASK_ULL(23, 8) 4742 #define CPT_INST_QSEL_SLOT GENMASK_ULL(7, 0) 4743 4744 #define CPT_INST_CREDIT_TH GENMASK_ULL(53, 32) 4745 #define CPT_INST_CREDIT_BPID GENMASK_ULL(30, 22) 4746 #define CPT_INST_CREDIT_CNT GENMASK_ULL(21, 0) 4747 4748 static void nix_inline_ipsec_cfg(struct rvu *rvu, struct nix_inline_ipsec_cfg *req, 4749 int blkaddr) 4750 { 4751 u8 cpt_idx, cpt_blkaddr; 4752 u64 val; 4753 4754 cpt_idx = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 4755 if (req->enable) { 4756 val = 0; 4757 /* Enable context prefetching */ 4758 if (!is_rvu_otx2(rvu)) 4759 val |= BIT_ULL(51); 4760 4761 /* Set OPCODE and EGRP */ 4762 val |= FIELD_PREP(IPSEC_GEN_CFG_EGRP, req->gen_cfg.egrp); 4763 val |= FIELD_PREP(IPSEC_GEN_CFG_OPCODE, req->gen_cfg.opcode); 4764 val |= FIELD_PREP(IPSEC_GEN_CFG_PARAM1, req->gen_cfg.param1); 4765 val |= FIELD_PREP(IPSEC_GEN_CFG_PARAM2, req->gen_cfg.param2); 4766 4767 rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, val); 4768 4769 /* Set CPT queue for inline IPSec */ 4770 val = FIELD_PREP(CPT_INST_QSEL_SLOT, req->inst_qsel.cpt_slot); 4771 val |= FIELD_PREP(CPT_INST_QSEL_PF_FUNC, 4772 req->inst_qsel.cpt_pf_func); 4773 4774 if (!is_rvu_otx2(rvu)) { 4775 cpt_blkaddr = (cpt_idx == 0) ? BLKADDR_CPT0 : 4776 BLKADDR_CPT1; 4777 val |= FIELD_PREP(CPT_INST_QSEL_BLOCK, cpt_blkaddr); 4778 } 4779 4780 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx), 4781 val); 4782 4783 /* Set CPT credit */ 4784 val = rvu_read64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx)); 4785 if ((val & 0x3FFFFF) != 0x3FFFFF) 4786 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), 4787 0x3FFFFF - val); 4788 4789 val = FIELD_PREP(CPT_INST_CREDIT_CNT, req->cpt_credit); 4790 val |= FIELD_PREP(CPT_INST_CREDIT_BPID, req->bpid); 4791 val |= FIELD_PREP(CPT_INST_CREDIT_TH, req->credit_th); 4792 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), val); 4793 } else { 4794 rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, 0x0); 4795 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx), 4796 0x0); 4797 val = rvu_read64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx)); 4798 if ((val & 0x3FFFFF) != 0x3FFFFF) 4799 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), 4800 0x3FFFFF - val); 4801 } 4802 } 4803 4804 int rvu_mbox_handler_nix_inline_ipsec_cfg(struct rvu *rvu, 4805 struct nix_inline_ipsec_cfg *req, 4806 struct msg_rsp *rsp) 4807 { 4808 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) 4809 return 0; 4810 4811 nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX0); 4812 if (is_block_implemented(rvu->hw, BLKADDR_CPT1)) 4813 nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX1); 4814 4815 return 0; 4816 } 4817 4818 int rvu_mbox_handler_nix_read_inline_ipsec_cfg(struct rvu *rvu, 4819 struct msg_req *req, 4820 struct nix_inline_ipsec_cfg *rsp) 4821 4822 { 4823 u64 val; 4824 4825 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) 4826 return 0; 4827 4828 val = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_RX_IPSEC_GEN_CFG); 4829 rsp->gen_cfg.egrp = FIELD_GET(IPSEC_GEN_CFG_EGRP, val); 4830 rsp->gen_cfg.opcode = FIELD_GET(IPSEC_GEN_CFG_OPCODE, val); 4831 rsp->gen_cfg.param1 = FIELD_GET(IPSEC_GEN_CFG_PARAM1, val); 4832 rsp->gen_cfg.param2 = FIELD_GET(IPSEC_GEN_CFG_PARAM2, val); 4833 4834 val = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_RX_CPTX_CREDIT(0)); 4835 rsp->cpt_credit = FIELD_GET(CPT_INST_CREDIT_CNT, val); 4836 rsp->credit_th = FIELD_GET(CPT_INST_CREDIT_TH, val); 4837 rsp->bpid = FIELD_GET(CPT_INST_CREDIT_BPID, val); 4838 4839 return 0; 4840 } 4841 4842 int rvu_mbox_handler_nix_inline_ipsec_lf_cfg(struct rvu *rvu, 4843 struct nix_inline_ipsec_lf_cfg *req, 4844 struct msg_rsp *rsp) 4845 { 4846 int lf, blkaddr, err; 4847 u64 val; 4848 4849 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) 4850 return 0; 4851 4852 err = nix_get_nixlf(rvu, req->hdr.pcifunc, &lf, &blkaddr); 4853 if (err) 4854 return err; 4855 4856 if (req->enable) { 4857 /* Set TT, TAG_CONST, SA_POW2_SIZE and LENM1_MAX */ 4858 val = (u64)req->ipsec_cfg0.tt << 44 | 4859 (u64)req->ipsec_cfg0.tag_const << 20 | 4860 (u64)req->ipsec_cfg0.sa_pow2_size << 16 | 4861 req->ipsec_cfg0.lenm1_max; 4862 4863 if (blkaddr == BLKADDR_NIX1) 4864 val |= BIT_ULL(46); 4865 4866 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG0(lf), val); 4867 4868 /* Set SA_IDX_W and SA_IDX_MAX */ 4869 val = (u64)req->ipsec_cfg1.sa_idx_w << 32 | 4870 req->ipsec_cfg1.sa_idx_max; 4871 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(lf), val); 4872 4873 /* Set SA base address */ 4874 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(lf), 4875 req->sa_base_addr); 4876 } else { 4877 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG0(lf), 0x0); 4878 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(lf), 0x0); 4879 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(lf), 4880 0x0); 4881 } 4882 4883 return 0; 4884 } 4885 4886 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc) 4887 { 4888 bool from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK); 4889 4890 /* overwrite vf mac address with default_mac */ 4891 if (from_vf) 4892 ether_addr_copy(pfvf->mac_addr, pfvf->default_mac); 4893 } 4894 4895 /* NIX ingress policers or bandwidth profiles APIs */ 4896 static void nix_config_rx_pkt_policer_precolor(struct rvu *rvu, int blkaddr) 4897 { 4898 struct npc_lt_def_cfg defs, *ltdefs; 4899 4900 ltdefs = &defs; 4901 memcpy(ltdefs, rvu->kpu.lt_def, sizeof(struct npc_lt_def_cfg)); 4902 4903 /* Extract PCP and DEI fields from outer VLAN from byte offset 4904 * 2 from the start of LB_PTR (ie TAG). 4905 * VLAN0 is Outer VLAN and VLAN1 is Inner VLAN. Inner VLAN 4906 * fields are considered when 'Tunnel enable' is set in profile. 4907 */ 4908 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN0_PCP_DEI, 4909 (2UL << 12) | (ltdefs->ovlan.lid << 8) | 4910 (ltdefs->ovlan.ltype_match << 4) | 4911 ltdefs->ovlan.ltype_mask); 4912 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN1_PCP_DEI, 4913 (2UL << 12) | (ltdefs->ivlan.lid << 8) | 4914 (ltdefs->ivlan.ltype_match << 4) | 4915 ltdefs->ivlan.ltype_mask); 4916 4917 /* DSCP field in outer and tunneled IPv4 packets */ 4918 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4_DSCP, 4919 (1UL << 12) | (ltdefs->rx_oip4.lid << 8) | 4920 (ltdefs->rx_oip4.ltype_match << 4) | 4921 ltdefs->rx_oip4.ltype_mask); 4922 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4_DSCP, 4923 (1UL << 12) | (ltdefs->rx_iip4.lid << 8) | 4924 (ltdefs->rx_iip4.ltype_match << 4) | 4925 ltdefs->rx_iip4.ltype_mask); 4926 4927 /* DSCP field (traffic class) in outer and tunneled IPv6 packets */ 4928 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6_DSCP, 4929 (1UL << 11) | (ltdefs->rx_oip6.lid << 8) | 4930 (ltdefs->rx_oip6.ltype_match << 4) | 4931 ltdefs->rx_oip6.ltype_mask); 4932 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6_DSCP, 4933 (1UL << 11) | (ltdefs->rx_iip6.lid << 8) | 4934 (ltdefs->rx_iip6.ltype_match << 4) | 4935 ltdefs->rx_iip6.ltype_mask); 4936 } 4937 4938 static int nix_init_policer_context(struct rvu *rvu, struct nix_hw *nix_hw, 4939 int layer, int prof_idx) 4940 { 4941 struct nix_cn10k_aq_enq_req aq_req; 4942 int rc; 4943 4944 memset(&aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 4945 4946 aq_req.qidx = (prof_idx & 0x3FFF) | (layer << 14); 4947 aq_req.ctype = NIX_AQ_CTYPE_BANDPROF; 4948 aq_req.op = NIX_AQ_INSTOP_INIT; 4949 4950 /* Context is all zeros, submit to AQ */ 4951 rc = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 4952 (struct nix_aq_enq_req *)&aq_req, NULL); 4953 if (rc) 4954 dev_err(rvu->dev, "Failed to INIT bandwidth profile layer %d profile %d\n", 4955 layer, prof_idx); 4956 return rc; 4957 } 4958 4959 static int nix_setup_ipolicers(struct rvu *rvu, 4960 struct nix_hw *nix_hw, int blkaddr) 4961 { 4962 struct rvu_hwinfo *hw = rvu->hw; 4963 struct nix_ipolicer *ipolicer; 4964 int err, layer, prof_idx; 4965 u64 cfg; 4966 4967 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST); 4968 if (!(cfg & BIT_ULL(61))) { 4969 hw->cap.ipolicer = false; 4970 return 0; 4971 } 4972 4973 hw->cap.ipolicer = true; 4974 nix_hw->ipolicer = devm_kcalloc(rvu->dev, BAND_PROF_NUM_LAYERS, 4975 sizeof(*ipolicer), GFP_KERNEL); 4976 if (!nix_hw->ipolicer) 4977 return -ENOMEM; 4978 4979 cfg = rvu_read64(rvu, blkaddr, NIX_AF_PL_CONST); 4980 4981 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 4982 ipolicer = &nix_hw->ipolicer[layer]; 4983 switch (layer) { 4984 case BAND_PROF_LEAF_LAYER: 4985 ipolicer->band_prof.max = cfg & 0XFFFF; 4986 break; 4987 case BAND_PROF_MID_LAYER: 4988 ipolicer->band_prof.max = (cfg >> 16) & 0XFFFF; 4989 break; 4990 case BAND_PROF_TOP_LAYER: 4991 ipolicer->band_prof.max = (cfg >> 32) & 0XFFFF; 4992 break; 4993 } 4994 4995 if (!ipolicer->band_prof.max) 4996 continue; 4997 4998 err = rvu_alloc_bitmap(&ipolicer->band_prof); 4999 if (err) 5000 return err; 5001 5002 ipolicer->pfvf_map = devm_kcalloc(rvu->dev, 5003 ipolicer->band_prof.max, 5004 sizeof(u16), GFP_KERNEL); 5005 if (!ipolicer->pfvf_map) 5006 return -ENOMEM; 5007 5008 ipolicer->match_id = devm_kcalloc(rvu->dev, 5009 ipolicer->band_prof.max, 5010 sizeof(u16), GFP_KERNEL); 5011 if (!ipolicer->match_id) 5012 return -ENOMEM; 5013 5014 for (prof_idx = 0; 5015 prof_idx < ipolicer->band_prof.max; prof_idx++) { 5016 /* Set AF as current owner for INIT ops to succeed */ 5017 ipolicer->pfvf_map[prof_idx] = 0x00; 5018 5019 /* There is no enable bit in the profile context, 5020 * so no context disable. So let's INIT them here 5021 * so that PF/VF later on have to just do WRITE to 5022 * setup policer rates and config. 5023 */ 5024 err = nix_init_policer_context(rvu, nix_hw, 5025 layer, prof_idx); 5026 if (err) 5027 return err; 5028 } 5029 5030 /* Allocate memory for maintaining ref_counts for MID level 5031 * profiles, this will be needed for leaf layer profiles' 5032 * aggregation. 5033 */ 5034 if (layer != BAND_PROF_MID_LAYER) 5035 continue; 5036 5037 ipolicer->ref_count = devm_kcalloc(rvu->dev, 5038 ipolicer->band_prof.max, 5039 sizeof(u16), GFP_KERNEL); 5040 if (!ipolicer->ref_count) 5041 return -ENOMEM; 5042 } 5043 5044 /* Set policer timeunit to 2us ie (19 + 1) * 100 nsec = 2us */ 5045 rvu_write64(rvu, blkaddr, NIX_AF_PL_TS, 19); 5046 5047 nix_config_rx_pkt_policer_precolor(rvu, blkaddr); 5048 5049 return 0; 5050 } 5051 5052 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw) 5053 { 5054 struct nix_ipolicer *ipolicer; 5055 int layer; 5056 5057 if (!rvu->hw->cap.ipolicer) 5058 return; 5059 5060 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5061 ipolicer = &nix_hw->ipolicer[layer]; 5062 5063 if (!ipolicer->band_prof.max) 5064 continue; 5065 5066 kfree(ipolicer->band_prof.bmap); 5067 } 5068 } 5069 5070 static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req, 5071 struct nix_hw *nix_hw, u16 pcifunc) 5072 { 5073 struct nix_ipolicer *ipolicer; 5074 int layer, hi_layer, prof_idx; 5075 5076 /* Bits [15:14] in profile index represent layer */ 5077 layer = (req->qidx >> 14) & 0x03; 5078 prof_idx = req->qidx & 0x3FFF; 5079 5080 ipolicer = &nix_hw->ipolicer[layer]; 5081 if (prof_idx >= ipolicer->band_prof.max) 5082 return -EINVAL; 5083 5084 /* Check if the profile is allocated to the requesting PCIFUNC or not 5085 * with the exception of AF. AF is allowed to read and update contexts. 5086 */ 5087 if (pcifunc && ipolicer->pfvf_map[prof_idx] != pcifunc) 5088 return -EINVAL; 5089 5090 /* If this profile is linked to higher layer profile then check 5091 * if that profile is also allocated to the requesting PCIFUNC 5092 * or not. 5093 */ 5094 if (!req->prof.hl_en) 5095 return 0; 5096 5097 /* Leaf layer profile can link only to mid layer and 5098 * mid layer to top layer. 5099 */ 5100 if (layer == BAND_PROF_LEAF_LAYER) 5101 hi_layer = BAND_PROF_MID_LAYER; 5102 else if (layer == BAND_PROF_MID_LAYER) 5103 hi_layer = BAND_PROF_TOP_LAYER; 5104 else 5105 return -EINVAL; 5106 5107 ipolicer = &nix_hw->ipolicer[hi_layer]; 5108 prof_idx = req->prof.band_prof_id; 5109 if (prof_idx >= ipolicer->band_prof.max || 5110 ipolicer->pfvf_map[prof_idx] != pcifunc) 5111 return -EINVAL; 5112 5113 return 0; 5114 } 5115 5116 int rvu_mbox_handler_nix_bandprof_alloc(struct rvu *rvu, 5117 struct nix_bandprof_alloc_req *req, 5118 struct nix_bandprof_alloc_rsp *rsp) 5119 { 5120 int blkaddr, layer, prof, idx, err; 5121 u16 pcifunc = req->hdr.pcifunc; 5122 struct nix_ipolicer *ipolicer; 5123 struct nix_hw *nix_hw; 5124 5125 if (!rvu->hw->cap.ipolicer) 5126 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5127 5128 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5129 if (err) 5130 return err; 5131 5132 mutex_lock(&rvu->rsrc_lock); 5133 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5134 if (layer == BAND_PROF_INVAL_LAYER) 5135 continue; 5136 if (!req->prof_count[layer]) 5137 continue; 5138 5139 ipolicer = &nix_hw->ipolicer[layer]; 5140 for (idx = 0; idx < req->prof_count[layer]; idx++) { 5141 /* Allocate a max of 'MAX_BANDPROF_PER_PFFUNC' profiles */ 5142 if (idx == MAX_BANDPROF_PER_PFFUNC) 5143 break; 5144 5145 prof = rvu_alloc_rsrc(&ipolicer->band_prof); 5146 if (prof < 0) 5147 break; 5148 rsp->prof_count[layer]++; 5149 rsp->prof_idx[layer][idx] = prof; 5150 ipolicer->pfvf_map[prof] = pcifunc; 5151 } 5152 } 5153 mutex_unlock(&rvu->rsrc_lock); 5154 return 0; 5155 } 5156 5157 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc) 5158 { 5159 int blkaddr, layer, prof_idx, err; 5160 struct nix_ipolicer *ipolicer; 5161 struct nix_hw *nix_hw; 5162 5163 if (!rvu->hw->cap.ipolicer) 5164 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5165 5166 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5167 if (err) 5168 return err; 5169 5170 mutex_lock(&rvu->rsrc_lock); 5171 /* Free all the profiles allocated to the PCIFUNC */ 5172 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5173 if (layer == BAND_PROF_INVAL_LAYER) 5174 continue; 5175 ipolicer = &nix_hw->ipolicer[layer]; 5176 5177 for (prof_idx = 0; prof_idx < ipolicer->band_prof.max; prof_idx++) { 5178 if (ipolicer->pfvf_map[prof_idx] != pcifunc) 5179 continue; 5180 5181 /* Clear ratelimit aggregation, if any */ 5182 if (layer == BAND_PROF_LEAF_LAYER && 5183 ipolicer->match_id[prof_idx]) 5184 nix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx); 5185 5186 ipolicer->pfvf_map[prof_idx] = 0x00; 5187 ipolicer->match_id[prof_idx] = 0; 5188 rvu_free_rsrc(&ipolicer->band_prof, prof_idx); 5189 } 5190 } 5191 mutex_unlock(&rvu->rsrc_lock); 5192 return 0; 5193 } 5194 5195 int rvu_mbox_handler_nix_bandprof_free(struct rvu *rvu, 5196 struct nix_bandprof_free_req *req, 5197 struct msg_rsp *rsp) 5198 { 5199 int blkaddr, layer, prof_idx, idx, err; 5200 u16 pcifunc = req->hdr.pcifunc; 5201 struct nix_ipolicer *ipolicer; 5202 struct nix_hw *nix_hw; 5203 5204 if (req->free_all) 5205 return nix_free_all_bandprof(rvu, pcifunc); 5206 5207 if (!rvu->hw->cap.ipolicer) 5208 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5209 5210 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5211 if (err) 5212 return err; 5213 5214 mutex_lock(&rvu->rsrc_lock); 5215 /* Free the requested profile indices */ 5216 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5217 if (layer == BAND_PROF_INVAL_LAYER) 5218 continue; 5219 if (!req->prof_count[layer]) 5220 continue; 5221 5222 ipolicer = &nix_hw->ipolicer[layer]; 5223 for (idx = 0; idx < req->prof_count[layer]; idx++) { 5224 prof_idx = req->prof_idx[layer][idx]; 5225 if (prof_idx >= ipolicer->band_prof.max || 5226 ipolicer->pfvf_map[prof_idx] != pcifunc) 5227 continue; 5228 5229 /* Clear ratelimit aggregation, if any */ 5230 if (layer == BAND_PROF_LEAF_LAYER && 5231 ipolicer->match_id[prof_idx]) 5232 nix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx); 5233 5234 ipolicer->pfvf_map[prof_idx] = 0x00; 5235 ipolicer->match_id[prof_idx] = 0; 5236 rvu_free_rsrc(&ipolicer->band_prof, prof_idx); 5237 if (idx == MAX_BANDPROF_PER_PFFUNC) 5238 break; 5239 } 5240 } 5241 mutex_unlock(&rvu->rsrc_lock); 5242 return 0; 5243 } 5244 5245 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 5246 struct nix_cn10k_aq_enq_req *aq_req, 5247 struct nix_cn10k_aq_enq_rsp *aq_rsp, 5248 u16 pcifunc, u8 ctype, u32 qidx) 5249 { 5250 memset(aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5251 aq_req->hdr.pcifunc = pcifunc; 5252 aq_req->ctype = ctype; 5253 aq_req->op = NIX_AQ_INSTOP_READ; 5254 aq_req->qidx = qidx; 5255 5256 return rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5257 (struct nix_aq_enq_req *)aq_req, 5258 (struct nix_aq_enq_rsp *)aq_rsp); 5259 } 5260 5261 static int nix_ipolicer_map_leaf_midprofs(struct rvu *rvu, 5262 struct nix_hw *nix_hw, 5263 struct nix_cn10k_aq_enq_req *aq_req, 5264 struct nix_cn10k_aq_enq_rsp *aq_rsp, 5265 u32 leaf_prof, u16 mid_prof) 5266 { 5267 memset(aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5268 aq_req->hdr.pcifunc = 0x00; 5269 aq_req->ctype = NIX_AQ_CTYPE_BANDPROF; 5270 aq_req->op = NIX_AQ_INSTOP_WRITE; 5271 aq_req->qidx = leaf_prof; 5272 5273 aq_req->prof.band_prof_id = mid_prof; 5274 aq_req->prof_mask.band_prof_id = GENMASK(6, 0); 5275 aq_req->prof.hl_en = 1; 5276 aq_req->prof_mask.hl_en = 1; 5277 5278 return rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5279 (struct nix_aq_enq_req *)aq_req, 5280 (struct nix_aq_enq_rsp *)aq_rsp); 5281 } 5282 5283 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 5284 u16 rq_idx, u16 match_id) 5285 { 5286 int leaf_prof, mid_prof, leaf_match; 5287 struct nix_cn10k_aq_enq_req aq_req; 5288 struct nix_cn10k_aq_enq_rsp aq_rsp; 5289 struct nix_ipolicer *ipolicer; 5290 struct nix_hw *nix_hw; 5291 int blkaddr, idx, rc; 5292 5293 if (!rvu->hw->cap.ipolicer) 5294 return 0; 5295 5296 rc = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5297 if (rc) 5298 return rc; 5299 5300 /* Fetch the RQ's context to see if policing is enabled */ 5301 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, pcifunc, 5302 NIX_AQ_CTYPE_RQ, rq_idx); 5303 if (rc) { 5304 dev_err(rvu->dev, 5305 "%s: Failed to fetch RQ%d context of PFFUNC 0x%x\n", 5306 __func__, rq_idx, pcifunc); 5307 return rc; 5308 } 5309 5310 if (!aq_rsp.rq.policer_ena) 5311 return 0; 5312 5313 /* Get the bandwidth profile ID mapped to this RQ */ 5314 leaf_prof = aq_rsp.rq.band_prof_id; 5315 5316 ipolicer = &nix_hw->ipolicer[BAND_PROF_LEAF_LAYER]; 5317 ipolicer->match_id[leaf_prof] = match_id; 5318 5319 /* Check if any other leaf profile is marked with same match_id */ 5320 for (idx = 0; idx < ipolicer->band_prof.max; idx++) { 5321 if (idx == leaf_prof) 5322 continue; 5323 if (ipolicer->match_id[idx] != match_id) 5324 continue; 5325 5326 leaf_match = idx; 5327 break; 5328 } 5329 5330 if (idx == ipolicer->band_prof.max) 5331 return 0; 5332 5333 /* Fetch the matching profile's context to check if it's already 5334 * mapped to a mid level profile. 5335 */ 5336 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5337 NIX_AQ_CTYPE_BANDPROF, leaf_match); 5338 if (rc) { 5339 dev_err(rvu->dev, 5340 "%s: Failed to fetch context of leaf profile %d\n", 5341 __func__, leaf_match); 5342 return rc; 5343 } 5344 5345 ipolicer = &nix_hw->ipolicer[BAND_PROF_MID_LAYER]; 5346 if (aq_rsp.prof.hl_en) { 5347 /* Get Mid layer prof index and map leaf_prof index 5348 * also such that flows that are being steered 5349 * to different RQs and marked with same match_id 5350 * are rate limited in a aggregate fashion 5351 */ 5352 mid_prof = aq_rsp.prof.band_prof_id; 5353 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5354 &aq_req, &aq_rsp, 5355 leaf_prof, mid_prof); 5356 if (rc) { 5357 dev_err(rvu->dev, 5358 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5359 __func__, leaf_prof, mid_prof); 5360 goto exit; 5361 } 5362 5363 mutex_lock(&rvu->rsrc_lock); 5364 ipolicer->ref_count[mid_prof]++; 5365 mutex_unlock(&rvu->rsrc_lock); 5366 goto exit; 5367 } 5368 5369 /* Allocate a mid layer profile and 5370 * map both 'leaf_prof' and 'leaf_match' profiles to it. 5371 */ 5372 mutex_lock(&rvu->rsrc_lock); 5373 mid_prof = rvu_alloc_rsrc(&ipolicer->band_prof); 5374 if (mid_prof < 0) { 5375 dev_err(rvu->dev, 5376 "%s: Unable to allocate mid layer profile\n", __func__); 5377 mutex_unlock(&rvu->rsrc_lock); 5378 goto exit; 5379 } 5380 mutex_unlock(&rvu->rsrc_lock); 5381 ipolicer->pfvf_map[mid_prof] = 0x00; 5382 ipolicer->ref_count[mid_prof] = 0; 5383 5384 /* Initialize mid layer profile same as 'leaf_prof' */ 5385 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5386 NIX_AQ_CTYPE_BANDPROF, leaf_prof); 5387 if (rc) { 5388 dev_err(rvu->dev, 5389 "%s: Failed to fetch context of leaf profile %d\n", 5390 __func__, leaf_prof); 5391 goto exit; 5392 } 5393 5394 memset(&aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5395 aq_req.hdr.pcifunc = 0x00; 5396 aq_req.qidx = (mid_prof & 0x3FFF) | (BAND_PROF_MID_LAYER << 14); 5397 aq_req.ctype = NIX_AQ_CTYPE_BANDPROF; 5398 aq_req.op = NIX_AQ_INSTOP_WRITE; 5399 memcpy(&aq_req.prof, &aq_rsp.prof, sizeof(struct nix_bandprof_s)); 5400 memset((char *)&aq_req.prof_mask, 0xff, sizeof(struct nix_bandprof_s)); 5401 /* Clear higher layer enable bit in the mid profile, just in case */ 5402 aq_req.prof.hl_en = 0; 5403 aq_req.prof_mask.hl_en = 1; 5404 5405 rc = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5406 (struct nix_aq_enq_req *)&aq_req, NULL); 5407 if (rc) { 5408 dev_err(rvu->dev, 5409 "%s: Failed to INIT context of mid layer profile %d\n", 5410 __func__, mid_prof); 5411 goto exit; 5412 } 5413 5414 /* Map both leaf profiles to this mid layer profile */ 5415 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5416 &aq_req, &aq_rsp, 5417 leaf_prof, mid_prof); 5418 if (rc) { 5419 dev_err(rvu->dev, 5420 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5421 __func__, leaf_prof, mid_prof); 5422 goto exit; 5423 } 5424 5425 mutex_lock(&rvu->rsrc_lock); 5426 ipolicer->ref_count[mid_prof]++; 5427 mutex_unlock(&rvu->rsrc_lock); 5428 5429 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5430 &aq_req, &aq_rsp, 5431 leaf_match, mid_prof); 5432 if (rc) { 5433 dev_err(rvu->dev, 5434 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5435 __func__, leaf_match, mid_prof); 5436 ipolicer->ref_count[mid_prof]--; 5437 goto exit; 5438 } 5439 5440 mutex_lock(&rvu->rsrc_lock); 5441 ipolicer->ref_count[mid_prof]++; 5442 mutex_unlock(&rvu->rsrc_lock); 5443 5444 exit: 5445 return rc; 5446 } 5447 5448 /* Called with mutex rsrc_lock */ 5449 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw, 5450 u32 leaf_prof) 5451 { 5452 struct nix_cn10k_aq_enq_req aq_req; 5453 struct nix_cn10k_aq_enq_rsp aq_rsp; 5454 struct nix_ipolicer *ipolicer; 5455 u16 mid_prof; 5456 int rc; 5457 5458 mutex_unlock(&rvu->rsrc_lock); 5459 5460 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5461 NIX_AQ_CTYPE_BANDPROF, leaf_prof); 5462 5463 mutex_lock(&rvu->rsrc_lock); 5464 if (rc) { 5465 dev_err(rvu->dev, 5466 "%s: Failed to fetch context of leaf profile %d\n", 5467 __func__, leaf_prof); 5468 return; 5469 } 5470 5471 if (!aq_rsp.prof.hl_en) 5472 return; 5473 5474 mid_prof = aq_rsp.prof.band_prof_id; 5475 ipolicer = &nix_hw->ipolicer[BAND_PROF_MID_LAYER]; 5476 ipolicer->ref_count[mid_prof]--; 5477 /* If ref_count is zero, free mid layer profile */ 5478 if (!ipolicer->ref_count[mid_prof]) { 5479 ipolicer->pfvf_map[mid_prof] = 0x00; 5480 rvu_free_rsrc(&ipolicer->band_prof, mid_prof); 5481 } 5482 } 5483 5484 int rvu_mbox_handler_nix_bandprof_get_hwinfo(struct rvu *rvu, struct msg_req *req, 5485 struct nix_bandprof_get_hwinfo_rsp *rsp) 5486 { 5487 struct nix_ipolicer *ipolicer; 5488 int blkaddr, layer, err; 5489 struct nix_hw *nix_hw; 5490 u64 tu; 5491 5492 if (!rvu->hw->cap.ipolicer) 5493 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5494 5495 err = nix_get_struct_ptrs(rvu, req->hdr.pcifunc, &nix_hw, &blkaddr); 5496 if (err) 5497 return err; 5498 5499 /* Return number of bandwidth profiles free at each layer */ 5500 mutex_lock(&rvu->rsrc_lock); 5501 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5502 if (layer == BAND_PROF_INVAL_LAYER) 5503 continue; 5504 5505 ipolicer = &nix_hw->ipolicer[layer]; 5506 rsp->prof_count[layer] = rvu_rsrc_free_count(&ipolicer->band_prof); 5507 } 5508 mutex_unlock(&rvu->rsrc_lock); 5509 5510 /* Set the policer timeunit in nanosec */ 5511 tu = rvu_read64(rvu, blkaddr, NIX_AF_PL_TS) & GENMASK_ULL(9, 0); 5512 rsp->policer_timeunit = (tu + 1) * 100; 5513 5514 return 0; 5515 } 5516