1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/pci.h> 10 11 #include "rvu_struct.h" 12 #include "rvu_reg.h" 13 #include "rvu.h" 14 #include "npc.h" 15 #include "cgx.h" 16 #include "lmac_common.h" 17 #include "rvu_npc_hash.h" 18 19 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc); 20 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, 21 int type, int chan_id); 22 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc, 23 int type, bool add); 24 static int nix_setup_ipolicers(struct rvu *rvu, 25 struct nix_hw *nix_hw, int blkaddr); 26 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw); 27 static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req, 28 struct nix_hw *nix_hw, u16 pcifunc); 29 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc); 30 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw, 31 u32 leaf_prof); 32 static const char *nix_get_ctx_name(int ctype); 33 34 enum mc_tbl_sz { 35 MC_TBL_SZ_256, 36 MC_TBL_SZ_512, 37 MC_TBL_SZ_1K, 38 MC_TBL_SZ_2K, 39 MC_TBL_SZ_4K, 40 MC_TBL_SZ_8K, 41 MC_TBL_SZ_16K, 42 MC_TBL_SZ_32K, 43 MC_TBL_SZ_64K, 44 }; 45 46 enum mc_buf_cnt { 47 MC_BUF_CNT_8, 48 MC_BUF_CNT_16, 49 MC_BUF_CNT_32, 50 MC_BUF_CNT_64, 51 MC_BUF_CNT_128, 52 MC_BUF_CNT_256, 53 MC_BUF_CNT_512, 54 MC_BUF_CNT_1024, 55 MC_BUF_CNT_2048, 56 }; 57 58 enum nix_makr_fmt_indexes { 59 NIX_MARK_CFG_IP_DSCP_RED, 60 NIX_MARK_CFG_IP_DSCP_YELLOW, 61 NIX_MARK_CFG_IP_DSCP_YELLOW_RED, 62 NIX_MARK_CFG_IP_ECN_RED, 63 NIX_MARK_CFG_IP_ECN_YELLOW, 64 NIX_MARK_CFG_IP_ECN_YELLOW_RED, 65 NIX_MARK_CFG_VLAN_DEI_RED, 66 NIX_MARK_CFG_VLAN_DEI_YELLOW, 67 NIX_MARK_CFG_VLAN_DEI_YELLOW_RED, 68 NIX_MARK_CFG_MAX, 69 }; 70 71 /* For now considering MC resources needed for broadcast 72 * pkt replication only. i.e 256 HWVFs + 12 PFs. 73 */ 74 #define MC_TBL_SIZE MC_TBL_SZ_512 75 #define MC_BUF_CNT MC_BUF_CNT_128 76 77 struct mce { 78 struct hlist_node node; 79 u16 pcifunc; 80 }; 81 82 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr) 83 { 84 int i = 0; 85 86 /*If blkaddr is 0, return the first nix block address*/ 87 if (blkaddr == 0) 88 return rvu->nix_blkaddr[blkaddr]; 89 90 while (i + 1 < MAX_NIX_BLKS) { 91 if (rvu->nix_blkaddr[i] == blkaddr) 92 return rvu->nix_blkaddr[i + 1]; 93 i++; 94 } 95 96 return 0; 97 } 98 99 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc) 100 { 101 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 102 int blkaddr; 103 104 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 105 if (!pfvf->nixlf || blkaddr < 0) 106 return false; 107 return true; 108 } 109 110 int rvu_get_nixlf_count(struct rvu *rvu) 111 { 112 int blkaddr = 0, max = 0; 113 struct rvu_block *block; 114 115 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 116 while (blkaddr) { 117 block = &rvu->hw->block[blkaddr]; 118 max += block->lf.max; 119 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 120 } 121 return max; 122 } 123 124 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr) 125 { 126 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 127 struct rvu_hwinfo *hw = rvu->hw; 128 int blkaddr; 129 130 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 131 if (!pfvf->nixlf || blkaddr < 0) 132 return NIX_AF_ERR_AF_LF_INVALID; 133 134 *nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 135 if (*nixlf < 0) 136 return NIX_AF_ERR_AF_LF_INVALID; 137 138 if (nix_blkaddr) 139 *nix_blkaddr = blkaddr; 140 141 return 0; 142 } 143 144 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 145 struct nix_hw **nix_hw, int *blkaddr) 146 { 147 struct rvu_pfvf *pfvf; 148 149 pfvf = rvu_get_pfvf(rvu, pcifunc); 150 *blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 151 if (!pfvf->nixlf || *blkaddr < 0) 152 return NIX_AF_ERR_AF_LF_INVALID; 153 154 *nix_hw = get_nix_hw(rvu->hw, *blkaddr); 155 if (!*nix_hw) 156 return NIX_AF_ERR_INVALID_NIXBLK; 157 return 0; 158 } 159 160 static void nix_mce_list_init(struct nix_mce_list *list, int max) 161 { 162 INIT_HLIST_HEAD(&list->head); 163 list->count = 0; 164 list->max = max; 165 } 166 167 static u16 nix_alloc_mce_list(struct nix_mcast *mcast, int count) 168 { 169 int idx; 170 171 if (!mcast) 172 return 0; 173 174 idx = mcast->next_free_mce; 175 mcast->next_free_mce += count; 176 return idx; 177 } 178 179 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr) 180 { 181 int nix_blkaddr = 0, i = 0; 182 struct rvu *rvu = hw->rvu; 183 184 nix_blkaddr = rvu_get_next_nix_blkaddr(rvu, nix_blkaddr); 185 while (nix_blkaddr) { 186 if (blkaddr == nix_blkaddr && hw->nix) 187 return &hw->nix[i]; 188 nix_blkaddr = rvu_get_next_nix_blkaddr(rvu, nix_blkaddr); 189 i++; 190 } 191 return NULL; 192 } 193 194 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu) 195 { 196 dwrr_mtu &= 0x1FULL; 197 198 /* MTU used for DWRR calculation is in power of 2 up until 64K bytes. 199 * Value of 4 is reserved for MTU value of 9728 bytes. 200 * Value of 5 is reserved for MTU value of 10240 bytes. 201 */ 202 switch (dwrr_mtu) { 203 case 4: 204 return 9728; 205 case 5: 206 return 10240; 207 default: 208 return BIT_ULL(dwrr_mtu); 209 } 210 211 return 0; 212 } 213 214 u32 convert_bytes_to_dwrr_mtu(u32 bytes) 215 { 216 /* MTU used for DWRR calculation is in power of 2 up until 64K bytes. 217 * Value of 4 is reserved for MTU value of 9728 bytes. 218 * Value of 5 is reserved for MTU value of 10240 bytes. 219 */ 220 if (bytes > BIT_ULL(16)) 221 return 0; 222 223 switch (bytes) { 224 case 9728: 225 return 4; 226 case 10240: 227 return 5; 228 default: 229 return ilog2(bytes); 230 } 231 232 return 0; 233 } 234 235 static void nix_rx_sync(struct rvu *rvu, int blkaddr) 236 { 237 int err; 238 239 /* Sync all in flight RX packets to LLC/DRAM */ 240 rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); 241 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true); 242 if (err) 243 dev_err(rvu->dev, "SYNC1: NIX RX software sync failed\n"); 244 245 /* SW_SYNC ensures all existing transactions are finished and pkts 246 * are written to LLC/DRAM, queues should be teared down after 247 * successful SW_SYNC. Due to a HW errata, in some rare scenarios 248 * an existing transaction might end after SW_SYNC operation. To 249 * ensure operation is fully done, do the SW_SYNC twice. 250 */ 251 rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); 252 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true); 253 if (err) 254 dev_err(rvu->dev, "SYNC2: NIX RX software sync failed\n"); 255 } 256 257 static bool is_valid_txschq(struct rvu *rvu, int blkaddr, 258 int lvl, u16 pcifunc, u16 schq) 259 { 260 struct rvu_hwinfo *hw = rvu->hw; 261 struct nix_txsch *txsch; 262 struct nix_hw *nix_hw; 263 u16 map_func; 264 265 nix_hw = get_nix_hw(rvu->hw, blkaddr); 266 if (!nix_hw) 267 return false; 268 269 txsch = &nix_hw->txsch[lvl]; 270 /* Check out of bounds */ 271 if (schq >= txsch->schq.max) 272 return false; 273 274 mutex_lock(&rvu->rsrc_lock); 275 map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]); 276 mutex_unlock(&rvu->rsrc_lock); 277 278 /* TLs aggegating traffic are shared across PF and VFs */ 279 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 280 if (rvu_get_pf(map_func) != rvu_get_pf(pcifunc)) 281 return false; 282 else 283 return true; 284 } 285 286 if (map_func != pcifunc) 287 return false; 288 289 return true; 290 } 291 292 static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf, 293 struct nix_lf_alloc_rsp *rsp, bool loop) 294 { 295 struct rvu_pfvf *parent_pf, *pfvf = rvu_get_pfvf(rvu, pcifunc); 296 u16 req_chan_base, req_chan_end, req_chan_cnt; 297 struct rvu_hwinfo *hw = rvu->hw; 298 struct sdp_node_info *sdp_info; 299 int pkind, pf, vf, lbkid, vfid; 300 u8 cgx_id, lmac_id; 301 bool from_vf; 302 int err; 303 304 pf = rvu_get_pf(pcifunc); 305 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK && 306 type != NIX_INTF_TYPE_SDP) 307 return 0; 308 309 switch (type) { 310 case NIX_INTF_TYPE_CGX: 311 pfvf->cgx_lmac = rvu->pf2cgxlmac_map[pf]; 312 rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id); 313 314 pkind = rvu_npc_get_pkind(rvu, pf); 315 if (pkind < 0) { 316 dev_err(rvu->dev, 317 "PF_Func 0x%x: Invalid pkind\n", pcifunc); 318 return -EINVAL; 319 } 320 pfvf->rx_chan_base = rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0); 321 pfvf->tx_chan_base = pfvf->rx_chan_base; 322 pfvf->rx_chan_cnt = 1; 323 pfvf->tx_chan_cnt = 1; 324 rsp->tx_link = cgx_id * hw->lmac_per_cgx + lmac_id; 325 326 cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, pkind); 327 rvu_npc_set_pkind(rvu, pkind, pfvf); 328 329 break; 330 case NIX_INTF_TYPE_LBK: 331 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 332 333 /* If NIX1 block is present on the silicon then NIXes are 334 * assigned alternatively for lbk interfaces. NIX0 should 335 * send packets on lbk link 1 channels and NIX1 should send 336 * on lbk link 0 channels for the communication between 337 * NIX0 and NIX1. 338 */ 339 lbkid = 0; 340 if (rvu->hw->lbk_links > 1) 341 lbkid = vf & 0x1 ? 0 : 1; 342 343 /* By default NIX0 is configured to send packet on lbk link 1 344 * (which corresponds to LBK1), same packet will receive on 345 * NIX1 over lbk link 0. If NIX1 sends packet on lbk link 0 346 * (which corresponds to LBK2) packet will receive on NIX0 lbk 347 * link 1. 348 * But if lbk links for NIX0 and NIX1 are negated, i.e NIX0 349 * transmits and receives on lbk link 0, whick corresponds 350 * to LBK1 block, back to back connectivity between NIX and 351 * LBK can be achieved (which is similar to 96xx) 352 * 353 * RX TX 354 * NIX0 lbk link 1 (LBK2) 1 (LBK1) 355 * NIX0 lbk link 0 (LBK0) 0 (LBK0) 356 * NIX1 lbk link 0 (LBK1) 0 (LBK2) 357 * NIX1 lbk link 1 (LBK3) 1 (LBK3) 358 */ 359 if (loop) 360 lbkid = !lbkid; 361 362 /* Note that AF's VFs work in pairs and talk over consecutive 363 * loopback channels.Therefore if odd number of AF VFs are 364 * enabled then the last VF remains with no pair. 365 */ 366 pfvf->rx_chan_base = rvu_nix_chan_lbk(rvu, lbkid, vf); 367 pfvf->tx_chan_base = vf & 0x1 ? 368 rvu_nix_chan_lbk(rvu, lbkid, vf - 1) : 369 rvu_nix_chan_lbk(rvu, lbkid, vf + 1); 370 pfvf->rx_chan_cnt = 1; 371 pfvf->tx_chan_cnt = 1; 372 rsp->tx_link = hw->cgx_links + lbkid; 373 pfvf->lbkid = lbkid; 374 rvu_npc_set_pkind(rvu, NPC_RX_LBK_PKIND, pfvf); 375 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 376 pfvf->rx_chan_base, 377 pfvf->rx_chan_cnt); 378 379 break; 380 case NIX_INTF_TYPE_SDP: 381 from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK); 382 parent_pf = &rvu->pf[rvu_get_pf(pcifunc)]; 383 sdp_info = parent_pf->sdp_info; 384 if (!sdp_info) { 385 dev_err(rvu->dev, "Invalid sdp_info pointer\n"); 386 return -EINVAL; 387 } 388 if (from_vf) { 389 req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn + 390 sdp_info->num_pf_rings; 391 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 392 for (vfid = 0; vfid < vf; vfid++) 393 req_chan_base += sdp_info->vf_rings[vfid]; 394 req_chan_cnt = sdp_info->vf_rings[vf]; 395 req_chan_end = req_chan_base + req_chan_cnt - 1; 396 if (req_chan_base < rvu_nix_chan_sdp(rvu, 0) || 397 req_chan_end > rvu_nix_chan_sdp(rvu, 255)) { 398 dev_err(rvu->dev, 399 "PF_Func 0x%x: Invalid channel base and count\n", 400 pcifunc); 401 return -EINVAL; 402 } 403 } else { 404 req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn; 405 req_chan_cnt = sdp_info->num_pf_rings; 406 } 407 408 pfvf->rx_chan_base = req_chan_base; 409 pfvf->rx_chan_cnt = req_chan_cnt; 410 pfvf->tx_chan_base = pfvf->rx_chan_base; 411 pfvf->tx_chan_cnt = pfvf->rx_chan_cnt; 412 413 rsp->tx_link = hw->cgx_links + hw->lbk_links; 414 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 415 pfvf->rx_chan_base, 416 pfvf->rx_chan_cnt); 417 break; 418 } 419 420 /* Add a UCAST forwarding rule in MCAM with this NIXLF attached 421 * RVU PF/VF's MAC address. 422 */ 423 rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, 424 pfvf->rx_chan_base, pfvf->mac_addr); 425 426 /* Add this PF_FUNC to bcast pkt replication list */ 427 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, true); 428 if (err) { 429 dev_err(rvu->dev, 430 "Bcast list, failed to enable PF_FUNC 0x%x\n", 431 pcifunc); 432 return err; 433 } 434 /* Install MCAM rule matching Ethernet broadcast mac address */ 435 rvu_npc_install_bcast_match_entry(rvu, pcifunc, 436 nixlf, pfvf->rx_chan_base); 437 438 pfvf->maxlen = NIC_HW_MIN_FRS; 439 pfvf->minlen = NIC_HW_MIN_FRS; 440 441 return 0; 442 } 443 444 static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf) 445 { 446 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 447 int err; 448 449 pfvf->maxlen = 0; 450 pfvf->minlen = 0; 451 452 /* Remove this PF_FUNC from bcast pkt replication list */ 453 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, false); 454 if (err) { 455 dev_err(rvu->dev, 456 "Bcast list, failed to disable PF_FUNC 0x%x\n", 457 pcifunc); 458 } 459 460 /* Free and disable any MCAM entries used by this NIX LF */ 461 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 462 463 /* Disable DMAC filters used */ 464 rvu_cgx_disable_dmac_entries(rvu, pcifunc); 465 } 466 467 int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu, 468 struct nix_bp_cfg_req *req, 469 struct msg_rsp *rsp) 470 { 471 u16 pcifunc = req->hdr.pcifunc; 472 struct rvu_pfvf *pfvf; 473 int blkaddr, pf, type; 474 u16 chan_base, chan; 475 u64 cfg; 476 477 pf = rvu_get_pf(pcifunc); 478 type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 479 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK) 480 return 0; 481 482 pfvf = rvu_get_pfvf(rvu, pcifunc); 483 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 484 485 chan_base = pfvf->rx_chan_base + req->chan_base; 486 for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) { 487 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan)); 488 rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan), 489 cfg & ~BIT_ULL(16)); 490 } 491 return 0; 492 } 493 494 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, 495 int type, int chan_id) 496 { 497 int bpid, blkaddr, lmac_chan_cnt, sdp_chan_cnt; 498 u16 cgx_bpid_cnt, lbk_bpid_cnt, sdp_bpid_cnt; 499 struct rvu_hwinfo *hw = rvu->hw; 500 struct rvu_pfvf *pfvf; 501 u8 cgx_id, lmac_id; 502 u64 cfg; 503 504 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc); 505 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST); 506 lmac_chan_cnt = cfg & 0xFF; 507 508 cgx_bpid_cnt = hw->cgx_links * lmac_chan_cnt; 509 lbk_bpid_cnt = hw->lbk_links * ((cfg >> 16) & 0xFF); 510 511 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 512 sdp_chan_cnt = cfg & 0xFFF; 513 sdp_bpid_cnt = hw->sdp_links * sdp_chan_cnt; 514 515 pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 516 517 /* Backpressure IDs range division 518 * CGX channles are mapped to (0 - 191) BPIDs 519 * LBK channles are mapped to (192 - 255) BPIDs 520 * SDP channles are mapped to (256 - 511) BPIDs 521 * 522 * Lmac channles and bpids mapped as follows 523 * cgx(0)_lmac(0)_chan(0 - 15) = bpid(0 - 15) 524 * cgx(0)_lmac(1)_chan(0 - 15) = bpid(16 - 31) .... 525 * cgx(1)_lmac(0)_chan(0 - 15) = bpid(64 - 79) .... 526 */ 527 switch (type) { 528 case NIX_INTF_TYPE_CGX: 529 if ((req->chan_base + req->chan_cnt) > 16) 530 return -EINVAL; 531 rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id); 532 /* Assign bpid based on cgx, lmac and chan id */ 533 bpid = (cgx_id * hw->lmac_per_cgx * lmac_chan_cnt) + 534 (lmac_id * lmac_chan_cnt) + req->chan_base; 535 536 if (req->bpid_per_chan) 537 bpid += chan_id; 538 if (bpid > cgx_bpid_cnt) 539 return -EINVAL; 540 break; 541 542 case NIX_INTF_TYPE_LBK: 543 if ((req->chan_base + req->chan_cnt) > 63) 544 return -EINVAL; 545 bpid = cgx_bpid_cnt + req->chan_base; 546 if (req->bpid_per_chan) 547 bpid += chan_id; 548 if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt)) 549 return -EINVAL; 550 break; 551 case NIX_INTF_TYPE_SDP: 552 if ((req->chan_base + req->chan_cnt) > 255) 553 return -EINVAL; 554 555 bpid = sdp_bpid_cnt + req->chan_base; 556 if (req->bpid_per_chan) 557 bpid += chan_id; 558 559 if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt + sdp_bpid_cnt)) 560 return -EINVAL; 561 break; 562 default: 563 return -EINVAL; 564 } 565 return bpid; 566 } 567 568 int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu, 569 struct nix_bp_cfg_req *req, 570 struct nix_bp_cfg_rsp *rsp) 571 { 572 int blkaddr, pf, type, chan_id = 0; 573 u16 pcifunc = req->hdr.pcifunc; 574 struct rvu_pfvf *pfvf; 575 u16 chan_base, chan; 576 s16 bpid, bpid_base; 577 u64 cfg; 578 579 pf = rvu_get_pf(pcifunc); 580 type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 581 if (is_sdp_pfvf(pcifunc)) 582 type = NIX_INTF_TYPE_SDP; 583 584 /* Enable backpressure only for CGX mapped PFs and LBK/SDP interface */ 585 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK && 586 type != NIX_INTF_TYPE_SDP) 587 return 0; 588 589 pfvf = rvu_get_pfvf(rvu, pcifunc); 590 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 591 592 bpid_base = rvu_nix_get_bpid(rvu, req, type, chan_id); 593 chan_base = pfvf->rx_chan_base + req->chan_base; 594 bpid = bpid_base; 595 596 for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) { 597 if (bpid < 0) { 598 dev_warn(rvu->dev, "Fail to enable backpressure\n"); 599 return -EINVAL; 600 } 601 602 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan)); 603 cfg &= ~GENMASK_ULL(8, 0); 604 rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan), 605 cfg | (bpid & GENMASK_ULL(8, 0)) | BIT_ULL(16)); 606 chan_id++; 607 bpid = rvu_nix_get_bpid(rvu, req, type, chan_id); 608 } 609 610 for (chan = 0; chan < req->chan_cnt; chan++) { 611 /* Map channel and bpid assign to it */ 612 rsp->chan_bpid[chan] = ((req->chan_base + chan) & 0x7F) << 10 | 613 (bpid_base & 0x3FF); 614 if (req->bpid_per_chan) 615 bpid_base++; 616 } 617 rsp->chan_cnt = req->chan_cnt; 618 619 return 0; 620 } 621 622 static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr, 623 u64 format, bool v4, u64 *fidx) 624 { 625 struct nix_lso_format field = {0}; 626 627 /* IP's Length field */ 628 field.layer = NIX_TXLAYER_OL3; 629 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 630 field.offset = v4 ? 2 : 4; 631 field.sizem1 = 1; /* i.e 2 bytes */ 632 field.alg = NIX_LSOALG_ADD_PAYLEN; 633 rvu_write64(rvu, blkaddr, 634 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 635 *(u64 *)&field); 636 637 /* No ID field in IPv6 header */ 638 if (!v4) 639 return; 640 641 /* IP's ID field */ 642 field.layer = NIX_TXLAYER_OL3; 643 field.offset = 4; 644 field.sizem1 = 1; /* i.e 2 bytes */ 645 field.alg = NIX_LSOALG_ADD_SEGNUM; 646 rvu_write64(rvu, blkaddr, 647 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 648 *(u64 *)&field); 649 } 650 651 static void nix_setup_lso_tso_l4(struct rvu *rvu, int blkaddr, 652 u64 format, u64 *fidx) 653 { 654 struct nix_lso_format field = {0}; 655 656 /* TCP's sequence number field */ 657 field.layer = NIX_TXLAYER_OL4; 658 field.offset = 4; 659 field.sizem1 = 3; /* i.e 4 bytes */ 660 field.alg = NIX_LSOALG_ADD_OFFSET; 661 rvu_write64(rvu, blkaddr, 662 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 663 *(u64 *)&field); 664 665 /* TCP's flags field */ 666 field.layer = NIX_TXLAYER_OL4; 667 field.offset = 12; 668 field.sizem1 = 1; /* 2 bytes */ 669 field.alg = NIX_LSOALG_TCP_FLAGS; 670 rvu_write64(rvu, blkaddr, 671 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 672 *(u64 *)&field); 673 } 674 675 static void nix_setup_lso(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 676 { 677 u64 cfg, idx, fidx = 0; 678 679 /* Get max HW supported format indices */ 680 cfg = (rvu_read64(rvu, blkaddr, NIX_AF_CONST1) >> 48) & 0xFF; 681 nix_hw->lso.total = cfg; 682 683 /* Enable LSO */ 684 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LSO_CFG); 685 /* For TSO, set first and middle segment flags to 686 * mask out PSH, RST & FIN flags in TCP packet 687 */ 688 cfg &= ~((0xFFFFULL << 32) | (0xFFFFULL << 16)); 689 cfg |= (0xFFF2ULL << 32) | (0xFFF2ULL << 16); 690 rvu_write64(rvu, blkaddr, NIX_AF_LSO_CFG, cfg | BIT_ULL(63)); 691 692 /* Setup default static LSO formats 693 * 694 * Configure format fields for TCPv4 segmentation offload 695 */ 696 idx = NIX_LSO_FORMAT_IDX_TSOV4; 697 nix_setup_lso_tso_l3(rvu, blkaddr, idx, true, &fidx); 698 nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx); 699 700 /* Set rest of the fields to NOP */ 701 for (; fidx < 8; fidx++) { 702 rvu_write64(rvu, blkaddr, 703 NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL); 704 } 705 nix_hw->lso.in_use++; 706 707 /* Configure format fields for TCPv6 segmentation offload */ 708 idx = NIX_LSO_FORMAT_IDX_TSOV6; 709 fidx = 0; 710 nix_setup_lso_tso_l3(rvu, blkaddr, idx, false, &fidx); 711 nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx); 712 713 /* Set rest of the fields to NOP */ 714 for (; fidx < 8; fidx++) { 715 rvu_write64(rvu, blkaddr, 716 NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL); 717 } 718 nix_hw->lso.in_use++; 719 } 720 721 static void nix_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf) 722 { 723 kfree(pfvf->rq_bmap); 724 kfree(pfvf->sq_bmap); 725 kfree(pfvf->cq_bmap); 726 if (pfvf->rq_ctx) 727 qmem_free(rvu->dev, pfvf->rq_ctx); 728 if (pfvf->sq_ctx) 729 qmem_free(rvu->dev, pfvf->sq_ctx); 730 if (pfvf->cq_ctx) 731 qmem_free(rvu->dev, pfvf->cq_ctx); 732 if (pfvf->rss_ctx) 733 qmem_free(rvu->dev, pfvf->rss_ctx); 734 if (pfvf->nix_qints_ctx) 735 qmem_free(rvu->dev, pfvf->nix_qints_ctx); 736 if (pfvf->cq_ints_ctx) 737 qmem_free(rvu->dev, pfvf->cq_ints_ctx); 738 739 pfvf->rq_bmap = NULL; 740 pfvf->cq_bmap = NULL; 741 pfvf->sq_bmap = NULL; 742 pfvf->rq_ctx = NULL; 743 pfvf->sq_ctx = NULL; 744 pfvf->cq_ctx = NULL; 745 pfvf->rss_ctx = NULL; 746 pfvf->nix_qints_ctx = NULL; 747 pfvf->cq_ints_ctx = NULL; 748 } 749 750 static int nixlf_rss_ctx_init(struct rvu *rvu, int blkaddr, 751 struct rvu_pfvf *pfvf, int nixlf, 752 int rss_sz, int rss_grps, int hwctx_size, 753 u64 way_mask, bool tag_lsb_as_adder) 754 { 755 int err, grp, num_indices; 756 u64 val; 757 758 /* RSS is not requested for this NIXLF */ 759 if (!rss_sz) 760 return 0; 761 num_indices = rss_sz * rss_grps; 762 763 /* Alloc NIX RSS HW context memory and config the base */ 764 err = qmem_alloc(rvu->dev, &pfvf->rss_ctx, num_indices, hwctx_size); 765 if (err) 766 return err; 767 768 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_BASE(nixlf), 769 (u64)pfvf->rss_ctx->iova); 770 771 /* Config full RSS table size, enable RSS and caching */ 772 val = BIT_ULL(36) | BIT_ULL(4) | way_mask << 20 | 773 ilog2(num_indices / MAX_RSS_INDIR_TBL_SIZE); 774 775 if (tag_lsb_as_adder) 776 val |= BIT_ULL(5); 777 778 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf), val); 779 /* Config RSS group offset and sizes */ 780 for (grp = 0; grp < rss_grps; grp++) 781 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_GRPX(nixlf, grp), 782 ((ilog2(rss_sz) - 1) << 16) | (rss_sz * grp)); 783 return 0; 784 } 785 786 static int nix_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block, 787 struct nix_aq_inst_s *inst) 788 { 789 struct admin_queue *aq = block->aq; 790 struct nix_aq_res_s *result; 791 int timeout = 1000; 792 u64 reg, head; 793 int ret; 794 795 result = (struct nix_aq_res_s *)aq->res->base; 796 797 /* Get current head pointer where to append this instruction */ 798 reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS); 799 head = (reg >> 4) & AQ_PTR_MASK; 800 801 memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)), 802 (void *)inst, aq->inst->entry_sz); 803 memset(result, 0, sizeof(*result)); 804 /* sync into memory */ 805 wmb(); 806 807 /* Ring the doorbell and wait for result */ 808 rvu_write64(rvu, block->addr, NIX_AF_AQ_DOOR, 1); 809 while (result->compcode == NIX_AQ_COMP_NOTDONE) { 810 cpu_relax(); 811 udelay(1); 812 timeout--; 813 if (!timeout) 814 return -EBUSY; 815 } 816 817 if (result->compcode != NIX_AQ_COMP_GOOD) { 818 /* TODO: Replace this with some error code */ 819 if (result->compcode == NIX_AQ_COMP_CTX_FAULT || 820 result->compcode == NIX_AQ_COMP_LOCKERR || 821 result->compcode == NIX_AQ_COMP_CTX_POISON) { 822 ret = rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX0_RX); 823 ret |= rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX0_TX); 824 ret |= rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX1_RX); 825 ret |= rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NIX1_TX); 826 if (ret) 827 dev_err(rvu->dev, 828 "%s: Not able to unlock cachelines\n", __func__); 829 } 830 831 return -EBUSY; 832 } 833 834 return 0; 835 } 836 837 static int rvu_nix_blk_aq_enq_inst(struct rvu *rvu, struct nix_hw *nix_hw, 838 struct nix_aq_enq_req *req, 839 struct nix_aq_enq_rsp *rsp) 840 { 841 struct rvu_hwinfo *hw = rvu->hw; 842 u16 pcifunc = req->hdr.pcifunc; 843 int nixlf, blkaddr, rc = 0; 844 struct nix_aq_inst_s inst; 845 struct rvu_block *block; 846 struct admin_queue *aq; 847 struct rvu_pfvf *pfvf; 848 void *ctx, *mask; 849 bool ena; 850 u64 cfg; 851 852 blkaddr = nix_hw->blkaddr; 853 block = &hw->block[blkaddr]; 854 aq = block->aq; 855 if (!aq) { 856 dev_warn(rvu->dev, "%s: NIX AQ not initialized\n", __func__); 857 return NIX_AF_ERR_AQ_ENQUEUE; 858 } 859 860 pfvf = rvu_get_pfvf(rvu, pcifunc); 861 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 862 863 /* Skip NIXLF check for broadcast MCE entry and bandwidth profile 864 * operations done by AF itself. 865 */ 866 if (!((!rsp && req->ctype == NIX_AQ_CTYPE_MCE) || 867 (req->ctype == NIX_AQ_CTYPE_BANDPROF && !pcifunc))) { 868 if (!pfvf->nixlf || nixlf < 0) 869 return NIX_AF_ERR_AF_LF_INVALID; 870 } 871 872 switch (req->ctype) { 873 case NIX_AQ_CTYPE_RQ: 874 /* Check if index exceeds max no of queues */ 875 if (!pfvf->rq_ctx || req->qidx >= pfvf->rq_ctx->qsize) 876 rc = NIX_AF_ERR_AQ_ENQUEUE; 877 break; 878 case NIX_AQ_CTYPE_SQ: 879 if (!pfvf->sq_ctx || req->qidx >= pfvf->sq_ctx->qsize) 880 rc = NIX_AF_ERR_AQ_ENQUEUE; 881 break; 882 case NIX_AQ_CTYPE_CQ: 883 if (!pfvf->cq_ctx || req->qidx >= pfvf->cq_ctx->qsize) 884 rc = NIX_AF_ERR_AQ_ENQUEUE; 885 break; 886 case NIX_AQ_CTYPE_RSS: 887 /* Check if RSS is enabled and qidx is within range */ 888 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf)); 889 if (!(cfg & BIT_ULL(4)) || !pfvf->rss_ctx || 890 (req->qidx >= (256UL << (cfg & 0xF)))) 891 rc = NIX_AF_ERR_AQ_ENQUEUE; 892 break; 893 case NIX_AQ_CTYPE_MCE: 894 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG); 895 896 /* Check if index exceeds MCE list length */ 897 if (!nix_hw->mcast.mce_ctx || 898 (req->qidx >= (256UL << (cfg & 0xF)))) 899 rc = NIX_AF_ERR_AQ_ENQUEUE; 900 901 /* Adding multicast lists for requests from PF/VFs is not 902 * yet supported, so ignore this. 903 */ 904 if (rsp) 905 rc = NIX_AF_ERR_AQ_ENQUEUE; 906 break; 907 case NIX_AQ_CTYPE_BANDPROF: 908 if (nix_verify_bandprof((struct nix_cn10k_aq_enq_req *)req, 909 nix_hw, pcifunc)) 910 rc = NIX_AF_ERR_INVALID_BANDPROF; 911 break; 912 default: 913 rc = NIX_AF_ERR_AQ_ENQUEUE; 914 } 915 916 if (rc) 917 return rc; 918 919 /* Check if SQ pointed SMQ belongs to this PF/VF or not */ 920 if (req->ctype == NIX_AQ_CTYPE_SQ && 921 ((req->op == NIX_AQ_INSTOP_INIT && req->sq.ena) || 922 (req->op == NIX_AQ_INSTOP_WRITE && 923 req->sq_mask.ena && req->sq_mask.smq && req->sq.ena))) { 924 if (!is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_SMQ, 925 pcifunc, req->sq.smq)) 926 return NIX_AF_ERR_AQ_ENQUEUE; 927 } 928 929 memset(&inst, 0, sizeof(struct nix_aq_inst_s)); 930 inst.lf = nixlf; 931 inst.cindex = req->qidx; 932 inst.ctype = req->ctype; 933 inst.op = req->op; 934 /* Currently we are not supporting enqueuing multiple instructions, 935 * so always choose first entry in result memory. 936 */ 937 inst.res_addr = (u64)aq->res->iova; 938 939 /* Hardware uses same aq->res->base for updating result of 940 * previous instruction hence wait here till it is done. 941 */ 942 spin_lock(&aq->lock); 943 944 /* Clean result + context memory */ 945 memset(aq->res->base, 0, aq->res->entry_sz); 946 /* Context needs to be written at RES_ADDR + 128 */ 947 ctx = aq->res->base + 128; 948 /* Mask needs to be written at RES_ADDR + 256 */ 949 mask = aq->res->base + 256; 950 951 switch (req->op) { 952 case NIX_AQ_INSTOP_WRITE: 953 if (req->ctype == NIX_AQ_CTYPE_RQ) 954 memcpy(mask, &req->rq_mask, 955 sizeof(struct nix_rq_ctx_s)); 956 else if (req->ctype == NIX_AQ_CTYPE_SQ) 957 memcpy(mask, &req->sq_mask, 958 sizeof(struct nix_sq_ctx_s)); 959 else if (req->ctype == NIX_AQ_CTYPE_CQ) 960 memcpy(mask, &req->cq_mask, 961 sizeof(struct nix_cq_ctx_s)); 962 else if (req->ctype == NIX_AQ_CTYPE_RSS) 963 memcpy(mask, &req->rss_mask, 964 sizeof(struct nix_rsse_s)); 965 else if (req->ctype == NIX_AQ_CTYPE_MCE) 966 memcpy(mask, &req->mce_mask, 967 sizeof(struct nix_rx_mce_s)); 968 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 969 memcpy(mask, &req->prof_mask, 970 sizeof(struct nix_bandprof_s)); 971 fallthrough; 972 case NIX_AQ_INSTOP_INIT: 973 if (req->ctype == NIX_AQ_CTYPE_RQ) 974 memcpy(ctx, &req->rq, sizeof(struct nix_rq_ctx_s)); 975 else if (req->ctype == NIX_AQ_CTYPE_SQ) 976 memcpy(ctx, &req->sq, sizeof(struct nix_sq_ctx_s)); 977 else if (req->ctype == NIX_AQ_CTYPE_CQ) 978 memcpy(ctx, &req->cq, sizeof(struct nix_cq_ctx_s)); 979 else if (req->ctype == NIX_AQ_CTYPE_RSS) 980 memcpy(ctx, &req->rss, sizeof(struct nix_rsse_s)); 981 else if (req->ctype == NIX_AQ_CTYPE_MCE) 982 memcpy(ctx, &req->mce, sizeof(struct nix_rx_mce_s)); 983 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 984 memcpy(ctx, &req->prof, sizeof(struct nix_bandprof_s)); 985 break; 986 case NIX_AQ_INSTOP_NOP: 987 case NIX_AQ_INSTOP_READ: 988 case NIX_AQ_INSTOP_LOCK: 989 case NIX_AQ_INSTOP_UNLOCK: 990 break; 991 default: 992 rc = NIX_AF_ERR_AQ_ENQUEUE; 993 spin_unlock(&aq->lock); 994 return rc; 995 } 996 997 /* Submit the instruction to AQ */ 998 rc = nix_aq_enqueue_wait(rvu, block, &inst); 999 if (rc) { 1000 spin_unlock(&aq->lock); 1001 return rc; 1002 } 1003 1004 /* Set RQ/SQ/CQ bitmap if respective queue hw context is enabled */ 1005 if (req->op == NIX_AQ_INSTOP_INIT) { 1006 if (req->ctype == NIX_AQ_CTYPE_RQ && req->rq.ena) 1007 __set_bit(req->qidx, pfvf->rq_bmap); 1008 if (req->ctype == NIX_AQ_CTYPE_SQ && req->sq.ena) 1009 __set_bit(req->qidx, pfvf->sq_bmap); 1010 if (req->ctype == NIX_AQ_CTYPE_CQ && req->cq.ena) 1011 __set_bit(req->qidx, pfvf->cq_bmap); 1012 } 1013 1014 if (req->op == NIX_AQ_INSTOP_WRITE) { 1015 if (req->ctype == NIX_AQ_CTYPE_RQ) { 1016 ena = (req->rq.ena & req->rq_mask.ena) | 1017 (test_bit(req->qidx, pfvf->rq_bmap) & 1018 ~req->rq_mask.ena); 1019 if (ena) 1020 __set_bit(req->qidx, pfvf->rq_bmap); 1021 else 1022 __clear_bit(req->qidx, pfvf->rq_bmap); 1023 } 1024 if (req->ctype == NIX_AQ_CTYPE_SQ) { 1025 ena = (req->rq.ena & req->sq_mask.ena) | 1026 (test_bit(req->qidx, pfvf->sq_bmap) & 1027 ~req->sq_mask.ena); 1028 if (ena) 1029 __set_bit(req->qidx, pfvf->sq_bmap); 1030 else 1031 __clear_bit(req->qidx, pfvf->sq_bmap); 1032 } 1033 if (req->ctype == NIX_AQ_CTYPE_CQ) { 1034 ena = (req->rq.ena & req->cq_mask.ena) | 1035 (test_bit(req->qidx, pfvf->cq_bmap) & 1036 ~req->cq_mask.ena); 1037 if (ena) 1038 __set_bit(req->qidx, pfvf->cq_bmap); 1039 else 1040 __clear_bit(req->qidx, pfvf->cq_bmap); 1041 } 1042 } 1043 1044 if (rsp) { 1045 /* Copy read context into mailbox */ 1046 if (req->op == NIX_AQ_INSTOP_READ) { 1047 if (req->ctype == NIX_AQ_CTYPE_RQ) 1048 memcpy(&rsp->rq, ctx, 1049 sizeof(struct nix_rq_ctx_s)); 1050 else if (req->ctype == NIX_AQ_CTYPE_SQ) 1051 memcpy(&rsp->sq, ctx, 1052 sizeof(struct nix_sq_ctx_s)); 1053 else if (req->ctype == NIX_AQ_CTYPE_CQ) 1054 memcpy(&rsp->cq, ctx, 1055 sizeof(struct nix_cq_ctx_s)); 1056 else if (req->ctype == NIX_AQ_CTYPE_RSS) 1057 memcpy(&rsp->rss, ctx, 1058 sizeof(struct nix_rsse_s)); 1059 else if (req->ctype == NIX_AQ_CTYPE_MCE) 1060 memcpy(&rsp->mce, ctx, 1061 sizeof(struct nix_rx_mce_s)); 1062 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 1063 memcpy(&rsp->prof, ctx, 1064 sizeof(struct nix_bandprof_s)); 1065 } 1066 } 1067 1068 spin_unlock(&aq->lock); 1069 return 0; 1070 } 1071 1072 static int rvu_nix_verify_aq_ctx(struct rvu *rvu, struct nix_hw *nix_hw, 1073 struct nix_aq_enq_req *req, u8 ctype) 1074 { 1075 struct nix_cn10k_aq_enq_req aq_req; 1076 struct nix_cn10k_aq_enq_rsp aq_rsp; 1077 int rc, word; 1078 1079 if (req->ctype != NIX_AQ_CTYPE_CQ) 1080 return 0; 1081 1082 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 1083 req->hdr.pcifunc, ctype, req->qidx); 1084 if (rc) { 1085 dev_err(rvu->dev, 1086 "%s: Failed to fetch %s%d context of PFFUNC 0x%x\n", 1087 __func__, nix_get_ctx_name(ctype), req->qidx, 1088 req->hdr.pcifunc); 1089 return rc; 1090 } 1091 1092 /* Make copy of original context & mask which are required 1093 * for resubmission 1094 */ 1095 memcpy(&aq_req.cq_mask, &req->cq_mask, sizeof(struct nix_cq_ctx_s)); 1096 memcpy(&aq_req.cq, &req->cq, sizeof(struct nix_cq_ctx_s)); 1097 1098 /* exclude fields which HW can update */ 1099 aq_req.cq_mask.cq_err = 0; 1100 aq_req.cq_mask.wrptr = 0; 1101 aq_req.cq_mask.tail = 0; 1102 aq_req.cq_mask.head = 0; 1103 aq_req.cq_mask.avg_level = 0; 1104 aq_req.cq_mask.update_time = 0; 1105 aq_req.cq_mask.substream = 0; 1106 1107 /* Context mask (cq_mask) holds mask value of fields which 1108 * are changed in AQ WRITE operation. 1109 * for example cq.drop = 0xa; 1110 * cq_mask.drop = 0xff; 1111 * Below logic performs '&' between cq and cq_mask so that non 1112 * updated fields are masked out for request and response 1113 * comparison 1114 */ 1115 for (word = 0; word < sizeof(struct nix_cq_ctx_s) / sizeof(u64); 1116 word++) { 1117 *(u64 *)((u8 *)&aq_rsp.cq + word * 8) &= 1118 (*(u64 *)((u8 *)&aq_req.cq_mask + word * 8)); 1119 *(u64 *)((u8 *)&aq_req.cq + word * 8) &= 1120 (*(u64 *)((u8 *)&aq_req.cq_mask + word * 8)); 1121 } 1122 1123 if (memcmp(&aq_req.cq, &aq_rsp.cq, sizeof(struct nix_cq_ctx_s))) 1124 return NIX_AF_ERR_AQ_CTX_RETRY_WRITE; 1125 1126 return 0; 1127 } 1128 1129 static int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req, 1130 struct nix_aq_enq_rsp *rsp) 1131 { 1132 struct nix_hw *nix_hw; 1133 int err, retries = 5; 1134 int blkaddr; 1135 1136 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc); 1137 if (blkaddr < 0) 1138 return NIX_AF_ERR_AF_LF_INVALID; 1139 1140 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1141 if (!nix_hw) 1142 return NIX_AF_ERR_INVALID_NIXBLK; 1143 1144 retry: 1145 err = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, req, rsp); 1146 1147 /* HW errata 'AQ Modification to CQ could be discarded on heavy traffic' 1148 * As a work around perfrom CQ context read after each AQ write. If AQ 1149 * read shows AQ write is not updated perform AQ write again. 1150 */ 1151 if (!err && req->op == NIX_AQ_INSTOP_WRITE) { 1152 err = rvu_nix_verify_aq_ctx(rvu, nix_hw, req, NIX_AQ_CTYPE_CQ); 1153 if (err == NIX_AF_ERR_AQ_CTX_RETRY_WRITE) { 1154 if (retries--) 1155 goto retry; 1156 else 1157 return NIX_AF_ERR_CQ_CTX_WRITE_ERR; 1158 } 1159 } 1160 1161 return err; 1162 } 1163 1164 static const char *nix_get_ctx_name(int ctype) 1165 { 1166 switch (ctype) { 1167 case NIX_AQ_CTYPE_CQ: 1168 return "CQ"; 1169 case NIX_AQ_CTYPE_SQ: 1170 return "SQ"; 1171 case NIX_AQ_CTYPE_RQ: 1172 return "RQ"; 1173 case NIX_AQ_CTYPE_RSS: 1174 return "RSS"; 1175 } 1176 return ""; 1177 } 1178 1179 static int nix_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req *req) 1180 { 1181 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 1182 struct nix_aq_enq_req aq_req; 1183 unsigned long *bmap; 1184 int qidx, q_cnt = 0; 1185 int err = 0, rc; 1186 1187 if (!pfvf->cq_ctx || !pfvf->sq_ctx || !pfvf->rq_ctx) 1188 return NIX_AF_ERR_AQ_ENQUEUE; 1189 1190 memset(&aq_req, 0, sizeof(struct nix_aq_enq_req)); 1191 aq_req.hdr.pcifunc = req->hdr.pcifunc; 1192 1193 if (req->ctype == NIX_AQ_CTYPE_CQ) { 1194 aq_req.cq.ena = 0; 1195 aq_req.cq_mask.ena = 1; 1196 aq_req.cq.bp_ena = 0; 1197 aq_req.cq_mask.bp_ena = 1; 1198 q_cnt = pfvf->cq_ctx->qsize; 1199 bmap = pfvf->cq_bmap; 1200 } 1201 if (req->ctype == NIX_AQ_CTYPE_SQ) { 1202 aq_req.sq.ena = 0; 1203 aq_req.sq_mask.ena = 1; 1204 q_cnt = pfvf->sq_ctx->qsize; 1205 bmap = pfvf->sq_bmap; 1206 } 1207 if (req->ctype == NIX_AQ_CTYPE_RQ) { 1208 aq_req.rq.ena = 0; 1209 aq_req.rq_mask.ena = 1; 1210 q_cnt = pfvf->rq_ctx->qsize; 1211 bmap = pfvf->rq_bmap; 1212 } 1213 1214 aq_req.ctype = req->ctype; 1215 aq_req.op = NIX_AQ_INSTOP_WRITE; 1216 1217 for (qidx = 0; qidx < q_cnt; qidx++) { 1218 if (!test_bit(qidx, bmap)) 1219 continue; 1220 aq_req.qidx = qidx; 1221 rc = rvu_nix_aq_enq_inst(rvu, &aq_req, NULL); 1222 if (rc) { 1223 err = rc; 1224 dev_err(rvu->dev, "Failed to disable %s:%d context\n", 1225 nix_get_ctx_name(req->ctype), qidx); 1226 } 1227 } 1228 1229 return err; 1230 } 1231 1232 #ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING 1233 static int nix_lf_hwctx_lockdown(struct rvu *rvu, struct nix_aq_enq_req *req) 1234 { 1235 struct nix_aq_enq_req lock_ctx_req; 1236 int err; 1237 1238 if (req->op != NIX_AQ_INSTOP_INIT) 1239 return 0; 1240 1241 if (req->ctype == NIX_AQ_CTYPE_MCE || 1242 req->ctype == NIX_AQ_CTYPE_DYNO) 1243 return 0; 1244 1245 memset(&lock_ctx_req, 0, sizeof(struct nix_aq_enq_req)); 1246 lock_ctx_req.hdr.pcifunc = req->hdr.pcifunc; 1247 lock_ctx_req.ctype = req->ctype; 1248 lock_ctx_req.op = NIX_AQ_INSTOP_LOCK; 1249 lock_ctx_req.qidx = req->qidx; 1250 err = rvu_nix_aq_enq_inst(rvu, &lock_ctx_req, NULL); 1251 if (err) 1252 dev_err(rvu->dev, 1253 "PFUNC 0x%x: Failed to lock NIX %s:%d context\n", 1254 req->hdr.pcifunc, 1255 nix_get_ctx_name(req->ctype), req->qidx); 1256 return err; 1257 } 1258 1259 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, 1260 struct nix_aq_enq_req *req, 1261 struct nix_aq_enq_rsp *rsp) 1262 { 1263 int err; 1264 1265 err = rvu_nix_aq_enq_inst(rvu, req, rsp); 1266 if (!err) 1267 err = nix_lf_hwctx_lockdown(rvu, req); 1268 return err; 1269 } 1270 #else 1271 1272 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, 1273 struct nix_aq_enq_req *req, 1274 struct nix_aq_enq_rsp *rsp) 1275 { 1276 return rvu_nix_aq_enq_inst(rvu, req, rsp); 1277 } 1278 #endif 1279 /* CN10K mbox handler */ 1280 int rvu_mbox_handler_nix_cn10k_aq_enq(struct rvu *rvu, 1281 struct nix_cn10k_aq_enq_req *req, 1282 struct nix_cn10k_aq_enq_rsp *rsp) 1283 { 1284 return rvu_nix_aq_enq_inst(rvu, (struct nix_aq_enq_req *)req, 1285 (struct nix_aq_enq_rsp *)rsp); 1286 } 1287 1288 int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu, 1289 struct hwctx_disable_req *req, 1290 struct msg_rsp *rsp) 1291 { 1292 return nix_lf_hwctx_disable(rvu, req); 1293 } 1294 1295 int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, 1296 struct nix_lf_alloc_req *req, 1297 struct nix_lf_alloc_rsp *rsp) 1298 { 1299 int nixlf, qints, hwctx_size, intf, err, rc = 0; 1300 struct rvu_hwinfo *hw = rvu->hw; 1301 u16 pcifunc = req->hdr.pcifunc; 1302 struct rvu_block *block; 1303 struct rvu_pfvf *pfvf; 1304 u64 cfg, ctx_cfg; 1305 int blkaddr; 1306 1307 if (!req->rq_cnt || !req->sq_cnt || !req->cq_cnt) 1308 return NIX_AF_ERR_PARAM; 1309 1310 if (req->way_mask) 1311 req->way_mask &= 0xFFFF; 1312 1313 pfvf = rvu_get_pfvf(rvu, pcifunc); 1314 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1315 if (!pfvf->nixlf || blkaddr < 0) 1316 return NIX_AF_ERR_AF_LF_INVALID; 1317 1318 block = &hw->block[blkaddr]; 1319 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 1320 if (nixlf < 0) 1321 return NIX_AF_ERR_AF_LF_INVALID; 1322 1323 /* Check if requested 'NIXLF <=> NPALF' mapping is valid */ 1324 if (req->npa_func) { 1325 /* If default, use 'this' NIXLF's PFFUNC */ 1326 if (req->npa_func == RVU_DEFAULT_PF_FUNC) 1327 req->npa_func = pcifunc; 1328 if (!is_pffunc_map_valid(rvu, req->npa_func, BLKTYPE_NPA)) 1329 return NIX_AF_INVAL_NPA_PF_FUNC; 1330 } 1331 1332 /* Check if requested 'NIXLF <=> SSOLF' mapping is valid */ 1333 if (req->sso_func) { 1334 /* If default, use 'this' NIXLF's PFFUNC */ 1335 if (req->sso_func == RVU_DEFAULT_PF_FUNC) 1336 req->sso_func = pcifunc; 1337 if (!is_pffunc_map_valid(rvu, req->sso_func, BLKTYPE_SSO)) 1338 return NIX_AF_INVAL_SSO_PF_FUNC; 1339 } 1340 1341 /* If RSS is being enabled, check if requested config is valid. 1342 * RSS table size should be power of two, otherwise 1343 * RSS_GRP::OFFSET + adder might go beyond that group or 1344 * won't be able to use entire table. 1345 */ 1346 if (req->rss_sz && (req->rss_sz > MAX_RSS_INDIR_TBL_SIZE || 1347 !is_power_of_2(req->rss_sz))) 1348 return NIX_AF_ERR_RSS_SIZE_INVALID; 1349 1350 if (req->rss_sz && 1351 (!req->rss_grps || req->rss_grps > MAX_RSS_GROUPS)) 1352 return NIX_AF_ERR_RSS_GRPS_INVALID; 1353 1354 /* Reset this NIX LF */ 1355 err = rvu_lf_reset(rvu, block, nixlf); 1356 if (err) { 1357 dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", 1358 block->addr - BLKADDR_NIX0, nixlf); 1359 return NIX_AF_ERR_LF_RESET; 1360 } 1361 1362 ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3); 1363 1364 /* Alloc NIX RQ HW context memory and config the base */ 1365 hwctx_size = 1UL << ((ctx_cfg >> 4) & 0xF); 1366 err = qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size); 1367 if (err) 1368 goto free_mem; 1369 1370 pfvf->rq_bmap = kcalloc(req->rq_cnt, sizeof(long), GFP_KERNEL); 1371 if (!pfvf->rq_bmap) 1372 goto free_mem; 1373 1374 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_BASE(nixlf), 1375 (u64)pfvf->rq_ctx->iova); 1376 1377 /* Set caching and queue count in HW */ 1378 cfg = BIT_ULL(36) | (req->rq_cnt - 1) | req->way_mask << 20; 1379 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_CFG(nixlf), cfg); 1380 1381 /* Alloc NIX SQ HW context memory and config the base */ 1382 hwctx_size = 1UL << (ctx_cfg & 0xF); 1383 err = qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size); 1384 if (err) 1385 goto free_mem; 1386 1387 pfvf->sq_bmap = kcalloc(req->sq_cnt, sizeof(long), GFP_KERNEL); 1388 if (!pfvf->sq_bmap) 1389 goto free_mem; 1390 1391 rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_BASE(nixlf), 1392 (u64)pfvf->sq_ctx->iova); 1393 1394 cfg = BIT_ULL(36) | (req->sq_cnt - 1) | req->way_mask << 20; 1395 rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_CFG(nixlf), cfg); 1396 1397 /* Alloc NIX CQ HW context memory and config the base */ 1398 hwctx_size = 1UL << ((ctx_cfg >> 8) & 0xF); 1399 err = qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size); 1400 if (err) 1401 goto free_mem; 1402 1403 pfvf->cq_bmap = kcalloc(req->cq_cnt, sizeof(long), GFP_KERNEL); 1404 if (!pfvf->cq_bmap) 1405 goto free_mem; 1406 1407 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_BASE(nixlf), 1408 (u64)pfvf->cq_ctx->iova); 1409 1410 cfg = BIT_ULL(36) | (req->cq_cnt - 1) | req->way_mask << 20; 1411 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_CFG(nixlf), cfg); 1412 1413 /* Initialize receive side scaling (RSS) */ 1414 hwctx_size = 1UL << ((ctx_cfg >> 12) & 0xF); 1415 err = nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, req->rss_sz, 1416 req->rss_grps, hwctx_size, req->way_mask, 1417 !!(req->flags & NIX_LF_RSS_TAG_LSB_AS_ADDER)); 1418 if (err) 1419 goto free_mem; 1420 1421 /* Alloc memory for CQINT's HW contexts */ 1422 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1423 qints = (cfg >> 24) & 0xFFF; 1424 hwctx_size = 1UL << ((ctx_cfg >> 24) & 0xF); 1425 err = qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size); 1426 if (err) 1427 goto free_mem; 1428 1429 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_BASE(nixlf), 1430 (u64)pfvf->cq_ints_ctx->iova); 1431 1432 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_CFG(nixlf), 1433 BIT_ULL(36) | req->way_mask << 20); 1434 1435 /* Alloc memory for QINT's HW contexts */ 1436 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1437 qints = (cfg >> 12) & 0xFFF; 1438 hwctx_size = 1UL << ((ctx_cfg >> 20) & 0xF); 1439 err = qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size); 1440 if (err) 1441 goto free_mem; 1442 1443 rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_BASE(nixlf), 1444 (u64)pfvf->nix_qints_ctx->iova); 1445 rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_CFG(nixlf), 1446 BIT_ULL(36) | req->way_mask << 20); 1447 1448 /* Setup VLANX TPID's. 1449 * Use VLAN1 for 802.1Q 1450 * and VLAN0 for 802.1AD. 1451 */ 1452 cfg = (0x8100ULL << 16) | 0x88A8ULL; 1453 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg); 1454 1455 /* Enable LMTST for this NIX LF */ 1456 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG2(nixlf), BIT_ULL(0)); 1457 1458 /* Set CQE/WQE size, NPA_PF_FUNC for SQBs and also SSO_PF_FUNC */ 1459 if (req->npa_func) 1460 cfg = req->npa_func; 1461 if (req->sso_func) 1462 cfg |= (u64)req->sso_func << 16; 1463 1464 cfg |= (u64)req->xqe_sz << 33; 1465 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf), cfg); 1466 1467 /* Config Rx pkt length, csum checks and apad enable / disable */ 1468 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), req->rx_cfg); 1469 1470 /* Configure pkind for TX parse config */ 1471 cfg = NPC_TX_DEF_PKIND; 1472 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg); 1473 1474 intf = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 1475 if (is_sdp_pfvf(pcifunc)) 1476 intf = NIX_INTF_TYPE_SDP; 1477 1478 err = nix_interface_init(rvu, pcifunc, intf, nixlf, rsp, 1479 !!(req->flags & NIX_LF_LBK_BLK_SEL)); 1480 if (err) 1481 goto free_mem; 1482 1483 /* Disable NPC entries as NIXLF's contexts are not initialized yet */ 1484 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 1485 1486 /* Configure RX VTAG Type 7 (strip) for vf vlan */ 1487 rvu_write64(rvu, blkaddr, 1488 NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, NIX_AF_LFX_RX_VTAG_TYPE7), 1489 VTAGSIZE_T4 | VTAG_STRIP); 1490 1491 goto exit; 1492 1493 free_mem: 1494 nix_ctx_free(rvu, pfvf); 1495 rc = -ENOMEM; 1496 1497 exit: 1498 /* Set macaddr of this PF/VF */ 1499 ether_addr_copy(rsp->mac_addr, pfvf->mac_addr); 1500 1501 /* set SQB size info */ 1502 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQ_CONST); 1503 rsp->sqb_size = (cfg >> 34) & 0xFFFF; 1504 rsp->rx_chan_base = pfvf->rx_chan_base; 1505 rsp->tx_chan_base = pfvf->tx_chan_base; 1506 rsp->rx_chan_cnt = pfvf->rx_chan_cnt; 1507 rsp->tx_chan_cnt = pfvf->tx_chan_cnt; 1508 rsp->lso_tsov4_idx = NIX_LSO_FORMAT_IDX_TSOV4; 1509 rsp->lso_tsov6_idx = NIX_LSO_FORMAT_IDX_TSOV6; 1510 /* Get HW supported stat count */ 1511 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 1512 rsp->lf_rx_stats = ((cfg >> 32) & 0xFF); 1513 rsp->lf_tx_stats = ((cfg >> 24) & 0xFF); 1514 /* Get count of CQ IRQs and error IRQs supported per LF */ 1515 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1516 rsp->qints = ((cfg >> 12) & 0xFFF); 1517 rsp->cints = ((cfg >> 24) & 0xFFF); 1518 rsp->cgx_links = hw->cgx_links; 1519 rsp->lbk_links = hw->lbk_links; 1520 rsp->sdp_links = hw->sdp_links; 1521 1522 return rc; 1523 } 1524 1525 int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct nix_lf_free_req *req, 1526 struct msg_rsp *rsp) 1527 { 1528 struct rvu_hwinfo *hw = rvu->hw; 1529 u16 pcifunc = req->hdr.pcifunc; 1530 struct rvu_block *block; 1531 int blkaddr, nixlf, err; 1532 struct rvu_pfvf *pfvf; 1533 1534 pfvf = rvu_get_pfvf(rvu, pcifunc); 1535 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1536 if (!pfvf->nixlf || blkaddr < 0) 1537 return NIX_AF_ERR_AF_LF_INVALID; 1538 1539 block = &hw->block[blkaddr]; 1540 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 1541 if (nixlf < 0) 1542 return NIX_AF_ERR_AF_LF_INVALID; 1543 1544 if (req->flags & NIX_LF_DISABLE_FLOWS) 1545 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 1546 else 1547 rvu_npc_free_mcam_entries(rvu, pcifunc, nixlf); 1548 1549 /* Free any tx vtag def entries used by this NIX LF */ 1550 if (!(req->flags & NIX_LF_DONT_FREE_TX_VTAG)) 1551 nix_free_tx_vtag_entries(rvu, pcifunc); 1552 1553 nix_interface_deinit(rvu, pcifunc, nixlf); 1554 1555 /* Reset this NIX LF */ 1556 err = rvu_lf_reset(rvu, block, nixlf); 1557 if (err) { 1558 dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", 1559 block->addr - BLKADDR_NIX0, nixlf); 1560 return NIX_AF_ERR_LF_RESET; 1561 } 1562 1563 nix_ctx_free(rvu, pfvf); 1564 1565 return 0; 1566 } 1567 1568 int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu, 1569 struct nix_mark_format_cfg *req, 1570 struct nix_mark_format_cfg_rsp *rsp) 1571 { 1572 u16 pcifunc = req->hdr.pcifunc; 1573 struct nix_hw *nix_hw; 1574 struct rvu_pfvf *pfvf; 1575 int blkaddr, rc; 1576 u32 cfg; 1577 1578 pfvf = rvu_get_pfvf(rvu, pcifunc); 1579 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1580 if (!pfvf->nixlf || blkaddr < 0) 1581 return NIX_AF_ERR_AF_LF_INVALID; 1582 1583 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1584 if (!nix_hw) 1585 return NIX_AF_ERR_INVALID_NIXBLK; 1586 1587 cfg = (((u32)req->offset & 0x7) << 16) | 1588 (((u32)req->y_mask & 0xF) << 12) | 1589 (((u32)req->y_val & 0xF) << 8) | 1590 (((u32)req->r_mask & 0xF) << 4) | ((u32)req->r_val & 0xF); 1591 1592 rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfg); 1593 if (rc < 0) { 1594 dev_err(rvu->dev, "No mark_format_ctl for (pf:%d, vf:%d)", 1595 rvu_get_pf(pcifunc), pcifunc & RVU_PFVF_FUNC_MASK); 1596 return NIX_AF_ERR_MARK_CFG_FAIL; 1597 } 1598 1599 rsp->mark_format_idx = rc; 1600 return 0; 1601 } 1602 1603 /* Handle shaper update specially for few revisions */ 1604 static bool 1605 handle_txschq_shaper_update(struct rvu *rvu, int blkaddr, int nixlf, 1606 int lvl, u64 reg, u64 regval) 1607 { 1608 u64 regbase, oldval, sw_xoff = 0; 1609 u64 dbgval, md_debug0 = 0; 1610 unsigned long poll_tmo; 1611 bool rate_reg = 0; 1612 u32 schq; 1613 1614 regbase = reg & 0xFFFF; 1615 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 1616 1617 /* Check for rate register */ 1618 switch (lvl) { 1619 case NIX_TXSCH_LVL_TL1: 1620 md_debug0 = NIX_AF_TL1X_MD_DEBUG0(schq); 1621 sw_xoff = NIX_AF_TL1X_SW_XOFF(schq); 1622 1623 rate_reg = !!(regbase == NIX_AF_TL1X_CIR(0)); 1624 break; 1625 case NIX_TXSCH_LVL_TL2: 1626 md_debug0 = NIX_AF_TL2X_MD_DEBUG0(schq); 1627 sw_xoff = NIX_AF_TL2X_SW_XOFF(schq); 1628 1629 rate_reg = (regbase == NIX_AF_TL2X_CIR(0) || 1630 regbase == NIX_AF_TL2X_PIR(0)); 1631 break; 1632 case NIX_TXSCH_LVL_TL3: 1633 md_debug0 = NIX_AF_TL3X_MD_DEBUG0(schq); 1634 sw_xoff = NIX_AF_TL3X_SW_XOFF(schq); 1635 1636 rate_reg = (regbase == NIX_AF_TL3X_CIR(0) || 1637 regbase == NIX_AF_TL3X_PIR(0)); 1638 break; 1639 case NIX_TXSCH_LVL_TL4: 1640 md_debug0 = NIX_AF_TL4X_MD_DEBUG0(schq); 1641 sw_xoff = NIX_AF_TL4X_SW_XOFF(schq); 1642 1643 rate_reg = (regbase == NIX_AF_TL4X_CIR(0) || 1644 regbase == NIX_AF_TL4X_PIR(0)); 1645 break; 1646 case NIX_TXSCH_LVL_MDQ: 1647 sw_xoff = NIX_AF_MDQX_SW_XOFF(schq); 1648 rate_reg = (regbase == NIX_AF_MDQX_CIR(0) || 1649 regbase == NIX_AF_MDQX_PIR(0)); 1650 break; 1651 } 1652 1653 if (!rate_reg) 1654 return false; 1655 1656 /* Nothing special to do when state is not toggled */ 1657 oldval = rvu_read64(rvu, blkaddr, reg); 1658 if ((oldval & 0x1) == (regval & 0x1)) { 1659 rvu_write64(rvu, blkaddr, reg, regval); 1660 return true; 1661 } 1662 1663 /* PIR/CIR disable */ 1664 if (!(regval & 0x1)) { 1665 rvu_write64(rvu, blkaddr, sw_xoff, 1); 1666 rvu_write64(rvu, blkaddr, reg, 0); 1667 udelay(4); 1668 rvu_write64(rvu, blkaddr, sw_xoff, 0); 1669 return true; 1670 } 1671 1672 /* PIR/CIR enable */ 1673 rvu_write64(rvu, blkaddr, sw_xoff, 1); 1674 if (md_debug0) { 1675 poll_tmo = jiffies + usecs_to_jiffies(10000); 1676 /* Wait until VLD(bit32) == 1 or C_CON(bit48) == 0 */ 1677 do { 1678 if (time_after(jiffies, poll_tmo)) { 1679 dev_err(rvu->dev, 1680 "NIXLF%d: TLX%u(lvl %u) CIR/PIR enable failed\n", 1681 nixlf, schq, lvl); 1682 goto exit; 1683 } 1684 usleep_range(1, 5); 1685 dbgval = rvu_read64(rvu, blkaddr, md_debug0); 1686 } while (!(dbgval & BIT_ULL(32)) && (dbgval & BIT_ULL(48))); 1687 } 1688 rvu_write64(rvu, blkaddr, reg, regval); 1689 exit: 1690 rvu_write64(rvu, blkaddr, sw_xoff, 0); 1691 return true; 1692 } 1693 1694 /* Disable shaping of pkts by a scheduler queue 1695 * at a given scheduler level. 1696 */ 1697 static void nix_reset_tx_shaping(struct rvu *rvu, int blkaddr, 1698 int nixlf, int lvl, int schq) 1699 { 1700 struct rvu_hwinfo *hw = rvu->hw; 1701 u64 cir_reg = 0, pir_reg = 0; 1702 u64 cfg; 1703 1704 switch (lvl) { 1705 case NIX_TXSCH_LVL_TL1: 1706 cir_reg = NIX_AF_TL1X_CIR(schq); 1707 pir_reg = 0; /* PIR not available at TL1 */ 1708 break; 1709 case NIX_TXSCH_LVL_TL2: 1710 cir_reg = NIX_AF_TL2X_CIR(schq); 1711 pir_reg = NIX_AF_TL2X_PIR(schq); 1712 break; 1713 case NIX_TXSCH_LVL_TL3: 1714 cir_reg = NIX_AF_TL3X_CIR(schq); 1715 pir_reg = NIX_AF_TL3X_PIR(schq); 1716 break; 1717 case NIX_TXSCH_LVL_TL4: 1718 cir_reg = NIX_AF_TL4X_CIR(schq); 1719 pir_reg = NIX_AF_TL4X_PIR(schq); 1720 break; 1721 case NIX_TXSCH_LVL_MDQ: 1722 cir_reg = NIX_AF_MDQX_CIR(schq); 1723 pir_reg = NIX_AF_MDQX_PIR(schq); 1724 break; 1725 } 1726 1727 /* Shaper state toggle needs wait/poll */ 1728 if (hw->cap.nix_shaper_toggle_wait) { 1729 if (cir_reg) 1730 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 1731 lvl, cir_reg, 0); 1732 if (pir_reg) 1733 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 1734 lvl, pir_reg, 0); 1735 return; 1736 } 1737 1738 if (!cir_reg) 1739 return; 1740 cfg = rvu_read64(rvu, blkaddr, cir_reg); 1741 rvu_write64(rvu, blkaddr, cir_reg, cfg & ~BIT_ULL(0)); 1742 1743 if (!pir_reg) 1744 return; 1745 cfg = rvu_read64(rvu, blkaddr, pir_reg); 1746 rvu_write64(rvu, blkaddr, pir_reg, cfg & ~BIT_ULL(0)); 1747 } 1748 1749 static void nix_reset_tx_linkcfg(struct rvu *rvu, int blkaddr, 1750 int lvl, int schq) 1751 { 1752 struct rvu_hwinfo *hw = rvu->hw; 1753 int link_level; 1754 int link; 1755 1756 if (lvl >= hw->cap.nix_tx_aggr_lvl) 1757 return; 1758 1759 /* Reset TL4's SDP link config */ 1760 if (lvl == NIX_TXSCH_LVL_TL4) 1761 rvu_write64(rvu, blkaddr, NIX_AF_TL4X_SDP_LINK_CFG(schq), 0x00); 1762 1763 link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ? 1764 NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2; 1765 if (lvl != link_level) 1766 return; 1767 1768 /* Reset TL2's CGX or LBK link config */ 1769 for (link = 0; link < (hw->cgx_links + hw->lbk_links); link++) 1770 rvu_write64(rvu, blkaddr, 1771 NIX_AF_TL3_TL2X_LINKX_CFG(schq, link), 0x00); 1772 } 1773 1774 static void nix_clear_tx_xoff(struct rvu *rvu, int blkaddr, 1775 int lvl, int schq) 1776 { 1777 struct rvu_hwinfo *hw = rvu->hw; 1778 u64 reg; 1779 1780 /* Skip this if shaping is not supported */ 1781 if (!hw->cap.nix_shaping) 1782 return; 1783 1784 /* Clear level specific SW_XOFF */ 1785 switch (lvl) { 1786 case NIX_TXSCH_LVL_TL1: 1787 reg = NIX_AF_TL1X_SW_XOFF(schq); 1788 break; 1789 case NIX_TXSCH_LVL_TL2: 1790 reg = NIX_AF_TL2X_SW_XOFF(schq); 1791 break; 1792 case NIX_TXSCH_LVL_TL3: 1793 reg = NIX_AF_TL3X_SW_XOFF(schq); 1794 break; 1795 case NIX_TXSCH_LVL_TL4: 1796 reg = NIX_AF_TL4X_SW_XOFF(schq); 1797 break; 1798 case NIX_TXSCH_LVL_MDQ: 1799 reg = NIX_AF_MDQX_SW_XOFF(schq); 1800 break; 1801 default: 1802 return; 1803 } 1804 1805 rvu_write64(rvu, blkaddr, reg, 0x0); 1806 } 1807 1808 static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc) 1809 { 1810 struct rvu_hwinfo *hw = rvu->hw; 1811 int pf = rvu_get_pf(pcifunc); 1812 u8 cgx_id = 0, lmac_id = 0; 1813 1814 if (is_afvf(pcifunc)) {/* LBK links */ 1815 return hw->cgx_links; 1816 } else if (is_pf_cgxmapped(rvu, pf)) { 1817 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1818 return (cgx_id * hw->lmac_per_cgx) + lmac_id; 1819 } 1820 1821 /* SDP link */ 1822 return hw->cgx_links + hw->lbk_links; 1823 } 1824 1825 static void nix_get_txschq_range(struct rvu *rvu, u16 pcifunc, 1826 int link, int *start, int *end) 1827 { 1828 struct rvu_hwinfo *hw = rvu->hw; 1829 int pf = rvu_get_pf(pcifunc); 1830 1831 if (is_afvf(pcifunc)) { /* LBK links */ 1832 *start = hw->cap.nix_txsch_per_cgx_lmac * link; 1833 *end = *start + hw->cap.nix_txsch_per_lbk_lmac; 1834 } else if (is_pf_cgxmapped(rvu, pf)) { /* CGX links */ 1835 *start = hw->cap.nix_txsch_per_cgx_lmac * link; 1836 *end = *start + hw->cap.nix_txsch_per_cgx_lmac; 1837 } else { /* SDP link */ 1838 *start = (hw->cap.nix_txsch_per_cgx_lmac * hw->cgx_links) + 1839 (hw->cap.nix_txsch_per_lbk_lmac * hw->lbk_links); 1840 *end = *start + hw->cap.nix_txsch_per_sdp_lmac; 1841 } 1842 } 1843 1844 static int nix_check_txschq_alloc_req(struct rvu *rvu, int lvl, u16 pcifunc, 1845 struct nix_hw *nix_hw, 1846 struct nix_txsch_alloc_req *req) 1847 { 1848 struct rvu_hwinfo *hw = rvu->hw; 1849 int schq, req_schq, free_cnt; 1850 struct nix_txsch *txsch; 1851 int link, start, end; 1852 1853 txsch = &nix_hw->txsch[lvl]; 1854 req_schq = req->schq_contig[lvl] + req->schq[lvl]; 1855 1856 if (!req_schq) 1857 return 0; 1858 1859 link = nix_get_tx_link(rvu, pcifunc); 1860 1861 /* For traffic aggregating scheduler level, one queue is enough */ 1862 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 1863 if (req_schq != 1) 1864 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1865 return 0; 1866 } 1867 1868 /* Get free SCHQ count and check if request can be accomodated */ 1869 if (hw->cap.nix_fixed_txschq_mapping) { 1870 nix_get_txschq_range(rvu, pcifunc, link, &start, &end); 1871 schq = start + (pcifunc & RVU_PFVF_FUNC_MASK); 1872 if (end <= txsch->schq.max && schq < end && 1873 !test_bit(schq, txsch->schq.bmap)) 1874 free_cnt = 1; 1875 else 1876 free_cnt = 0; 1877 } else { 1878 free_cnt = rvu_rsrc_free_count(&txsch->schq); 1879 } 1880 1881 if (free_cnt < req_schq || req_schq > MAX_TXSCHQ_PER_FUNC) 1882 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1883 1884 /* If contiguous queues are needed, check for availability */ 1885 if (!hw->cap.nix_fixed_txschq_mapping && req->schq_contig[lvl] && 1886 !rvu_rsrc_check_contig(&txsch->schq, req->schq_contig[lvl])) 1887 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1888 1889 return 0; 1890 } 1891 1892 static void nix_txsch_alloc(struct rvu *rvu, struct nix_txsch *txsch, 1893 struct nix_txsch_alloc_rsp *rsp, 1894 int lvl, int start, int end) 1895 { 1896 struct rvu_hwinfo *hw = rvu->hw; 1897 u16 pcifunc = rsp->hdr.pcifunc; 1898 int idx, schq; 1899 1900 /* For traffic aggregating levels, queue alloc is based 1901 * on transmit link to which PF_FUNC is mapped to. 1902 */ 1903 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 1904 /* A single TL queue is allocated */ 1905 if (rsp->schq_contig[lvl]) { 1906 rsp->schq_contig[lvl] = 1; 1907 rsp->schq_contig_list[lvl][0] = start; 1908 } 1909 1910 /* Both contig and non-contig reqs doesn't make sense here */ 1911 if (rsp->schq_contig[lvl]) 1912 rsp->schq[lvl] = 0; 1913 1914 if (rsp->schq[lvl]) { 1915 rsp->schq[lvl] = 1; 1916 rsp->schq_list[lvl][0] = start; 1917 } 1918 return; 1919 } 1920 1921 /* Adjust the queue request count if HW supports 1922 * only one queue per level configuration. 1923 */ 1924 if (hw->cap.nix_fixed_txschq_mapping) { 1925 idx = pcifunc & RVU_PFVF_FUNC_MASK; 1926 schq = start + idx; 1927 if (idx >= (end - start) || test_bit(schq, txsch->schq.bmap)) { 1928 rsp->schq_contig[lvl] = 0; 1929 rsp->schq[lvl] = 0; 1930 return; 1931 } 1932 1933 if (rsp->schq_contig[lvl]) { 1934 rsp->schq_contig[lvl] = 1; 1935 set_bit(schq, txsch->schq.bmap); 1936 rsp->schq_contig_list[lvl][0] = schq; 1937 rsp->schq[lvl] = 0; 1938 } else if (rsp->schq[lvl]) { 1939 rsp->schq[lvl] = 1; 1940 set_bit(schq, txsch->schq.bmap); 1941 rsp->schq_list[lvl][0] = schq; 1942 } 1943 return; 1944 } 1945 1946 /* Allocate contiguous queue indices requesty first */ 1947 if (rsp->schq_contig[lvl]) { 1948 schq = bitmap_find_next_zero_area(txsch->schq.bmap, 1949 txsch->schq.max, start, 1950 rsp->schq_contig[lvl], 0); 1951 if (schq >= end) 1952 rsp->schq_contig[lvl] = 0; 1953 for (idx = 0; idx < rsp->schq_contig[lvl]; idx++) { 1954 set_bit(schq, txsch->schq.bmap); 1955 rsp->schq_contig_list[lvl][idx] = schq; 1956 schq++; 1957 } 1958 } 1959 1960 /* Allocate non-contiguous queue indices */ 1961 if (rsp->schq[lvl]) { 1962 idx = 0; 1963 for (schq = start; schq < end; schq++) { 1964 if (!test_bit(schq, txsch->schq.bmap)) { 1965 set_bit(schq, txsch->schq.bmap); 1966 rsp->schq_list[lvl][idx++] = schq; 1967 } 1968 if (idx == rsp->schq[lvl]) 1969 break; 1970 } 1971 /* Update how many were allocated */ 1972 rsp->schq[lvl] = idx; 1973 } 1974 } 1975 1976 int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu, 1977 struct nix_txsch_alloc_req *req, 1978 struct nix_txsch_alloc_rsp *rsp) 1979 { 1980 struct rvu_hwinfo *hw = rvu->hw; 1981 u16 pcifunc = req->hdr.pcifunc; 1982 int link, blkaddr, rc = 0; 1983 int lvl, idx, start, end; 1984 struct nix_txsch *txsch; 1985 struct nix_hw *nix_hw; 1986 u32 *pfvf_map; 1987 int nixlf; 1988 u16 schq; 1989 1990 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 1991 if (rc) 1992 return rc; 1993 1994 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1995 if (!nix_hw) 1996 return NIX_AF_ERR_INVALID_NIXBLK; 1997 1998 mutex_lock(&rvu->rsrc_lock); 1999 2000 /* Check if request is valid as per HW capabilities 2001 * and can be accomodated. 2002 */ 2003 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2004 rc = nix_check_txschq_alloc_req(rvu, lvl, pcifunc, nix_hw, req); 2005 if (rc) 2006 goto err; 2007 } 2008 2009 /* Allocate requested Tx scheduler queues */ 2010 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2011 txsch = &nix_hw->txsch[lvl]; 2012 pfvf_map = txsch->pfvf_map; 2013 2014 if (!req->schq[lvl] && !req->schq_contig[lvl]) 2015 continue; 2016 2017 rsp->schq[lvl] = req->schq[lvl]; 2018 rsp->schq_contig[lvl] = req->schq_contig[lvl]; 2019 2020 link = nix_get_tx_link(rvu, pcifunc); 2021 2022 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 2023 start = link; 2024 end = link; 2025 } else if (hw->cap.nix_fixed_txschq_mapping) { 2026 nix_get_txschq_range(rvu, pcifunc, link, &start, &end); 2027 } else { 2028 start = 0; 2029 end = txsch->schq.max; 2030 } 2031 2032 nix_txsch_alloc(rvu, txsch, rsp, lvl, start, end); 2033 2034 /* Reset queue config */ 2035 for (idx = 0; idx < req->schq_contig[lvl]; idx++) { 2036 schq = rsp->schq_contig_list[lvl][idx]; 2037 if (!(TXSCH_MAP_FLAGS(pfvf_map[schq]) & 2038 NIX_TXSCHQ_CFG_DONE)) 2039 pfvf_map[schq] = TXSCH_MAP(pcifunc, 0); 2040 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2041 nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq); 2042 } 2043 2044 for (idx = 0; idx < req->schq[lvl]; idx++) { 2045 schq = rsp->schq_list[lvl][idx]; 2046 if (!(TXSCH_MAP_FLAGS(pfvf_map[schq]) & 2047 NIX_TXSCHQ_CFG_DONE)) 2048 pfvf_map[schq] = TXSCH_MAP(pcifunc, 0); 2049 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2050 nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq); 2051 } 2052 } 2053 2054 rsp->aggr_level = hw->cap.nix_tx_aggr_lvl; 2055 rsp->aggr_lvl_rr_prio = TXSCH_TL1_DFLT_RR_PRIO; 2056 rsp->link_cfg_lvl = rvu_read64(rvu, blkaddr, 2057 NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ? 2058 NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2; 2059 goto exit; 2060 err: 2061 rc = NIX_AF_ERR_TLX_ALLOC_FAIL; 2062 exit: 2063 mutex_unlock(&rvu->rsrc_lock); 2064 return rc; 2065 } 2066 2067 static int nix_smq_flush(struct rvu *rvu, int blkaddr, 2068 int smq, u16 pcifunc, int nixlf) 2069 { 2070 int pf = rvu_get_pf(pcifunc); 2071 u8 cgx_id = 0, lmac_id = 0; 2072 int err, restore_tx_en = 0; 2073 u64 cfg; 2074 2075 if (!is_rvu_otx2(rvu)) { 2076 /* Skip SMQ flush if pkt count is zero */ 2077 cfg = rvu_read64(rvu, blkaddr, NIX_AF_MDQX_IN_MD_COUNT(smq)); 2078 if (!cfg) 2079 return 0; 2080 } 2081 2082 /* enable cgx tx if disabled */ 2083 if (is_pf_cgxmapped(rvu, pf)) { 2084 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 2085 restore_tx_en = !rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), 2086 lmac_id, true); 2087 } 2088 2089 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq)); 2090 /* Do SMQ flush and set enqueue xoff */ 2091 cfg |= BIT_ULL(50) | BIT_ULL(49); 2092 rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg); 2093 2094 /* Disable backpressure from physical link, 2095 * otherwise SMQ flush may stall. 2096 */ 2097 rvu_cgx_enadis_rx_bp(rvu, pf, false); 2098 2099 /* Wait for flush to complete */ 2100 err = rvu_poll_reg(rvu, blkaddr, 2101 NIX_AF_SMQX_CFG(smq), BIT_ULL(49), true); 2102 if (err) 2103 dev_err(rvu->dev, 2104 "NIXLF%d: SMQ%d flush failed\n", nixlf, smq); 2105 2106 rvu_cgx_enadis_rx_bp(rvu, pf, true); 2107 /* restore cgx tx state */ 2108 if (restore_tx_en) 2109 rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false); 2110 return err; 2111 } 2112 2113 static int nix_txschq_free(struct rvu *rvu, u16 pcifunc) 2114 { 2115 int blkaddr, nixlf, lvl, schq, err; 2116 struct rvu_hwinfo *hw = rvu->hw; 2117 struct nix_txsch *txsch; 2118 struct nix_hw *nix_hw; 2119 u16 map_func; 2120 2121 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2122 if (blkaddr < 0) 2123 return NIX_AF_ERR_AF_LF_INVALID; 2124 2125 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2126 if (!nix_hw) 2127 return NIX_AF_ERR_INVALID_NIXBLK; 2128 2129 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2130 if (nixlf < 0) 2131 return NIX_AF_ERR_AF_LF_INVALID; 2132 2133 /* Disable TL2/3 queue links and all XOFF's before SMQ flush*/ 2134 mutex_lock(&rvu->rsrc_lock); 2135 for (lvl = NIX_TXSCH_LVL_MDQ; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2136 txsch = &nix_hw->txsch[lvl]; 2137 2138 if (lvl >= hw->cap.nix_tx_aggr_lvl) 2139 continue; 2140 2141 for (schq = 0; schq < txsch->schq.max; schq++) { 2142 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2143 continue; 2144 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2145 nix_clear_tx_xoff(rvu, blkaddr, lvl, schq); 2146 } 2147 } 2148 nix_clear_tx_xoff(rvu, blkaddr, NIX_TXSCH_LVL_TL1, 2149 nix_get_tx_link(rvu, pcifunc)); 2150 2151 /* On PF cleanup, clear cfg done flag as 2152 * PF would have changed default config. 2153 */ 2154 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) { 2155 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL1]; 2156 schq = nix_get_tx_link(rvu, pcifunc); 2157 /* Do not clear pcifunc in txsch->pfvf_map[schq] because 2158 * VF might be using this TL1 queue 2159 */ 2160 map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]); 2161 txsch->pfvf_map[schq] = TXSCH_SET_FLAG(map_func, 0x0); 2162 } 2163 2164 /* Flush SMQs */ 2165 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 2166 for (schq = 0; schq < txsch->schq.max; schq++) { 2167 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2168 continue; 2169 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf); 2170 } 2171 2172 /* Now free scheduler queues to free pool */ 2173 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2174 /* TLs above aggregation level are shared across all PF 2175 * and it's VFs, hence skip freeing them. 2176 */ 2177 if (lvl >= hw->cap.nix_tx_aggr_lvl) 2178 continue; 2179 2180 txsch = &nix_hw->txsch[lvl]; 2181 for (schq = 0; schq < txsch->schq.max; schq++) { 2182 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2183 continue; 2184 rvu_free_rsrc(&txsch->schq, schq); 2185 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 2186 } 2187 } 2188 mutex_unlock(&rvu->rsrc_lock); 2189 2190 /* Sync cached info for this LF in NDC-TX to LLC/DRAM */ 2191 rvu_write64(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12) | nixlf); 2192 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12), true); 2193 if (err) 2194 dev_err(rvu->dev, "NDC-TX sync failed for NIXLF %d\n", nixlf); 2195 2196 return 0; 2197 } 2198 2199 static int nix_txschq_free_one(struct rvu *rvu, 2200 struct nix_txsch_free_req *req) 2201 { 2202 struct rvu_hwinfo *hw = rvu->hw; 2203 u16 pcifunc = req->hdr.pcifunc; 2204 int lvl, schq, nixlf, blkaddr; 2205 struct nix_txsch *txsch; 2206 struct nix_hw *nix_hw; 2207 u32 *pfvf_map; 2208 int rc; 2209 2210 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2211 if (blkaddr < 0) 2212 return NIX_AF_ERR_AF_LF_INVALID; 2213 2214 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2215 if (!nix_hw) 2216 return NIX_AF_ERR_INVALID_NIXBLK; 2217 2218 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2219 if (nixlf < 0) 2220 return NIX_AF_ERR_AF_LF_INVALID; 2221 2222 lvl = req->schq_lvl; 2223 schq = req->schq; 2224 txsch = &nix_hw->txsch[lvl]; 2225 2226 if (lvl >= hw->cap.nix_tx_aggr_lvl || schq >= txsch->schq.max) 2227 return 0; 2228 2229 pfvf_map = txsch->pfvf_map; 2230 mutex_lock(&rvu->rsrc_lock); 2231 2232 if (TXSCH_MAP_FUNC(pfvf_map[schq]) != pcifunc) { 2233 rc = NIX_AF_ERR_TLX_INVALID; 2234 goto err; 2235 } 2236 2237 /* Clear SW_XOFF of this resource only. 2238 * For SMQ level, all path XOFF's 2239 * need to be made clear by user 2240 */ 2241 nix_clear_tx_xoff(rvu, blkaddr, lvl, schq); 2242 2243 /* Flush if it is a SMQ. Onus of disabling 2244 * TL2/3 queue links before SMQ flush is on user 2245 */ 2246 if (lvl == NIX_TXSCH_LVL_SMQ && 2247 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf)) { 2248 rc = NIX_AF_SMQ_FLUSH_FAILED; 2249 goto err; 2250 } 2251 2252 /* Free the resource */ 2253 rvu_free_rsrc(&txsch->schq, schq); 2254 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 2255 mutex_unlock(&rvu->rsrc_lock); 2256 return 0; 2257 err: 2258 mutex_unlock(&rvu->rsrc_lock); 2259 return rc; 2260 } 2261 2262 int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu, 2263 struct nix_txsch_free_req *req, 2264 struct msg_rsp *rsp) 2265 { 2266 if (req->flags & TXSCHQ_FREE_ALL) 2267 return nix_txschq_free(rvu, req->hdr.pcifunc); 2268 else 2269 return nix_txschq_free_one(rvu, req); 2270 } 2271 2272 static bool is_txschq_hierarchy_valid(struct rvu *rvu, u16 pcifunc, int blkaddr, 2273 int lvl, u64 reg, u64 regval) 2274 { 2275 u64 regbase = reg & 0xFFFF; 2276 u16 schq, parent; 2277 2278 if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, lvl, reg)) 2279 return false; 2280 2281 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2282 /* Check if this schq belongs to this PF/VF or not */ 2283 if (!is_valid_txschq(rvu, blkaddr, lvl, pcifunc, schq)) 2284 return false; 2285 2286 parent = (regval >> 16) & 0x1FF; 2287 /* Validate MDQ's TL4 parent */ 2288 if (regbase == NIX_AF_MDQX_PARENT(0) && 2289 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL4, pcifunc, parent)) 2290 return false; 2291 2292 /* Validate TL4's TL3 parent */ 2293 if (regbase == NIX_AF_TL4X_PARENT(0) && 2294 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL3, pcifunc, parent)) 2295 return false; 2296 2297 /* Validate TL3's TL2 parent */ 2298 if (regbase == NIX_AF_TL3X_PARENT(0) && 2299 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL2, pcifunc, parent)) 2300 return false; 2301 2302 /* Validate TL2's TL1 parent */ 2303 if (regbase == NIX_AF_TL2X_PARENT(0) && 2304 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL1, pcifunc, parent)) 2305 return false; 2306 2307 return true; 2308 } 2309 2310 static bool is_txschq_shaping_valid(struct rvu_hwinfo *hw, int lvl, u64 reg) 2311 { 2312 u64 regbase; 2313 2314 if (hw->cap.nix_shaping) 2315 return true; 2316 2317 /* If shaping and coloring is not supported, then 2318 * *_CIR and *_PIR registers should not be configured. 2319 */ 2320 regbase = reg & 0xFFFF; 2321 2322 switch (lvl) { 2323 case NIX_TXSCH_LVL_TL1: 2324 if (regbase == NIX_AF_TL1X_CIR(0)) 2325 return false; 2326 break; 2327 case NIX_TXSCH_LVL_TL2: 2328 if (regbase == NIX_AF_TL2X_CIR(0) || 2329 regbase == NIX_AF_TL2X_PIR(0)) 2330 return false; 2331 break; 2332 case NIX_TXSCH_LVL_TL3: 2333 if (regbase == NIX_AF_TL3X_CIR(0) || 2334 regbase == NIX_AF_TL3X_PIR(0)) 2335 return false; 2336 break; 2337 case NIX_TXSCH_LVL_TL4: 2338 if (regbase == NIX_AF_TL4X_CIR(0) || 2339 regbase == NIX_AF_TL4X_PIR(0)) 2340 return false; 2341 break; 2342 case NIX_TXSCH_LVL_MDQ: 2343 if (regbase == NIX_AF_MDQX_CIR(0) || 2344 regbase == NIX_AF_MDQX_PIR(0)) 2345 return false; 2346 break; 2347 } 2348 return true; 2349 } 2350 2351 static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw, 2352 u16 pcifunc, int blkaddr) 2353 { 2354 u32 *pfvf_map; 2355 int schq; 2356 2357 schq = nix_get_tx_link(rvu, pcifunc); 2358 pfvf_map = nix_hw->txsch[NIX_TXSCH_LVL_TL1].pfvf_map; 2359 /* Skip if PF has already done the config */ 2360 if (TXSCH_MAP_FLAGS(pfvf_map[schq]) & NIX_TXSCHQ_CFG_DONE) 2361 return; 2362 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_TOPOLOGY(schq), 2363 (TXSCH_TL1_DFLT_RR_PRIO << 1)); 2364 2365 /* On OcteonTx2 the config was in bytes and newer silcons 2366 * it's changed to weight. 2367 */ 2368 if (!rvu->hw->cap.nix_common_dwrr_mtu) 2369 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq), 2370 TXSCH_TL1_DFLT_RR_QTM); 2371 else 2372 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq), 2373 CN10K_MAX_DWRR_WEIGHT); 2374 2375 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_CIR(schq), 0x00); 2376 pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], NIX_TXSCHQ_CFG_DONE); 2377 } 2378 2379 /* Register offset - [15:0] 2380 * Scheduler Queue number - [25:16] 2381 */ 2382 #define NIX_TX_SCHQ_MASK GENMASK_ULL(25, 0) 2383 2384 static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw, 2385 int blkaddr, struct nix_txschq_config *req, 2386 struct nix_txschq_config *rsp) 2387 { 2388 u16 pcifunc = req->hdr.pcifunc; 2389 int idx, schq; 2390 u64 reg; 2391 2392 for (idx = 0; idx < req->num_regs; idx++) { 2393 reg = req->reg[idx]; 2394 reg &= NIX_TX_SCHQ_MASK; 2395 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2396 if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, req->lvl, reg) || 2397 !is_valid_txschq(rvu, blkaddr, req->lvl, pcifunc, schq)) 2398 return NIX_AF_INVAL_TXSCHQ_CFG; 2399 rsp->regval[idx] = rvu_read64(rvu, blkaddr, reg); 2400 } 2401 rsp->lvl = req->lvl; 2402 rsp->num_regs = req->num_regs; 2403 return 0; 2404 } 2405 2406 static void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, 2407 u16 pcifunc, struct nix_txsch *txsch) 2408 { 2409 struct rvu_hwinfo *hw = rvu->hw; 2410 int lbk_link_start, lbk_links; 2411 u8 pf = rvu_get_pf(pcifunc); 2412 int schq; 2413 2414 if (!is_pf_cgxmapped(rvu, pf)) 2415 return; 2416 2417 lbk_link_start = hw->cgx_links; 2418 2419 for (schq = 0; schq < txsch->schq.max; schq++) { 2420 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2421 continue; 2422 /* Enable all LBK links with channel 63 by default so that 2423 * packets can be sent to LBK with a NPC TX MCAM rule 2424 */ 2425 lbk_links = hw->lbk_links; 2426 while (lbk_links--) 2427 rvu_write64(rvu, blkaddr, 2428 NIX_AF_TL3_TL2X_LINKX_CFG(schq, 2429 lbk_link_start + 2430 lbk_links), 2431 BIT_ULL(12) | RVU_SWITCH_LBK_CHAN); 2432 } 2433 } 2434 2435 int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu, 2436 struct nix_txschq_config *req, 2437 struct nix_txschq_config *rsp) 2438 { 2439 u64 reg, val, regval, schq_regbase, val_mask; 2440 struct rvu_hwinfo *hw = rvu->hw; 2441 u16 pcifunc = req->hdr.pcifunc; 2442 struct nix_txsch *txsch; 2443 struct nix_hw *nix_hw; 2444 int blkaddr, idx, err; 2445 int nixlf, schq; 2446 u32 *pfvf_map; 2447 2448 if (req->lvl >= NIX_TXSCH_LVL_CNT || 2449 req->num_regs > MAX_REGS_PER_MBOX_MSG) 2450 return NIX_AF_INVAL_TXSCHQ_CFG; 2451 2452 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 2453 if (err) 2454 return err; 2455 2456 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2457 if (!nix_hw) 2458 return NIX_AF_ERR_INVALID_NIXBLK; 2459 2460 if (req->read) 2461 return nix_txschq_cfg_read(rvu, nix_hw, blkaddr, req, rsp); 2462 2463 txsch = &nix_hw->txsch[req->lvl]; 2464 pfvf_map = txsch->pfvf_map; 2465 2466 if (req->lvl >= hw->cap.nix_tx_aggr_lvl && 2467 pcifunc & RVU_PFVF_FUNC_MASK) { 2468 mutex_lock(&rvu->rsrc_lock); 2469 if (req->lvl == NIX_TXSCH_LVL_TL1) 2470 nix_tl1_default_cfg(rvu, nix_hw, pcifunc, blkaddr); 2471 mutex_unlock(&rvu->rsrc_lock); 2472 return 0; 2473 } 2474 2475 for (idx = 0; idx < req->num_regs; idx++) { 2476 reg = req->reg[idx]; 2477 reg &= NIX_TX_SCHQ_MASK; 2478 regval = req->regval[idx]; 2479 schq_regbase = reg & 0xFFFF; 2480 val_mask = req->regval_mask[idx]; 2481 2482 if (!is_txschq_hierarchy_valid(rvu, pcifunc, blkaddr, 2483 txsch->lvl, reg, regval)) 2484 return NIX_AF_INVAL_TXSCHQ_CFG; 2485 2486 /* Check if shaping and coloring is supported */ 2487 if (!is_txschq_shaping_valid(hw, req->lvl, reg)) 2488 continue; 2489 2490 val = rvu_read64(rvu, blkaddr, reg); 2491 regval = (val & val_mask) | (regval & ~val_mask); 2492 2493 /* Handle shaping state toggle specially */ 2494 if (hw->cap.nix_shaper_toggle_wait && 2495 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 2496 req->lvl, reg, regval)) 2497 continue; 2498 2499 /* Replace PF/VF visible NIXLF slot with HW NIXLF id */ 2500 if (schq_regbase == NIX_AF_SMQX_CFG(0)) { 2501 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 2502 pcifunc, 0); 2503 regval &= ~(0x7FULL << 24); 2504 regval |= ((u64)nixlf << 24); 2505 } 2506 2507 /* Clear 'BP_ENA' config, if it's not allowed */ 2508 if (!hw->cap.nix_tx_link_bp) { 2509 if (schq_regbase == NIX_AF_TL4X_SDP_LINK_CFG(0) || 2510 (schq_regbase & 0xFF00) == 2511 NIX_AF_TL3_TL2X_LINKX_CFG(0, 0)) 2512 regval &= ~BIT_ULL(13); 2513 } 2514 2515 /* Mark config as done for TL1 by PF */ 2516 if (schq_regbase >= NIX_AF_TL1X_SCHEDULE(0) && 2517 schq_regbase <= NIX_AF_TL1X_GREEN_BYTES(0)) { 2518 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2519 mutex_lock(&rvu->rsrc_lock); 2520 pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], 2521 NIX_TXSCHQ_CFG_DONE); 2522 mutex_unlock(&rvu->rsrc_lock); 2523 } 2524 2525 /* SMQ flush is special hence split register writes such 2526 * that flush first and write rest of the bits later. 2527 */ 2528 if (schq_regbase == NIX_AF_SMQX_CFG(0) && 2529 (regval & BIT_ULL(49))) { 2530 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2531 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf); 2532 regval &= ~BIT_ULL(49); 2533 } 2534 rvu_write64(rvu, blkaddr, reg, regval); 2535 } 2536 2537 rvu_nix_tx_tl2_cfg(rvu, blkaddr, pcifunc, 2538 &nix_hw->txsch[NIX_TXSCH_LVL_TL2]); 2539 return 0; 2540 } 2541 2542 static int nix_rx_vtag_cfg(struct rvu *rvu, int nixlf, int blkaddr, 2543 struct nix_vtag_config *req) 2544 { 2545 u64 regval = req->vtag_size; 2546 2547 if (req->rx.vtag_type > NIX_AF_LFX_RX_VTAG_TYPE7 || 2548 req->vtag_size > VTAGSIZE_T8) 2549 return -EINVAL; 2550 2551 /* RX VTAG Type 7 reserved for vf vlan */ 2552 if (req->rx.vtag_type == NIX_AF_LFX_RX_VTAG_TYPE7) 2553 return NIX_AF_ERR_RX_VTAG_INUSE; 2554 2555 if (req->rx.capture_vtag) 2556 regval |= BIT_ULL(5); 2557 if (req->rx.strip_vtag) 2558 regval |= BIT_ULL(4); 2559 2560 rvu_write64(rvu, blkaddr, 2561 NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, req->rx.vtag_type), regval); 2562 return 0; 2563 } 2564 2565 static int nix_tx_vtag_free(struct rvu *rvu, int blkaddr, 2566 u16 pcifunc, int index) 2567 { 2568 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2569 struct nix_txvlan *vlan; 2570 2571 if (!nix_hw) 2572 return NIX_AF_ERR_INVALID_NIXBLK; 2573 2574 vlan = &nix_hw->txvlan; 2575 if (vlan->entry2pfvf_map[index] != pcifunc) 2576 return NIX_AF_ERR_PARAM; 2577 2578 rvu_write64(rvu, blkaddr, 2579 NIX_AF_TX_VTAG_DEFX_DATA(index), 0x0ull); 2580 rvu_write64(rvu, blkaddr, 2581 NIX_AF_TX_VTAG_DEFX_CTL(index), 0x0ull); 2582 2583 vlan->entry2pfvf_map[index] = 0; 2584 rvu_free_rsrc(&vlan->rsrc, index); 2585 2586 return 0; 2587 } 2588 2589 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc) 2590 { 2591 struct nix_txvlan *vlan; 2592 struct nix_hw *nix_hw; 2593 int index, blkaddr; 2594 2595 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2596 if (blkaddr < 0) 2597 return; 2598 2599 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2600 if (!nix_hw) 2601 return; 2602 2603 vlan = &nix_hw->txvlan; 2604 2605 mutex_lock(&vlan->rsrc_lock); 2606 /* Scan all the entries and free the ones mapped to 'pcifunc' */ 2607 for (index = 0; index < vlan->rsrc.max; index++) { 2608 if (vlan->entry2pfvf_map[index] == pcifunc) 2609 nix_tx_vtag_free(rvu, blkaddr, pcifunc, index); 2610 } 2611 mutex_unlock(&vlan->rsrc_lock); 2612 } 2613 2614 static int nix_tx_vtag_alloc(struct rvu *rvu, int blkaddr, 2615 u64 vtag, u8 size) 2616 { 2617 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2618 struct nix_txvlan *vlan; 2619 u64 regval; 2620 int index; 2621 2622 if (!nix_hw) 2623 return NIX_AF_ERR_INVALID_NIXBLK; 2624 2625 vlan = &nix_hw->txvlan; 2626 2627 mutex_lock(&vlan->rsrc_lock); 2628 2629 index = rvu_alloc_rsrc(&vlan->rsrc); 2630 if (index < 0) { 2631 mutex_unlock(&vlan->rsrc_lock); 2632 return index; 2633 } 2634 2635 mutex_unlock(&vlan->rsrc_lock); 2636 2637 regval = size ? vtag : vtag << 32; 2638 2639 rvu_write64(rvu, blkaddr, 2640 NIX_AF_TX_VTAG_DEFX_DATA(index), regval); 2641 rvu_write64(rvu, blkaddr, 2642 NIX_AF_TX_VTAG_DEFX_CTL(index), size); 2643 2644 return index; 2645 } 2646 2647 static int nix_tx_vtag_decfg(struct rvu *rvu, int blkaddr, 2648 struct nix_vtag_config *req) 2649 { 2650 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2651 u16 pcifunc = req->hdr.pcifunc; 2652 int idx0 = req->tx.vtag0_idx; 2653 int idx1 = req->tx.vtag1_idx; 2654 struct nix_txvlan *vlan; 2655 int err = 0; 2656 2657 if (!nix_hw) 2658 return NIX_AF_ERR_INVALID_NIXBLK; 2659 2660 vlan = &nix_hw->txvlan; 2661 if (req->tx.free_vtag0 && req->tx.free_vtag1) 2662 if (vlan->entry2pfvf_map[idx0] != pcifunc || 2663 vlan->entry2pfvf_map[idx1] != pcifunc) 2664 return NIX_AF_ERR_PARAM; 2665 2666 mutex_lock(&vlan->rsrc_lock); 2667 2668 if (req->tx.free_vtag0) { 2669 err = nix_tx_vtag_free(rvu, blkaddr, pcifunc, idx0); 2670 if (err) 2671 goto exit; 2672 } 2673 2674 if (req->tx.free_vtag1) 2675 err = nix_tx_vtag_free(rvu, blkaddr, pcifunc, idx1); 2676 2677 exit: 2678 mutex_unlock(&vlan->rsrc_lock); 2679 return err; 2680 } 2681 2682 static int nix_tx_vtag_cfg(struct rvu *rvu, int blkaddr, 2683 struct nix_vtag_config *req, 2684 struct nix_vtag_config_rsp *rsp) 2685 { 2686 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2687 struct nix_txvlan *vlan; 2688 u16 pcifunc = req->hdr.pcifunc; 2689 2690 if (!nix_hw) 2691 return NIX_AF_ERR_INVALID_NIXBLK; 2692 2693 vlan = &nix_hw->txvlan; 2694 if (req->tx.cfg_vtag0) { 2695 rsp->vtag0_idx = 2696 nix_tx_vtag_alloc(rvu, blkaddr, 2697 req->tx.vtag0, req->vtag_size); 2698 2699 if (rsp->vtag0_idx < 0) 2700 return NIX_AF_ERR_TX_VTAG_NOSPC; 2701 2702 vlan->entry2pfvf_map[rsp->vtag0_idx] = pcifunc; 2703 } 2704 2705 if (req->tx.cfg_vtag1) { 2706 rsp->vtag1_idx = 2707 nix_tx_vtag_alloc(rvu, blkaddr, 2708 req->tx.vtag1, req->vtag_size); 2709 2710 if (rsp->vtag1_idx < 0) 2711 goto err_free; 2712 2713 vlan->entry2pfvf_map[rsp->vtag1_idx] = pcifunc; 2714 } 2715 2716 return 0; 2717 2718 err_free: 2719 if (req->tx.cfg_vtag0) 2720 nix_tx_vtag_free(rvu, blkaddr, pcifunc, rsp->vtag0_idx); 2721 2722 return NIX_AF_ERR_TX_VTAG_NOSPC; 2723 } 2724 2725 int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu, 2726 struct nix_vtag_config *req, 2727 struct nix_vtag_config_rsp *rsp) 2728 { 2729 u16 pcifunc = req->hdr.pcifunc; 2730 int blkaddr, nixlf, err; 2731 2732 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 2733 if (err) 2734 return err; 2735 2736 if (req->cfg_type) { 2737 /* rx vtag configuration */ 2738 err = nix_rx_vtag_cfg(rvu, nixlf, blkaddr, req); 2739 if (err) 2740 return NIX_AF_ERR_PARAM; 2741 } else { 2742 /* tx vtag configuration */ 2743 if ((req->tx.cfg_vtag0 || req->tx.cfg_vtag1) && 2744 (req->tx.free_vtag0 || req->tx.free_vtag1)) 2745 return NIX_AF_ERR_PARAM; 2746 2747 if (req->tx.cfg_vtag0 || req->tx.cfg_vtag1) 2748 return nix_tx_vtag_cfg(rvu, blkaddr, req, rsp); 2749 2750 if (req->tx.free_vtag0 || req->tx.free_vtag1) 2751 return nix_tx_vtag_decfg(rvu, blkaddr, req); 2752 } 2753 2754 return 0; 2755 } 2756 2757 static int nix_blk_setup_mce(struct rvu *rvu, struct nix_hw *nix_hw, 2758 int mce, u8 op, u16 pcifunc, int next, bool eol) 2759 { 2760 struct nix_aq_enq_req aq_req; 2761 int err; 2762 2763 aq_req.hdr.pcifunc = 0; 2764 aq_req.ctype = NIX_AQ_CTYPE_MCE; 2765 aq_req.op = op; 2766 aq_req.qidx = mce; 2767 2768 /* Use RSS with RSS index 0 */ 2769 aq_req.mce.op = 1; 2770 aq_req.mce.index = 0; 2771 aq_req.mce.eol = eol; 2772 aq_req.mce.pf_func = pcifunc; 2773 aq_req.mce.next = next; 2774 2775 /* All fields valid */ 2776 *(u64 *)(&aq_req.mce_mask) = ~0ULL; 2777 2778 err = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, &aq_req, NULL); 2779 if (err) { 2780 dev_err(rvu->dev, "Failed to setup Bcast MCE for PF%d:VF%d\n", 2781 rvu_get_pf(pcifunc), pcifunc & RVU_PFVF_FUNC_MASK); 2782 return err; 2783 } 2784 return 0; 2785 } 2786 2787 static int nix_update_mce_list_entry(struct nix_mce_list *mce_list, 2788 u16 pcifunc, bool add) 2789 { 2790 struct mce *mce, *tail = NULL; 2791 bool delete = false; 2792 2793 /* Scan through the current list */ 2794 hlist_for_each_entry(mce, &mce_list->head, node) { 2795 /* If already exists, then delete */ 2796 if (mce->pcifunc == pcifunc && !add) { 2797 delete = true; 2798 break; 2799 } else if (mce->pcifunc == pcifunc && add) { 2800 /* entry already exists */ 2801 return 0; 2802 } 2803 tail = mce; 2804 } 2805 2806 if (delete) { 2807 hlist_del(&mce->node); 2808 kfree(mce); 2809 mce_list->count--; 2810 return 0; 2811 } 2812 2813 if (!add) 2814 return 0; 2815 2816 /* Add a new one to the list, at the tail */ 2817 mce = kzalloc(sizeof(*mce), GFP_KERNEL); 2818 if (!mce) 2819 return -ENOMEM; 2820 mce->pcifunc = pcifunc; 2821 if (!tail) 2822 hlist_add_head(&mce->node, &mce_list->head); 2823 else 2824 hlist_add_behind(&mce->node, &tail->node); 2825 mce_list->count++; 2826 return 0; 2827 } 2828 2829 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 2830 struct nix_mce_list *mce_list, 2831 int mce_idx, int mcam_index, bool add) 2832 { 2833 int err = 0, idx, next_idx, last_idx, blkaddr, npc_blkaddr; 2834 struct npc_mcam *mcam = &rvu->hw->mcam; 2835 struct nix_mcast *mcast; 2836 struct nix_hw *nix_hw; 2837 struct mce *mce; 2838 2839 if (!mce_list) 2840 return -EINVAL; 2841 2842 /* Get this PF/VF func's MCE index */ 2843 idx = mce_idx + (pcifunc & RVU_PFVF_FUNC_MASK); 2844 2845 if (idx > (mce_idx + mce_list->max)) { 2846 dev_err(rvu->dev, 2847 "%s: Idx %d > max MCE idx %d, for PF%d bcast list\n", 2848 __func__, idx, mce_list->max, 2849 pcifunc >> RVU_PFVF_PF_SHIFT); 2850 return -EINVAL; 2851 } 2852 2853 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 2854 if (err) 2855 return err; 2856 2857 mcast = &nix_hw->mcast; 2858 mutex_lock(&mcast->mce_lock); 2859 2860 err = nix_update_mce_list_entry(mce_list, pcifunc, add); 2861 if (err) 2862 goto end; 2863 2864 /* Disable MCAM entry in NPC */ 2865 if (!mce_list->count) { 2866 npc_blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2867 npc_enable_mcam_entry(rvu, mcam, npc_blkaddr, mcam_index, false); 2868 goto end; 2869 } 2870 2871 /* Dump the updated list to HW */ 2872 idx = mce_idx; 2873 last_idx = idx + mce_list->count - 1; 2874 hlist_for_each_entry(mce, &mce_list->head, node) { 2875 if (idx > last_idx) 2876 break; 2877 2878 next_idx = idx + 1; 2879 /* EOL should be set in last MCE */ 2880 err = nix_blk_setup_mce(rvu, nix_hw, idx, NIX_AQ_INSTOP_WRITE, 2881 mce->pcifunc, next_idx, 2882 (next_idx > last_idx) ? true : false); 2883 if (err) 2884 goto end; 2885 idx++; 2886 } 2887 2888 end: 2889 mutex_unlock(&mcast->mce_lock); 2890 return err; 2891 } 2892 2893 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 2894 struct nix_mce_list **mce_list, int *mce_idx) 2895 { 2896 struct rvu_hwinfo *hw = rvu->hw; 2897 struct rvu_pfvf *pfvf; 2898 2899 if (!hw->cap.nix_rx_multicast || 2900 !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc & ~RVU_PFVF_FUNC_MASK))) { 2901 *mce_list = NULL; 2902 *mce_idx = 0; 2903 return; 2904 } 2905 2906 /* Get this PF/VF func's MCE index */ 2907 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 2908 2909 if (type == NIXLF_BCAST_ENTRY) { 2910 *mce_list = &pfvf->bcast_mce_list; 2911 *mce_idx = pfvf->bcast_mce_idx; 2912 } else if (type == NIXLF_ALLMULTI_ENTRY) { 2913 *mce_list = &pfvf->mcast_mce_list; 2914 *mce_idx = pfvf->mcast_mce_idx; 2915 } else if (type == NIXLF_PROMISC_ENTRY) { 2916 *mce_list = &pfvf->promisc_mce_list; 2917 *mce_idx = pfvf->promisc_mce_idx; 2918 } else { 2919 *mce_list = NULL; 2920 *mce_idx = 0; 2921 } 2922 } 2923 2924 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc, 2925 int type, bool add) 2926 { 2927 int err = 0, nixlf, blkaddr, mcam_index, mce_idx; 2928 struct npc_mcam *mcam = &rvu->hw->mcam; 2929 struct rvu_hwinfo *hw = rvu->hw; 2930 struct nix_mce_list *mce_list; 2931 int pf; 2932 2933 /* skip multicast pkt replication for AF's VFs & SDP links */ 2934 if (is_afvf(pcifunc) || is_sdp_pfvf(pcifunc)) 2935 return 0; 2936 2937 if (!hw->cap.nix_rx_multicast) 2938 return 0; 2939 2940 pf = rvu_get_pf(pcifunc); 2941 if (!is_pf_cgxmapped(rvu, pf)) 2942 return 0; 2943 2944 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2945 if (blkaddr < 0) 2946 return -EINVAL; 2947 2948 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2949 if (nixlf < 0) 2950 return -EINVAL; 2951 2952 nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx); 2953 2954 mcam_index = npc_get_nixlf_mcam_index(mcam, 2955 pcifunc & ~RVU_PFVF_FUNC_MASK, 2956 nixlf, type); 2957 err = nix_update_mce_list(rvu, pcifunc, mce_list, 2958 mce_idx, mcam_index, add); 2959 return err; 2960 } 2961 2962 static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw) 2963 { 2964 struct nix_mcast *mcast = &nix_hw->mcast; 2965 int err, pf, numvfs, idx; 2966 struct rvu_pfvf *pfvf; 2967 u16 pcifunc; 2968 u64 cfg; 2969 2970 /* Skip PF0 (i.e AF) */ 2971 for (pf = 1; pf < (rvu->cgx_mapped_pfs + 1); pf++) { 2972 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2973 /* If PF is not enabled, nothing to do */ 2974 if (!((cfg >> 20) & 0x01)) 2975 continue; 2976 /* Get numVFs attached to this PF */ 2977 numvfs = (cfg >> 12) & 0xFF; 2978 2979 pfvf = &rvu->pf[pf]; 2980 2981 /* This NIX0/1 block mapped to PF ? */ 2982 if (pfvf->nix_blkaddr != nix_hw->blkaddr) 2983 continue; 2984 2985 /* save start idx of broadcast mce list */ 2986 pfvf->bcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2987 nix_mce_list_init(&pfvf->bcast_mce_list, numvfs + 1); 2988 2989 /* save start idx of multicast mce list */ 2990 pfvf->mcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2991 nix_mce_list_init(&pfvf->mcast_mce_list, numvfs + 1); 2992 2993 /* save the start idx of promisc mce list */ 2994 pfvf->promisc_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2995 nix_mce_list_init(&pfvf->promisc_mce_list, numvfs + 1); 2996 2997 for (idx = 0; idx < (numvfs + 1); idx++) { 2998 /* idx-0 is for PF, followed by VFs */ 2999 pcifunc = (pf << RVU_PFVF_PF_SHIFT); 3000 pcifunc |= idx; 3001 /* Add dummy entries now, so that we don't have to check 3002 * for whether AQ_OP should be INIT/WRITE later on. 3003 * Will be updated when a NIXLF is attached/detached to 3004 * these PF/VFs. 3005 */ 3006 err = nix_blk_setup_mce(rvu, nix_hw, 3007 pfvf->bcast_mce_idx + idx, 3008 NIX_AQ_INSTOP_INIT, 3009 pcifunc, 0, true); 3010 if (err) 3011 return err; 3012 3013 /* add dummy entries to multicast mce list */ 3014 err = nix_blk_setup_mce(rvu, nix_hw, 3015 pfvf->mcast_mce_idx + idx, 3016 NIX_AQ_INSTOP_INIT, 3017 pcifunc, 0, true); 3018 if (err) 3019 return err; 3020 3021 /* add dummy entries to promisc mce list */ 3022 err = nix_blk_setup_mce(rvu, nix_hw, 3023 pfvf->promisc_mce_idx + idx, 3024 NIX_AQ_INSTOP_INIT, 3025 pcifunc, 0, true); 3026 if (err) 3027 return err; 3028 } 3029 } 3030 return 0; 3031 } 3032 3033 static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 3034 { 3035 struct nix_mcast *mcast = &nix_hw->mcast; 3036 struct rvu_hwinfo *hw = rvu->hw; 3037 int err, size; 3038 3039 size = (rvu_read64(rvu, blkaddr, NIX_AF_CONST3) >> 16) & 0x0F; 3040 size = (1ULL << size); 3041 3042 /* Alloc memory for multicast/mirror replication entries */ 3043 err = qmem_alloc(rvu->dev, &mcast->mce_ctx, 3044 (256UL << MC_TBL_SIZE), size); 3045 if (err) 3046 return -ENOMEM; 3047 3048 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BASE, 3049 (u64)mcast->mce_ctx->iova); 3050 3051 /* Set max list length equal to max no of VFs per PF + PF itself */ 3052 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG, 3053 BIT_ULL(36) | (hw->max_vfs_per_pf << 4) | MC_TBL_SIZE); 3054 3055 /* Alloc memory for multicast replication buffers */ 3056 size = rvu_read64(rvu, blkaddr, NIX_AF_MC_MIRROR_CONST) & 0xFFFF; 3057 err = qmem_alloc(rvu->dev, &mcast->mcast_buf, 3058 (8UL << MC_BUF_CNT), size); 3059 if (err) 3060 return -ENOMEM; 3061 3062 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_BASE, 3063 (u64)mcast->mcast_buf->iova); 3064 3065 /* Alloc pkind for NIX internal RX multicast/mirror replay */ 3066 mcast->replay_pkind = rvu_alloc_rsrc(&hw->pkind.rsrc); 3067 3068 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_CFG, 3069 BIT_ULL(63) | (mcast->replay_pkind << 24) | 3070 BIT_ULL(20) | MC_BUF_CNT); 3071 3072 mutex_init(&mcast->mce_lock); 3073 3074 return nix_setup_mce_tables(rvu, nix_hw); 3075 } 3076 3077 static int nix_setup_txvlan(struct rvu *rvu, struct nix_hw *nix_hw) 3078 { 3079 struct nix_txvlan *vlan = &nix_hw->txvlan; 3080 int err; 3081 3082 /* Allocate resource bimap for tx vtag def registers*/ 3083 vlan->rsrc.max = NIX_TX_VTAG_DEF_MAX; 3084 err = rvu_alloc_bitmap(&vlan->rsrc); 3085 if (err) 3086 return -ENOMEM; 3087 3088 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */ 3089 vlan->entry2pfvf_map = devm_kcalloc(rvu->dev, vlan->rsrc.max, 3090 sizeof(u16), GFP_KERNEL); 3091 if (!vlan->entry2pfvf_map) 3092 goto free_mem; 3093 3094 mutex_init(&vlan->rsrc_lock); 3095 return 0; 3096 3097 free_mem: 3098 kfree(vlan->rsrc.bmap); 3099 return -ENOMEM; 3100 } 3101 3102 static int nix_setup_txschq(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 3103 { 3104 struct nix_txsch *txsch; 3105 int err, lvl, schq; 3106 u64 cfg, reg; 3107 3108 /* Get scheduler queue count of each type and alloc 3109 * bitmap for each for alloc/free/attach operations. 3110 */ 3111 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 3112 txsch = &nix_hw->txsch[lvl]; 3113 txsch->lvl = lvl; 3114 switch (lvl) { 3115 case NIX_TXSCH_LVL_SMQ: 3116 reg = NIX_AF_MDQ_CONST; 3117 break; 3118 case NIX_TXSCH_LVL_TL4: 3119 reg = NIX_AF_TL4_CONST; 3120 break; 3121 case NIX_TXSCH_LVL_TL3: 3122 reg = NIX_AF_TL3_CONST; 3123 break; 3124 case NIX_TXSCH_LVL_TL2: 3125 reg = NIX_AF_TL2_CONST; 3126 break; 3127 case NIX_TXSCH_LVL_TL1: 3128 reg = NIX_AF_TL1_CONST; 3129 break; 3130 } 3131 cfg = rvu_read64(rvu, blkaddr, reg); 3132 txsch->schq.max = cfg & 0xFFFF; 3133 err = rvu_alloc_bitmap(&txsch->schq); 3134 if (err) 3135 return err; 3136 3137 /* Allocate memory for scheduler queues to 3138 * PF/VF pcifunc mapping info. 3139 */ 3140 txsch->pfvf_map = devm_kcalloc(rvu->dev, txsch->schq.max, 3141 sizeof(u32), GFP_KERNEL); 3142 if (!txsch->pfvf_map) 3143 return -ENOMEM; 3144 for (schq = 0; schq < txsch->schq.max; schq++) 3145 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 3146 } 3147 3148 /* Setup a default value of 8192 as DWRR MTU */ 3149 if (rvu->hw->cap.nix_common_dwrr_mtu) { 3150 rvu_write64(rvu, blkaddr, NIX_AF_DWRR_RPM_MTU, 3151 convert_bytes_to_dwrr_mtu(8192)); 3152 rvu_write64(rvu, blkaddr, NIX_AF_DWRR_SDP_MTU, 3153 convert_bytes_to_dwrr_mtu(8192)); 3154 } 3155 3156 return 0; 3157 } 3158 3159 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 3160 int blkaddr, u32 cfg) 3161 { 3162 int fmt_idx; 3163 3164 for (fmt_idx = 0; fmt_idx < nix_hw->mark_format.in_use; fmt_idx++) { 3165 if (nix_hw->mark_format.cfg[fmt_idx] == cfg) 3166 return fmt_idx; 3167 } 3168 if (fmt_idx >= nix_hw->mark_format.total) 3169 return -ERANGE; 3170 3171 rvu_write64(rvu, blkaddr, NIX_AF_MARK_FORMATX_CTL(fmt_idx), cfg); 3172 nix_hw->mark_format.cfg[fmt_idx] = cfg; 3173 nix_hw->mark_format.in_use++; 3174 return fmt_idx; 3175 } 3176 3177 static int nix_af_mark_format_setup(struct rvu *rvu, struct nix_hw *nix_hw, 3178 int blkaddr) 3179 { 3180 u64 cfgs[] = { 3181 [NIX_MARK_CFG_IP_DSCP_RED] = 0x10003, 3182 [NIX_MARK_CFG_IP_DSCP_YELLOW] = 0x11200, 3183 [NIX_MARK_CFG_IP_DSCP_YELLOW_RED] = 0x11203, 3184 [NIX_MARK_CFG_IP_ECN_RED] = 0x6000c, 3185 [NIX_MARK_CFG_IP_ECN_YELLOW] = 0x60c00, 3186 [NIX_MARK_CFG_IP_ECN_YELLOW_RED] = 0x60c0c, 3187 [NIX_MARK_CFG_VLAN_DEI_RED] = 0x30008, 3188 [NIX_MARK_CFG_VLAN_DEI_YELLOW] = 0x30800, 3189 [NIX_MARK_CFG_VLAN_DEI_YELLOW_RED] = 0x30808, 3190 }; 3191 int i, rc; 3192 u64 total; 3193 3194 total = (rvu_read64(rvu, blkaddr, NIX_AF_PSE_CONST) & 0xFF00) >> 8; 3195 nix_hw->mark_format.total = (u8)total; 3196 nix_hw->mark_format.cfg = devm_kcalloc(rvu->dev, total, sizeof(u32), 3197 GFP_KERNEL); 3198 if (!nix_hw->mark_format.cfg) 3199 return -ENOMEM; 3200 for (i = 0; i < NIX_MARK_CFG_MAX; i++) { 3201 rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfgs[i]); 3202 if (rc < 0) 3203 dev_err(rvu->dev, "Err %d in setup mark format %d\n", 3204 i, rc); 3205 } 3206 3207 return 0; 3208 } 3209 3210 static void rvu_get_lbk_link_max_frs(struct rvu *rvu, u16 *max_mtu) 3211 { 3212 /* CN10K supports LBK FIFO size 72 KB */ 3213 if (rvu->hw->lbk_bufsize == 0x12000) 3214 *max_mtu = CN10K_LBK_LINK_MAX_FRS; 3215 else 3216 *max_mtu = NIC_HW_MAX_FRS; 3217 } 3218 3219 static void rvu_get_lmac_link_max_frs(struct rvu *rvu, u16 *max_mtu) 3220 { 3221 int fifo_size = rvu_cgx_get_fifolen(rvu); 3222 3223 /* RPM supports FIFO len 128 KB and RPM2 supports double the 3224 * FIFO len to accommodate 8 LMACS 3225 */ 3226 if (fifo_size == 0x20000 || fifo_size == 0x40000) 3227 *max_mtu = CN10K_LMAC_LINK_MAX_FRS; 3228 else 3229 *max_mtu = NIC_HW_MAX_FRS; 3230 } 3231 3232 int rvu_mbox_handler_nix_get_hw_info(struct rvu *rvu, struct msg_req *req, 3233 struct nix_hw_info *rsp) 3234 { 3235 u16 pcifunc = req->hdr.pcifunc; 3236 u64 dwrr_mtu; 3237 int blkaddr; 3238 3239 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 3240 if (blkaddr < 0) 3241 return NIX_AF_ERR_AF_LF_INVALID; 3242 3243 if (is_afvf(pcifunc)) 3244 rvu_get_lbk_link_max_frs(rvu, &rsp->max_mtu); 3245 else 3246 rvu_get_lmac_link_max_frs(rvu, &rsp->max_mtu); 3247 3248 rsp->min_mtu = NIC_HW_MIN_FRS; 3249 3250 if (!rvu->hw->cap.nix_common_dwrr_mtu) { 3251 /* Return '1' on OTx2 */ 3252 rsp->rpm_dwrr_mtu = 1; 3253 rsp->sdp_dwrr_mtu = 1; 3254 return 0; 3255 } 3256 3257 dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_RPM_MTU); 3258 rsp->rpm_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu); 3259 3260 dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_SDP_MTU); 3261 rsp->sdp_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu); 3262 3263 return 0; 3264 } 3265 3266 int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req, 3267 struct msg_rsp *rsp) 3268 { 3269 u16 pcifunc = req->hdr.pcifunc; 3270 int i, nixlf, blkaddr, err; 3271 u64 stats; 3272 3273 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3274 if (err) 3275 return err; 3276 3277 /* Get stats count supported by HW */ 3278 stats = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 3279 3280 /* Reset tx stats */ 3281 for (i = 0; i < ((stats >> 24) & 0xFF); i++) 3282 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_STATX(nixlf, i), 0); 3283 3284 /* Reset rx stats */ 3285 for (i = 0; i < ((stats >> 32) & 0xFF); i++) 3286 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, i), 0); 3287 3288 return 0; 3289 } 3290 3291 /* Returns the ALG index to be set into NPC_RX_ACTION */ 3292 static int get_flowkey_alg_idx(struct nix_hw *nix_hw, u32 flow_cfg) 3293 { 3294 int i; 3295 3296 /* Scan over exiting algo entries to find a match */ 3297 for (i = 0; i < nix_hw->flowkey.in_use; i++) 3298 if (nix_hw->flowkey.flowkey[i] == flow_cfg) 3299 return i; 3300 3301 return -ERANGE; 3302 } 3303 3304 static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) 3305 { 3306 int idx, nr_field, key_off, field_marker, keyoff_marker; 3307 int max_key_off, max_bit_pos, group_member; 3308 struct nix_rx_flowkey_alg *field; 3309 struct nix_rx_flowkey_alg tmp; 3310 u32 key_type, valid_key; 3311 int l4_key_offset = 0; 3312 3313 if (!alg) 3314 return -EINVAL; 3315 3316 #define FIELDS_PER_ALG 5 3317 #define MAX_KEY_OFF 40 3318 /* Clear all fields */ 3319 memset(alg, 0, sizeof(uint64_t) * FIELDS_PER_ALG); 3320 3321 /* Each of the 32 possible flow key algorithm definitions should 3322 * fall into above incremental config (except ALG0). Otherwise a 3323 * single NPC MCAM entry is not sufficient for supporting RSS. 3324 * 3325 * If a different definition or combination needed then NPC MCAM 3326 * has to be programmed to filter such pkts and it's action should 3327 * point to this definition to calculate flowtag or hash. 3328 * 3329 * The `for loop` goes over _all_ protocol field and the following 3330 * variables depicts the state machine forward progress logic. 3331 * 3332 * keyoff_marker - Enabled when hash byte length needs to be accounted 3333 * in field->key_offset update. 3334 * field_marker - Enabled when a new field needs to be selected. 3335 * group_member - Enabled when protocol is part of a group. 3336 */ 3337 3338 keyoff_marker = 0; max_key_off = 0; group_member = 0; 3339 nr_field = 0; key_off = 0; field_marker = 1; 3340 field = &tmp; max_bit_pos = fls(flow_cfg); 3341 for (idx = 0; 3342 idx < max_bit_pos && nr_field < FIELDS_PER_ALG && 3343 key_off < MAX_KEY_OFF; idx++) { 3344 key_type = BIT(idx); 3345 valid_key = flow_cfg & key_type; 3346 /* Found a field marker, reset the field values */ 3347 if (field_marker) 3348 memset(&tmp, 0, sizeof(tmp)); 3349 3350 field_marker = true; 3351 keyoff_marker = true; 3352 switch (key_type) { 3353 case NIX_FLOW_KEY_TYPE_PORT: 3354 field->sel_chan = true; 3355 /* This should be set to 1, when SEL_CHAN is set */ 3356 field->bytesm1 = 1; 3357 break; 3358 case NIX_FLOW_KEY_TYPE_IPV4_PROTO: 3359 field->lid = NPC_LID_LC; 3360 field->hdr_offset = 9; /* offset */ 3361 field->bytesm1 = 0; /* 1 byte */ 3362 field->ltype_match = NPC_LT_LC_IP; 3363 field->ltype_mask = 0xF; 3364 break; 3365 case NIX_FLOW_KEY_TYPE_IPV4: 3366 case NIX_FLOW_KEY_TYPE_INNR_IPV4: 3367 field->lid = NPC_LID_LC; 3368 field->ltype_match = NPC_LT_LC_IP; 3369 if (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV4) { 3370 field->lid = NPC_LID_LG; 3371 field->ltype_match = NPC_LT_LG_TU_IP; 3372 } 3373 field->hdr_offset = 12; /* SIP offset */ 3374 field->bytesm1 = 7; /* SIP + DIP, 8 bytes */ 3375 field->ltype_mask = 0xF; /* Match only IPv4 */ 3376 keyoff_marker = false; 3377 break; 3378 case NIX_FLOW_KEY_TYPE_IPV6: 3379 case NIX_FLOW_KEY_TYPE_INNR_IPV6: 3380 field->lid = NPC_LID_LC; 3381 field->ltype_match = NPC_LT_LC_IP6; 3382 if (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV6) { 3383 field->lid = NPC_LID_LG; 3384 field->ltype_match = NPC_LT_LG_TU_IP6; 3385 } 3386 field->hdr_offset = 8; /* SIP offset */ 3387 field->bytesm1 = 31; /* SIP + DIP, 32 bytes */ 3388 field->ltype_mask = 0xF; /* Match only IPv6 */ 3389 break; 3390 case NIX_FLOW_KEY_TYPE_TCP: 3391 case NIX_FLOW_KEY_TYPE_UDP: 3392 case NIX_FLOW_KEY_TYPE_SCTP: 3393 case NIX_FLOW_KEY_TYPE_INNR_TCP: 3394 case NIX_FLOW_KEY_TYPE_INNR_UDP: 3395 case NIX_FLOW_KEY_TYPE_INNR_SCTP: 3396 field->lid = NPC_LID_LD; 3397 if (key_type == NIX_FLOW_KEY_TYPE_INNR_TCP || 3398 key_type == NIX_FLOW_KEY_TYPE_INNR_UDP || 3399 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) 3400 field->lid = NPC_LID_LH; 3401 field->bytesm1 = 3; /* Sport + Dport, 4 bytes */ 3402 3403 /* Enum values for NPC_LID_LD and NPC_LID_LG are same, 3404 * so no need to change the ltype_match, just change 3405 * the lid for inner protocols 3406 */ 3407 BUILD_BUG_ON((int)NPC_LT_LD_TCP != 3408 (int)NPC_LT_LH_TU_TCP); 3409 BUILD_BUG_ON((int)NPC_LT_LD_UDP != 3410 (int)NPC_LT_LH_TU_UDP); 3411 BUILD_BUG_ON((int)NPC_LT_LD_SCTP != 3412 (int)NPC_LT_LH_TU_SCTP); 3413 3414 if ((key_type == NIX_FLOW_KEY_TYPE_TCP || 3415 key_type == NIX_FLOW_KEY_TYPE_INNR_TCP) && 3416 valid_key) { 3417 field->ltype_match |= NPC_LT_LD_TCP; 3418 group_member = true; 3419 } else if ((key_type == NIX_FLOW_KEY_TYPE_UDP || 3420 key_type == NIX_FLOW_KEY_TYPE_INNR_UDP) && 3421 valid_key) { 3422 field->ltype_match |= NPC_LT_LD_UDP; 3423 group_member = true; 3424 } else if ((key_type == NIX_FLOW_KEY_TYPE_SCTP || 3425 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) && 3426 valid_key) { 3427 field->ltype_match |= NPC_LT_LD_SCTP; 3428 group_member = true; 3429 } 3430 field->ltype_mask = ~field->ltype_match; 3431 if (key_type == NIX_FLOW_KEY_TYPE_SCTP || 3432 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) { 3433 /* Handle the case where any of the group item 3434 * is enabled in the group but not the final one 3435 */ 3436 if (group_member) { 3437 valid_key = true; 3438 group_member = false; 3439 } 3440 } else { 3441 field_marker = false; 3442 keyoff_marker = false; 3443 } 3444 3445 /* TCP/UDP/SCTP and ESP/AH falls at same offset so 3446 * remember the TCP key offset of 40 byte hash key. 3447 */ 3448 if (key_type == NIX_FLOW_KEY_TYPE_TCP) 3449 l4_key_offset = key_off; 3450 break; 3451 case NIX_FLOW_KEY_TYPE_NVGRE: 3452 field->lid = NPC_LID_LD; 3453 field->hdr_offset = 4; /* VSID offset */ 3454 field->bytesm1 = 2; 3455 field->ltype_match = NPC_LT_LD_NVGRE; 3456 field->ltype_mask = 0xF; 3457 break; 3458 case NIX_FLOW_KEY_TYPE_VXLAN: 3459 case NIX_FLOW_KEY_TYPE_GENEVE: 3460 field->lid = NPC_LID_LE; 3461 field->bytesm1 = 2; 3462 field->hdr_offset = 4; 3463 field->ltype_mask = 0xF; 3464 field_marker = false; 3465 keyoff_marker = false; 3466 3467 if (key_type == NIX_FLOW_KEY_TYPE_VXLAN && valid_key) { 3468 field->ltype_match |= NPC_LT_LE_VXLAN; 3469 group_member = true; 3470 } 3471 3472 if (key_type == NIX_FLOW_KEY_TYPE_GENEVE && valid_key) { 3473 field->ltype_match |= NPC_LT_LE_GENEVE; 3474 group_member = true; 3475 } 3476 3477 if (key_type == NIX_FLOW_KEY_TYPE_GENEVE) { 3478 if (group_member) { 3479 field->ltype_mask = ~field->ltype_match; 3480 field_marker = true; 3481 keyoff_marker = true; 3482 valid_key = true; 3483 group_member = false; 3484 } 3485 } 3486 break; 3487 case NIX_FLOW_KEY_TYPE_ETH_DMAC: 3488 case NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC: 3489 field->lid = NPC_LID_LA; 3490 field->ltype_match = NPC_LT_LA_ETHER; 3491 if (key_type == NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC) { 3492 field->lid = NPC_LID_LF; 3493 field->ltype_match = NPC_LT_LF_TU_ETHER; 3494 } 3495 field->hdr_offset = 0; 3496 field->bytesm1 = 5; /* DMAC 6 Byte */ 3497 field->ltype_mask = 0xF; 3498 break; 3499 case NIX_FLOW_KEY_TYPE_IPV6_EXT: 3500 field->lid = NPC_LID_LC; 3501 field->hdr_offset = 40; /* IPV6 hdr */ 3502 field->bytesm1 = 0; /* 1 Byte ext hdr*/ 3503 field->ltype_match = NPC_LT_LC_IP6_EXT; 3504 field->ltype_mask = 0xF; 3505 break; 3506 case NIX_FLOW_KEY_TYPE_GTPU: 3507 field->lid = NPC_LID_LE; 3508 field->hdr_offset = 4; 3509 field->bytesm1 = 3; /* 4 bytes TID*/ 3510 field->ltype_match = NPC_LT_LE_GTPU; 3511 field->ltype_mask = 0xF; 3512 break; 3513 case NIX_FLOW_KEY_TYPE_VLAN: 3514 field->lid = NPC_LID_LB; 3515 field->hdr_offset = 2; /* Skip TPID (2-bytes) */ 3516 field->bytesm1 = 1; /* 2 Bytes (Actually 12 bits) */ 3517 field->ltype_match = NPC_LT_LB_CTAG; 3518 field->ltype_mask = 0xF; 3519 field->fn_mask = 1; /* Mask out the first nibble */ 3520 break; 3521 case NIX_FLOW_KEY_TYPE_AH: 3522 case NIX_FLOW_KEY_TYPE_ESP: 3523 field->hdr_offset = 0; 3524 field->bytesm1 = 7; /* SPI + sequence number */ 3525 field->ltype_mask = 0xF; 3526 field->lid = NPC_LID_LE; 3527 field->ltype_match = NPC_LT_LE_ESP; 3528 if (key_type == NIX_FLOW_KEY_TYPE_AH) { 3529 field->lid = NPC_LID_LD; 3530 field->ltype_match = NPC_LT_LD_AH; 3531 field->hdr_offset = 4; 3532 keyoff_marker = false; 3533 } 3534 break; 3535 } 3536 field->ena = 1; 3537 3538 /* Found a valid flow key type */ 3539 if (valid_key) { 3540 /* Use the key offset of TCP/UDP/SCTP fields 3541 * for ESP/AH fields. 3542 */ 3543 if (key_type == NIX_FLOW_KEY_TYPE_ESP || 3544 key_type == NIX_FLOW_KEY_TYPE_AH) 3545 key_off = l4_key_offset; 3546 field->key_offset = key_off; 3547 memcpy(&alg[nr_field], field, sizeof(*field)); 3548 max_key_off = max(max_key_off, field->bytesm1 + 1); 3549 3550 /* Found a field marker, get the next field */ 3551 if (field_marker) 3552 nr_field++; 3553 } 3554 3555 /* Found a keyoff marker, update the new key_off */ 3556 if (keyoff_marker) { 3557 key_off += max_key_off; 3558 max_key_off = 0; 3559 } 3560 } 3561 /* Processed all the flow key types */ 3562 if (idx == max_bit_pos && key_off <= MAX_KEY_OFF) 3563 return 0; 3564 else 3565 return NIX_AF_ERR_RSS_NOSPC_FIELD; 3566 } 3567 3568 static int reserve_flowkey_alg_idx(struct rvu *rvu, int blkaddr, u32 flow_cfg) 3569 { 3570 u64 field[FIELDS_PER_ALG]; 3571 struct nix_hw *hw; 3572 int fid, rc; 3573 3574 hw = get_nix_hw(rvu->hw, blkaddr); 3575 if (!hw) 3576 return NIX_AF_ERR_INVALID_NIXBLK; 3577 3578 /* No room to add new flow hash algoritham */ 3579 if (hw->flowkey.in_use >= NIX_FLOW_KEY_ALG_MAX) 3580 return NIX_AF_ERR_RSS_NOSPC_ALGO; 3581 3582 /* Generate algo fields for the given flow_cfg */ 3583 rc = set_flowkey_fields((struct nix_rx_flowkey_alg *)field, flow_cfg); 3584 if (rc) 3585 return rc; 3586 3587 /* Update ALGX_FIELDX register with generated fields */ 3588 for (fid = 0; fid < FIELDS_PER_ALG; fid++) 3589 rvu_write64(rvu, blkaddr, 3590 NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(hw->flowkey.in_use, 3591 fid), field[fid]); 3592 3593 /* Store the flow_cfg for futher lookup */ 3594 rc = hw->flowkey.in_use; 3595 hw->flowkey.flowkey[rc] = flow_cfg; 3596 hw->flowkey.in_use++; 3597 3598 return rc; 3599 } 3600 3601 int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu, 3602 struct nix_rss_flowkey_cfg *req, 3603 struct nix_rss_flowkey_cfg_rsp *rsp) 3604 { 3605 u16 pcifunc = req->hdr.pcifunc; 3606 int alg_idx, nixlf, blkaddr; 3607 struct nix_hw *nix_hw; 3608 int err; 3609 3610 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3611 if (err) 3612 return err; 3613 3614 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3615 if (!nix_hw) 3616 return NIX_AF_ERR_INVALID_NIXBLK; 3617 3618 alg_idx = get_flowkey_alg_idx(nix_hw, req->flowkey_cfg); 3619 /* Failed to get algo index from the exiting list, reserve new */ 3620 if (alg_idx < 0) { 3621 alg_idx = reserve_flowkey_alg_idx(rvu, blkaddr, 3622 req->flowkey_cfg); 3623 if (alg_idx < 0) 3624 return alg_idx; 3625 } 3626 rsp->alg_idx = alg_idx; 3627 rvu_npc_update_flowkey_alg_idx(rvu, pcifunc, nixlf, req->group, 3628 alg_idx, req->mcam_index); 3629 return 0; 3630 } 3631 3632 static int nix_rx_flowkey_alg_cfg(struct rvu *rvu, int blkaddr) 3633 { 3634 u32 flowkey_cfg, minkey_cfg; 3635 int alg, fid, rc; 3636 3637 /* Disable all flow key algx fieldx */ 3638 for (alg = 0; alg < NIX_FLOW_KEY_ALG_MAX; alg++) { 3639 for (fid = 0; fid < FIELDS_PER_ALG; fid++) 3640 rvu_write64(rvu, blkaddr, 3641 NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(alg, fid), 3642 0); 3643 } 3644 3645 /* IPv4/IPv6 SIP/DIPs */ 3646 flowkey_cfg = NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6; 3647 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3648 if (rc < 0) 3649 return rc; 3650 3651 /* TCPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3652 minkey_cfg = flowkey_cfg; 3653 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP; 3654 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3655 if (rc < 0) 3656 return rc; 3657 3658 /* UDPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3659 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_UDP; 3660 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3661 if (rc < 0) 3662 return rc; 3663 3664 /* SCTPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3665 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_SCTP; 3666 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3667 if (rc < 0) 3668 return rc; 3669 3670 /* TCP/UDP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3671 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3672 NIX_FLOW_KEY_TYPE_UDP; 3673 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3674 if (rc < 0) 3675 return rc; 3676 3677 /* TCP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3678 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3679 NIX_FLOW_KEY_TYPE_SCTP; 3680 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3681 if (rc < 0) 3682 return rc; 3683 3684 /* UDP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3685 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_UDP | 3686 NIX_FLOW_KEY_TYPE_SCTP; 3687 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3688 if (rc < 0) 3689 return rc; 3690 3691 /* TCP/UDP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3692 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3693 NIX_FLOW_KEY_TYPE_UDP | NIX_FLOW_KEY_TYPE_SCTP; 3694 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3695 if (rc < 0) 3696 return rc; 3697 3698 return 0; 3699 } 3700 3701 int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu, 3702 struct nix_set_mac_addr *req, 3703 struct msg_rsp *rsp) 3704 { 3705 bool from_vf = req->hdr.pcifunc & RVU_PFVF_FUNC_MASK; 3706 u16 pcifunc = req->hdr.pcifunc; 3707 int blkaddr, nixlf, err; 3708 struct rvu_pfvf *pfvf; 3709 3710 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3711 if (err) 3712 return err; 3713 3714 pfvf = rvu_get_pfvf(rvu, pcifunc); 3715 3716 /* untrusted VF can't overwrite admin(PF) changes */ 3717 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && 3718 (from_vf && test_bit(PF_SET_VF_MAC, &pfvf->flags))) { 3719 dev_warn(rvu->dev, 3720 "MAC address set by admin(PF) cannot be overwritten by untrusted VF"); 3721 return -EPERM; 3722 } 3723 3724 ether_addr_copy(pfvf->mac_addr, req->mac_addr); 3725 3726 rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, 3727 pfvf->rx_chan_base, req->mac_addr); 3728 3729 if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && from_vf) 3730 ether_addr_copy(pfvf->default_mac, req->mac_addr); 3731 3732 rvu_switch_update_rules(rvu, pcifunc); 3733 3734 return 0; 3735 } 3736 3737 int rvu_mbox_handler_nix_get_mac_addr(struct rvu *rvu, 3738 struct msg_req *req, 3739 struct nix_get_mac_addr_rsp *rsp) 3740 { 3741 u16 pcifunc = req->hdr.pcifunc; 3742 struct rvu_pfvf *pfvf; 3743 3744 if (!is_nixlf_attached(rvu, pcifunc)) 3745 return NIX_AF_ERR_AF_LF_INVALID; 3746 3747 pfvf = rvu_get_pfvf(rvu, pcifunc); 3748 3749 ether_addr_copy(rsp->mac_addr, pfvf->mac_addr); 3750 3751 return 0; 3752 } 3753 3754 int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req, 3755 struct msg_rsp *rsp) 3756 { 3757 bool allmulti, promisc, nix_rx_multicast; 3758 u16 pcifunc = req->hdr.pcifunc; 3759 struct rvu_pfvf *pfvf; 3760 int nixlf, err; 3761 3762 pfvf = rvu_get_pfvf(rvu, pcifunc); 3763 promisc = req->mode & NIX_RX_MODE_PROMISC ? true : false; 3764 allmulti = req->mode & NIX_RX_MODE_ALLMULTI ? true : false; 3765 pfvf->use_mce_list = req->mode & NIX_RX_MODE_USE_MCE ? true : false; 3766 3767 nix_rx_multicast = rvu->hw->cap.nix_rx_multicast & pfvf->use_mce_list; 3768 3769 if (is_vf(pcifunc) && !nix_rx_multicast && 3770 (promisc || allmulti)) { 3771 dev_warn_ratelimited(rvu->dev, 3772 "VF promisc/multicast not supported\n"); 3773 return 0; 3774 } 3775 3776 /* untrusted VF can't configure promisc/allmulti */ 3777 if (is_vf(pcifunc) && !test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && 3778 (promisc || allmulti)) 3779 return 0; 3780 3781 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 3782 if (err) 3783 return err; 3784 3785 if (nix_rx_multicast) { 3786 /* add/del this PF_FUNC to/from mcast pkt replication list */ 3787 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_ALLMULTI_ENTRY, 3788 allmulti); 3789 if (err) { 3790 dev_err(rvu->dev, 3791 "Failed to update pcifunc 0x%x to multicast list\n", 3792 pcifunc); 3793 return err; 3794 } 3795 3796 /* add/del this PF_FUNC to/from promisc pkt replication list */ 3797 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_PROMISC_ENTRY, 3798 promisc); 3799 if (err) { 3800 dev_err(rvu->dev, 3801 "Failed to update pcifunc 0x%x to promisc list\n", 3802 pcifunc); 3803 return err; 3804 } 3805 } 3806 3807 /* install/uninstall allmulti entry */ 3808 if (allmulti) { 3809 rvu_npc_install_allmulti_entry(rvu, pcifunc, nixlf, 3810 pfvf->rx_chan_base); 3811 } else { 3812 if (!nix_rx_multicast) 3813 rvu_npc_enable_allmulti_entry(rvu, pcifunc, nixlf, false); 3814 } 3815 3816 /* install/uninstall promisc entry */ 3817 if (promisc) { 3818 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 3819 pfvf->rx_chan_base, 3820 pfvf->rx_chan_cnt); 3821 3822 if (rvu_npc_exact_has_match_table(rvu)) 3823 rvu_npc_exact_promisc_enable(rvu, pcifunc); 3824 } else { 3825 if (!nix_rx_multicast) 3826 rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf, false); 3827 3828 if (rvu_npc_exact_has_match_table(rvu)) 3829 rvu_npc_exact_promisc_disable(rvu, pcifunc); 3830 } 3831 3832 return 0; 3833 } 3834 3835 static void nix_find_link_frs(struct rvu *rvu, 3836 struct nix_frs_cfg *req, u16 pcifunc) 3837 { 3838 int pf = rvu_get_pf(pcifunc); 3839 struct rvu_pfvf *pfvf; 3840 int maxlen, minlen; 3841 int numvfs, hwvf; 3842 int vf; 3843 3844 /* Update with requester's min/max lengths */ 3845 pfvf = rvu_get_pfvf(rvu, pcifunc); 3846 pfvf->maxlen = req->maxlen; 3847 if (req->update_minlen) 3848 pfvf->minlen = req->minlen; 3849 3850 maxlen = req->maxlen; 3851 minlen = req->update_minlen ? req->minlen : 0; 3852 3853 /* Get this PF's numVFs and starting hwvf */ 3854 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 3855 3856 /* For each VF, compare requested max/minlen */ 3857 for (vf = 0; vf < numvfs; vf++) { 3858 pfvf = &rvu->hwvf[hwvf + vf]; 3859 if (pfvf->maxlen > maxlen) 3860 maxlen = pfvf->maxlen; 3861 if (req->update_minlen && 3862 pfvf->minlen && pfvf->minlen < minlen) 3863 minlen = pfvf->minlen; 3864 } 3865 3866 /* Compare requested max/minlen with PF's max/minlen */ 3867 pfvf = &rvu->pf[pf]; 3868 if (pfvf->maxlen > maxlen) 3869 maxlen = pfvf->maxlen; 3870 if (req->update_minlen && 3871 pfvf->minlen && pfvf->minlen < minlen) 3872 minlen = pfvf->minlen; 3873 3874 /* Update the request with max/min PF's and it's VF's max/min */ 3875 req->maxlen = maxlen; 3876 if (req->update_minlen) 3877 req->minlen = minlen; 3878 } 3879 3880 static int 3881 nix_config_link_credits(struct rvu *rvu, int blkaddr, int link, 3882 u16 pcifunc, u64 tx_credits) 3883 { 3884 struct rvu_hwinfo *hw = rvu->hw; 3885 int pf = rvu_get_pf(pcifunc); 3886 u8 cgx_id = 0, lmac_id = 0; 3887 unsigned long poll_tmo; 3888 bool restore_tx_en = 0; 3889 struct nix_hw *nix_hw; 3890 u64 cfg, sw_xoff = 0; 3891 u32 schq = 0; 3892 u32 credits; 3893 int rc; 3894 3895 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3896 if (!nix_hw) 3897 return NIX_AF_ERR_INVALID_NIXBLK; 3898 3899 if (tx_credits == nix_hw->tx_credits[link]) 3900 return 0; 3901 3902 /* Enable cgx tx if disabled for credits to be back */ 3903 if (is_pf_cgxmapped(rvu, pf)) { 3904 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 3905 restore_tx_en = !rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), 3906 lmac_id, true); 3907 } 3908 3909 mutex_lock(&rvu->rsrc_lock); 3910 /* Disable new traffic to link */ 3911 if (hw->cap.nix_shaping) { 3912 schq = nix_get_tx_link(rvu, pcifunc); 3913 sw_xoff = rvu_read64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq)); 3914 rvu_write64(rvu, blkaddr, 3915 NIX_AF_TL1X_SW_XOFF(schq), BIT_ULL(0)); 3916 } 3917 3918 rc = NIX_AF_ERR_LINK_CREDITS; 3919 poll_tmo = jiffies + usecs_to_jiffies(200000); 3920 /* Wait for credits to return */ 3921 do { 3922 if (time_after(jiffies, poll_tmo)) 3923 goto exit; 3924 usleep_range(100, 200); 3925 3926 cfg = rvu_read64(rvu, blkaddr, 3927 NIX_AF_TX_LINKX_NORM_CREDIT(link)); 3928 credits = (cfg >> 12) & 0xFFFFFULL; 3929 } while (credits != nix_hw->tx_credits[link]); 3930 3931 cfg &= ~(0xFFFFFULL << 12); 3932 cfg |= (tx_credits << 12); 3933 rvu_write64(rvu, blkaddr, NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg); 3934 rc = 0; 3935 3936 nix_hw->tx_credits[link] = tx_credits; 3937 3938 exit: 3939 /* Enable traffic back */ 3940 if (hw->cap.nix_shaping && !sw_xoff) 3941 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq), 0); 3942 3943 /* Restore state of cgx tx */ 3944 if (restore_tx_en) 3945 rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false); 3946 3947 mutex_unlock(&rvu->rsrc_lock); 3948 return rc; 3949 } 3950 3951 int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req, 3952 struct msg_rsp *rsp) 3953 { 3954 struct rvu_hwinfo *hw = rvu->hw; 3955 u16 pcifunc = req->hdr.pcifunc; 3956 int pf = rvu_get_pf(pcifunc); 3957 int blkaddr, schq, link = -1; 3958 struct nix_txsch *txsch; 3959 u64 cfg, lmac_fifo_len; 3960 struct nix_hw *nix_hw; 3961 struct rvu_pfvf *pfvf; 3962 u8 cgx = 0, lmac = 0; 3963 u16 max_mtu; 3964 3965 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 3966 if (blkaddr < 0) 3967 return NIX_AF_ERR_AF_LF_INVALID; 3968 3969 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3970 if (!nix_hw) 3971 return NIX_AF_ERR_INVALID_NIXBLK; 3972 3973 if (is_afvf(pcifunc)) 3974 rvu_get_lbk_link_max_frs(rvu, &max_mtu); 3975 else 3976 rvu_get_lmac_link_max_frs(rvu, &max_mtu); 3977 3978 if (!req->sdp_link && req->maxlen > max_mtu) 3979 return NIX_AF_ERR_FRS_INVALID; 3980 3981 if (req->update_minlen && req->minlen < NIC_HW_MIN_FRS) 3982 return NIX_AF_ERR_FRS_INVALID; 3983 3984 /* Check if requester wants to update SMQ's */ 3985 if (!req->update_smq) 3986 goto rx_frscfg; 3987 3988 /* Update min/maxlen in each of the SMQ attached to this PF/VF */ 3989 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 3990 mutex_lock(&rvu->rsrc_lock); 3991 for (schq = 0; schq < txsch->schq.max; schq++) { 3992 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 3993 continue; 3994 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq)); 3995 cfg = (cfg & ~(0xFFFFULL << 8)) | ((u64)req->maxlen << 8); 3996 if (req->update_minlen) 3997 cfg = (cfg & ~0x7FULL) | ((u64)req->minlen & 0x7F); 3998 rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq), cfg); 3999 } 4000 mutex_unlock(&rvu->rsrc_lock); 4001 4002 rx_frscfg: 4003 /* Check if config is for SDP link */ 4004 if (req->sdp_link) { 4005 if (!hw->sdp_links) 4006 return NIX_AF_ERR_RX_LINK_INVALID; 4007 link = hw->cgx_links + hw->lbk_links; 4008 goto linkcfg; 4009 } 4010 4011 /* Check if the request is from CGX mapped RVU PF */ 4012 if (is_pf_cgxmapped(rvu, pf)) { 4013 /* Get CGX and LMAC to which this PF is mapped and find link */ 4014 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac); 4015 link = (cgx * hw->lmac_per_cgx) + lmac; 4016 } else if (pf == 0) { 4017 /* For VFs of PF0 ingress is LBK port, so config LBK link */ 4018 pfvf = rvu_get_pfvf(rvu, pcifunc); 4019 link = hw->cgx_links + pfvf->lbkid; 4020 } 4021 4022 if (link < 0) 4023 return NIX_AF_ERR_RX_LINK_INVALID; 4024 4025 nix_find_link_frs(rvu, req, pcifunc); 4026 4027 linkcfg: 4028 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link)); 4029 cfg = (cfg & ~(0xFFFFULL << 16)) | ((u64)req->maxlen << 16); 4030 if (req->update_minlen) 4031 cfg = (cfg & ~0xFFFFULL) | req->minlen; 4032 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), cfg); 4033 4034 if (req->sdp_link || pf == 0) 4035 return 0; 4036 4037 /* Update transmit credits for CGX links */ 4038 lmac_fifo_len = rvu_cgx_get_lmac_fifolen(rvu, cgx, lmac); 4039 if (!lmac_fifo_len) { 4040 dev_err(rvu->dev, 4041 "%s: Failed to get CGX/RPM%d:LMAC%d FIFO size\n", 4042 __func__, cgx, lmac); 4043 return 0; 4044 } 4045 return nix_config_link_credits(rvu, blkaddr, link, pcifunc, 4046 (lmac_fifo_len - req->maxlen) / 16); 4047 } 4048 4049 int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req, 4050 struct msg_rsp *rsp) 4051 { 4052 int nixlf, blkaddr, err; 4053 u64 cfg; 4054 4055 err = nix_get_nixlf(rvu, req->hdr.pcifunc, &nixlf, &blkaddr); 4056 if (err) 4057 return err; 4058 4059 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf)); 4060 /* Set the interface configuration */ 4061 if (req->len_verify & BIT(0)) 4062 cfg |= BIT_ULL(41); 4063 else 4064 cfg &= ~BIT_ULL(41); 4065 4066 if (req->len_verify & BIT(1)) 4067 cfg |= BIT_ULL(40); 4068 else 4069 cfg &= ~BIT_ULL(40); 4070 4071 if (req->csum_verify & BIT(0)) 4072 cfg |= BIT_ULL(37); 4073 else 4074 cfg &= ~BIT_ULL(37); 4075 4076 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), cfg); 4077 4078 return 0; 4079 } 4080 4081 static u64 rvu_get_lbk_link_credits(struct rvu *rvu, u16 lbk_max_frs) 4082 { 4083 /* CN10k supports 72KB FIFO size and max packet size of 64k */ 4084 if (rvu->hw->lbk_bufsize == 0x12000) 4085 return (rvu->hw->lbk_bufsize - lbk_max_frs) / 16; 4086 4087 return 1600; /* 16 * max LBK datarate = 16 * 100Gbps */ 4088 } 4089 4090 static void nix_link_config(struct rvu *rvu, int blkaddr, 4091 struct nix_hw *nix_hw) 4092 { 4093 struct rvu_hwinfo *hw = rvu->hw; 4094 int cgx, lmac_cnt, slink, link; 4095 u16 lbk_max_frs, lmac_max_frs; 4096 unsigned long lmac_bmap; 4097 u64 tx_credits, cfg; 4098 u64 lmac_fifo_len; 4099 int iter; 4100 4101 rvu_get_lbk_link_max_frs(rvu, &lbk_max_frs); 4102 rvu_get_lmac_link_max_frs(rvu, &lmac_max_frs); 4103 4104 /* Set default min/max packet lengths allowed on NIX Rx links. 4105 * 4106 * With HW reset minlen value of 60byte, HW will treat ARP pkts 4107 * as undersize and report them to SW as error pkts, hence 4108 * setting it to 40 bytes. 4109 */ 4110 for (link = 0; link < hw->cgx_links; link++) { 4111 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4112 ((u64)lmac_max_frs << 16) | NIC_HW_MIN_FRS); 4113 } 4114 4115 for (link = hw->cgx_links; link < hw->lbk_links; link++) { 4116 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4117 ((u64)lbk_max_frs << 16) | NIC_HW_MIN_FRS); 4118 } 4119 if (hw->sdp_links) { 4120 link = hw->cgx_links + hw->lbk_links; 4121 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4122 SDP_HW_MAX_FRS << 16 | NIC_HW_MIN_FRS); 4123 } 4124 4125 /* Set credits for Tx links assuming max packet length allowed. 4126 * This will be reconfigured based on MTU set for PF/VF. 4127 */ 4128 for (cgx = 0; cgx < hw->cgx; cgx++) { 4129 lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); 4130 /* Skip when cgx is not available or lmac cnt is zero */ 4131 if (lmac_cnt <= 0) 4132 continue; 4133 slink = cgx * hw->lmac_per_cgx; 4134 4135 /* Get LMAC id's from bitmap */ 4136 lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu)); 4137 for_each_set_bit(iter, &lmac_bmap, rvu->hw->lmac_per_cgx) { 4138 lmac_fifo_len = rvu_cgx_get_lmac_fifolen(rvu, cgx, iter); 4139 if (!lmac_fifo_len) { 4140 dev_err(rvu->dev, 4141 "%s: Failed to get CGX/RPM%d:LMAC%d FIFO size\n", 4142 __func__, cgx, iter); 4143 continue; 4144 } 4145 tx_credits = (lmac_fifo_len - lmac_max_frs) / 16; 4146 /* Enable credits and set credit pkt count to max allowed */ 4147 cfg = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1); 4148 4149 link = iter + slink; 4150 nix_hw->tx_credits[link] = tx_credits; 4151 rvu_write64(rvu, blkaddr, 4152 NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg); 4153 } 4154 } 4155 4156 /* Set Tx credits for LBK link */ 4157 slink = hw->cgx_links; 4158 for (link = slink; link < (slink + hw->lbk_links); link++) { 4159 tx_credits = rvu_get_lbk_link_credits(rvu, lbk_max_frs); 4160 nix_hw->tx_credits[link] = tx_credits; 4161 /* Enable credits and set credit pkt count to max allowed */ 4162 tx_credits = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1); 4163 rvu_write64(rvu, blkaddr, 4164 NIX_AF_TX_LINKX_NORM_CREDIT(link), tx_credits); 4165 } 4166 } 4167 4168 static int nix_calibrate_x2p(struct rvu *rvu, int blkaddr) 4169 { 4170 int idx, err; 4171 u64 status; 4172 4173 /* Start X2P bus calibration */ 4174 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4175 rvu_read64(rvu, blkaddr, NIX_AF_CFG) | BIT_ULL(9)); 4176 /* Wait for calibration to complete */ 4177 err = rvu_poll_reg(rvu, blkaddr, 4178 NIX_AF_STATUS, BIT_ULL(10), false); 4179 if (err) { 4180 dev_err(rvu->dev, "NIX X2P bus calibration failed\n"); 4181 return err; 4182 } 4183 4184 status = rvu_read64(rvu, blkaddr, NIX_AF_STATUS); 4185 /* Check if CGX devices are ready */ 4186 for (idx = 0; idx < rvu->cgx_cnt_max; idx++) { 4187 /* Skip when cgx port is not available */ 4188 if (!rvu_cgx_pdata(idx, rvu) || 4189 (status & (BIT_ULL(16 + idx)))) 4190 continue; 4191 dev_err(rvu->dev, 4192 "CGX%d didn't respond to NIX X2P calibration\n", idx); 4193 err = -EBUSY; 4194 } 4195 4196 /* Check if LBK is ready */ 4197 if (!(status & BIT_ULL(19))) { 4198 dev_err(rvu->dev, 4199 "LBK didn't respond to NIX X2P calibration\n"); 4200 err = -EBUSY; 4201 } 4202 4203 /* Clear 'calibrate_x2p' bit */ 4204 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4205 rvu_read64(rvu, blkaddr, NIX_AF_CFG) & ~BIT_ULL(9)); 4206 if (err || (status & 0x3FFULL)) 4207 dev_err(rvu->dev, 4208 "NIX X2P calibration failed, status 0x%llx\n", status); 4209 if (err) 4210 return err; 4211 return 0; 4212 } 4213 4214 static int nix_aq_init(struct rvu *rvu, struct rvu_block *block) 4215 { 4216 u64 cfg; 4217 int err; 4218 4219 /* Set admin queue endianness */ 4220 cfg = rvu_read64(rvu, block->addr, NIX_AF_CFG); 4221 #ifdef __BIG_ENDIAN 4222 cfg |= BIT_ULL(8); 4223 rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg); 4224 #else 4225 cfg &= ~BIT_ULL(8); 4226 rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg); 4227 #endif 4228 4229 /* Do not bypass NDC cache */ 4230 cfg = rvu_read64(rvu, block->addr, NIX_AF_NDC_CFG); 4231 cfg &= ~0x3FFEULL; 4232 #ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING 4233 /* Disable caching of SQB aka SQEs */ 4234 cfg |= 0x04ULL; 4235 #endif 4236 rvu_write64(rvu, block->addr, NIX_AF_NDC_CFG, cfg); 4237 4238 /* Result structure can be followed by RQ/SQ/CQ context at 4239 * RES + 128bytes and a write mask at RES + 256 bytes, depending on 4240 * operation type. Alloc sufficient result memory for all operations. 4241 */ 4242 err = rvu_aq_alloc(rvu, &block->aq, 4243 Q_COUNT(AQ_SIZE), sizeof(struct nix_aq_inst_s), 4244 ALIGN(sizeof(struct nix_aq_res_s), 128) + 256); 4245 if (err) 4246 return err; 4247 4248 rvu_write64(rvu, block->addr, NIX_AF_AQ_CFG, AQ_SIZE); 4249 rvu_write64(rvu, block->addr, 4250 NIX_AF_AQ_BASE, (u64)block->aq->inst->iova); 4251 return 0; 4252 } 4253 4254 static void rvu_nix_setup_capabilities(struct rvu *rvu, int blkaddr) 4255 { 4256 struct rvu_hwinfo *hw = rvu->hw; 4257 u64 hw_const; 4258 4259 hw_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 4260 4261 /* On OcteonTx2 DWRR quantum is directly configured into each of 4262 * the transmit scheduler queues. And PF/VF drivers were free to 4263 * config any value upto 2^24. 4264 * On CN10K, HW is modified, the quantum configuration at scheduler 4265 * queues is in terms of weight. And SW needs to setup a base DWRR MTU 4266 * at NIX_AF_DWRR_RPM_MTU / NIX_AF_DWRR_SDP_MTU. HW will do 4267 * 'DWRR MTU * weight' to get the quantum. 4268 * 4269 * Check if HW uses a common MTU for all DWRR quantum configs. 4270 * On OcteonTx2 this register field is '0'. 4271 */ 4272 if (((hw_const >> 56) & 0x10) == 0x10) 4273 hw->cap.nix_common_dwrr_mtu = true; 4274 } 4275 4276 static int rvu_nix_block_init(struct rvu *rvu, struct nix_hw *nix_hw) 4277 { 4278 const struct npc_lt_def_cfg *ltdefs; 4279 struct rvu_hwinfo *hw = rvu->hw; 4280 int blkaddr = nix_hw->blkaddr; 4281 struct rvu_block *block; 4282 int err; 4283 u64 cfg; 4284 4285 block = &hw->block[blkaddr]; 4286 4287 if (is_rvu_96xx_B0(rvu)) { 4288 /* As per a HW errata in 96xx A0/B0 silicon, NIX may corrupt 4289 * internal state when conditional clocks are turned off. 4290 * Hence enable them. 4291 */ 4292 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4293 rvu_read64(rvu, blkaddr, NIX_AF_CFG) | 0x40ULL); 4294 4295 /* Set chan/link to backpressure TL3 instead of TL2 */ 4296 rvu_write64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL, 0x01); 4297 4298 /* Disable SQ manager's sticky mode operation (set TM6 = 0) 4299 * This sticky mode is known to cause SQ stalls when multiple 4300 * SQs are mapped to same SMQ and transmitting pkts at a time. 4301 */ 4302 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS); 4303 cfg &= ~BIT_ULL(15); 4304 rvu_write64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS, cfg); 4305 } 4306 4307 ltdefs = rvu->kpu.lt_def; 4308 /* Calibrate X2P bus to check if CGX/LBK links are fine */ 4309 err = nix_calibrate_x2p(rvu, blkaddr); 4310 if (err) 4311 return err; 4312 4313 /* Setup capabilities of the NIX block */ 4314 rvu_nix_setup_capabilities(rvu, blkaddr); 4315 4316 /* Initialize admin queue */ 4317 err = nix_aq_init(rvu, block); 4318 if (err) 4319 return err; 4320 4321 /* Restore CINT timer delay to HW reset values */ 4322 rvu_write64(rvu, blkaddr, NIX_AF_CINT_DELAY, 0x0ULL); 4323 4324 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SEB_CFG); 4325 4326 /* For better performance use NDC TX instead of NDC RX for SQ's SQEs" */ 4327 cfg |= 1ULL; 4328 if (!is_rvu_otx2(rvu)) 4329 cfg |= NIX_PTP_1STEP_EN; 4330 4331 rvu_write64(rvu, blkaddr, NIX_AF_SEB_CFG, cfg); 4332 4333 if (!is_rvu_otx2(rvu)) 4334 rvu_nix_block_cn10k_init(rvu, nix_hw); 4335 4336 if (is_block_implemented(hw, blkaddr)) { 4337 err = nix_setup_txschq(rvu, nix_hw, blkaddr); 4338 if (err) 4339 return err; 4340 4341 err = nix_setup_ipolicers(rvu, nix_hw, blkaddr); 4342 if (err) 4343 return err; 4344 4345 err = nix_af_mark_format_setup(rvu, nix_hw, blkaddr); 4346 if (err) 4347 return err; 4348 4349 err = nix_setup_mcast(rvu, nix_hw, blkaddr); 4350 if (err) 4351 return err; 4352 4353 err = nix_setup_txvlan(rvu, nix_hw); 4354 if (err) 4355 return err; 4356 4357 /* Configure segmentation offload formats */ 4358 nix_setup_lso(rvu, nix_hw, blkaddr); 4359 4360 /* Config Outer/Inner L2, IP, TCP, UDP and SCTP NPC layer info. 4361 * This helps HW protocol checker to identify headers 4362 * and validate length and checksums. 4363 */ 4364 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OL2, 4365 (ltdefs->rx_ol2.lid << 8) | (ltdefs->rx_ol2.ltype_match << 4) | 4366 ltdefs->rx_ol2.ltype_mask); 4367 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4, 4368 (ltdefs->rx_oip4.lid << 8) | (ltdefs->rx_oip4.ltype_match << 4) | 4369 ltdefs->rx_oip4.ltype_mask); 4370 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4, 4371 (ltdefs->rx_iip4.lid << 8) | (ltdefs->rx_iip4.ltype_match << 4) | 4372 ltdefs->rx_iip4.ltype_mask); 4373 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6, 4374 (ltdefs->rx_oip6.lid << 8) | (ltdefs->rx_oip6.ltype_match << 4) | 4375 ltdefs->rx_oip6.ltype_mask); 4376 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6, 4377 (ltdefs->rx_iip6.lid << 8) | (ltdefs->rx_iip6.ltype_match << 4) | 4378 ltdefs->rx_iip6.ltype_mask); 4379 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OTCP, 4380 (ltdefs->rx_otcp.lid << 8) | (ltdefs->rx_otcp.ltype_match << 4) | 4381 ltdefs->rx_otcp.ltype_mask); 4382 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ITCP, 4383 (ltdefs->rx_itcp.lid << 8) | (ltdefs->rx_itcp.ltype_match << 4) | 4384 ltdefs->rx_itcp.ltype_mask); 4385 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OUDP, 4386 (ltdefs->rx_oudp.lid << 8) | (ltdefs->rx_oudp.ltype_match << 4) | 4387 ltdefs->rx_oudp.ltype_mask); 4388 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IUDP, 4389 (ltdefs->rx_iudp.lid << 8) | (ltdefs->rx_iudp.ltype_match << 4) | 4390 ltdefs->rx_iudp.ltype_mask); 4391 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OSCTP, 4392 (ltdefs->rx_osctp.lid << 8) | (ltdefs->rx_osctp.ltype_match << 4) | 4393 ltdefs->rx_osctp.ltype_mask); 4394 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ISCTP, 4395 (ltdefs->rx_isctp.lid << 8) | (ltdefs->rx_isctp.ltype_match << 4) | 4396 ltdefs->rx_isctp.ltype_mask); 4397 4398 if (!is_rvu_otx2(rvu)) { 4399 /* Enable APAD calculation for other protocols 4400 * matching APAD0 and APAD1 lt def registers. 4401 */ 4402 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_CST_APAD0, 4403 (ltdefs->rx_apad0.valid << 11) | 4404 (ltdefs->rx_apad0.lid << 8) | 4405 (ltdefs->rx_apad0.ltype_match << 4) | 4406 ltdefs->rx_apad0.ltype_mask); 4407 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_CST_APAD1, 4408 (ltdefs->rx_apad1.valid << 11) | 4409 (ltdefs->rx_apad1.lid << 8) | 4410 (ltdefs->rx_apad1.ltype_match << 4) | 4411 ltdefs->rx_apad1.ltype_mask); 4412 4413 /* Receive ethertype defination register defines layer 4414 * information in NPC_RESULT_S to identify the Ethertype 4415 * location in L2 header. Used for Ethertype overwriting 4416 * in inline IPsec flow. 4417 */ 4418 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ET(0), 4419 (ltdefs->rx_et[0].offset << 12) | 4420 (ltdefs->rx_et[0].valid << 11) | 4421 (ltdefs->rx_et[0].lid << 8) | 4422 (ltdefs->rx_et[0].ltype_match << 4) | 4423 ltdefs->rx_et[0].ltype_mask); 4424 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ET(1), 4425 (ltdefs->rx_et[1].offset << 12) | 4426 (ltdefs->rx_et[1].valid << 11) | 4427 (ltdefs->rx_et[1].lid << 8) | 4428 (ltdefs->rx_et[1].ltype_match << 4) | 4429 ltdefs->rx_et[1].ltype_mask); 4430 } 4431 4432 err = nix_rx_flowkey_alg_cfg(rvu, blkaddr); 4433 if (err) 4434 return err; 4435 4436 nix_hw->tx_credits = kcalloc(hw->cgx_links + hw->lbk_links, 4437 sizeof(u64), GFP_KERNEL); 4438 if (!nix_hw->tx_credits) 4439 return -ENOMEM; 4440 4441 /* Initialize CGX/LBK/SDP link credits, min/max pkt lengths */ 4442 nix_link_config(rvu, blkaddr, nix_hw); 4443 4444 /* Enable Channel backpressure */ 4445 rvu_write64(rvu, blkaddr, NIX_AF_RX_CFG, BIT_ULL(0)); 4446 } 4447 return 0; 4448 } 4449 4450 int rvu_nix_init(struct rvu *rvu) 4451 { 4452 struct rvu_hwinfo *hw = rvu->hw; 4453 struct nix_hw *nix_hw; 4454 int blkaddr = 0, err; 4455 int i = 0; 4456 4457 hw->nix = devm_kcalloc(rvu->dev, MAX_NIX_BLKS, sizeof(struct nix_hw), 4458 GFP_KERNEL); 4459 if (!hw->nix) 4460 return -ENOMEM; 4461 4462 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4463 while (blkaddr) { 4464 nix_hw = &hw->nix[i]; 4465 nix_hw->rvu = rvu; 4466 nix_hw->blkaddr = blkaddr; 4467 err = rvu_nix_block_init(rvu, nix_hw); 4468 if (err) 4469 return err; 4470 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4471 i++; 4472 } 4473 4474 return 0; 4475 } 4476 4477 static void rvu_nix_block_freemem(struct rvu *rvu, int blkaddr, 4478 struct rvu_block *block) 4479 { 4480 struct nix_txsch *txsch; 4481 struct nix_mcast *mcast; 4482 struct nix_txvlan *vlan; 4483 struct nix_hw *nix_hw; 4484 int lvl; 4485 4486 rvu_aq_free(rvu, block->aq); 4487 4488 if (is_block_implemented(rvu->hw, blkaddr)) { 4489 nix_hw = get_nix_hw(rvu->hw, blkaddr); 4490 if (!nix_hw) 4491 return; 4492 4493 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 4494 txsch = &nix_hw->txsch[lvl]; 4495 kfree(txsch->schq.bmap); 4496 } 4497 4498 kfree(nix_hw->tx_credits); 4499 4500 nix_ipolicer_freemem(rvu, nix_hw); 4501 4502 vlan = &nix_hw->txvlan; 4503 kfree(vlan->rsrc.bmap); 4504 mutex_destroy(&vlan->rsrc_lock); 4505 4506 mcast = &nix_hw->mcast; 4507 qmem_free(rvu->dev, mcast->mce_ctx); 4508 qmem_free(rvu->dev, mcast->mcast_buf); 4509 mutex_destroy(&mcast->mce_lock); 4510 } 4511 } 4512 4513 void rvu_nix_freemem(struct rvu *rvu) 4514 { 4515 struct rvu_hwinfo *hw = rvu->hw; 4516 struct rvu_block *block; 4517 int blkaddr = 0; 4518 4519 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4520 while (blkaddr) { 4521 block = &hw->block[blkaddr]; 4522 rvu_nix_block_freemem(rvu, blkaddr, block); 4523 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4524 } 4525 } 4526 4527 int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req, 4528 struct msg_rsp *rsp) 4529 { 4530 u16 pcifunc = req->hdr.pcifunc; 4531 struct rvu_pfvf *pfvf; 4532 int nixlf, err; 4533 4534 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 4535 if (err) 4536 return err; 4537 4538 rvu_npc_enable_default_entries(rvu, pcifunc, nixlf); 4539 4540 npc_mcam_enable_flows(rvu, pcifunc); 4541 4542 pfvf = rvu_get_pfvf(rvu, pcifunc); 4543 set_bit(NIXLF_INITIALIZED, &pfvf->flags); 4544 4545 rvu_switch_update_rules(rvu, pcifunc); 4546 4547 return rvu_cgx_start_stop_io(rvu, pcifunc, true); 4548 } 4549 4550 int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req, 4551 struct msg_rsp *rsp) 4552 { 4553 u16 pcifunc = req->hdr.pcifunc; 4554 struct rvu_pfvf *pfvf; 4555 int nixlf, err; 4556 4557 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 4558 if (err) 4559 return err; 4560 4561 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 4562 4563 pfvf = rvu_get_pfvf(rvu, pcifunc); 4564 clear_bit(NIXLF_INITIALIZED, &pfvf->flags); 4565 4566 return rvu_cgx_start_stop_io(rvu, pcifunc, false); 4567 } 4568 4569 #define RX_SA_BASE GENMASK_ULL(52, 7) 4570 4571 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int nixlf) 4572 { 4573 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 4574 struct hwctx_disable_req ctx_req; 4575 int pf = rvu_get_pf(pcifunc); 4576 struct mac_ops *mac_ops; 4577 u8 cgx_id, lmac_id; 4578 u64 sa_base; 4579 void *cgxd; 4580 int err; 4581 4582 ctx_req.hdr.pcifunc = pcifunc; 4583 4584 /* Cleanup NPC MCAM entries, free Tx scheduler queues being used */ 4585 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 4586 rvu_npc_free_mcam_entries(rvu, pcifunc, nixlf); 4587 nix_interface_deinit(rvu, pcifunc, nixlf); 4588 nix_rx_sync(rvu, blkaddr); 4589 nix_txschq_free(rvu, pcifunc); 4590 4591 clear_bit(NIXLF_INITIALIZED, &pfvf->flags); 4592 4593 rvu_cgx_start_stop_io(rvu, pcifunc, false); 4594 4595 if (pfvf->sq_ctx) { 4596 ctx_req.ctype = NIX_AQ_CTYPE_SQ; 4597 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4598 if (err) 4599 dev_err(rvu->dev, "SQ ctx disable failed\n"); 4600 } 4601 4602 if (pfvf->rq_ctx) { 4603 ctx_req.ctype = NIX_AQ_CTYPE_RQ; 4604 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4605 if (err) 4606 dev_err(rvu->dev, "RQ ctx disable failed\n"); 4607 } 4608 4609 if (pfvf->cq_ctx) { 4610 ctx_req.ctype = NIX_AQ_CTYPE_CQ; 4611 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4612 if (err) 4613 dev_err(rvu->dev, "CQ ctx disable failed\n"); 4614 } 4615 4616 /* reset HW config done for Switch headers */ 4617 rvu_npc_set_parse_mode(rvu, pcifunc, OTX2_PRIV_FLAGS_DEFAULT, 4618 (PKIND_TX | PKIND_RX), 0, 0, 0, 0); 4619 4620 /* Disabling CGX and NPC config done for PTP */ 4621 if (pfvf->hw_rx_tstamp_en) { 4622 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 4623 cgxd = rvu_cgx_pdata(cgx_id, rvu); 4624 mac_ops = get_mac_ops(cgxd); 4625 mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, false); 4626 /* Undo NPC config done for PTP */ 4627 if (npc_config_ts_kpuaction(rvu, pf, pcifunc, false)) 4628 dev_err(rvu->dev, "NPC config for PTP failed\n"); 4629 pfvf->hw_rx_tstamp_en = false; 4630 } 4631 4632 /* reset priority flow control config */ 4633 rvu_cgx_prio_flow_ctrl_cfg(rvu, pcifunc, 0, 0, 0); 4634 4635 /* reset 802.3x flow control config */ 4636 rvu_cgx_cfg_pause_frm(rvu, pcifunc, 0, 0); 4637 4638 nix_ctx_free(rvu, pfvf); 4639 4640 nix_free_all_bandprof(rvu, pcifunc); 4641 4642 sa_base = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(nixlf)); 4643 if (FIELD_GET(RX_SA_BASE, sa_base)) { 4644 err = rvu_cpt_ctx_flush(rvu, pcifunc); 4645 if (err) 4646 dev_err(rvu->dev, 4647 "CPT ctx flush failed with error: %d\n", err); 4648 } 4649 } 4650 4651 #define NIX_AF_LFX_TX_CFG_PTP_EN BIT_ULL(32) 4652 4653 static int rvu_nix_lf_ptp_tx_cfg(struct rvu *rvu, u16 pcifunc, bool enable) 4654 { 4655 struct rvu_hwinfo *hw = rvu->hw; 4656 struct rvu_block *block; 4657 int blkaddr, pf; 4658 int nixlf; 4659 u64 cfg; 4660 4661 pf = rvu_get_pf(pcifunc); 4662 if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP)) 4663 return 0; 4664 4665 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 4666 if (blkaddr < 0) 4667 return NIX_AF_ERR_AF_LF_INVALID; 4668 4669 block = &hw->block[blkaddr]; 4670 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 4671 if (nixlf < 0) 4672 return NIX_AF_ERR_AF_LF_INVALID; 4673 4674 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf)); 4675 4676 if (enable) 4677 cfg |= NIX_AF_LFX_TX_CFG_PTP_EN; 4678 else 4679 cfg &= ~NIX_AF_LFX_TX_CFG_PTP_EN; 4680 4681 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg); 4682 4683 return 0; 4684 } 4685 4686 int rvu_mbox_handler_nix_lf_ptp_tx_enable(struct rvu *rvu, struct msg_req *req, 4687 struct msg_rsp *rsp) 4688 { 4689 return rvu_nix_lf_ptp_tx_cfg(rvu, req->hdr.pcifunc, true); 4690 } 4691 4692 int rvu_mbox_handler_nix_lf_ptp_tx_disable(struct rvu *rvu, struct msg_req *req, 4693 struct msg_rsp *rsp) 4694 { 4695 return rvu_nix_lf_ptp_tx_cfg(rvu, req->hdr.pcifunc, false); 4696 } 4697 4698 int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu, 4699 struct nix_lso_format_cfg *req, 4700 struct nix_lso_format_cfg_rsp *rsp) 4701 { 4702 u16 pcifunc = req->hdr.pcifunc; 4703 struct nix_hw *nix_hw; 4704 struct rvu_pfvf *pfvf; 4705 int blkaddr, idx, f; 4706 u64 reg; 4707 4708 pfvf = rvu_get_pfvf(rvu, pcifunc); 4709 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 4710 if (!pfvf->nixlf || blkaddr < 0) 4711 return NIX_AF_ERR_AF_LF_INVALID; 4712 4713 nix_hw = get_nix_hw(rvu->hw, blkaddr); 4714 if (!nix_hw) 4715 return NIX_AF_ERR_INVALID_NIXBLK; 4716 4717 /* Find existing matching LSO format, if any */ 4718 for (idx = 0; idx < nix_hw->lso.in_use; idx++) { 4719 for (f = 0; f < NIX_LSO_FIELD_MAX; f++) { 4720 reg = rvu_read64(rvu, blkaddr, 4721 NIX_AF_LSO_FORMATX_FIELDX(idx, f)); 4722 if (req->fields[f] != (reg & req->field_mask)) 4723 break; 4724 } 4725 4726 if (f == NIX_LSO_FIELD_MAX) 4727 break; 4728 } 4729 4730 if (idx < nix_hw->lso.in_use) { 4731 /* Match found */ 4732 rsp->lso_format_idx = idx; 4733 return 0; 4734 } 4735 4736 if (nix_hw->lso.in_use == nix_hw->lso.total) 4737 return NIX_AF_ERR_LSO_CFG_FAIL; 4738 4739 rsp->lso_format_idx = nix_hw->lso.in_use++; 4740 4741 for (f = 0; f < NIX_LSO_FIELD_MAX; f++) 4742 rvu_write64(rvu, blkaddr, 4743 NIX_AF_LSO_FORMATX_FIELDX(rsp->lso_format_idx, f), 4744 req->fields[f]); 4745 4746 return 0; 4747 } 4748 4749 #define IPSEC_GEN_CFG_EGRP GENMASK_ULL(50, 48) 4750 #define IPSEC_GEN_CFG_OPCODE GENMASK_ULL(47, 32) 4751 #define IPSEC_GEN_CFG_PARAM1 GENMASK_ULL(31, 16) 4752 #define IPSEC_GEN_CFG_PARAM2 GENMASK_ULL(15, 0) 4753 4754 #define CPT_INST_QSEL_BLOCK GENMASK_ULL(28, 24) 4755 #define CPT_INST_QSEL_PF_FUNC GENMASK_ULL(23, 8) 4756 #define CPT_INST_QSEL_SLOT GENMASK_ULL(7, 0) 4757 4758 #define CPT_INST_CREDIT_TH GENMASK_ULL(53, 32) 4759 #define CPT_INST_CREDIT_BPID GENMASK_ULL(30, 22) 4760 #define CPT_INST_CREDIT_CNT GENMASK_ULL(21, 0) 4761 4762 static void nix_inline_ipsec_cfg(struct rvu *rvu, struct nix_inline_ipsec_cfg *req, 4763 int blkaddr) 4764 { 4765 u8 cpt_idx, cpt_blkaddr; 4766 u64 val; 4767 4768 cpt_idx = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 4769 if (req->enable) { 4770 val = 0; 4771 /* Enable context prefetching */ 4772 if (!is_rvu_otx2(rvu)) 4773 val |= BIT_ULL(51); 4774 4775 /* Set OPCODE and EGRP */ 4776 val |= FIELD_PREP(IPSEC_GEN_CFG_EGRP, req->gen_cfg.egrp); 4777 val |= FIELD_PREP(IPSEC_GEN_CFG_OPCODE, req->gen_cfg.opcode); 4778 val |= FIELD_PREP(IPSEC_GEN_CFG_PARAM1, req->gen_cfg.param1); 4779 val |= FIELD_PREP(IPSEC_GEN_CFG_PARAM2, req->gen_cfg.param2); 4780 4781 rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, val); 4782 4783 /* Set CPT queue for inline IPSec */ 4784 val = FIELD_PREP(CPT_INST_QSEL_SLOT, req->inst_qsel.cpt_slot); 4785 val |= FIELD_PREP(CPT_INST_QSEL_PF_FUNC, 4786 req->inst_qsel.cpt_pf_func); 4787 4788 if (!is_rvu_otx2(rvu)) { 4789 cpt_blkaddr = (cpt_idx == 0) ? BLKADDR_CPT0 : 4790 BLKADDR_CPT1; 4791 val |= FIELD_PREP(CPT_INST_QSEL_BLOCK, cpt_blkaddr); 4792 } 4793 4794 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx), 4795 val); 4796 4797 /* Set CPT credit */ 4798 val = rvu_read64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx)); 4799 if ((val & 0x3FFFFF) != 0x3FFFFF) 4800 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), 4801 0x3FFFFF - val); 4802 4803 val = FIELD_PREP(CPT_INST_CREDIT_CNT, req->cpt_credit); 4804 val |= FIELD_PREP(CPT_INST_CREDIT_BPID, req->bpid); 4805 val |= FIELD_PREP(CPT_INST_CREDIT_TH, req->credit_th); 4806 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), val); 4807 } else { 4808 rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, 0x0); 4809 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx), 4810 0x0); 4811 val = rvu_read64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx)); 4812 if ((val & 0x3FFFFF) != 0x3FFFFF) 4813 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), 4814 0x3FFFFF - val); 4815 } 4816 } 4817 4818 int rvu_mbox_handler_nix_inline_ipsec_cfg(struct rvu *rvu, 4819 struct nix_inline_ipsec_cfg *req, 4820 struct msg_rsp *rsp) 4821 { 4822 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) 4823 return 0; 4824 4825 nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX0); 4826 if (is_block_implemented(rvu->hw, BLKADDR_CPT1)) 4827 nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX1); 4828 4829 return 0; 4830 } 4831 4832 int rvu_mbox_handler_nix_read_inline_ipsec_cfg(struct rvu *rvu, 4833 struct msg_req *req, 4834 struct nix_inline_ipsec_cfg *rsp) 4835 4836 { 4837 u64 val; 4838 4839 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) 4840 return 0; 4841 4842 val = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_RX_IPSEC_GEN_CFG); 4843 rsp->gen_cfg.egrp = FIELD_GET(IPSEC_GEN_CFG_EGRP, val); 4844 rsp->gen_cfg.opcode = FIELD_GET(IPSEC_GEN_CFG_OPCODE, val); 4845 rsp->gen_cfg.param1 = FIELD_GET(IPSEC_GEN_CFG_PARAM1, val); 4846 rsp->gen_cfg.param2 = FIELD_GET(IPSEC_GEN_CFG_PARAM2, val); 4847 4848 val = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_RX_CPTX_CREDIT(0)); 4849 rsp->cpt_credit = FIELD_GET(CPT_INST_CREDIT_CNT, val); 4850 rsp->credit_th = FIELD_GET(CPT_INST_CREDIT_TH, val); 4851 rsp->bpid = FIELD_GET(CPT_INST_CREDIT_BPID, val); 4852 4853 return 0; 4854 } 4855 4856 int rvu_mbox_handler_nix_inline_ipsec_lf_cfg(struct rvu *rvu, 4857 struct nix_inline_ipsec_lf_cfg *req, 4858 struct msg_rsp *rsp) 4859 { 4860 int lf, blkaddr, err; 4861 u64 val; 4862 4863 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) 4864 return 0; 4865 4866 err = nix_get_nixlf(rvu, req->hdr.pcifunc, &lf, &blkaddr); 4867 if (err) 4868 return err; 4869 4870 if (req->enable) { 4871 /* Set TT, TAG_CONST, SA_POW2_SIZE and LENM1_MAX */ 4872 val = (u64)req->ipsec_cfg0.tt << 44 | 4873 (u64)req->ipsec_cfg0.tag_const << 20 | 4874 (u64)req->ipsec_cfg0.sa_pow2_size << 16 | 4875 req->ipsec_cfg0.lenm1_max; 4876 4877 if (blkaddr == BLKADDR_NIX1) 4878 val |= BIT_ULL(46); 4879 4880 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG0(lf), val); 4881 4882 /* Set SA_IDX_W and SA_IDX_MAX */ 4883 val = (u64)req->ipsec_cfg1.sa_idx_w << 32 | 4884 req->ipsec_cfg1.sa_idx_max; 4885 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(lf), val); 4886 4887 /* Set SA base address */ 4888 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(lf), 4889 req->sa_base_addr); 4890 } else { 4891 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG0(lf), 0x0); 4892 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(lf), 0x0); 4893 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(lf), 4894 0x0); 4895 } 4896 4897 return 0; 4898 } 4899 4900 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc) 4901 { 4902 bool from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK); 4903 4904 /* overwrite vf mac address with default_mac */ 4905 if (from_vf) 4906 ether_addr_copy(pfvf->mac_addr, pfvf->default_mac); 4907 } 4908 4909 /* NIX ingress policers or bandwidth profiles APIs */ 4910 static void nix_config_rx_pkt_policer_precolor(struct rvu *rvu, int blkaddr) 4911 { 4912 struct npc_lt_def_cfg defs, *ltdefs; 4913 4914 ltdefs = &defs; 4915 memcpy(ltdefs, rvu->kpu.lt_def, sizeof(struct npc_lt_def_cfg)); 4916 4917 /* Extract PCP and DEI fields from outer VLAN from byte offset 4918 * 2 from the start of LB_PTR (ie TAG). 4919 * VLAN0 is Outer VLAN and VLAN1 is Inner VLAN. Inner VLAN 4920 * fields are considered when 'Tunnel enable' is set in profile. 4921 */ 4922 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN0_PCP_DEI, 4923 (2UL << 12) | (ltdefs->ovlan.lid << 8) | 4924 (ltdefs->ovlan.ltype_match << 4) | 4925 ltdefs->ovlan.ltype_mask); 4926 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN1_PCP_DEI, 4927 (2UL << 12) | (ltdefs->ivlan.lid << 8) | 4928 (ltdefs->ivlan.ltype_match << 4) | 4929 ltdefs->ivlan.ltype_mask); 4930 4931 /* DSCP field in outer and tunneled IPv4 packets */ 4932 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4_DSCP, 4933 (1UL << 12) | (ltdefs->rx_oip4.lid << 8) | 4934 (ltdefs->rx_oip4.ltype_match << 4) | 4935 ltdefs->rx_oip4.ltype_mask); 4936 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4_DSCP, 4937 (1UL << 12) | (ltdefs->rx_iip4.lid << 8) | 4938 (ltdefs->rx_iip4.ltype_match << 4) | 4939 ltdefs->rx_iip4.ltype_mask); 4940 4941 /* DSCP field (traffic class) in outer and tunneled IPv6 packets */ 4942 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6_DSCP, 4943 (1UL << 11) | (ltdefs->rx_oip6.lid << 8) | 4944 (ltdefs->rx_oip6.ltype_match << 4) | 4945 ltdefs->rx_oip6.ltype_mask); 4946 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6_DSCP, 4947 (1UL << 11) | (ltdefs->rx_iip6.lid << 8) | 4948 (ltdefs->rx_iip6.ltype_match << 4) | 4949 ltdefs->rx_iip6.ltype_mask); 4950 } 4951 4952 static int nix_init_policer_context(struct rvu *rvu, struct nix_hw *nix_hw, 4953 int layer, int prof_idx) 4954 { 4955 struct nix_cn10k_aq_enq_req aq_req; 4956 int rc; 4957 4958 memset(&aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 4959 4960 aq_req.qidx = (prof_idx & 0x3FFF) | (layer << 14); 4961 aq_req.ctype = NIX_AQ_CTYPE_BANDPROF; 4962 aq_req.op = NIX_AQ_INSTOP_INIT; 4963 4964 /* Context is all zeros, submit to AQ */ 4965 rc = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 4966 (struct nix_aq_enq_req *)&aq_req, NULL); 4967 if (rc) 4968 dev_err(rvu->dev, "Failed to INIT bandwidth profile layer %d profile %d\n", 4969 layer, prof_idx); 4970 return rc; 4971 } 4972 4973 static int nix_setup_ipolicers(struct rvu *rvu, 4974 struct nix_hw *nix_hw, int blkaddr) 4975 { 4976 struct rvu_hwinfo *hw = rvu->hw; 4977 struct nix_ipolicer *ipolicer; 4978 int err, layer, prof_idx; 4979 u64 cfg; 4980 4981 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST); 4982 if (!(cfg & BIT_ULL(61))) { 4983 hw->cap.ipolicer = false; 4984 return 0; 4985 } 4986 4987 hw->cap.ipolicer = true; 4988 nix_hw->ipolicer = devm_kcalloc(rvu->dev, BAND_PROF_NUM_LAYERS, 4989 sizeof(*ipolicer), GFP_KERNEL); 4990 if (!nix_hw->ipolicer) 4991 return -ENOMEM; 4992 4993 cfg = rvu_read64(rvu, blkaddr, NIX_AF_PL_CONST); 4994 4995 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 4996 ipolicer = &nix_hw->ipolicer[layer]; 4997 switch (layer) { 4998 case BAND_PROF_LEAF_LAYER: 4999 ipolicer->band_prof.max = cfg & 0XFFFF; 5000 break; 5001 case BAND_PROF_MID_LAYER: 5002 ipolicer->band_prof.max = (cfg >> 16) & 0XFFFF; 5003 break; 5004 case BAND_PROF_TOP_LAYER: 5005 ipolicer->band_prof.max = (cfg >> 32) & 0XFFFF; 5006 break; 5007 } 5008 5009 if (!ipolicer->band_prof.max) 5010 continue; 5011 5012 err = rvu_alloc_bitmap(&ipolicer->band_prof); 5013 if (err) 5014 return err; 5015 5016 ipolicer->pfvf_map = devm_kcalloc(rvu->dev, 5017 ipolicer->band_prof.max, 5018 sizeof(u16), GFP_KERNEL); 5019 if (!ipolicer->pfvf_map) 5020 return -ENOMEM; 5021 5022 ipolicer->match_id = devm_kcalloc(rvu->dev, 5023 ipolicer->band_prof.max, 5024 sizeof(u16), GFP_KERNEL); 5025 if (!ipolicer->match_id) 5026 return -ENOMEM; 5027 5028 for (prof_idx = 0; 5029 prof_idx < ipolicer->band_prof.max; prof_idx++) { 5030 /* Set AF as current owner for INIT ops to succeed */ 5031 ipolicer->pfvf_map[prof_idx] = 0x00; 5032 5033 /* There is no enable bit in the profile context, 5034 * so no context disable. So let's INIT them here 5035 * so that PF/VF later on have to just do WRITE to 5036 * setup policer rates and config. 5037 */ 5038 err = nix_init_policer_context(rvu, nix_hw, 5039 layer, prof_idx); 5040 if (err) 5041 return err; 5042 } 5043 5044 /* Allocate memory for maintaining ref_counts for MID level 5045 * profiles, this will be needed for leaf layer profiles' 5046 * aggregation. 5047 */ 5048 if (layer != BAND_PROF_MID_LAYER) 5049 continue; 5050 5051 ipolicer->ref_count = devm_kcalloc(rvu->dev, 5052 ipolicer->band_prof.max, 5053 sizeof(u16), GFP_KERNEL); 5054 if (!ipolicer->ref_count) 5055 return -ENOMEM; 5056 } 5057 5058 /* Set policer timeunit to 2us ie (19 + 1) * 100 nsec = 2us */ 5059 rvu_write64(rvu, blkaddr, NIX_AF_PL_TS, 19); 5060 5061 nix_config_rx_pkt_policer_precolor(rvu, blkaddr); 5062 5063 return 0; 5064 } 5065 5066 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw) 5067 { 5068 struct nix_ipolicer *ipolicer; 5069 int layer; 5070 5071 if (!rvu->hw->cap.ipolicer) 5072 return; 5073 5074 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5075 ipolicer = &nix_hw->ipolicer[layer]; 5076 5077 if (!ipolicer->band_prof.max) 5078 continue; 5079 5080 kfree(ipolicer->band_prof.bmap); 5081 } 5082 } 5083 5084 static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req, 5085 struct nix_hw *nix_hw, u16 pcifunc) 5086 { 5087 struct nix_ipolicer *ipolicer; 5088 int layer, hi_layer, prof_idx; 5089 5090 /* Bits [15:14] in profile index represent layer */ 5091 layer = (req->qidx >> 14) & 0x03; 5092 prof_idx = req->qidx & 0x3FFF; 5093 5094 ipolicer = &nix_hw->ipolicer[layer]; 5095 if (prof_idx >= ipolicer->band_prof.max) 5096 return -EINVAL; 5097 5098 /* Check if the profile is allocated to the requesting PCIFUNC or not 5099 * with the exception of AF. AF is allowed to read and update contexts. 5100 */ 5101 if (pcifunc && ipolicer->pfvf_map[prof_idx] != pcifunc) 5102 return -EINVAL; 5103 5104 /* If this profile is linked to higher layer profile then check 5105 * if that profile is also allocated to the requesting PCIFUNC 5106 * or not. 5107 */ 5108 if (!req->prof.hl_en) 5109 return 0; 5110 5111 /* Leaf layer profile can link only to mid layer and 5112 * mid layer to top layer. 5113 */ 5114 if (layer == BAND_PROF_LEAF_LAYER) 5115 hi_layer = BAND_PROF_MID_LAYER; 5116 else if (layer == BAND_PROF_MID_LAYER) 5117 hi_layer = BAND_PROF_TOP_LAYER; 5118 else 5119 return -EINVAL; 5120 5121 ipolicer = &nix_hw->ipolicer[hi_layer]; 5122 prof_idx = req->prof.band_prof_id; 5123 if (prof_idx >= ipolicer->band_prof.max || 5124 ipolicer->pfvf_map[prof_idx] != pcifunc) 5125 return -EINVAL; 5126 5127 return 0; 5128 } 5129 5130 int rvu_mbox_handler_nix_bandprof_alloc(struct rvu *rvu, 5131 struct nix_bandprof_alloc_req *req, 5132 struct nix_bandprof_alloc_rsp *rsp) 5133 { 5134 int blkaddr, layer, prof, idx, err; 5135 u16 pcifunc = req->hdr.pcifunc; 5136 struct nix_ipolicer *ipolicer; 5137 struct nix_hw *nix_hw; 5138 5139 if (!rvu->hw->cap.ipolicer) 5140 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5141 5142 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5143 if (err) 5144 return err; 5145 5146 mutex_lock(&rvu->rsrc_lock); 5147 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5148 if (layer == BAND_PROF_INVAL_LAYER) 5149 continue; 5150 if (!req->prof_count[layer]) 5151 continue; 5152 5153 ipolicer = &nix_hw->ipolicer[layer]; 5154 for (idx = 0; idx < req->prof_count[layer]; idx++) { 5155 /* Allocate a max of 'MAX_BANDPROF_PER_PFFUNC' profiles */ 5156 if (idx == MAX_BANDPROF_PER_PFFUNC) 5157 break; 5158 5159 prof = rvu_alloc_rsrc(&ipolicer->band_prof); 5160 if (prof < 0) 5161 break; 5162 rsp->prof_count[layer]++; 5163 rsp->prof_idx[layer][idx] = prof; 5164 ipolicer->pfvf_map[prof] = pcifunc; 5165 } 5166 } 5167 mutex_unlock(&rvu->rsrc_lock); 5168 return 0; 5169 } 5170 5171 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc) 5172 { 5173 int blkaddr, layer, prof_idx, err; 5174 struct nix_ipolicer *ipolicer; 5175 struct nix_hw *nix_hw; 5176 5177 if (!rvu->hw->cap.ipolicer) 5178 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5179 5180 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5181 if (err) 5182 return err; 5183 5184 mutex_lock(&rvu->rsrc_lock); 5185 /* Free all the profiles allocated to the PCIFUNC */ 5186 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5187 if (layer == BAND_PROF_INVAL_LAYER) 5188 continue; 5189 ipolicer = &nix_hw->ipolicer[layer]; 5190 5191 for (prof_idx = 0; prof_idx < ipolicer->band_prof.max; prof_idx++) { 5192 if (ipolicer->pfvf_map[prof_idx] != pcifunc) 5193 continue; 5194 5195 /* Clear ratelimit aggregation, if any */ 5196 if (layer == BAND_PROF_LEAF_LAYER && 5197 ipolicer->match_id[prof_idx]) 5198 nix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx); 5199 5200 ipolicer->pfvf_map[prof_idx] = 0x00; 5201 ipolicer->match_id[prof_idx] = 0; 5202 rvu_free_rsrc(&ipolicer->band_prof, prof_idx); 5203 } 5204 } 5205 mutex_unlock(&rvu->rsrc_lock); 5206 return 0; 5207 } 5208 5209 int rvu_mbox_handler_nix_bandprof_free(struct rvu *rvu, 5210 struct nix_bandprof_free_req *req, 5211 struct msg_rsp *rsp) 5212 { 5213 int blkaddr, layer, prof_idx, idx, err; 5214 u16 pcifunc = req->hdr.pcifunc; 5215 struct nix_ipolicer *ipolicer; 5216 struct nix_hw *nix_hw; 5217 5218 if (req->free_all) 5219 return nix_free_all_bandprof(rvu, pcifunc); 5220 5221 if (!rvu->hw->cap.ipolicer) 5222 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5223 5224 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5225 if (err) 5226 return err; 5227 5228 mutex_lock(&rvu->rsrc_lock); 5229 /* Free the requested profile indices */ 5230 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5231 if (layer == BAND_PROF_INVAL_LAYER) 5232 continue; 5233 if (!req->prof_count[layer]) 5234 continue; 5235 5236 ipolicer = &nix_hw->ipolicer[layer]; 5237 for (idx = 0; idx < req->prof_count[layer]; idx++) { 5238 prof_idx = req->prof_idx[layer][idx]; 5239 if (prof_idx >= ipolicer->band_prof.max || 5240 ipolicer->pfvf_map[prof_idx] != pcifunc) 5241 continue; 5242 5243 /* Clear ratelimit aggregation, if any */ 5244 if (layer == BAND_PROF_LEAF_LAYER && 5245 ipolicer->match_id[prof_idx]) 5246 nix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx); 5247 5248 ipolicer->pfvf_map[prof_idx] = 0x00; 5249 ipolicer->match_id[prof_idx] = 0; 5250 rvu_free_rsrc(&ipolicer->band_prof, prof_idx); 5251 if (idx == MAX_BANDPROF_PER_PFFUNC) 5252 break; 5253 } 5254 } 5255 mutex_unlock(&rvu->rsrc_lock); 5256 return 0; 5257 } 5258 5259 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 5260 struct nix_cn10k_aq_enq_req *aq_req, 5261 struct nix_cn10k_aq_enq_rsp *aq_rsp, 5262 u16 pcifunc, u8 ctype, u32 qidx) 5263 { 5264 memset(aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5265 aq_req->hdr.pcifunc = pcifunc; 5266 aq_req->ctype = ctype; 5267 aq_req->op = NIX_AQ_INSTOP_READ; 5268 aq_req->qidx = qidx; 5269 5270 return rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5271 (struct nix_aq_enq_req *)aq_req, 5272 (struct nix_aq_enq_rsp *)aq_rsp); 5273 } 5274 5275 static int nix_ipolicer_map_leaf_midprofs(struct rvu *rvu, 5276 struct nix_hw *nix_hw, 5277 struct nix_cn10k_aq_enq_req *aq_req, 5278 struct nix_cn10k_aq_enq_rsp *aq_rsp, 5279 u32 leaf_prof, u16 mid_prof) 5280 { 5281 memset(aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5282 aq_req->hdr.pcifunc = 0x00; 5283 aq_req->ctype = NIX_AQ_CTYPE_BANDPROF; 5284 aq_req->op = NIX_AQ_INSTOP_WRITE; 5285 aq_req->qidx = leaf_prof; 5286 5287 aq_req->prof.band_prof_id = mid_prof; 5288 aq_req->prof_mask.band_prof_id = GENMASK(6, 0); 5289 aq_req->prof.hl_en = 1; 5290 aq_req->prof_mask.hl_en = 1; 5291 5292 return rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5293 (struct nix_aq_enq_req *)aq_req, 5294 (struct nix_aq_enq_rsp *)aq_rsp); 5295 } 5296 5297 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 5298 u16 rq_idx, u16 match_id) 5299 { 5300 int leaf_prof, mid_prof, leaf_match; 5301 struct nix_cn10k_aq_enq_req aq_req; 5302 struct nix_cn10k_aq_enq_rsp aq_rsp; 5303 struct nix_ipolicer *ipolicer; 5304 struct nix_hw *nix_hw; 5305 int blkaddr, idx, rc; 5306 5307 if (!rvu->hw->cap.ipolicer) 5308 return 0; 5309 5310 rc = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5311 if (rc) 5312 return rc; 5313 5314 /* Fetch the RQ's context to see if policing is enabled */ 5315 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, pcifunc, 5316 NIX_AQ_CTYPE_RQ, rq_idx); 5317 if (rc) { 5318 dev_err(rvu->dev, 5319 "%s: Failed to fetch RQ%d context of PFFUNC 0x%x\n", 5320 __func__, rq_idx, pcifunc); 5321 return rc; 5322 } 5323 5324 if (!aq_rsp.rq.policer_ena) 5325 return 0; 5326 5327 /* Get the bandwidth profile ID mapped to this RQ */ 5328 leaf_prof = aq_rsp.rq.band_prof_id; 5329 5330 ipolicer = &nix_hw->ipolicer[BAND_PROF_LEAF_LAYER]; 5331 ipolicer->match_id[leaf_prof] = match_id; 5332 5333 /* Check if any other leaf profile is marked with same match_id */ 5334 for (idx = 0; idx < ipolicer->band_prof.max; idx++) { 5335 if (idx == leaf_prof) 5336 continue; 5337 if (ipolicer->match_id[idx] != match_id) 5338 continue; 5339 5340 leaf_match = idx; 5341 break; 5342 } 5343 5344 if (idx == ipolicer->band_prof.max) 5345 return 0; 5346 5347 /* Fetch the matching profile's context to check if it's already 5348 * mapped to a mid level profile. 5349 */ 5350 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5351 NIX_AQ_CTYPE_BANDPROF, leaf_match); 5352 if (rc) { 5353 dev_err(rvu->dev, 5354 "%s: Failed to fetch context of leaf profile %d\n", 5355 __func__, leaf_match); 5356 return rc; 5357 } 5358 5359 ipolicer = &nix_hw->ipolicer[BAND_PROF_MID_LAYER]; 5360 if (aq_rsp.prof.hl_en) { 5361 /* Get Mid layer prof index and map leaf_prof index 5362 * also such that flows that are being steered 5363 * to different RQs and marked with same match_id 5364 * are rate limited in a aggregate fashion 5365 */ 5366 mid_prof = aq_rsp.prof.band_prof_id; 5367 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5368 &aq_req, &aq_rsp, 5369 leaf_prof, mid_prof); 5370 if (rc) { 5371 dev_err(rvu->dev, 5372 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5373 __func__, leaf_prof, mid_prof); 5374 goto exit; 5375 } 5376 5377 mutex_lock(&rvu->rsrc_lock); 5378 ipolicer->ref_count[mid_prof]++; 5379 mutex_unlock(&rvu->rsrc_lock); 5380 goto exit; 5381 } 5382 5383 /* Allocate a mid layer profile and 5384 * map both 'leaf_prof' and 'leaf_match' profiles to it. 5385 */ 5386 mutex_lock(&rvu->rsrc_lock); 5387 mid_prof = rvu_alloc_rsrc(&ipolicer->band_prof); 5388 if (mid_prof < 0) { 5389 dev_err(rvu->dev, 5390 "%s: Unable to allocate mid layer profile\n", __func__); 5391 mutex_unlock(&rvu->rsrc_lock); 5392 goto exit; 5393 } 5394 mutex_unlock(&rvu->rsrc_lock); 5395 ipolicer->pfvf_map[mid_prof] = 0x00; 5396 ipolicer->ref_count[mid_prof] = 0; 5397 5398 /* Initialize mid layer profile same as 'leaf_prof' */ 5399 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5400 NIX_AQ_CTYPE_BANDPROF, leaf_prof); 5401 if (rc) { 5402 dev_err(rvu->dev, 5403 "%s: Failed to fetch context of leaf profile %d\n", 5404 __func__, leaf_prof); 5405 goto exit; 5406 } 5407 5408 memset(&aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5409 aq_req.hdr.pcifunc = 0x00; 5410 aq_req.qidx = (mid_prof & 0x3FFF) | (BAND_PROF_MID_LAYER << 14); 5411 aq_req.ctype = NIX_AQ_CTYPE_BANDPROF; 5412 aq_req.op = NIX_AQ_INSTOP_WRITE; 5413 memcpy(&aq_req.prof, &aq_rsp.prof, sizeof(struct nix_bandprof_s)); 5414 memset((char *)&aq_req.prof_mask, 0xff, sizeof(struct nix_bandprof_s)); 5415 /* Clear higher layer enable bit in the mid profile, just in case */ 5416 aq_req.prof.hl_en = 0; 5417 aq_req.prof_mask.hl_en = 1; 5418 5419 rc = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5420 (struct nix_aq_enq_req *)&aq_req, NULL); 5421 if (rc) { 5422 dev_err(rvu->dev, 5423 "%s: Failed to INIT context of mid layer profile %d\n", 5424 __func__, mid_prof); 5425 goto exit; 5426 } 5427 5428 /* Map both leaf profiles to this mid layer profile */ 5429 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5430 &aq_req, &aq_rsp, 5431 leaf_prof, mid_prof); 5432 if (rc) { 5433 dev_err(rvu->dev, 5434 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5435 __func__, leaf_prof, mid_prof); 5436 goto exit; 5437 } 5438 5439 mutex_lock(&rvu->rsrc_lock); 5440 ipolicer->ref_count[mid_prof]++; 5441 mutex_unlock(&rvu->rsrc_lock); 5442 5443 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5444 &aq_req, &aq_rsp, 5445 leaf_match, mid_prof); 5446 if (rc) { 5447 dev_err(rvu->dev, 5448 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5449 __func__, leaf_match, mid_prof); 5450 ipolicer->ref_count[mid_prof]--; 5451 goto exit; 5452 } 5453 5454 mutex_lock(&rvu->rsrc_lock); 5455 ipolicer->ref_count[mid_prof]++; 5456 mutex_unlock(&rvu->rsrc_lock); 5457 5458 exit: 5459 return rc; 5460 } 5461 5462 /* Called with mutex rsrc_lock */ 5463 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw, 5464 u32 leaf_prof) 5465 { 5466 struct nix_cn10k_aq_enq_req aq_req; 5467 struct nix_cn10k_aq_enq_rsp aq_rsp; 5468 struct nix_ipolicer *ipolicer; 5469 u16 mid_prof; 5470 int rc; 5471 5472 mutex_unlock(&rvu->rsrc_lock); 5473 5474 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5475 NIX_AQ_CTYPE_BANDPROF, leaf_prof); 5476 5477 mutex_lock(&rvu->rsrc_lock); 5478 if (rc) { 5479 dev_err(rvu->dev, 5480 "%s: Failed to fetch context of leaf profile %d\n", 5481 __func__, leaf_prof); 5482 return; 5483 } 5484 5485 if (!aq_rsp.prof.hl_en) 5486 return; 5487 5488 mid_prof = aq_rsp.prof.band_prof_id; 5489 ipolicer = &nix_hw->ipolicer[BAND_PROF_MID_LAYER]; 5490 ipolicer->ref_count[mid_prof]--; 5491 /* If ref_count is zero, free mid layer profile */ 5492 if (!ipolicer->ref_count[mid_prof]) { 5493 ipolicer->pfvf_map[mid_prof] = 0x00; 5494 rvu_free_rsrc(&ipolicer->band_prof, mid_prof); 5495 } 5496 } 5497 5498 int rvu_mbox_handler_nix_bandprof_get_hwinfo(struct rvu *rvu, struct msg_req *req, 5499 struct nix_bandprof_get_hwinfo_rsp *rsp) 5500 { 5501 struct nix_ipolicer *ipolicer; 5502 int blkaddr, layer, err; 5503 struct nix_hw *nix_hw; 5504 u64 tu; 5505 5506 if (!rvu->hw->cap.ipolicer) 5507 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5508 5509 err = nix_get_struct_ptrs(rvu, req->hdr.pcifunc, &nix_hw, &blkaddr); 5510 if (err) 5511 return err; 5512 5513 /* Return number of bandwidth profiles free at each layer */ 5514 mutex_lock(&rvu->rsrc_lock); 5515 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5516 if (layer == BAND_PROF_INVAL_LAYER) 5517 continue; 5518 5519 ipolicer = &nix_hw->ipolicer[layer]; 5520 rsp->prof_count[layer] = rvu_rsrc_free_count(&ipolicer->band_prof); 5521 } 5522 mutex_unlock(&rvu->rsrc_lock); 5523 5524 /* Set the policer timeunit in nanosec */ 5525 tu = rvu_read64(rvu, blkaddr, NIX_AF_PL_TS) & GENMASK_ULL(9, 0); 5526 rsp->policer_timeunit = (tu + 1) * 100; 5527 5528 return 0; 5529 } 5530