1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/pci.h> 10 11 #include "rvu_struct.h" 12 #include "rvu_reg.h" 13 #include "rvu.h" 14 #include "npc.h" 15 #include "cgx.h" 16 #include "lmac_common.h" 17 18 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc); 19 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, 20 int type, int chan_id); 21 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc, 22 int type, bool add); 23 static int nix_setup_ipolicers(struct rvu *rvu, 24 struct nix_hw *nix_hw, int blkaddr); 25 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw); 26 static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req, 27 struct nix_hw *nix_hw, u16 pcifunc); 28 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc); 29 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw, 30 u32 leaf_prof); 31 static const char *nix_get_ctx_name(int ctype); 32 33 enum mc_tbl_sz { 34 MC_TBL_SZ_256, 35 MC_TBL_SZ_512, 36 MC_TBL_SZ_1K, 37 MC_TBL_SZ_2K, 38 MC_TBL_SZ_4K, 39 MC_TBL_SZ_8K, 40 MC_TBL_SZ_16K, 41 MC_TBL_SZ_32K, 42 MC_TBL_SZ_64K, 43 }; 44 45 enum mc_buf_cnt { 46 MC_BUF_CNT_8, 47 MC_BUF_CNT_16, 48 MC_BUF_CNT_32, 49 MC_BUF_CNT_64, 50 MC_BUF_CNT_128, 51 MC_BUF_CNT_256, 52 MC_BUF_CNT_512, 53 MC_BUF_CNT_1024, 54 MC_BUF_CNT_2048, 55 }; 56 57 enum nix_makr_fmt_indexes { 58 NIX_MARK_CFG_IP_DSCP_RED, 59 NIX_MARK_CFG_IP_DSCP_YELLOW, 60 NIX_MARK_CFG_IP_DSCP_YELLOW_RED, 61 NIX_MARK_CFG_IP_ECN_RED, 62 NIX_MARK_CFG_IP_ECN_YELLOW, 63 NIX_MARK_CFG_IP_ECN_YELLOW_RED, 64 NIX_MARK_CFG_VLAN_DEI_RED, 65 NIX_MARK_CFG_VLAN_DEI_YELLOW, 66 NIX_MARK_CFG_VLAN_DEI_YELLOW_RED, 67 NIX_MARK_CFG_MAX, 68 }; 69 70 /* For now considering MC resources needed for broadcast 71 * pkt replication only. i.e 256 HWVFs + 12 PFs. 72 */ 73 #define MC_TBL_SIZE MC_TBL_SZ_512 74 #define MC_BUF_CNT MC_BUF_CNT_128 75 76 struct mce { 77 struct hlist_node node; 78 u16 pcifunc; 79 }; 80 81 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr) 82 { 83 int i = 0; 84 85 /*If blkaddr is 0, return the first nix block address*/ 86 if (blkaddr == 0) 87 return rvu->nix_blkaddr[blkaddr]; 88 89 while (i + 1 < MAX_NIX_BLKS) { 90 if (rvu->nix_blkaddr[i] == blkaddr) 91 return rvu->nix_blkaddr[i + 1]; 92 i++; 93 } 94 95 return 0; 96 } 97 98 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc) 99 { 100 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 101 int blkaddr; 102 103 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 104 if (!pfvf->nixlf || blkaddr < 0) 105 return false; 106 return true; 107 } 108 109 int rvu_get_nixlf_count(struct rvu *rvu) 110 { 111 int blkaddr = 0, max = 0; 112 struct rvu_block *block; 113 114 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 115 while (blkaddr) { 116 block = &rvu->hw->block[blkaddr]; 117 max += block->lf.max; 118 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 119 } 120 return max; 121 } 122 123 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr) 124 { 125 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 126 struct rvu_hwinfo *hw = rvu->hw; 127 int blkaddr; 128 129 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 130 if (!pfvf->nixlf || blkaddr < 0) 131 return NIX_AF_ERR_AF_LF_INVALID; 132 133 *nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 134 if (*nixlf < 0) 135 return NIX_AF_ERR_AF_LF_INVALID; 136 137 if (nix_blkaddr) 138 *nix_blkaddr = blkaddr; 139 140 return 0; 141 } 142 143 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 144 struct nix_hw **nix_hw, int *blkaddr) 145 { 146 struct rvu_pfvf *pfvf; 147 148 pfvf = rvu_get_pfvf(rvu, pcifunc); 149 *blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 150 if (!pfvf->nixlf || *blkaddr < 0) 151 return NIX_AF_ERR_AF_LF_INVALID; 152 153 *nix_hw = get_nix_hw(rvu->hw, *blkaddr); 154 if (!*nix_hw) 155 return NIX_AF_ERR_INVALID_NIXBLK; 156 return 0; 157 } 158 159 static void nix_mce_list_init(struct nix_mce_list *list, int max) 160 { 161 INIT_HLIST_HEAD(&list->head); 162 list->count = 0; 163 list->max = max; 164 } 165 166 static u16 nix_alloc_mce_list(struct nix_mcast *mcast, int count) 167 { 168 int idx; 169 170 if (!mcast) 171 return 0; 172 173 idx = mcast->next_free_mce; 174 mcast->next_free_mce += count; 175 return idx; 176 } 177 178 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr) 179 { 180 int nix_blkaddr = 0, i = 0; 181 struct rvu *rvu = hw->rvu; 182 183 nix_blkaddr = rvu_get_next_nix_blkaddr(rvu, nix_blkaddr); 184 while (nix_blkaddr) { 185 if (blkaddr == nix_blkaddr && hw->nix) 186 return &hw->nix[i]; 187 nix_blkaddr = rvu_get_next_nix_blkaddr(rvu, nix_blkaddr); 188 i++; 189 } 190 return NULL; 191 } 192 193 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu) 194 { 195 dwrr_mtu &= 0x1FULL; 196 197 /* MTU used for DWRR calculation is in power of 2 up until 64K bytes. 198 * Value of 4 is reserved for MTU value of 9728 bytes. 199 * Value of 5 is reserved for MTU value of 10240 bytes. 200 */ 201 switch (dwrr_mtu) { 202 case 4: 203 return 9728; 204 case 5: 205 return 10240; 206 default: 207 return BIT_ULL(dwrr_mtu); 208 } 209 210 return 0; 211 } 212 213 u32 convert_bytes_to_dwrr_mtu(u32 bytes) 214 { 215 /* MTU used for DWRR calculation is in power of 2 up until 64K bytes. 216 * Value of 4 is reserved for MTU value of 9728 bytes. 217 * Value of 5 is reserved for MTU value of 10240 bytes. 218 */ 219 if (bytes > BIT_ULL(16)) 220 return 0; 221 222 switch (bytes) { 223 case 9728: 224 return 4; 225 case 10240: 226 return 5; 227 default: 228 return ilog2(bytes); 229 } 230 231 return 0; 232 } 233 234 static void nix_rx_sync(struct rvu *rvu, int blkaddr) 235 { 236 int err; 237 238 /* Sync all in flight RX packets to LLC/DRAM */ 239 rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); 240 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true); 241 if (err) 242 dev_err(rvu->dev, "SYNC1: NIX RX software sync failed\n"); 243 244 /* SW_SYNC ensures all existing transactions are finished and pkts 245 * are written to LLC/DRAM, queues should be teared down after 246 * successful SW_SYNC. Due to a HW errata, in some rare scenarios 247 * an existing transaction might end after SW_SYNC operation. To 248 * ensure operation is fully done, do the SW_SYNC twice. 249 */ 250 rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); 251 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true); 252 if (err) 253 dev_err(rvu->dev, "SYNC2: NIX RX software sync failed\n"); 254 } 255 256 static bool is_valid_txschq(struct rvu *rvu, int blkaddr, 257 int lvl, u16 pcifunc, u16 schq) 258 { 259 struct rvu_hwinfo *hw = rvu->hw; 260 struct nix_txsch *txsch; 261 struct nix_hw *nix_hw; 262 u16 map_func; 263 264 nix_hw = get_nix_hw(rvu->hw, blkaddr); 265 if (!nix_hw) 266 return false; 267 268 txsch = &nix_hw->txsch[lvl]; 269 /* Check out of bounds */ 270 if (schq >= txsch->schq.max) 271 return false; 272 273 mutex_lock(&rvu->rsrc_lock); 274 map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]); 275 mutex_unlock(&rvu->rsrc_lock); 276 277 /* TLs aggegating traffic are shared across PF and VFs */ 278 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 279 if (rvu_get_pf(map_func) != rvu_get_pf(pcifunc)) 280 return false; 281 else 282 return true; 283 } 284 285 if (map_func != pcifunc) 286 return false; 287 288 return true; 289 } 290 291 static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf, 292 struct nix_lf_alloc_rsp *rsp, bool loop) 293 { 294 struct rvu_pfvf *parent_pf, *pfvf = rvu_get_pfvf(rvu, pcifunc); 295 u16 req_chan_base, req_chan_end, req_chan_cnt; 296 struct rvu_hwinfo *hw = rvu->hw; 297 struct sdp_node_info *sdp_info; 298 int pkind, pf, vf, lbkid, vfid; 299 struct mac_ops *mac_ops; 300 u8 cgx_id, lmac_id; 301 bool from_vf; 302 int err; 303 304 pf = rvu_get_pf(pcifunc); 305 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK && 306 type != NIX_INTF_TYPE_SDP) 307 return 0; 308 309 switch (type) { 310 case NIX_INTF_TYPE_CGX: 311 pfvf->cgx_lmac = rvu->pf2cgxlmac_map[pf]; 312 rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id); 313 314 pkind = rvu_npc_get_pkind(rvu, pf); 315 if (pkind < 0) { 316 dev_err(rvu->dev, 317 "PF_Func 0x%x: Invalid pkind\n", pcifunc); 318 return -EINVAL; 319 } 320 pfvf->rx_chan_base = rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0); 321 pfvf->tx_chan_base = pfvf->rx_chan_base; 322 pfvf->rx_chan_cnt = 1; 323 pfvf->tx_chan_cnt = 1; 324 rsp->tx_link = cgx_id * hw->lmac_per_cgx + lmac_id; 325 326 cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, pkind); 327 rvu_npc_set_pkind(rvu, pkind, pfvf); 328 329 mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu)); 330 331 /* By default we enable pause frames */ 332 if ((pcifunc & RVU_PFVF_FUNC_MASK) == 0) 333 mac_ops->mac_enadis_pause_frm(rvu_cgx_pdata(cgx_id, 334 rvu), 335 lmac_id, true, true); 336 break; 337 case NIX_INTF_TYPE_LBK: 338 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 339 340 /* If NIX1 block is present on the silicon then NIXes are 341 * assigned alternatively for lbk interfaces. NIX0 should 342 * send packets on lbk link 1 channels and NIX1 should send 343 * on lbk link 0 channels for the communication between 344 * NIX0 and NIX1. 345 */ 346 lbkid = 0; 347 if (rvu->hw->lbk_links > 1) 348 lbkid = vf & 0x1 ? 0 : 1; 349 350 /* By default NIX0 is configured to send packet on lbk link 1 351 * (which corresponds to LBK1), same packet will receive on 352 * NIX1 over lbk link 0. If NIX1 sends packet on lbk link 0 353 * (which corresponds to LBK2) packet will receive on NIX0 lbk 354 * link 1. 355 * But if lbk links for NIX0 and NIX1 are negated, i.e NIX0 356 * transmits and receives on lbk link 0, whick corresponds 357 * to LBK1 block, back to back connectivity between NIX and 358 * LBK can be achieved (which is similar to 96xx) 359 * 360 * RX TX 361 * NIX0 lbk link 1 (LBK2) 1 (LBK1) 362 * NIX0 lbk link 0 (LBK0) 0 (LBK0) 363 * NIX1 lbk link 0 (LBK1) 0 (LBK2) 364 * NIX1 lbk link 1 (LBK3) 1 (LBK3) 365 */ 366 if (loop) 367 lbkid = !lbkid; 368 369 /* Note that AF's VFs work in pairs and talk over consecutive 370 * loopback channels.Therefore if odd number of AF VFs are 371 * enabled then the last VF remains with no pair. 372 */ 373 pfvf->rx_chan_base = rvu_nix_chan_lbk(rvu, lbkid, vf); 374 pfvf->tx_chan_base = vf & 0x1 ? 375 rvu_nix_chan_lbk(rvu, lbkid, vf - 1) : 376 rvu_nix_chan_lbk(rvu, lbkid, vf + 1); 377 pfvf->rx_chan_cnt = 1; 378 pfvf->tx_chan_cnt = 1; 379 rsp->tx_link = hw->cgx_links + lbkid; 380 pfvf->lbkid = lbkid; 381 rvu_npc_set_pkind(rvu, NPC_RX_LBK_PKIND, pfvf); 382 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 383 pfvf->rx_chan_base, 384 pfvf->rx_chan_cnt); 385 386 break; 387 case NIX_INTF_TYPE_SDP: 388 from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK); 389 parent_pf = &rvu->pf[rvu_get_pf(pcifunc)]; 390 sdp_info = parent_pf->sdp_info; 391 if (!sdp_info) { 392 dev_err(rvu->dev, "Invalid sdp_info pointer\n"); 393 return -EINVAL; 394 } 395 if (from_vf) { 396 req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn + 397 sdp_info->num_pf_rings; 398 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 399 for (vfid = 0; vfid < vf; vfid++) 400 req_chan_base += sdp_info->vf_rings[vfid]; 401 req_chan_cnt = sdp_info->vf_rings[vf]; 402 req_chan_end = req_chan_base + req_chan_cnt - 1; 403 if (req_chan_base < rvu_nix_chan_sdp(rvu, 0) || 404 req_chan_end > rvu_nix_chan_sdp(rvu, 255)) { 405 dev_err(rvu->dev, 406 "PF_Func 0x%x: Invalid channel base and count\n", 407 pcifunc); 408 return -EINVAL; 409 } 410 } else { 411 req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn; 412 req_chan_cnt = sdp_info->num_pf_rings; 413 } 414 415 pfvf->rx_chan_base = req_chan_base; 416 pfvf->rx_chan_cnt = req_chan_cnt; 417 pfvf->tx_chan_base = pfvf->rx_chan_base; 418 pfvf->tx_chan_cnt = pfvf->rx_chan_cnt; 419 420 rsp->tx_link = hw->cgx_links + hw->lbk_links; 421 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 422 pfvf->rx_chan_base, 423 pfvf->rx_chan_cnt); 424 break; 425 } 426 427 /* Add a UCAST forwarding rule in MCAM with this NIXLF attached 428 * RVU PF/VF's MAC address. 429 */ 430 rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, 431 pfvf->rx_chan_base, pfvf->mac_addr); 432 433 /* Add this PF_FUNC to bcast pkt replication list */ 434 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, true); 435 if (err) { 436 dev_err(rvu->dev, 437 "Bcast list, failed to enable PF_FUNC 0x%x\n", 438 pcifunc); 439 return err; 440 } 441 /* Install MCAM rule matching Ethernet broadcast mac address */ 442 rvu_npc_install_bcast_match_entry(rvu, pcifunc, 443 nixlf, pfvf->rx_chan_base); 444 445 pfvf->maxlen = NIC_HW_MIN_FRS; 446 pfvf->minlen = NIC_HW_MIN_FRS; 447 448 return 0; 449 } 450 451 static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf) 452 { 453 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 454 int err; 455 456 pfvf->maxlen = 0; 457 pfvf->minlen = 0; 458 459 /* Remove this PF_FUNC from bcast pkt replication list */ 460 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, false); 461 if (err) { 462 dev_err(rvu->dev, 463 "Bcast list, failed to disable PF_FUNC 0x%x\n", 464 pcifunc); 465 } 466 467 /* Free and disable any MCAM entries used by this NIX LF */ 468 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 469 470 /* Disable DMAC filters used */ 471 rvu_cgx_disable_dmac_entries(rvu, pcifunc); 472 } 473 474 int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu, 475 struct nix_bp_cfg_req *req, 476 struct msg_rsp *rsp) 477 { 478 u16 pcifunc = req->hdr.pcifunc; 479 struct rvu_pfvf *pfvf; 480 int blkaddr, pf, type; 481 u16 chan_base, chan; 482 u64 cfg; 483 484 pf = rvu_get_pf(pcifunc); 485 type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 486 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK) 487 return 0; 488 489 pfvf = rvu_get_pfvf(rvu, pcifunc); 490 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 491 492 chan_base = pfvf->rx_chan_base + req->chan_base; 493 for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) { 494 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan)); 495 rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan), 496 cfg & ~BIT_ULL(16)); 497 } 498 return 0; 499 } 500 501 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, 502 int type, int chan_id) 503 { 504 int bpid, blkaddr, lmac_chan_cnt, sdp_chan_cnt; 505 u16 cgx_bpid_cnt, lbk_bpid_cnt, sdp_bpid_cnt; 506 struct rvu_hwinfo *hw = rvu->hw; 507 struct rvu_pfvf *pfvf; 508 u8 cgx_id, lmac_id; 509 u64 cfg; 510 511 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc); 512 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST); 513 lmac_chan_cnt = cfg & 0xFF; 514 515 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 516 sdp_chan_cnt = cfg & 0xFFF; 517 518 cgx_bpid_cnt = hw->cgx_links * lmac_chan_cnt; 519 lbk_bpid_cnt = hw->lbk_links * ((cfg >> 16) & 0xFF); 520 sdp_bpid_cnt = hw->sdp_links * sdp_chan_cnt; 521 522 pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 523 524 /* Backpressure IDs range division 525 * CGX channles are mapped to (0 - 191) BPIDs 526 * LBK channles are mapped to (192 - 255) BPIDs 527 * SDP channles are mapped to (256 - 511) BPIDs 528 * 529 * Lmac channles and bpids mapped as follows 530 * cgx(0)_lmac(0)_chan(0 - 15) = bpid(0 - 15) 531 * cgx(0)_lmac(1)_chan(0 - 15) = bpid(16 - 31) .... 532 * cgx(1)_lmac(0)_chan(0 - 15) = bpid(64 - 79) .... 533 */ 534 switch (type) { 535 case NIX_INTF_TYPE_CGX: 536 if ((req->chan_base + req->chan_cnt) > 15) 537 return -EINVAL; 538 rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id); 539 /* Assign bpid based on cgx, lmac and chan id */ 540 bpid = (cgx_id * hw->lmac_per_cgx * lmac_chan_cnt) + 541 (lmac_id * lmac_chan_cnt) + req->chan_base; 542 543 if (req->bpid_per_chan) 544 bpid += chan_id; 545 if (bpid > cgx_bpid_cnt) 546 return -EINVAL; 547 break; 548 549 case NIX_INTF_TYPE_LBK: 550 if ((req->chan_base + req->chan_cnt) > 63) 551 return -EINVAL; 552 bpid = cgx_bpid_cnt + req->chan_base; 553 if (req->bpid_per_chan) 554 bpid += chan_id; 555 if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt)) 556 return -EINVAL; 557 break; 558 case NIX_INTF_TYPE_SDP: 559 if ((req->chan_base + req->chan_cnt) > 255) 560 return -EINVAL; 561 562 bpid = sdp_bpid_cnt + req->chan_base; 563 if (req->bpid_per_chan) 564 bpid += chan_id; 565 566 if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt + sdp_bpid_cnt)) 567 return -EINVAL; 568 break; 569 default: 570 return -EINVAL; 571 } 572 return bpid; 573 } 574 575 int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu, 576 struct nix_bp_cfg_req *req, 577 struct nix_bp_cfg_rsp *rsp) 578 { 579 int blkaddr, pf, type, chan_id = 0; 580 u16 pcifunc = req->hdr.pcifunc; 581 struct rvu_pfvf *pfvf; 582 u16 chan_base, chan; 583 s16 bpid, bpid_base; 584 u64 cfg; 585 586 pf = rvu_get_pf(pcifunc); 587 type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 588 if (is_sdp_pfvf(pcifunc)) 589 type = NIX_INTF_TYPE_SDP; 590 591 /* Enable backpressure only for CGX mapped PFs and LBK/SDP interface */ 592 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK && 593 type != NIX_INTF_TYPE_SDP) 594 return 0; 595 596 pfvf = rvu_get_pfvf(rvu, pcifunc); 597 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 598 599 bpid_base = rvu_nix_get_bpid(rvu, req, type, chan_id); 600 chan_base = pfvf->rx_chan_base + req->chan_base; 601 bpid = bpid_base; 602 603 for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) { 604 if (bpid < 0) { 605 dev_warn(rvu->dev, "Fail to enable backpressure\n"); 606 return -EINVAL; 607 } 608 609 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan)); 610 cfg &= ~GENMASK_ULL(8, 0); 611 rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan), 612 cfg | (bpid & GENMASK_ULL(8, 0)) | BIT_ULL(16)); 613 chan_id++; 614 bpid = rvu_nix_get_bpid(rvu, req, type, chan_id); 615 } 616 617 for (chan = 0; chan < req->chan_cnt; chan++) { 618 /* Map channel and bpid assign to it */ 619 rsp->chan_bpid[chan] = ((req->chan_base + chan) & 0x7F) << 10 | 620 (bpid_base & 0x3FF); 621 if (req->bpid_per_chan) 622 bpid_base++; 623 } 624 rsp->chan_cnt = req->chan_cnt; 625 626 return 0; 627 } 628 629 static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr, 630 u64 format, bool v4, u64 *fidx) 631 { 632 struct nix_lso_format field = {0}; 633 634 /* IP's Length field */ 635 field.layer = NIX_TXLAYER_OL3; 636 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 637 field.offset = v4 ? 2 : 4; 638 field.sizem1 = 1; /* i.e 2 bytes */ 639 field.alg = NIX_LSOALG_ADD_PAYLEN; 640 rvu_write64(rvu, blkaddr, 641 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 642 *(u64 *)&field); 643 644 /* No ID field in IPv6 header */ 645 if (!v4) 646 return; 647 648 /* IP's ID field */ 649 field.layer = NIX_TXLAYER_OL3; 650 field.offset = 4; 651 field.sizem1 = 1; /* i.e 2 bytes */ 652 field.alg = NIX_LSOALG_ADD_SEGNUM; 653 rvu_write64(rvu, blkaddr, 654 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 655 *(u64 *)&field); 656 } 657 658 static void nix_setup_lso_tso_l4(struct rvu *rvu, int blkaddr, 659 u64 format, u64 *fidx) 660 { 661 struct nix_lso_format field = {0}; 662 663 /* TCP's sequence number field */ 664 field.layer = NIX_TXLAYER_OL4; 665 field.offset = 4; 666 field.sizem1 = 3; /* i.e 4 bytes */ 667 field.alg = NIX_LSOALG_ADD_OFFSET; 668 rvu_write64(rvu, blkaddr, 669 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 670 *(u64 *)&field); 671 672 /* TCP's flags field */ 673 field.layer = NIX_TXLAYER_OL4; 674 field.offset = 12; 675 field.sizem1 = 1; /* 2 bytes */ 676 field.alg = NIX_LSOALG_TCP_FLAGS; 677 rvu_write64(rvu, blkaddr, 678 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 679 *(u64 *)&field); 680 } 681 682 static void nix_setup_lso(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 683 { 684 u64 cfg, idx, fidx = 0; 685 686 /* Get max HW supported format indices */ 687 cfg = (rvu_read64(rvu, blkaddr, NIX_AF_CONST1) >> 48) & 0xFF; 688 nix_hw->lso.total = cfg; 689 690 /* Enable LSO */ 691 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LSO_CFG); 692 /* For TSO, set first and middle segment flags to 693 * mask out PSH, RST & FIN flags in TCP packet 694 */ 695 cfg &= ~((0xFFFFULL << 32) | (0xFFFFULL << 16)); 696 cfg |= (0xFFF2ULL << 32) | (0xFFF2ULL << 16); 697 rvu_write64(rvu, blkaddr, NIX_AF_LSO_CFG, cfg | BIT_ULL(63)); 698 699 /* Setup default static LSO formats 700 * 701 * Configure format fields for TCPv4 segmentation offload 702 */ 703 idx = NIX_LSO_FORMAT_IDX_TSOV4; 704 nix_setup_lso_tso_l3(rvu, blkaddr, idx, true, &fidx); 705 nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx); 706 707 /* Set rest of the fields to NOP */ 708 for (; fidx < 8; fidx++) { 709 rvu_write64(rvu, blkaddr, 710 NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL); 711 } 712 nix_hw->lso.in_use++; 713 714 /* Configure format fields for TCPv6 segmentation offload */ 715 idx = NIX_LSO_FORMAT_IDX_TSOV6; 716 fidx = 0; 717 nix_setup_lso_tso_l3(rvu, blkaddr, idx, false, &fidx); 718 nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx); 719 720 /* Set rest of the fields to NOP */ 721 for (; fidx < 8; fidx++) { 722 rvu_write64(rvu, blkaddr, 723 NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL); 724 } 725 nix_hw->lso.in_use++; 726 } 727 728 static void nix_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf) 729 { 730 kfree(pfvf->rq_bmap); 731 kfree(pfvf->sq_bmap); 732 kfree(pfvf->cq_bmap); 733 if (pfvf->rq_ctx) 734 qmem_free(rvu->dev, pfvf->rq_ctx); 735 if (pfvf->sq_ctx) 736 qmem_free(rvu->dev, pfvf->sq_ctx); 737 if (pfvf->cq_ctx) 738 qmem_free(rvu->dev, pfvf->cq_ctx); 739 if (pfvf->rss_ctx) 740 qmem_free(rvu->dev, pfvf->rss_ctx); 741 if (pfvf->nix_qints_ctx) 742 qmem_free(rvu->dev, pfvf->nix_qints_ctx); 743 if (pfvf->cq_ints_ctx) 744 qmem_free(rvu->dev, pfvf->cq_ints_ctx); 745 746 pfvf->rq_bmap = NULL; 747 pfvf->cq_bmap = NULL; 748 pfvf->sq_bmap = NULL; 749 pfvf->rq_ctx = NULL; 750 pfvf->sq_ctx = NULL; 751 pfvf->cq_ctx = NULL; 752 pfvf->rss_ctx = NULL; 753 pfvf->nix_qints_ctx = NULL; 754 pfvf->cq_ints_ctx = NULL; 755 } 756 757 static int nixlf_rss_ctx_init(struct rvu *rvu, int blkaddr, 758 struct rvu_pfvf *pfvf, int nixlf, 759 int rss_sz, int rss_grps, int hwctx_size, 760 u64 way_mask, bool tag_lsb_as_adder) 761 { 762 int err, grp, num_indices; 763 u64 val; 764 765 /* RSS is not requested for this NIXLF */ 766 if (!rss_sz) 767 return 0; 768 num_indices = rss_sz * rss_grps; 769 770 /* Alloc NIX RSS HW context memory and config the base */ 771 err = qmem_alloc(rvu->dev, &pfvf->rss_ctx, num_indices, hwctx_size); 772 if (err) 773 return err; 774 775 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_BASE(nixlf), 776 (u64)pfvf->rss_ctx->iova); 777 778 /* Config full RSS table size, enable RSS and caching */ 779 val = BIT_ULL(36) | BIT_ULL(4) | way_mask << 20 | 780 ilog2(num_indices / MAX_RSS_INDIR_TBL_SIZE); 781 782 if (tag_lsb_as_adder) 783 val |= BIT_ULL(5); 784 785 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf), val); 786 /* Config RSS group offset and sizes */ 787 for (grp = 0; grp < rss_grps; grp++) 788 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_GRPX(nixlf, grp), 789 ((ilog2(rss_sz) - 1) << 16) | (rss_sz * grp)); 790 return 0; 791 } 792 793 static int nix_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block, 794 struct nix_aq_inst_s *inst) 795 { 796 struct admin_queue *aq = block->aq; 797 struct nix_aq_res_s *result; 798 int timeout = 1000; 799 u64 reg, head; 800 801 result = (struct nix_aq_res_s *)aq->res->base; 802 803 /* Get current head pointer where to append this instruction */ 804 reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS); 805 head = (reg >> 4) & AQ_PTR_MASK; 806 807 memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)), 808 (void *)inst, aq->inst->entry_sz); 809 memset(result, 0, sizeof(*result)); 810 /* sync into memory */ 811 wmb(); 812 813 /* Ring the doorbell and wait for result */ 814 rvu_write64(rvu, block->addr, NIX_AF_AQ_DOOR, 1); 815 while (result->compcode == NIX_AQ_COMP_NOTDONE) { 816 cpu_relax(); 817 udelay(1); 818 timeout--; 819 if (!timeout) 820 return -EBUSY; 821 } 822 823 if (result->compcode != NIX_AQ_COMP_GOOD) 824 /* TODO: Replace this with some error code */ 825 return -EBUSY; 826 827 return 0; 828 } 829 830 static int rvu_nix_blk_aq_enq_inst(struct rvu *rvu, struct nix_hw *nix_hw, 831 struct nix_aq_enq_req *req, 832 struct nix_aq_enq_rsp *rsp) 833 { 834 struct rvu_hwinfo *hw = rvu->hw; 835 u16 pcifunc = req->hdr.pcifunc; 836 int nixlf, blkaddr, rc = 0; 837 struct nix_aq_inst_s inst; 838 struct rvu_block *block; 839 struct admin_queue *aq; 840 struct rvu_pfvf *pfvf; 841 void *ctx, *mask; 842 bool ena; 843 u64 cfg; 844 845 blkaddr = nix_hw->blkaddr; 846 block = &hw->block[blkaddr]; 847 aq = block->aq; 848 if (!aq) { 849 dev_warn(rvu->dev, "%s: NIX AQ not initialized\n", __func__); 850 return NIX_AF_ERR_AQ_ENQUEUE; 851 } 852 853 pfvf = rvu_get_pfvf(rvu, pcifunc); 854 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 855 856 /* Skip NIXLF check for broadcast MCE entry and bandwidth profile 857 * operations done by AF itself. 858 */ 859 if (!((!rsp && req->ctype == NIX_AQ_CTYPE_MCE) || 860 (req->ctype == NIX_AQ_CTYPE_BANDPROF && !pcifunc))) { 861 if (!pfvf->nixlf || nixlf < 0) 862 return NIX_AF_ERR_AF_LF_INVALID; 863 } 864 865 switch (req->ctype) { 866 case NIX_AQ_CTYPE_RQ: 867 /* Check if index exceeds max no of queues */ 868 if (!pfvf->rq_ctx || req->qidx >= pfvf->rq_ctx->qsize) 869 rc = NIX_AF_ERR_AQ_ENQUEUE; 870 break; 871 case NIX_AQ_CTYPE_SQ: 872 if (!pfvf->sq_ctx || req->qidx >= pfvf->sq_ctx->qsize) 873 rc = NIX_AF_ERR_AQ_ENQUEUE; 874 break; 875 case NIX_AQ_CTYPE_CQ: 876 if (!pfvf->cq_ctx || req->qidx >= pfvf->cq_ctx->qsize) 877 rc = NIX_AF_ERR_AQ_ENQUEUE; 878 break; 879 case NIX_AQ_CTYPE_RSS: 880 /* Check if RSS is enabled and qidx is within range */ 881 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf)); 882 if (!(cfg & BIT_ULL(4)) || !pfvf->rss_ctx || 883 (req->qidx >= (256UL << (cfg & 0xF)))) 884 rc = NIX_AF_ERR_AQ_ENQUEUE; 885 break; 886 case NIX_AQ_CTYPE_MCE: 887 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG); 888 889 /* Check if index exceeds MCE list length */ 890 if (!nix_hw->mcast.mce_ctx || 891 (req->qidx >= (256UL << (cfg & 0xF)))) 892 rc = NIX_AF_ERR_AQ_ENQUEUE; 893 894 /* Adding multicast lists for requests from PF/VFs is not 895 * yet supported, so ignore this. 896 */ 897 if (rsp) 898 rc = NIX_AF_ERR_AQ_ENQUEUE; 899 break; 900 case NIX_AQ_CTYPE_BANDPROF: 901 if (nix_verify_bandprof((struct nix_cn10k_aq_enq_req *)req, 902 nix_hw, pcifunc)) 903 rc = NIX_AF_ERR_INVALID_BANDPROF; 904 break; 905 default: 906 rc = NIX_AF_ERR_AQ_ENQUEUE; 907 } 908 909 if (rc) 910 return rc; 911 912 /* Check if SQ pointed SMQ belongs to this PF/VF or not */ 913 if (req->ctype == NIX_AQ_CTYPE_SQ && 914 ((req->op == NIX_AQ_INSTOP_INIT && req->sq.ena) || 915 (req->op == NIX_AQ_INSTOP_WRITE && 916 req->sq_mask.ena && req->sq_mask.smq && req->sq.ena))) { 917 if (!is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_SMQ, 918 pcifunc, req->sq.smq)) 919 return NIX_AF_ERR_AQ_ENQUEUE; 920 } 921 922 memset(&inst, 0, sizeof(struct nix_aq_inst_s)); 923 inst.lf = nixlf; 924 inst.cindex = req->qidx; 925 inst.ctype = req->ctype; 926 inst.op = req->op; 927 /* Currently we are not supporting enqueuing multiple instructions, 928 * so always choose first entry in result memory. 929 */ 930 inst.res_addr = (u64)aq->res->iova; 931 932 /* Hardware uses same aq->res->base for updating result of 933 * previous instruction hence wait here till it is done. 934 */ 935 spin_lock(&aq->lock); 936 937 /* Clean result + context memory */ 938 memset(aq->res->base, 0, aq->res->entry_sz); 939 /* Context needs to be written at RES_ADDR + 128 */ 940 ctx = aq->res->base + 128; 941 /* Mask needs to be written at RES_ADDR + 256 */ 942 mask = aq->res->base + 256; 943 944 switch (req->op) { 945 case NIX_AQ_INSTOP_WRITE: 946 if (req->ctype == NIX_AQ_CTYPE_RQ) 947 memcpy(mask, &req->rq_mask, 948 sizeof(struct nix_rq_ctx_s)); 949 else if (req->ctype == NIX_AQ_CTYPE_SQ) 950 memcpy(mask, &req->sq_mask, 951 sizeof(struct nix_sq_ctx_s)); 952 else if (req->ctype == NIX_AQ_CTYPE_CQ) 953 memcpy(mask, &req->cq_mask, 954 sizeof(struct nix_cq_ctx_s)); 955 else if (req->ctype == NIX_AQ_CTYPE_RSS) 956 memcpy(mask, &req->rss_mask, 957 sizeof(struct nix_rsse_s)); 958 else if (req->ctype == NIX_AQ_CTYPE_MCE) 959 memcpy(mask, &req->mce_mask, 960 sizeof(struct nix_rx_mce_s)); 961 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 962 memcpy(mask, &req->prof_mask, 963 sizeof(struct nix_bandprof_s)); 964 fallthrough; 965 case NIX_AQ_INSTOP_INIT: 966 if (req->ctype == NIX_AQ_CTYPE_RQ) 967 memcpy(ctx, &req->rq, sizeof(struct nix_rq_ctx_s)); 968 else if (req->ctype == NIX_AQ_CTYPE_SQ) 969 memcpy(ctx, &req->sq, sizeof(struct nix_sq_ctx_s)); 970 else if (req->ctype == NIX_AQ_CTYPE_CQ) 971 memcpy(ctx, &req->cq, sizeof(struct nix_cq_ctx_s)); 972 else if (req->ctype == NIX_AQ_CTYPE_RSS) 973 memcpy(ctx, &req->rss, sizeof(struct nix_rsse_s)); 974 else if (req->ctype == NIX_AQ_CTYPE_MCE) 975 memcpy(ctx, &req->mce, sizeof(struct nix_rx_mce_s)); 976 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 977 memcpy(ctx, &req->prof, sizeof(struct nix_bandprof_s)); 978 break; 979 case NIX_AQ_INSTOP_NOP: 980 case NIX_AQ_INSTOP_READ: 981 case NIX_AQ_INSTOP_LOCK: 982 case NIX_AQ_INSTOP_UNLOCK: 983 break; 984 default: 985 rc = NIX_AF_ERR_AQ_ENQUEUE; 986 spin_unlock(&aq->lock); 987 return rc; 988 } 989 990 /* Submit the instruction to AQ */ 991 rc = nix_aq_enqueue_wait(rvu, block, &inst); 992 if (rc) { 993 spin_unlock(&aq->lock); 994 return rc; 995 } 996 997 /* Set RQ/SQ/CQ bitmap if respective queue hw context is enabled */ 998 if (req->op == NIX_AQ_INSTOP_INIT) { 999 if (req->ctype == NIX_AQ_CTYPE_RQ && req->rq.ena) 1000 __set_bit(req->qidx, pfvf->rq_bmap); 1001 if (req->ctype == NIX_AQ_CTYPE_SQ && req->sq.ena) 1002 __set_bit(req->qidx, pfvf->sq_bmap); 1003 if (req->ctype == NIX_AQ_CTYPE_CQ && req->cq.ena) 1004 __set_bit(req->qidx, pfvf->cq_bmap); 1005 } 1006 1007 if (req->op == NIX_AQ_INSTOP_WRITE) { 1008 if (req->ctype == NIX_AQ_CTYPE_RQ) { 1009 ena = (req->rq.ena & req->rq_mask.ena) | 1010 (test_bit(req->qidx, pfvf->rq_bmap) & 1011 ~req->rq_mask.ena); 1012 if (ena) 1013 __set_bit(req->qidx, pfvf->rq_bmap); 1014 else 1015 __clear_bit(req->qidx, pfvf->rq_bmap); 1016 } 1017 if (req->ctype == NIX_AQ_CTYPE_SQ) { 1018 ena = (req->rq.ena & req->sq_mask.ena) | 1019 (test_bit(req->qidx, pfvf->sq_bmap) & 1020 ~req->sq_mask.ena); 1021 if (ena) 1022 __set_bit(req->qidx, pfvf->sq_bmap); 1023 else 1024 __clear_bit(req->qidx, pfvf->sq_bmap); 1025 } 1026 if (req->ctype == NIX_AQ_CTYPE_CQ) { 1027 ena = (req->rq.ena & req->cq_mask.ena) | 1028 (test_bit(req->qidx, pfvf->cq_bmap) & 1029 ~req->cq_mask.ena); 1030 if (ena) 1031 __set_bit(req->qidx, pfvf->cq_bmap); 1032 else 1033 __clear_bit(req->qidx, pfvf->cq_bmap); 1034 } 1035 } 1036 1037 if (rsp) { 1038 /* Copy read context into mailbox */ 1039 if (req->op == NIX_AQ_INSTOP_READ) { 1040 if (req->ctype == NIX_AQ_CTYPE_RQ) 1041 memcpy(&rsp->rq, ctx, 1042 sizeof(struct nix_rq_ctx_s)); 1043 else if (req->ctype == NIX_AQ_CTYPE_SQ) 1044 memcpy(&rsp->sq, ctx, 1045 sizeof(struct nix_sq_ctx_s)); 1046 else if (req->ctype == NIX_AQ_CTYPE_CQ) 1047 memcpy(&rsp->cq, ctx, 1048 sizeof(struct nix_cq_ctx_s)); 1049 else if (req->ctype == NIX_AQ_CTYPE_RSS) 1050 memcpy(&rsp->rss, ctx, 1051 sizeof(struct nix_rsse_s)); 1052 else if (req->ctype == NIX_AQ_CTYPE_MCE) 1053 memcpy(&rsp->mce, ctx, 1054 sizeof(struct nix_rx_mce_s)); 1055 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 1056 memcpy(&rsp->prof, ctx, 1057 sizeof(struct nix_bandprof_s)); 1058 } 1059 } 1060 1061 spin_unlock(&aq->lock); 1062 return 0; 1063 } 1064 1065 static int rvu_nix_verify_aq_ctx(struct rvu *rvu, struct nix_hw *nix_hw, 1066 struct nix_aq_enq_req *req, u8 ctype) 1067 { 1068 struct nix_cn10k_aq_enq_req aq_req; 1069 struct nix_cn10k_aq_enq_rsp aq_rsp; 1070 int rc, word; 1071 1072 if (req->ctype != NIX_AQ_CTYPE_CQ) 1073 return 0; 1074 1075 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 1076 req->hdr.pcifunc, ctype, req->qidx); 1077 if (rc) { 1078 dev_err(rvu->dev, 1079 "%s: Failed to fetch %s%d context of PFFUNC 0x%x\n", 1080 __func__, nix_get_ctx_name(ctype), req->qidx, 1081 req->hdr.pcifunc); 1082 return rc; 1083 } 1084 1085 /* Make copy of original context & mask which are required 1086 * for resubmission 1087 */ 1088 memcpy(&aq_req.cq_mask, &req->cq_mask, sizeof(struct nix_cq_ctx_s)); 1089 memcpy(&aq_req.cq, &req->cq, sizeof(struct nix_cq_ctx_s)); 1090 1091 /* exclude fields which HW can update */ 1092 aq_req.cq_mask.cq_err = 0; 1093 aq_req.cq_mask.wrptr = 0; 1094 aq_req.cq_mask.tail = 0; 1095 aq_req.cq_mask.head = 0; 1096 aq_req.cq_mask.avg_level = 0; 1097 aq_req.cq_mask.update_time = 0; 1098 aq_req.cq_mask.substream = 0; 1099 1100 /* Context mask (cq_mask) holds mask value of fields which 1101 * are changed in AQ WRITE operation. 1102 * for example cq.drop = 0xa; 1103 * cq_mask.drop = 0xff; 1104 * Below logic performs '&' between cq and cq_mask so that non 1105 * updated fields are masked out for request and response 1106 * comparison 1107 */ 1108 for (word = 0; word < sizeof(struct nix_cq_ctx_s) / sizeof(u64); 1109 word++) { 1110 *(u64 *)((u8 *)&aq_rsp.cq + word * 8) &= 1111 (*(u64 *)((u8 *)&aq_req.cq_mask + word * 8)); 1112 *(u64 *)((u8 *)&aq_req.cq + word * 8) &= 1113 (*(u64 *)((u8 *)&aq_req.cq_mask + word * 8)); 1114 } 1115 1116 if (memcmp(&aq_req.cq, &aq_rsp.cq, sizeof(struct nix_cq_ctx_s))) 1117 return NIX_AF_ERR_AQ_CTX_RETRY_WRITE; 1118 1119 return 0; 1120 } 1121 1122 static int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req, 1123 struct nix_aq_enq_rsp *rsp) 1124 { 1125 struct nix_hw *nix_hw; 1126 int err, retries = 5; 1127 int blkaddr; 1128 1129 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc); 1130 if (blkaddr < 0) 1131 return NIX_AF_ERR_AF_LF_INVALID; 1132 1133 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1134 if (!nix_hw) 1135 return NIX_AF_ERR_INVALID_NIXBLK; 1136 1137 retry: 1138 err = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, req, rsp); 1139 1140 /* HW errata 'AQ Modification to CQ could be discarded on heavy traffic' 1141 * As a work around perfrom CQ context read after each AQ write. If AQ 1142 * read shows AQ write is not updated perform AQ write again. 1143 */ 1144 if (!err && req->op == NIX_AQ_INSTOP_WRITE) { 1145 err = rvu_nix_verify_aq_ctx(rvu, nix_hw, req, NIX_AQ_CTYPE_CQ); 1146 if (err == NIX_AF_ERR_AQ_CTX_RETRY_WRITE) { 1147 if (retries--) 1148 goto retry; 1149 else 1150 return NIX_AF_ERR_CQ_CTX_WRITE_ERR; 1151 } 1152 } 1153 1154 return err; 1155 } 1156 1157 static const char *nix_get_ctx_name(int ctype) 1158 { 1159 switch (ctype) { 1160 case NIX_AQ_CTYPE_CQ: 1161 return "CQ"; 1162 case NIX_AQ_CTYPE_SQ: 1163 return "SQ"; 1164 case NIX_AQ_CTYPE_RQ: 1165 return "RQ"; 1166 case NIX_AQ_CTYPE_RSS: 1167 return "RSS"; 1168 } 1169 return ""; 1170 } 1171 1172 static int nix_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req *req) 1173 { 1174 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 1175 struct nix_aq_enq_req aq_req; 1176 unsigned long *bmap; 1177 int qidx, q_cnt = 0; 1178 int err = 0, rc; 1179 1180 if (!pfvf->cq_ctx || !pfvf->sq_ctx || !pfvf->rq_ctx) 1181 return NIX_AF_ERR_AQ_ENQUEUE; 1182 1183 memset(&aq_req, 0, sizeof(struct nix_aq_enq_req)); 1184 aq_req.hdr.pcifunc = req->hdr.pcifunc; 1185 1186 if (req->ctype == NIX_AQ_CTYPE_CQ) { 1187 aq_req.cq.ena = 0; 1188 aq_req.cq_mask.ena = 1; 1189 aq_req.cq.bp_ena = 0; 1190 aq_req.cq_mask.bp_ena = 1; 1191 q_cnt = pfvf->cq_ctx->qsize; 1192 bmap = pfvf->cq_bmap; 1193 } 1194 if (req->ctype == NIX_AQ_CTYPE_SQ) { 1195 aq_req.sq.ena = 0; 1196 aq_req.sq_mask.ena = 1; 1197 q_cnt = pfvf->sq_ctx->qsize; 1198 bmap = pfvf->sq_bmap; 1199 } 1200 if (req->ctype == NIX_AQ_CTYPE_RQ) { 1201 aq_req.rq.ena = 0; 1202 aq_req.rq_mask.ena = 1; 1203 q_cnt = pfvf->rq_ctx->qsize; 1204 bmap = pfvf->rq_bmap; 1205 } 1206 1207 aq_req.ctype = req->ctype; 1208 aq_req.op = NIX_AQ_INSTOP_WRITE; 1209 1210 for (qidx = 0; qidx < q_cnt; qidx++) { 1211 if (!test_bit(qidx, bmap)) 1212 continue; 1213 aq_req.qidx = qidx; 1214 rc = rvu_nix_aq_enq_inst(rvu, &aq_req, NULL); 1215 if (rc) { 1216 err = rc; 1217 dev_err(rvu->dev, "Failed to disable %s:%d context\n", 1218 nix_get_ctx_name(req->ctype), qidx); 1219 } 1220 } 1221 1222 return err; 1223 } 1224 1225 #ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING 1226 static int nix_lf_hwctx_lockdown(struct rvu *rvu, struct nix_aq_enq_req *req) 1227 { 1228 struct nix_aq_enq_req lock_ctx_req; 1229 int err; 1230 1231 if (req->op != NIX_AQ_INSTOP_INIT) 1232 return 0; 1233 1234 if (req->ctype == NIX_AQ_CTYPE_MCE || 1235 req->ctype == NIX_AQ_CTYPE_DYNO) 1236 return 0; 1237 1238 memset(&lock_ctx_req, 0, sizeof(struct nix_aq_enq_req)); 1239 lock_ctx_req.hdr.pcifunc = req->hdr.pcifunc; 1240 lock_ctx_req.ctype = req->ctype; 1241 lock_ctx_req.op = NIX_AQ_INSTOP_LOCK; 1242 lock_ctx_req.qidx = req->qidx; 1243 err = rvu_nix_aq_enq_inst(rvu, &lock_ctx_req, NULL); 1244 if (err) 1245 dev_err(rvu->dev, 1246 "PFUNC 0x%x: Failed to lock NIX %s:%d context\n", 1247 req->hdr.pcifunc, 1248 nix_get_ctx_name(req->ctype), req->qidx); 1249 return err; 1250 } 1251 1252 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, 1253 struct nix_aq_enq_req *req, 1254 struct nix_aq_enq_rsp *rsp) 1255 { 1256 int err; 1257 1258 err = rvu_nix_aq_enq_inst(rvu, req, rsp); 1259 if (!err) 1260 err = nix_lf_hwctx_lockdown(rvu, req); 1261 return err; 1262 } 1263 #else 1264 1265 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, 1266 struct nix_aq_enq_req *req, 1267 struct nix_aq_enq_rsp *rsp) 1268 { 1269 return rvu_nix_aq_enq_inst(rvu, req, rsp); 1270 } 1271 #endif 1272 /* CN10K mbox handler */ 1273 int rvu_mbox_handler_nix_cn10k_aq_enq(struct rvu *rvu, 1274 struct nix_cn10k_aq_enq_req *req, 1275 struct nix_cn10k_aq_enq_rsp *rsp) 1276 { 1277 return rvu_nix_aq_enq_inst(rvu, (struct nix_aq_enq_req *)req, 1278 (struct nix_aq_enq_rsp *)rsp); 1279 } 1280 1281 int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu, 1282 struct hwctx_disable_req *req, 1283 struct msg_rsp *rsp) 1284 { 1285 return nix_lf_hwctx_disable(rvu, req); 1286 } 1287 1288 int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, 1289 struct nix_lf_alloc_req *req, 1290 struct nix_lf_alloc_rsp *rsp) 1291 { 1292 int nixlf, qints, hwctx_size, intf, err, rc = 0; 1293 struct rvu_hwinfo *hw = rvu->hw; 1294 u16 pcifunc = req->hdr.pcifunc; 1295 struct rvu_block *block; 1296 struct rvu_pfvf *pfvf; 1297 u64 cfg, ctx_cfg; 1298 int blkaddr; 1299 1300 if (!req->rq_cnt || !req->sq_cnt || !req->cq_cnt) 1301 return NIX_AF_ERR_PARAM; 1302 1303 if (req->way_mask) 1304 req->way_mask &= 0xFFFF; 1305 1306 pfvf = rvu_get_pfvf(rvu, pcifunc); 1307 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1308 if (!pfvf->nixlf || blkaddr < 0) 1309 return NIX_AF_ERR_AF_LF_INVALID; 1310 1311 block = &hw->block[blkaddr]; 1312 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 1313 if (nixlf < 0) 1314 return NIX_AF_ERR_AF_LF_INVALID; 1315 1316 /* Check if requested 'NIXLF <=> NPALF' mapping is valid */ 1317 if (req->npa_func) { 1318 /* If default, use 'this' NIXLF's PFFUNC */ 1319 if (req->npa_func == RVU_DEFAULT_PF_FUNC) 1320 req->npa_func = pcifunc; 1321 if (!is_pffunc_map_valid(rvu, req->npa_func, BLKTYPE_NPA)) 1322 return NIX_AF_INVAL_NPA_PF_FUNC; 1323 } 1324 1325 /* Check if requested 'NIXLF <=> SSOLF' mapping is valid */ 1326 if (req->sso_func) { 1327 /* If default, use 'this' NIXLF's PFFUNC */ 1328 if (req->sso_func == RVU_DEFAULT_PF_FUNC) 1329 req->sso_func = pcifunc; 1330 if (!is_pffunc_map_valid(rvu, req->sso_func, BLKTYPE_SSO)) 1331 return NIX_AF_INVAL_SSO_PF_FUNC; 1332 } 1333 1334 /* If RSS is being enabled, check if requested config is valid. 1335 * RSS table size should be power of two, otherwise 1336 * RSS_GRP::OFFSET + adder might go beyond that group or 1337 * won't be able to use entire table. 1338 */ 1339 if (req->rss_sz && (req->rss_sz > MAX_RSS_INDIR_TBL_SIZE || 1340 !is_power_of_2(req->rss_sz))) 1341 return NIX_AF_ERR_RSS_SIZE_INVALID; 1342 1343 if (req->rss_sz && 1344 (!req->rss_grps || req->rss_grps > MAX_RSS_GROUPS)) 1345 return NIX_AF_ERR_RSS_GRPS_INVALID; 1346 1347 /* Reset this NIX LF */ 1348 err = rvu_lf_reset(rvu, block, nixlf); 1349 if (err) { 1350 dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", 1351 block->addr - BLKADDR_NIX0, nixlf); 1352 return NIX_AF_ERR_LF_RESET; 1353 } 1354 1355 ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3); 1356 1357 /* Alloc NIX RQ HW context memory and config the base */ 1358 hwctx_size = 1UL << ((ctx_cfg >> 4) & 0xF); 1359 err = qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size); 1360 if (err) 1361 goto free_mem; 1362 1363 pfvf->rq_bmap = kcalloc(req->rq_cnt, sizeof(long), GFP_KERNEL); 1364 if (!pfvf->rq_bmap) 1365 goto free_mem; 1366 1367 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_BASE(nixlf), 1368 (u64)pfvf->rq_ctx->iova); 1369 1370 /* Set caching and queue count in HW */ 1371 cfg = BIT_ULL(36) | (req->rq_cnt - 1) | req->way_mask << 20; 1372 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_CFG(nixlf), cfg); 1373 1374 /* Alloc NIX SQ HW context memory and config the base */ 1375 hwctx_size = 1UL << (ctx_cfg & 0xF); 1376 err = qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size); 1377 if (err) 1378 goto free_mem; 1379 1380 pfvf->sq_bmap = kcalloc(req->sq_cnt, sizeof(long), GFP_KERNEL); 1381 if (!pfvf->sq_bmap) 1382 goto free_mem; 1383 1384 rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_BASE(nixlf), 1385 (u64)pfvf->sq_ctx->iova); 1386 1387 cfg = BIT_ULL(36) | (req->sq_cnt - 1) | req->way_mask << 20; 1388 rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_CFG(nixlf), cfg); 1389 1390 /* Alloc NIX CQ HW context memory and config the base */ 1391 hwctx_size = 1UL << ((ctx_cfg >> 8) & 0xF); 1392 err = qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size); 1393 if (err) 1394 goto free_mem; 1395 1396 pfvf->cq_bmap = kcalloc(req->cq_cnt, sizeof(long), GFP_KERNEL); 1397 if (!pfvf->cq_bmap) 1398 goto free_mem; 1399 1400 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_BASE(nixlf), 1401 (u64)pfvf->cq_ctx->iova); 1402 1403 cfg = BIT_ULL(36) | (req->cq_cnt - 1) | req->way_mask << 20; 1404 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_CFG(nixlf), cfg); 1405 1406 /* Initialize receive side scaling (RSS) */ 1407 hwctx_size = 1UL << ((ctx_cfg >> 12) & 0xF); 1408 err = nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, req->rss_sz, 1409 req->rss_grps, hwctx_size, req->way_mask, 1410 !!(req->flags & NIX_LF_RSS_TAG_LSB_AS_ADDER)); 1411 if (err) 1412 goto free_mem; 1413 1414 /* Alloc memory for CQINT's HW contexts */ 1415 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1416 qints = (cfg >> 24) & 0xFFF; 1417 hwctx_size = 1UL << ((ctx_cfg >> 24) & 0xF); 1418 err = qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size); 1419 if (err) 1420 goto free_mem; 1421 1422 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_BASE(nixlf), 1423 (u64)pfvf->cq_ints_ctx->iova); 1424 1425 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_CFG(nixlf), 1426 BIT_ULL(36) | req->way_mask << 20); 1427 1428 /* Alloc memory for QINT's HW contexts */ 1429 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1430 qints = (cfg >> 12) & 0xFFF; 1431 hwctx_size = 1UL << ((ctx_cfg >> 20) & 0xF); 1432 err = qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size); 1433 if (err) 1434 goto free_mem; 1435 1436 rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_BASE(nixlf), 1437 (u64)pfvf->nix_qints_ctx->iova); 1438 rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_CFG(nixlf), 1439 BIT_ULL(36) | req->way_mask << 20); 1440 1441 /* Setup VLANX TPID's. 1442 * Use VLAN1 for 802.1Q 1443 * and VLAN0 for 802.1AD. 1444 */ 1445 cfg = (0x8100ULL << 16) | 0x88A8ULL; 1446 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg); 1447 1448 /* Enable LMTST for this NIX LF */ 1449 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG2(nixlf), BIT_ULL(0)); 1450 1451 /* Set CQE/WQE size, NPA_PF_FUNC for SQBs and also SSO_PF_FUNC */ 1452 if (req->npa_func) 1453 cfg = req->npa_func; 1454 if (req->sso_func) 1455 cfg |= (u64)req->sso_func << 16; 1456 1457 cfg |= (u64)req->xqe_sz << 33; 1458 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf), cfg); 1459 1460 /* Config Rx pkt length, csum checks and apad enable / disable */ 1461 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), req->rx_cfg); 1462 1463 /* Configure pkind for TX parse config */ 1464 cfg = NPC_TX_DEF_PKIND; 1465 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg); 1466 1467 intf = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 1468 if (is_sdp_pfvf(pcifunc)) 1469 intf = NIX_INTF_TYPE_SDP; 1470 1471 err = nix_interface_init(rvu, pcifunc, intf, nixlf, rsp, 1472 !!(req->flags & NIX_LF_LBK_BLK_SEL)); 1473 if (err) 1474 goto free_mem; 1475 1476 /* Disable NPC entries as NIXLF's contexts are not initialized yet */ 1477 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 1478 1479 /* Configure RX VTAG Type 7 (strip) for vf vlan */ 1480 rvu_write64(rvu, blkaddr, 1481 NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, NIX_AF_LFX_RX_VTAG_TYPE7), 1482 VTAGSIZE_T4 | VTAG_STRIP); 1483 1484 goto exit; 1485 1486 free_mem: 1487 nix_ctx_free(rvu, pfvf); 1488 rc = -ENOMEM; 1489 1490 exit: 1491 /* Set macaddr of this PF/VF */ 1492 ether_addr_copy(rsp->mac_addr, pfvf->mac_addr); 1493 1494 /* set SQB size info */ 1495 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQ_CONST); 1496 rsp->sqb_size = (cfg >> 34) & 0xFFFF; 1497 rsp->rx_chan_base = pfvf->rx_chan_base; 1498 rsp->tx_chan_base = pfvf->tx_chan_base; 1499 rsp->rx_chan_cnt = pfvf->rx_chan_cnt; 1500 rsp->tx_chan_cnt = pfvf->tx_chan_cnt; 1501 rsp->lso_tsov4_idx = NIX_LSO_FORMAT_IDX_TSOV4; 1502 rsp->lso_tsov6_idx = NIX_LSO_FORMAT_IDX_TSOV6; 1503 /* Get HW supported stat count */ 1504 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 1505 rsp->lf_rx_stats = ((cfg >> 32) & 0xFF); 1506 rsp->lf_tx_stats = ((cfg >> 24) & 0xFF); 1507 /* Get count of CQ IRQs and error IRQs supported per LF */ 1508 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1509 rsp->qints = ((cfg >> 12) & 0xFFF); 1510 rsp->cints = ((cfg >> 24) & 0xFFF); 1511 rsp->cgx_links = hw->cgx_links; 1512 rsp->lbk_links = hw->lbk_links; 1513 rsp->sdp_links = hw->sdp_links; 1514 1515 return rc; 1516 } 1517 1518 int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct nix_lf_free_req *req, 1519 struct msg_rsp *rsp) 1520 { 1521 struct rvu_hwinfo *hw = rvu->hw; 1522 u16 pcifunc = req->hdr.pcifunc; 1523 struct rvu_block *block; 1524 int blkaddr, nixlf, err; 1525 struct rvu_pfvf *pfvf; 1526 1527 pfvf = rvu_get_pfvf(rvu, pcifunc); 1528 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1529 if (!pfvf->nixlf || blkaddr < 0) 1530 return NIX_AF_ERR_AF_LF_INVALID; 1531 1532 block = &hw->block[blkaddr]; 1533 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 1534 if (nixlf < 0) 1535 return NIX_AF_ERR_AF_LF_INVALID; 1536 1537 if (req->flags & NIX_LF_DISABLE_FLOWS) 1538 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 1539 else 1540 rvu_npc_free_mcam_entries(rvu, pcifunc, nixlf); 1541 1542 /* Free any tx vtag def entries used by this NIX LF */ 1543 if (!(req->flags & NIX_LF_DONT_FREE_TX_VTAG)) 1544 nix_free_tx_vtag_entries(rvu, pcifunc); 1545 1546 nix_interface_deinit(rvu, pcifunc, nixlf); 1547 1548 /* Reset this NIX LF */ 1549 err = rvu_lf_reset(rvu, block, nixlf); 1550 if (err) { 1551 dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", 1552 block->addr - BLKADDR_NIX0, nixlf); 1553 return NIX_AF_ERR_LF_RESET; 1554 } 1555 1556 nix_ctx_free(rvu, pfvf); 1557 1558 return 0; 1559 } 1560 1561 int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu, 1562 struct nix_mark_format_cfg *req, 1563 struct nix_mark_format_cfg_rsp *rsp) 1564 { 1565 u16 pcifunc = req->hdr.pcifunc; 1566 struct nix_hw *nix_hw; 1567 struct rvu_pfvf *pfvf; 1568 int blkaddr, rc; 1569 u32 cfg; 1570 1571 pfvf = rvu_get_pfvf(rvu, pcifunc); 1572 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1573 if (!pfvf->nixlf || blkaddr < 0) 1574 return NIX_AF_ERR_AF_LF_INVALID; 1575 1576 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1577 if (!nix_hw) 1578 return NIX_AF_ERR_INVALID_NIXBLK; 1579 1580 cfg = (((u32)req->offset & 0x7) << 16) | 1581 (((u32)req->y_mask & 0xF) << 12) | 1582 (((u32)req->y_val & 0xF) << 8) | 1583 (((u32)req->r_mask & 0xF) << 4) | ((u32)req->r_val & 0xF); 1584 1585 rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfg); 1586 if (rc < 0) { 1587 dev_err(rvu->dev, "No mark_format_ctl for (pf:%d, vf:%d)", 1588 rvu_get_pf(pcifunc), pcifunc & RVU_PFVF_FUNC_MASK); 1589 return NIX_AF_ERR_MARK_CFG_FAIL; 1590 } 1591 1592 rsp->mark_format_idx = rc; 1593 return 0; 1594 } 1595 1596 /* Handle shaper update specially for few revisions */ 1597 static bool 1598 handle_txschq_shaper_update(struct rvu *rvu, int blkaddr, int nixlf, 1599 int lvl, u64 reg, u64 regval) 1600 { 1601 u64 regbase, oldval, sw_xoff = 0; 1602 u64 dbgval, md_debug0 = 0; 1603 unsigned long poll_tmo; 1604 bool rate_reg = 0; 1605 u32 schq; 1606 1607 regbase = reg & 0xFFFF; 1608 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 1609 1610 /* Check for rate register */ 1611 switch (lvl) { 1612 case NIX_TXSCH_LVL_TL1: 1613 md_debug0 = NIX_AF_TL1X_MD_DEBUG0(schq); 1614 sw_xoff = NIX_AF_TL1X_SW_XOFF(schq); 1615 1616 rate_reg = !!(regbase == NIX_AF_TL1X_CIR(0)); 1617 break; 1618 case NIX_TXSCH_LVL_TL2: 1619 md_debug0 = NIX_AF_TL2X_MD_DEBUG0(schq); 1620 sw_xoff = NIX_AF_TL2X_SW_XOFF(schq); 1621 1622 rate_reg = (regbase == NIX_AF_TL2X_CIR(0) || 1623 regbase == NIX_AF_TL2X_PIR(0)); 1624 break; 1625 case NIX_TXSCH_LVL_TL3: 1626 md_debug0 = NIX_AF_TL3X_MD_DEBUG0(schq); 1627 sw_xoff = NIX_AF_TL3X_SW_XOFF(schq); 1628 1629 rate_reg = (regbase == NIX_AF_TL3X_CIR(0) || 1630 regbase == NIX_AF_TL3X_PIR(0)); 1631 break; 1632 case NIX_TXSCH_LVL_TL4: 1633 md_debug0 = NIX_AF_TL4X_MD_DEBUG0(schq); 1634 sw_xoff = NIX_AF_TL4X_SW_XOFF(schq); 1635 1636 rate_reg = (regbase == NIX_AF_TL4X_CIR(0) || 1637 regbase == NIX_AF_TL4X_PIR(0)); 1638 break; 1639 case NIX_TXSCH_LVL_MDQ: 1640 sw_xoff = NIX_AF_MDQX_SW_XOFF(schq); 1641 rate_reg = (regbase == NIX_AF_MDQX_CIR(0) || 1642 regbase == NIX_AF_MDQX_PIR(0)); 1643 break; 1644 } 1645 1646 if (!rate_reg) 1647 return false; 1648 1649 /* Nothing special to do when state is not toggled */ 1650 oldval = rvu_read64(rvu, blkaddr, reg); 1651 if ((oldval & 0x1) == (regval & 0x1)) { 1652 rvu_write64(rvu, blkaddr, reg, regval); 1653 return true; 1654 } 1655 1656 /* PIR/CIR disable */ 1657 if (!(regval & 0x1)) { 1658 rvu_write64(rvu, blkaddr, sw_xoff, 1); 1659 rvu_write64(rvu, blkaddr, reg, 0); 1660 udelay(4); 1661 rvu_write64(rvu, blkaddr, sw_xoff, 0); 1662 return true; 1663 } 1664 1665 /* PIR/CIR enable */ 1666 rvu_write64(rvu, blkaddr, sw_xoff, 1); 1667 if (md_debug0) { 1668 poll_tmo = jiffies + usecs_to_jiffies(10000); 1669 /* Wait until VLD(bit32) == 1 or C_CON(bit48) == 0 */ 1670 do { 1671 if (time_after(jiffies, poll_tmo)) { 1672 dev_err(rvu->dev, 1673 "NIXLF%d: TLX%u(lvl %u) CIR/PIR enable failed\n", 1674 nixlf, schq, lvl); 1675 goto exit; 1676 } 1677 usleep_range(1, 5); 1678 dbgval = rvu_read64(rvu, blkaddr, md_debug0); 1679 } while (!(dbgval & BIT_ULL(32)) && (dbgval & BIT_ULL(48))); 1680 } 1681 rvu_write64(rvu, blkaddr, reg, regval); 1682 exit: 1683 rvu_write64(rvu, blkaddr, sw_xoff, 0); 1684 return true; 1685 } 1686 1687 /* Disable shaping of pkts by a scheduler queue 1688 * at a given scheduler level. 1689 */ 1690 static void nix_reset_tx_shaping(struct rvu *rvu, int blkaddr, 1691 int nixlf, int lvl, int schq) 1692 { 1693 struct rvu_hwinfo *hw = rvu->hw; 1694 u64 cir_reg = 0, pir_reg = 0; 1695 u64 cfg; 1696 1697 switch (lvl) { 1698 case NIX_TXSCH_LVL_TL1: 1699 cir_reg = NIX_AF_TL1X_CIR(schq); 1700 pir_reg = 0; /* PIR not available at TL1 */ 1701 break; 1702 case NIX_TXSCH_LVL_TL2: 1703 cir_reg = NIX_AF_TL2X_CIR(schq); 1704 pir_reg = NIX_AF_TL2X_PIR(schq); 1705 break; 1706 case NIX_TXSCH_LVL_TL3: 1707 cir_reg = NIX_AF_TL3X_CIR(schq); 1708 pir_reg = NIX_AF_TL3X_PIR(schq); 1709 break; 1710 case NIX_TXSCH_LVL_TL4: 1711 cir_reg = NIX_AF_TL4X_CIR(schq); 1712 pir_reg = NIX_AF_TL4X_PIR(schq); 1713 break; 1714 case NIX_TXSCH_LVL_MDQ: 1715 cir_reg = NIX_AF_MDQX_CIR(schq); 1716 pir_reg = NIX_AF_MDQX_PIR(schq); 1717 break; 1718 } 1719 1720 /* Shaper state toggle needs wait/poll */ 1721 if (hw->cap.nix_shaper_toggle_wait) { 1722 if (cir_reg) 1723 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 1724 lvl, cir_reg, 0); 1725 if (pir_reg) 1726 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 1727 lvl, pir_reg, 0); 1728 return; 1729 } 1730 1731 if (!cir_reg) 1732 return; 1733 cfg = rvu_read64(rvu, blkaddr, cir_reg); 1734 rvu_write64(rvu, blkaddr, cir_reg, cfg & ~BIT_ULL(0)); 1735 1736 if (!pir_reg) 1737 return; 1738 cfg = rvu_read64(rvu, blkaddr, pir_reg); 1739 rvu_write64(rvu, blkaddr, pir_reg, cfg & ~BIT_ULL(0)); 1740 } 1741 1742 static void nix_reset_tx_linkcfg(struct rvu *rvu, int blkaddr, 1743 int lvl, int schq) 1744 { 1745 struct rvu_hwinfo *hw = rvu->hw; 1746 int link_level; 1747 int link; 1748 1749 if (lvl >= hw->cap.nix_tx_aggr_lvl) 1750 return; 1751 1752 /* Reset TL4's SDP link config */ 1753 if (lvl == NIX_TXSCH_LVL_TL4) 1754 rvu_write64(rvu, blkaddr, NIX_AF_TL4X_SDP_LINK_CFG(schq), 0x00); 1755 1756 link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ? 1757 NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2; 1758 if (lvl != link_level) 1759 return; 1760 1761 /* Reset TL2's CGX or LBK link config */ 1762 for (link = 0; link < (hw->cgx_links + hw->lbk_links); link++) 1763 rvu_write64(rvu, blkaddr, 1764 NIX_AF_TL3_TL2X_LINKX_CFG(schq, link), 0x00); 1765 } 1766 1767 static void nix_clear_tx_xoff(struct rvu *rvu, int blkaddr, 1768 int lvl, int schq) 1769 { 1770 struct rvu_hwinfo *hw = rvu->hw; 1771 u64 reg; 1772 1773 /* Skip this if shaping is not supported */ 1774 if (!hw->cap.nix_shaping) 1775 return; 1776 1777 /* Clear level specific SW_XOFF */ 1778 switch (lvl) { 1779 case NIX_TXSCH_LVL_TL1: 1780 reg = NIX_AF_TL1X_SW_XOFF(schq); 1781 break; 1782 case NIX_TXSCH_LVL_TL2: 1783 reg = NIX_AF_TL2X_SW_XOFF(schq); 1784 break; 1785 case NIX_TXSCH_LVL_TL3: 1786 reg = NIX_AF_TL3X_SW_XOFF(schq); 1787 break; 1788 case NIX_TXSCH_LVL_TL4: 1789 reg = NIX_AF_TL4X_SW_XOFF(schq); 1790 break; 1791 case NIX_TXSCH_LVL_MDQ: 1792 reg = NIX_AF_MDQX_SW_XOFF(schq); 1793 break; 1794 default: 1795 return; 1796 } 1797 1798 rvu_write64(rvu, blkaddr, reg, 0x0); 1799 } 1800 1801 static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc) 1802 { 1803 struct rvu_hwinfo *hw = rvu->hw; 1804 int pf = rvu_get_pf(pcifunc); 1805 u8 cgx_id = 0, lmac_id = 0; 1806 1807 if (is_afvf(pcifunc)) {/* LBK links */ 1808 return hw->cgx_links; 1809 } else if (is_pf_cgxmapped(rvu, pf)) { 1810 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1811 return (cgx_id * hw->lmac_per_cgx) + lmac_id; 1812 } 1813 1814 /* SDP link */ 1815 return hw->cgx_links + hw->lbk_links; 1816 } 1817 1818 static void nix_get_txschq_range(struct rvu *rvu, u16 pcifunc, 1819 int link, int *start, int *end) 1820 { 1821 struct rvu_hwinfo *hw = rvu->hw; 1822 int pf = rvu_get_pf(pcifunc); 1823 1824 if (is_afvf(pcifunc)) { /* LBK links */ 1825 *start = hw->cap.nix_txsch_per_cgx_lmac * link; 1826 *end = *start + hw->cap.nix_txsch_per_lbk_lmac; 1827 } else if (is_pf_cgxmapped(rvu, pf)) { /* CGX links */ 1828 *start = hw->cap.nix_txsch_per_cgx_lmac * link; 1829 *end = *start + hw->cap.nix_txsch_per_cgx_lmac; 1830 } else { /* SDP link */ 1831 *start = (hw->cap.nix_txsch_per_cgx_lmac * hw->cgx_links) + 1832 (hw->cap.nix_txsch_per_lbk_lmac * hw->lbk_links); 1833 *end = *start + hw->cap.nix_txsch_per_sdp_lmac; 1834 } 1835 } 1836 1837 static int nix_check_txschq_alloc_req(struct rvu *rvu, int lvl, u16 pcifunc, 1838 struct nix_hw *nix_hw, 1839 struct nix_txsch_alloc_req *req) 1840 { 1841 struct rvu_hwinfo *hw = rvu->hw; 1842 int schq, req_schq, free_cnt; 1843 struct nix_txsch *txsch; 1844 int link, start, end; 1845 1846 txsch = &nix_hw->txsch[lvl]; 1847 req_schq = req->schq_contig[lvl] + req->schq[lvl]; 1848 1849 if (!req_schq) 1850 return 0; 1851 1852 link = nix_get_tx_link(rvu, pcifunc); 1853 1854 /* For traffic aggregating scheduler level, one queue is enough */ 1855 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 1856 if (req_schq != 1) 1857 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1858 return 0; 1859 } 1860 1861 /* Get free SCHQ count and check if request can be accomodated */ 1862 if (hw->cap.nix_fixed_txschq_mapping) { 1863 nix_get_txschq_range(rvu, pcifunc, link, &start, &end); 1864 schq = start + (pcifunc & RVU_PFVF_FUNC_MASK); 1865 if (end <= txsch->schq.max && schq < end && 1866 !test_bit(schq, txsch->schq.bmap)) 1867 free_cnt = 1; 1868 else 1869 free_cnt = 0; 1870 } else { 1871 free_cnt = rvu_rsrc_free_count(&txsch->schq); 1872 } 1873 1874 if (free_cnt < req_schq || req_schq > MAX_TXSCHQ_PER_FUNC) 1875 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1876 1877 /* If contiguous queues are needed, check for availability */ 1878 if (!hw->cap.nix_fixed_txschq_mapping && req->schq_contig[lvl] && 1879 !rvu_rsrc_check_contig(&txsch->schq, req->schq_contig[lvl])) 1880 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1881 1882 return 0; 1883 } 1884 1885 static void nix_txsch_alloc(struct rvu *rvu, struct nix_txsch *txsch, 1886 struct nix_txsch_alloc_rsp *rsp, 1887 int lvl, int start, int end) 1888 { 1889 struct rvu_hwinfo *hw = rvu->hw; 1890 u16 pcifunc = rsp->hdr.pcifunc; 1891 int idx, schq; 1892 1893 /* For traffic aggregating levels, queue alloc is based 1894 * on transmit link to which PF_FUNC is mapped to. 1895 */ 1896 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 1897 /* A single TL queue is allocated */ 1898 if (rsp->schq_contig[lvl]) { 1899 rsp->schq_contig[lvl] = 1; 1900 rsp->schq_contig_list[lvl][0] = start; 1901 } 1902 1903 /* Both contig and non-contig reqs doesn't make sense here */ 1904 if (rsp->schq_contig[lvl]) 1905 rsp->schq[lvl] = 0; 1906 1907 if (rsp->schq[lvl]) { 1908 rsp->schq[lvl] = 1; 1909 rsp->schq_list[lvl][0] = start; 1910 } 1911 return; 1912 } 1913 1914 /* Adjust the queue request count if HW supports 1915 * only one queue per level configuration. 1916 */ 1917 if (hw->cap.nix_fixed_txschq_mapping) { 1918 idx = pcifunc & RVU_PFVF_FUNC_MASK; 1919 schq = start + idx; 1920 if (idx >= (end - start) || test_bit(schq, txsch->schq.bmap)) { 1921 rsp->schq_contig[lvl] = 0; 1922 rsp->schq[lvl] = 0; 1923 return; 1924 } 1925 1926 if (rsp->schq_contig[lvl]) { 1927 rsp->schq_contig[lvl] = 1; 1928 set_bit(schq, txsch->schq.bmap); 1929 rsp->schq_contig_list[lvl][0] = schq; 1930 rsp->schq[lvl] = 0; 1931 } else if (rsp->schq[lvl]) { 1932 rsp->schq[lvl] = 1; 1933 set_bit(schq, txsch->schq.bmap); 1934 rsp->schq_list[lvl][0] = schq; 1935 } 1936 return; 1937 } 1938 1939 /* Allocate contiguous queue indices requesty first */ 1940 if (rsp->schq_contig[lvl]) { 1941 schq = bitmap_find_next_zero_area(txsch->schq.bmap, 1942 txsch->schq.max, start, 1943 rsp->schq_contig[lvl], 0); 1944 if (schq >= end) 1945 rsp->schq_contig[lvl] = 0; 1946 for (idx = 0; idx < rsp->schq_contig[lvl]; idx++) { 1947 set_bit(schq, txsch->schq.bmap); 1948 rsp->schq_contig_list[lvl][idx] = schq; 1949 schq++; 1950 } 1951 } 1952 1953 /* Allocate non-contiguous queue indices */ 1954 if (rsp->schq[lvl]) { 1955 idx = 0; 1956 for (schq = start; schq < end; schq++) { 1957 if (!test_bit(schq, txsch->schq.bmap)) { 1958 set_bit(schq, txsch->schq.bmap); 1959 rsp->schq_list[lvl][idx++] = schq; 1960 } 1961 if (idx == rsp->schq[lvl]) 1962 break; 1963 } 1964 /* Update how many were allocated */ 1965 rsp->schq[lvl] = idx; 1966 } 1967 } 1968 1969 int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu, 1970 struct nix_txsch_alloc_req *req, 1971 struct nix_txsch_alloc_rsp *rsp) 1972 { 1973 struct rvu_hwinfo *hw = rvu->hw; 1974 u16 pcifunc = req->hdr.pcifunc; 1975 int link, blkaddr, rc = 0; 1976 int lvl, idx, start, end; 1977 struct nix_txsch *txsch; 1978 struct nix_hw *nix_hw; 1979 u32 *pfvf_map; 1980 int nixlf; 1981 u16 schq; 1982 1983 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 1984 if (rc) 1985 return rc; 1986 1987 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1988 if (!nix_hw) 1989 return NIX_AF_ERR_INVALID_NIXBLK; 1990 1991 mutex_lock(&rvu->rsrc_lock); 1992 1993 /* Check if request is valid as per HW capabilities 1994 * and can be accomodated. 1995 */ 1996 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1997 rc = nix_check_txschq_alloc_req(rvu, lvl, pcifunc, nix_hw, req); 1998 if (rc) 1999 goto err; 2000 } 2001 2002 /* Allocate requested Tx scheduler queues */ 2003 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2004 txsch = &nix_hw->txsch[lvl]; 2005 pfvf_map = txsch->pfvf_map; 2006 2007 if (!req->schq[lvl] && !req->schq_contig[lvl]) 2008 continue; 2009 2010 rsp->schq[lvl] = req->schq[lvl]; 2011 rsp->schq_contig[lvl] = req->schq_contig[lvl]; 2012 2013 link = nix_get_tx_link(rvu, pcifunc); 2014 2015 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 2016 start = link; 2017 end = link; 2018 } else if (hw->cap.nix_fixed_txschq_mapping) { 2019 nix_get_txschq_range(rvu, pcifunc, link, &start, &end); 2020 } else { 2021 start = 0; 2022 end = txsch->schq.max; 2023 } 2024 2025 nix_txsch_alloc(rvu, txsch, rsp, lvl, start, end); 2026 2027 /* Reset queue config */ 2028 for (idx = 0; idx < req->schq_contig[lvl]; idx++) { 2029 schq = rsp->schq_contig_list[lvl][idx]; 2030 if (!(TXSCH_MAP_FLAGS(pfvf_map[schq]) & 2031 NIX_TXSCHQ_CFG_DONE)) 2032 pfvf_map[schq] = TXSCH_MAP(pcifunc, 0); 2033 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2034 nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq); 2035 } 2036 2037 for (idx = 0; idx < req->schq[lvl]; idx++) { 2038 schq = rsp->schq_list[lvl][idx]; 2039 if (!(TXSCH_MAP_FLAGS(pfvf_map[schq]) & 2040 NIX_TXSCHQ_CFG_DONE)) 2041 pfvf_map[schq] = TXSCH_MAP(pcifunc, 0); 2042 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2043 nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq); 2044 } 2045 } 2046 2047 rsp->aggr_level = hw->cap.nix_tx_aggr_lvl; 2048 rsp->aggr_lvl_rr_prio = TXSCH_TL1_DFLT_RR_PRIO; 2049 rsp->link_cfg_lvl = rvu_read64(rvu, blkaddr, 2050 NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ? 2051 NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2; 2052 goto exit; 2053 err: 2054 rc = NIX_AF_ERR_TLX_ALLOC_FAIL; 2055 exit: 2056 mutex_unlock(&rvu->rsrc_lock); 2057 return rc; 2058 } 2059 2060 static int nix_smq_flush(struct rvu *rvu, int blkaddr, 2061 int smq, u16 pcifunc, int nixlf) 2062 { 2063 int pf = rvu_get_pf(pcifunc); 2064 u8 cgx_id = 0, lmac_id = 0; 2065 int err, restore_tx_en = 0; 2066 u64 cfg; 2067 2068 /* enable cgx tx if disabled */ 2069 if (is_pf_cgxmapped(rvu, pf)) { 2070 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 2071 restore_tx_en = !cgx_lmac_tx_enable(rvu_cgx_pdata(cgx_id, rvu), 2072 lmac_id, true); 2073 } 2074 2075 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq)); 2076 /* Do SMQ flush and set enqueue xoff */ 2077 cfg |= BIT_ULL(50) | BIT_ULL(49); 2078 rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg); 2079 2080 /* Disable backpressure from physical link, 2081 * otherwise SMQ flush may stall. 2082 */ 2083 rvu_cgx_enadis_rx_bp(rvu, pf, false); 2084 2085 /* Wait for flush to complete */ 2086 err = rvu_poll_reg(rvu, blkaddr, 2087 NIX_AF_SMQX_CFG(smq), BIT_ULL(49), true); 2088 if (err) 2089 dev_err(rvu->dev, 2090 "NIXLF%d: SMQ%d flush failed\n", nixlf, smq); 2091 2092 rvu_cgx_enadis_rx_bp(rvu, pf, true); 2093 /* restore cgx tx state */ 2094 if (restore_tx_en) 2095 cgx_lmac_tx_enable(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false); 2096 return err; 2097 } 2098 2099 static int nix_txschq_free(struct rvu *rvu, u16 pcifunc) 2100 { 2101 int blkaddr, nixlf, lvl, schq, err; 2102 struct rvu_hwinfo *hw = rvu->hw; 2103 struct nix_txsch *txsch; 2104 struct nix_hw *nix_hw; 2105 u16 map_func; 2106 2107 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2108 if (blkaddr < 0) 2109 return NIX_AF_ERR_AF_LF_INVALID; 2110 2111 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2112 if (!nix_hw) 2113 return NIX_AF_ERR_INVALID_NIXBLK; 2114 2115 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2116 if (nixlf < 0) 2117 return NIX_AF_ERR_AF_LF_INVALID; 2118 2119 /* Disable TL2/3 queue links and all XOFF's before SMQ flush*/ 2120 mutex_lock(&rvu->rsrc_lock); 2121 for (lvl = NIX_TXSCH_LVL_MDQ; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2122 txsch = &nix_hw->txsch[lvl]; 2123 2124 if (lvl >= hw->cap.nix_tx_aggr_lvl) 2125 continue; 2126 2127 for (schq = 0; schq < txsch->schq.max; schq++) { 2128 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2129 continue; 2130 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2131 nix_clear_tx_xoff(rvu, blkaddr, lvl, schq); 2132 } 2133 } 2134 nix_clear_tx_xoff(rvu, blkaddr, NIX_TXSCH_LVL_TL1, 2135 nix_get_tx_link(rvu, pcifunc)); 2136 2137 /* On PF cleanup, clear cfg done flag as 2138 * PF would have changed default config. 2139 */ 2140 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) { 2141 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL1]; 2142 schq = nix_get_tx_link(rvu, pcifunc); 2143 /* Do not clear pcifunc in txsch->pfvf_map[schq] because 2144 * VF might be using this TL1 queue 2145 */ 2146 map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]); 2147 txsch->pfvf_map[schq] = TXSCH_SET_FLAG(map_func, 0x0); 2148 } 2149 2150 /* Flush SMQs */ 2151 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 2152 for (schq = 0; schq < txsch->schq.max; schq++) { 2153 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2154 continue; 2155 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf); 2156 } 2157 2158 /* Now free scheduler queues to free pool */ 2159 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2160 /* TLs above aggregation level are shared across all PF 2161 * and it's VFs, hence skip freeing them. 2162 */ 2163 if (lvl >= hw->cap.nix_tx_aggr_lvl) 2164 continue; 2165 2166 txsch = &nix_hw->txsch[lvl]; 2167 for (schq = 0; schq < txsch->schq.max; schq++) { 2168 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2169 continue; 2170 rvu_free_rsrc(&txsch->schq, schq); 2171 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 2172 } 2173 } 2174 mutex_unlock(&rvu->rsrc_lock); 2175 2176 /* Sync cached info for this LF in NDC-TX to LLC/DRAM */ 2177 rvu_write64(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12) | nixlf); 2178 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12), true); 2179 if (err) 2180 dev_err(rvu->dev, "NDC-TX sync failed for NIXLF %d\n", nixlf); 2181 2182 return 0; 2183 } 2184 2185 static int nix_txschq_free_one(struct rvu *rvu, 2186 struct nix_txsch_free_req *req) 2187 { 2188 struct rvu_hwinfo *hw = rvu->hw; 2189 u16 pcifunc = req->hdr.pcifunc; 2190 int lvl, schq, nixlf, blkaddr; 2191 struct nix_txsch *txsch; 2192 struct nix_hw *nix_hw; 2193 u32 *pfvf_map; 2194 int rc; 2195 2196 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2197 if (blkaddr < 0) 2198 return NIX_AF_ERR_AF_LF_INVALID; 2199 2200 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2201 if (!nix_hw) 2202 return NIX_AF_ERR_INVALID_NIXBLK; 2203 2204 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2205 if (nixlf < 0) 2206 return NIX_AF_ERR_AF_LF_INVALID; 2207 2208 lvl = req->schq_lvl; 2209 schq = req->schq; 2210 txsch = &nix_hw->txsch[lvl]; 2211 2212 if (lvl >= hw->cap.nix_tx_aggr_lvl || schq >= txsch->schq.max) 2213 return 0; 2214 2215 pfvf_map = txsch->pfvf_map; 2216 mutex_lock(&rvu->rsrc_lock); 2217 2218 if (TXSCH_MAP_FUNC(pfvf_map[schq]) != pcifunc) { 2219 rc = NIX_AF_ERR_TLX_INVALID; 2220 goto err; 2221 } 2222 2223 /* Clear SW_XOFF of this resource only. 2224 * For SMQ level, all path XOFF's 2225 * need to be made clear by user 2226 */ 2227 nix_clear_tx_xoff(rvu, blkaddr, lvl, schq); 2228 2229 /* Flush if it is a SMQ. Onus of disabling 2230 * TL2/3 queue links before SMQ flush is on user 2231 */ 2232 if (lvl == NIX_TXSCH_LVL_SMQ && 2233 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf)) { 2234 rc = NIX_AF_SMQ_FLUSH_FAILED; 2235 goto err; 2236 } 2237 2238 /* Free the resource */ 2239 rvu_free_rsrc(&txsch->schq, schq); 2240 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 2241 mutex_unlock(&rvu->rsrc_lock); 2242 return 0; 2243 err: 2244 mutex_unlock(&rvu->rsrc_lock); 2245 return rc; 2246 } 2247 2248 int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu, 2249 struct nix_txsch_free_req *req, 2250 struct msg_rsp *rsp) 2251 { 2252 if (req->flags & TXSCHQ_FREE_ALL) 2253 return nix_txschq_free(rvu, req->hdr.pcifunc); 2254 else 2255 return nix_txschq_free_one(rvu, req); 2256 } 2257 2258 static bool is_txschq_hierarchy_valid(struct rvu *rvu, u16 pcifunc, int blkaddr, 2259 int lvl, u64 reg, u64 regval) 2260 { 2261 u64 regbase = reg & 0xFFFF; 2262 u16 schq, parent; 2263 2264 if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, lvl, reg)) 2265 return false; 2266 2267 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2268 /* Check if this schq belongs to this PF/VF or not */ 2269 if (!is_valid_txschq(rvu, blkaddr, lvl, pcifunc, schq)) 2270 return false; 2271 2272 parent = (regval >> 16) & 0x1FF; 2273 /* Validate MDQ's TL4 parent */ 2274 if (regbase == NIX_AF_MDQX_PARENT(0) && 2275 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL4, pcifunc, parent)) 2276 return false; 2277 2278 /* Validate TL4's TL3 parent */ 2279 if (regbase == NIX_AF_TL4X_PARENT(0) && 2280 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL3, pcifunc, parent)) 2281 return false; 2282 2283 /* Validate TL3's TL2 parent */ 2284 if (regbase == NIX_AF_TL3X_PARENT(0) && 2285 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL2, pcifunc, parent)) 2286 return false; 2287 2288 /* Validate TL2's TL1 parent */ 2289 if (regbase == NIX_AF_TL2X_PARENT(0) && 2290 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL1, pcifunc, parent)) 2291 return false; 2292 2293 return true; 2294 } 2295 2296 static bool is_txschq_shaping_valid(struct rvu_hwinfo *hw, int lvl, u64 reg) 2297 { 2298 u64 regbase; 2299 2300 if (hw->cap.nix_shaping) 2301 return true; 2302 2303 /* If shaping and coloring is not supported, then 2304 * *_CIR and *_PIR registers should not be configured. 2305 */ 2306 regbase = reg & 0xFFFF; 2307 2308 switch (lvl) { 2309 case NIX_TXSCH_LVL_TL1: 2310 if (regbase == NIX_AF_TL1X_CIR(0)) 2311 return false; 2312 break; 2313 case NIX_TXSCH_LVL_TL2: 2314 if (regbase == NIX_AF_TL2X_CIR(0) || 2315 regbase == NIX_AF_TL2X_PIR(0)) 2316 return false; 2317 break; 2318 case NIX_TXSCH_LVL_TL3: 2319 if (regbase == NIX_AF_TL3X_CIR(0) || 2320 regbase == NIX_AF_TL3X_PIR(0)) 2321 return false; 2322 break; 2323 case NIX_TXSCH_LVL_TL4: 2324 if (regbase == NIX_AF_TL4X_CIR(0) || 2325 regbase == NIX_AF_TL4X_PIR(0)) 2326 return false; 2327 break; 2328 case NIX_TXSCH_LVL_MDQ: 2329 if (regbase == NIX_AF_MDQX_CIR(0) || 2330 regbase == NIX_AF_MDQX_PIR(0)) 2331 return false; 2332 break; 2333 } 2334 return true; 2335 } 2336 2337 static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw, 2338 u16 pcifunc, int blkaddr) 2339 { 2340 u32 *pfvf_map; 2341 int schq; 2342 2343 schq = nix_get_tx_link(rvu, pcifunc); 2344 pfvf_map = nix_hw->txsch[NIX_TXSCH_LVL_TL1].pfvf_map; 2345 /* Skip if PF has already done the config */ 2346 if (TXSCH_MAP_FLAGS(pfvf_map[schq]) & NIX_TXSCHQ_CFG_DONE) 2347 return; 2348 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_TOPOLOGY(schq), 2349 (TXSCH_TL1_DFLT_RR_PRIO << 1)); 2350 2351 /* On OcteonTx2 the config was in bytes and newer silcons 2352 * it's changed to weight. 2353 */ 2354 if (!rvu->hw->cap.nix_common_dwrr_mtu) 2355 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq), 2356 TXSCH_TL1_DFLT_RR_QTM); 2357 else 2358 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq), 2359 CN10K_MAX_DWRR_WEIGHT); 2360 2361 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_CIR(schq), 0x00); 2362 pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], NIX_TXSCHQ_CFG_DONE); 2363 } 2364 2365 /* Register offset - [15:0] 2366 * Scheduler Queue number - [25:16] 2367 */ 2368 #define NIX_TX_SCHQ_MASK GENMASK_ULL(25, 0) 2369 2370 static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw, 2371 int blkaddr, struct nix_txschq_config *req, 2372 struct nix_txschq_config *rsp) 2373 { 2374 u16 pcifunc = req->hdr.pcifunc; 2375 int idx, schq; 2376 u64 reg; 2377 2378 for (idx = 0; idx < req->num_regs; idx++) { 2379 reg = req->reg[idx]; 2380 reg &= NIX_TX_SCHQ_MASK; 2381 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2382 if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, req->lvl, reg) || 2383 !is_valid_txschq(rvu, blkaddr, req->lvl, pcifunc, schq)) 2384 return NIX_AF_INVAL_TXSCHQ_CFG; 2385 rsp->regval[idx] = rvu_read64(rvu, blkaddr, reg); 2386 } 2387 rsp->lvl = req->lvl; 2388 rsp->num_regs = req->num_regs; 2389 return 0; 2390 } 2391 2392 static void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, 2393 u16 pcifunc, struct nix_txsch *txsch) 2394 { 2395 struct rvu_hwinfo *hw = rvu->hw; 2396 int lbk_link_start, lbk_links; 2397 u8 pf = rvu_get_pf(pcifunc); 2398 int schq; 2399 2400 if (!is_pf_cgxmapped(rvu, pf)) 2401 return; 2402 2403 lbk_link_start = hw->cgx_links; 2404 2405 for (schq = 0; schq < txsch->schq.max; schq++) { 2406 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2407 continue; 2408 /* Enable all LBK links with channel 63 by default so that 2409 * packets can be sent to LBK with a NPC TX MCAM rule 2410 */ 2411 lbk_links = hw->lbk_links; 2412 while (lbk_links--) 2413 rvu_write64(rvu, blkaddr, 2414 NIX_AF_TL3_TL2X_LINKX_CFG(schq, 2415 lbk_link_start + 2416 lbk_links), 2417 BIT_ULL(12) | RVU_SWITCH_LBK_CHAN); 2418 } 2419 } 2420 2421 int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu, 2422 struct nix_txschq_config *req, 2423 struct nix_txschq_config *rsp) 2424 { 2425 u64 reg, val, regval, schq_regbase, val_mask; 2426 struct rvu_hwinfo *hw = rvu->hw; 2427 u16 pcifunc = req->hdr.pcifunc; 2428 struct nix_txsch *txsch; 2429 struct nix_hw *nix_hw; 2430 int blkaddr, idx, err; 2431 int nixlf, schq; 2432 u32 *pfvf_map; 2433 2434 if (req->lvl >= NIX_TXSCH_LVL_CNT || 2435 req->num_regs > MAX_REGS_PER_MBOX_MSG) 2436 return NIX_AF_INVAL_TXSCHQ_CFG; 2437 2438 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 2439 if (err) 2440 return err; 2441 2442 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2443 if (!nix_hw) 2444 return NIX_AF_ERR_INVALID_NIXBLK; 2445 2446 if (req->read) 2447 return nix_txschq_cfg_read(rvu, nix_hw, blkaddr, req, rsp); 2448 2449 txsch = &nix_hw->txsch[req->lvl]; 2450 pfvf_map = txsch->pfvf_map; 2451 2452 if (req->lvl >= hw->cap.nix_tx_aggr_lvl && 2453 pcifunc & RVU_PFVF_FUNC_MASK) { 2454 mutex_lock(&rvu->rsrc_lock); 2455 if (req->lvl == NIX_TXSCH_LVL_TL1) 2456 nix_tl1_default_cfg(rvu, nix_hw, pcifunc, blkaddr); 2457 mutex_unlock(&rvu->rsrc_lock); 2458 return 0; 2459 } 2460 2461 for (idx = 0; idx < req->num_regs; idx++) { 2462 reg = req->reg[idx]; 2463 reg &= NIX_TX_SCHQ_MASK; 2464 regval = req->regval[idx]; 2465 schq_regbase = reg & 0xFFFF; 2466 val_mask = req->regval_mask[idx]; 2467 2468 if (!is_txschq_hierarchy_valid(rvu, pcifunc, blkaddr, 2469 txsch->lvl, reg, regval)) 2470 return NIX_AF_INVAL_TXSCHQ_CFG; 2471 2472 /* Check if shaping and coloring is supported */ 2473 if (!is_txschq_shaping_valid(hw, req->lvl, reg)) 2474 continue; 2475 2476 val = rvu_read64(rvu, blkaddr, reg); 2477 regval = (val & val_mask) | (regval & ~val_mask); 2478 2479 /* Handle shaping state toggle specially */ 2480 if (hw->cap.nix_shaper_toggle_wait && 2481 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 2482 req->lvl, reg, regval)) 2483 continue; 2484 2485 /* Replace PF/VF visible NIXLF slot with HW NIXLF id */ 2486 if (schq_regbase == NIX_AF_SMQX_CFG(0)) { 2487 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 2488 pcifunc, 0); 2489 regval &= ~(0x7FULL << 24); 2490 regval |= ((u64)nixlf << 24); 2491 } 2492 2493 /* Clear 'BP_ENA' config, if it's not allowed */ 2494 if (!hw->cap.nix_tx_link_bp) { 2495 if (schq_regbase == NIX_AF_TL4X_SDP_LINK_CFG(0) || 2496 (schq_regbase & 0xFF00) == 2497 NIX_AF_TL3_TL2X_LINKX_CFG(0, 0)) 2498 regval &= ~BIT_ULL(13); 2499 } 2500 2501 /* Mark config as done for TL1 by PF */ 2502 if (schq_regbase >= NIX_AF_TL1X_SCHEDULE(0) && 2503 schq_regbase <= NIX_AF_TL1X_GREEN_BYTES(0)) { 2504 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2505 mutex_lock(&rvu->rsrc_lock); 2506 pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], 2507 NIX_TXSCHQ_CFG_DONE); 2508 mutex_unlock(&rvu->rsrc_lock); 2509 } 2510 2511 /* SMQ flush is special hence split register writes such 2512 * that flush first and write rest of the bits later. 2513 */ 2514 if (schq_regbase == NIX_AF_SMQX_CFG(0) && 2515 (regval & BIT_ULL(49))) { 2516 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2517 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf); 2518 regval &= ~BIT_ULL(49); 2519 } 2520 rvu_write64(rvu, blkaddr, reg, regval); 2521 } 2522 2523 rvu_nix_tx_tl2_cfg(rvu, blkaddr, pcifunc, 2524 &nix_hw->txsch[NIX_TXSCH_LVL_TL2]); 2525 return 0; 2526 } 2527 2528 static int nix_rx_vtag_cfg(struct rvu *rvu, int nixlf, int blkaddr, 2529 struct nix_vtag_config *req) 2530 { 2531 u64 regval = req->vtag_size; 2532 2533 if (req->rx.vtag_type > NIX_AF_LFX_RX_VTAG_TYPE7 || 2534 req->vtag_size > VTAGSIZE_T8) 2535 return -EINVAL; 2536 2537 /* RX VTAG Type 7 reserved for vf vlan */ 2538 if (req->rx.vtag_type == NIX_AF_LFX_RX_VTAG_TYPE7) 2539 return NIX_AF_ERR_RX_VTAG_INUSE; 2540 2541 if (req->rx.capture_vtag) 2542 regval |= BIT_ULL(5); 2543 if (req->rx.strip_vtag) 2544 regval |= BIT_ULL(4); 2545 2546 rvu_write64(rvu, blkaddr, 2547 NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, req->rx.vtag_type), regval); 2548 return 0; 2549 } 2550 2551 static int nix_tx_vtag_free(struct rvu *rvu, int blkaddr, 2552 u16 pcifunc, int index) 2553 { 2554 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2555 struct nix_txvlan *vlan; 2556 2557 if (!nix_hw) 2558 return NIX_AF_ERR_INVALID_NIXBLK; 2559 2560 vlan = &nix_hw->txvlan; 2561 if (vlan->entry2pfvf_map[index] != pcifunc) 2562 return NIX_AF_ERR_PARAM; 2563 2564 rvu_write64(rvu, blkaddr, 2565 NIX_AF_TX_VTAG_DEFX_DATA(index), 0x0ull); 2566 rvu_write64(rvu, blkaddr, 2567 NIX_AF_TX_VTAG_DEFX_CTL(index), 0x0ull); 2568 2569 vlan->entry2pfvf_map[index] = 0; 2570 rvu_free_rsrc(&vlan->rsrc, index); 2571 2572 return 0; 2573 } 2574 2575 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc) 2576 { 2577 struct nix_txvlan *vlan; 2578 struct nix_hw *nix_hw; 2579 int index, blkaddr; 2580 2581 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2582 if (blkaddr < 0) 2583 return; 2584 2585 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2586 if (!nix_hw) 2587 return; 2588 2589 vlan = &nix_hw->txvlan; 2590 2591 mutex_lock(&vlan->rsrc_lock); 2592 /* Scan all the entries and free the ones mapped to 'pcifunc' */ 2593 for (index = 0; index < vlan->rsrc.max; index++) { 2594 if (vlan->entry2pfvf_map[index] == pcifunc) 2595 nix_tx_vtag_free(rvu, blkaddr, pcifunc, index); 2596 } 2597 mutex_unlock(&vlan->rsrc_lock); 2598 } 2599 2600 static int nix_tx_vtag_alloc(struct rvu *rvu, int blkaddr, 2601 u64 vtag, u8 size) 2602 { 2603 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2604 struct nix_txvlan *vlan; 2605 u64 regval; 2606 int index; 2607 2608 if (!nix_hw) 2609 return NIX_AF_ERR_INVALID_NIXBLK; 2610 2611 vlan = &nix_hw->txvlan; 2612 2613 mutex_lock(&vlan->rsrc_lock); 2614 2615 index = rvu_alloc_rsrc(&vlan->rsrc); 2616 if (index < 0) { 2617 mutex_unlock(&vlan->rsrc_lock); 2618 return index; 2619 } 2620 2621 mutex_unlock(&vlan->rsrc_lock); 2622 2623 regval = size ? vtag : vtag << 32; 2624 2625 rvu_write64(rvu, blkaddr, 2626 NIX_AF_TX_VTAG_DEFX_DATA(index), regval); 2627 rvu_write64(rvu, blkaddr, 2628 NIX_AF_TX_VTAG_DEFX_CTL(index), size); 2629 2630 return index; 2631 } 2632 2633 static int nix_tx_vtag_decfg(struct rvu *rvu, int blkaddr, 2634 struct nix_vtag_config *req) 2635 { 2636 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2637 u16 pcifunc = req->hdr.pcifunc; 2638 int idx0 = req->tx.vtag0_idx; 2639 int idx1 = req->tx.vtag1_idx; 2640 struct nix_txvlan *vlan; 2641 int err = 0; 2642 2643 if (!nix_hw) 2644 return NIX_AF_ERR_INVALID_NIXBLK; 2645 2646 vlan = &nix_hw->txvlan; 2647 if (req->tx.free_vtag0 && req->tx.free_vtag1) 2648 if (vlan->entry2pfvf_map[idx0] != pcifunc || 2649 vlan->entry2pfvf_map[idx1] != pcifunc) 2650 return NIX_AF_ERR_PARAM; 2651 2652 mutex_lock(&vlan->rsrc_lock); 2653 2654 if (req->tx.free_vtag0) { 2655 err = nix_tx_vtag_free(rvu, blkaddr, pcifunc, idx0); 2656 if (err) 2657 goto exit; 2658 } 2659 2660 if (req->tx.free_vtag1) 2661 err = nix_tx_vtag_free(rvu, blkaddr, pcifunc, idx1); 2662 2663 exit: 2664 mutex_unlock(&vlan->rsrc_lock); 2665 return err; 2666 } 2667 2668 static int nix_tx_vtag_cfg(struct rvu *rvu, int blkaddr, 2669 struct nix_vtag_config *req, 2670 struct nix_vtag_config_rsp *rsp) 2671 { 2672 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2673 struct nix_txvlan *vlan; 2674 u16 pcifunc = req->hdr.pcifunc; 2675 2676 if (!nix_hw) 2677 return NIX_AF_ERR_INVALID_NIXBLK; 2678 2679 vlan = &nix_hw->txvlan; 2680 if (req->tx.cfg_vtag0) { 2681 rsp->vtag0_idx = 2682 nix_tx_vtag_alloc(rvu, blkaddr, 2683 req->tx.vtag0, req->vtag_size); 2684 2685 if (rsp->vtag0_idx < 0) 2686 return NIX_AF_ERR_TX_VTAG_NOSPC; 2687 2688 vlan->entry2pfvf_map[rsp->vtag0_idx] = pcifunc; 2689 } 2690 2691 if (req->tx.cfg_vtag1) { 2692 rsp->vtag1_idx = 2693 nix_tx_vtag_alloc(rvu, blkaddr, 2694 req->tx.vtag1, req->vtag_size); 2695 2696 if (rsp->vtag1_idx < 0) 2697 goto err_free; 2698 2699 vlan->entry2pfvf_map[rsp->vtag1_idx] = pcifunc; 2700 } 2701 2702 return 0; 2703 2704 err_free: 2705 if (req->tx.cfg_vtag0) 2706 nix_tx_vtag_free(rvu, blkaddr, pcifunc, rsp->vtag0_idx); 2707 2708 return NIX_AF_ERR_TX_VTAG_NOSPC; 2709 } 2710 2711 int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu, 2712 struct nix_vtag_config *req, 2713 struct nix_vtag_config_rsp *rsp) 2714 { 2715 u16 pcifunc = req->hdr.pcifunc; 2716 int blkaddr, nixlf, err; 2717 2718 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 2719 if (err) 2720 return err; 2721 2722 if (req->cfg_type) { 2723 /* rx vtag configuration */ 2724 err = nix_rx_vtag_cfg(rvu, nixlf, blkaddr, req); 2725 if (err) 2726 return NIX_AF_ERR_PARAM; 2727 } else { 2728 /* tx vtag configuration */ 2729 if ((req->tx.cfg_vtag0 || req->tx.cfg_vtag1) && 2730 (req->tx.free_vtag0 || req->tx.free_vtag1)) 2731 return NIX_AF_ERR_PARAM; 2732 2733 if (req->tx.cfg_vtag0 || req->tx.cfg_vtag1) 2734 return nix_tx_vtag_cfg(rvu, blkaddr, req, rsp); 2735 2736 if (req->tx.free_vtag0 || req->tx.free_vtag1) 2737 return nix_tx_vtag_decfg(rvu, blkaddr, req); 2738 } 2739 2740 return 0; 2741 } 2742 2743 static int nix_blk_setup_mce(struct rvu *rvu, struct nix_hw *nix_hw, 2744 int mce, u8 op, u16 pcifunc, int next, bool eol) 2745 { 2746 struct nix_aq_enq_req aq_req; 2747 int err; 2748 2749 aq_req.hdr.pcifunc = 0; 2750 aq_req.ctype = NIX_AQ_CTYPE_MCE; 2751 aq_req.op = op; 2752 aq_req.qidx = mce; 2753 2754 /* Use RSS with RSS index 0 */ 2755 aq_req.mce.op = 1; 2756 aq_req.mce.index = 0; 2757 aq_req.mce.eol = eol; 2758 aq_req.mce.pf_func = pcifunc; 2759 aq_req.mce.next = next; 2760 2761 /* All fields valid */ 2762 *(u64 *)(&aq_req.mce_mask) = ~0ULL; 2763 2764 err = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, &aq_req, NULL); 2765 if (err) { 2766 dev_err(rvu->dev, "Failed to setup Bcast MCE for PF%d:VF%d\n", 2767 rvu_get_pf(pcifunc), pcifunc & RVU_PFVF_FUNC_MASK); 2768 return err; 2769 } 2770 return 0; 2771 } 2772 2773 static int nix_update_mce_list_entry(struct nix_mce_list *mce_list, 2774 u16 pcifunc, bool add) 2775 { 2776 struct mce *mce, *tail = NULL; 2777 bool delete = false; 2778 2779 /* Scan through the current list */ 2780 hlist_for_each_entry(mce, &mce_list->head, node) { 2781 /* If already exists, then delete */ 2782 if (mce->pcifunc == pcifunc && !add) { 2783 delete = true; 2784 break; 2785 } else if (mce->pcifunc == pcifunc && add) { 2786 /* entry already exists */ 2787 return 0; 2788 } 2789 tail = mce; 2790 } 2791 2792 if (delete) { 2793 hlist_del(&mce->node); 2794 kfree(mce); 2795 mce_list->count--; 2796 return 0; 2797 } 2798 2799 if (!add) 2800 return 0; 2801 2802 /* Add a new one to the list, at the tail */ 2803 mce = kzalloc(sizeof(*mce), GFP_KERNEL); 2804 if (!mce) 2805 return -ENOMEM; 2806 mce->pcifunc = pcifunc; 2807 if (!tail) 2808 hlist_add_head(&mce->node, &mce_list->head); 2809 else 2810 hlist_add_behind(&mce->node, &tail->node); 2811 mce_list->count++; 2812 return 0; 2813 } 2814 2815 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 2816 struct nix_mce_list *mce_list, 2817 int mce_idx, int mcam_index, bool add) 2818 { 2819 int err = 0, idx, next_idx, last_idx, blkaddr, npc_blkaddr; 2820 struct npc_mcam *mcam = &rvu->hw->mcam; 2821 struct nix_mcast *mcast; 2822 struct nix_hw *nix_hw; 2823 struct mce *mce; 2824 2825 if (!mce_list) 2826 return -EINVAL; 2827 2828 /* Get this PF/VF func's MCE index */ 2829 idx = mce_idx + (pcifunc & RVU_PFVF_FUNC_MASK); 2830 2831 if (idx > (mce_idx + mce_list->max)) { 2832 dev_err(rvu->dev, 2833 "%s: Idx %d > max MCE idx %d, for PF%d bcast list\n", 2834 __func__, idx, mce_list->max, 2835 pcifunc >> RVU_PFVF_PF_SHIFT); 2836 return -EINVAL; 2837 } 2838 2839 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 2840 if (err) 2841 return err; 2842 2843 mcast = &nix_hw->mcast; 2844 mutex_lock(&mcast->mce_lock); 2845 2846 err = nix_update_mce_list_entry(mce_list, pcifunc, add); 2847 if (err) 2848 goto end; 2849 2850 /* Disable MCAM entry in NPC */ 2851 if (!mce_list->count) { 2852 npc_blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2853 npc_enable_mcam_entry(rvu, mcam, npc_blkaddr, mcam_index, false); 2854 goto end; 2855 } 2856 2857 /* Dump the updated list to HW */ 2858 idx = mce_idx; 2859 last_idx = idx + mce_list->count - 1; 2860 hlist_for_each_entry(mce, &mce_list->head, node) { 2861 if (idx > last_idx) 2862 break; 2863 2864 next_idx = idx + 1; 2865 /* EOL should be set in last MCE */ 2866 err = nix_blk_setup_mce(rvu, nix_hw, idx, NIX_AQ_INSTOP_WRITE, 2867 mce->pcifunc, next_idx, 2868 (next_idx > last_idx) ? true : false); 2869 if (err) 2870 goto end; 2871 idx++; 2872 } 2873 2874 end: 2875 mutex_unlock(&mcast->mce_lock); 2876 return err; 2877 } 2878 2879 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 2880 struct nix_mce_list **mce_list, int *mce_idx) 2881 { 2882 struct rvu_hwinfo *hw = rvu->hw; 2883 struct rvu_pfvf *pfvf; 2884 2885 if (!hw->cap.nix_rx_multicast || 2886 !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc & ~RVU_PFVF_FUNC_MASK))) { 2887 *mce_list = NULL; 2888 *mce_idx = 0; 2889 return; 2890 } 2891 2892 /* Get this PF/VF func's MCE index */ 2893 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 2894 2895 if (type == NIXLF_BCAST_ENTRY) { 2896 *mce_list = &pfvf->bcast_mce_list; 2897 *mce_idx = pfvf->bcast_mce_idx; 2898 } else if (type == NIXLF_ALLMULTI_ENTRY) { 2899 *mce_list = &pfvf->mcast_mce_list; 2900 *mce_idx = pfvf->mcast_mce_idx; 2901 } else if (type == NIXLF_PROMISC_ENTRY) { 2902 *mce_list = &pfvf->promisc_mce_list; 2903 *mce_idx = pfvf->promisc_mce_idx; 2904 } else { 2905 *mce_list = NULL; 2906 *mce_idx = 0; 2907 } 2908 } 2909 2910 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc, 2911 int type, bool add) 2912 { 2913 int err = 0, nixlf, blkaddr, mcam_index, mce_idx; 2914 struct npc_mcam *mcam = &rvu->hw->mcam; 2915 struct rvu_hwinfo *hw = rvu->hw; 2916 struct nix_mce_list *mce_list; 2917 int pf; 2918 2919 /* skip multicast pkt replication for AF's VFs & SDP links */ 2920 if (is_afvf(pcifunc) || is_sdp_pfvf(pcifunc)) 2921 return 0; 2922 2923 if (!hw->cap.nix_rx_multicast) 2924 return 0; 2925 2926 pf = rvu_get_pf(pcifunc); 2927 if (!is_pf_cgxmapped(rvu, pf)) 2928 return 0; 2929 2930 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2931 if (blkaddr < 0) 2932 return -EINVAL; 2933 2934 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2935 if (nixlf < 0) 2936 return -EINVAL; 2937 2938 nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx); 2939 2940 mcam_index = npc_get_nixlf_mcam_index(mcam, 2941 pcifunc & ~RVU_PFVF_FUNC_MASK, 2942 nixlf, type); 2943 err = nix_update_mce_list(rvu, pcifunc, mce_list, 2944 mce_idx, mcam_index, add); 2945 return err; 2946 } 2947 2948 static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw) 2949 { 2950 struct nix_mcast *mcast = &nix_hw->mcast; 2951 int err, pf, numvfs, idx; 2952 struct rvu_pfvf *pfvf; 2953 u16 pcifunc; 2954 u64 cfg; 2955 2956 /* Skip PF0 (i.e AF) */ 2957 for (pf = 1; pf < (rvu->cgx_mapped_pfs + 1); pf++) { 2958 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2959 /* If PF is not enabled, nothing to do */ 2960 if (!((cfg >> 20) & 0x01)) 2961 continue; 2962 /* Get numVFs attached to this PF */ 2963 numvfs = (cfg >> 12) & 0xFF; 2964 2965 pfvf = &rvu->pf[pf]; 2966 2967 /* This NIX0/1 block mapped to PF ? */ 2968 if (pfvf->nix_blkaddr != nix_hw->blkaddr) 2969 continue; 2970 2971 /* save start idx of broadcast mce list */ 2972 pfvf->bcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2973 nix_mce_list_init(&pfvf->bcast_mce_list, numvfs + 1); 2974 2975 /* save start idx of multicast mce list */ 2976 pfvf->mcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2977 nix_mce_list_init(&pfvf->mcast_mce_list, numvfs + 1); 2978 2979 /* save the start idx of promisc mce list */ 2980 pfvf->promisc_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2981 nix_mce_list_init(&pfvf->promisc_mce_list, numvfs + 1); 2982 2983 for (idx = 0; idx < (numvfs + 1); idx++) { 2984 /* idx-0 is for PF, followed by VFs */ 2985 pcifunc = (pf << RVU_PFVF_PF_SHIFT); 2986 pcifunc |= idx; 2987 /* Add dummy entries now, so that we don't have to check 2988 * for whether AQ_OP should be INIT/WRITE later on. 2989 * Will be updated when a NIXLF is attached/detached to 2990 * these PF/VFs. 2991 */ 2992 err = nix_blk_setup_mce(rvu, nix_hw, 2993 pfvf->bcast_mce_idx + idx, 2994 NIX_AQ_INSTOP_INIT, 2995 pcifunc, 0, true); 2996 if (err) 2997 return err; 2998 2999 /* add dummy entries to multicast mce list */ 3000 err = nix_blk_setup_mce(rvu, nix_hw, 3001 pfvf->mcast_mce_idx + idx, 3002 NIX_AQ_INSTOP_INIT, 3003 pcifunc, 0, true); 3004 if (err) 3005 return err; 3006 3007 /* add dummy entries to promisc mce list */ 3008 err = nix_blk_setup_mce(rvu, nix_hw, 3009 pfvf->promisc_mce_idx + idx, 3010 NIX_AQ_INSTOP_INIT, 3011 pcifunc, 0, true); 3012 if (err) 3013 return err; 3014 } 3015 } 3016 return 0; 3017 } 3018 3019 static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 3020 { 3021 struct nix_mcast *mcast = &nix_hw->mcast; 3022 struct rvu_hwinfo *hw = rvu->hw; 3023 int err, size; 3024 3025 size = (rvu_read64(rvu, blkaddr, NIX_AF_CONST3) >> 16) & 0x0F; 3026 size = (1ULL << size); 3027 3028 /* Alloc memory for multicast/mirror replication entries */ 3029 err = qmem_alloc(rvu->dev, &mcast->mce_ctx, 3030 (256UL << MC_TBL_SIZE), size); 3031 if (err) 3032 return -ENOMEM; 3033 3034 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BASE, 3035 (u64)mcast->mce_ctx->iova); 3036 3037 /* Set max list length equal to max no of VFs per PF + PF itself */ 3038 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG, 3039 BIT_ULL(36) | (hw->max_vfs_per_pf << 4) | MC_TBL_SIZE); 3040 3041 /* Alloc memory for multicast replication buffers */ 3042 size = rvu_read64(rvu, blkaddr, NIX_AF_MC_MIRROR_CONST) & 0xFFFF; 3043 err = qmem_alloc(rvu->dev, &mcast->mcast_buf, 3044 (8UL << MC_BUF_CNT), size); 3045 if (err) 3046 return -ENOMEM; 3047 3048 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_BASE, 3049 (u64)mcast->mcast_buf->iova); 3050 3051 /* Alloc pkind for NIX internal RX multicast/mirror replay */ 3052 mcast->replay_pkind = rvu_alloc_rsrc(&hw->pkind.rsrc); 3053 3054 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_CFG, 3055 BIT_ULL(63) | (mcast->replay_pkind << 24) | 3056 BIT_ULL(20) | MC_BUF_CNT); 3057 3058 mutex_init(&mcast->mce_lock); 3059 3060 return nix_setup_mce_tables(rvu, nix_hw); 3061 } 3062 3063 static int nix_setup_txvlan(struct rvu *rvu, struct nix_hw *nix_hw) 3064 { 3065 struct nix_txvlan *vlan = &nix_hw->txvlan; 3066 int err; 3067 3068 /* Allocate resource bimap for tx vtag def registers*/ 3069 vlan->rsrc.max = NIX_TX_VTAG_DEF_MAX; 3070 err = rvu_alloc_bitmap(&vlan->rsrc); 3071 if (err) 3072 return -ENOMEM; 3073 3074 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */ 3075 vlan->entry2pfvf_map = devm_kcalloc(rvu->dev, vlan->rsrc.max, 3076 sizeof(u16), GFP_KERNEL); 3077 if (!vlan->entry2pfvf_map) 3078 goto free_mem; 3079 3080 mutex_init(&vlan->rsrc_lock); 3081 return 0; 3082 3083 free_mem: 3084 kfree(vlan->rsrc.bmap); 3085 return -ENOMEM; 3086 } 3087 3088 static int nix_setup_txschq(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 3089 { 3090 struct nix_txsch *txsch; 3091 int err, lvl, schq; 3092 u64 cfg, reg; 3093 3094 /* Get scheduler queue count of each type and alloc 3095 * bitmap for each for alloc/free/attach operations. 3096 */ 3097 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 3098 txsch = &nix_hw->txsch[lvl]; 3099 txsch->lvl = lvl; 3100 switch (lvl) { 3101 case NIX_TXSCH_LVL_SMQ: 3102 reg = NIX_AF_MDQ_CONST; 3103 break; 3104 case NIX_TXSCH_LVL_TL4: 3105 reg = NIX_AF_TL4_CONST; 3106 break; 3107 case NIX_TXSCH_LVL_TL3: 3108 reg = NIX_AF_TL3_CONST; 3109 break; 3110 case NIX_TXSCH_LVL_TL2: 3111 reg = NIX_AF_TL2_CONST; 3112 break; 3113 case NIX_TXSCH_LVL_TL1: 3114 reg = NIX_AF_TL1_CONST; 3115 break; 3116 } 3117 cfg = rvu_read64(rvu, blkaddr, reg); 3118 txsch->schq.max = cfg & 0xFFFF; 3119 err = rvu_alloc_bitmap(&txsch->schq); 3120 if (err) 3121 return err; 3122 3123 /* Allocate memory for scheduler queues to 3124 * PF/VF pcifunc mapping info. 3125 */ 3126 txsch->pfvf_map = devm_kcalloc(rvu->dev, txsch->schq.max, 3127 sizeof(u32), GFP_KERNEL); 3128 if (!txsch->pfvf_map) 3129 return -ENOMEM; 3130 for (schq = 0; schq < txsch->schq.max; schq++) 3131 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 3132 } 3133 3134 /* Setup a default value of 8192 as DWRR MTU */ 3135 if (rvu->hw->cap.nix_common_dwrr_mtu) { 3136 rvu_write64(rvu, blkaddr, NIX_AF_DWRR_RPM_MTU, 3137 convert_bytes_to_dwrr_mtu(8192)); 3138 rvu_write64(rvu, blkaddr, NIX_AF_DWRR_SDP_MTU, 3139 convert_bytes_to_dwrr_mtu(8192)); 3140 } 3141 3142 return 0; 3143 } 3144 3145 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 3146 int blkaddr, u32 cfg) 3147 { 3148 int fmt_idx; 3149 3150 for (fmt_idx = 0; fmt_idx < nix_hw->mark_format.in_use; fmt_idx++) { 3151 if (nix_hw->mark_format.cfg[fmt_idx] == cfg) 3152 return fmt_idx; 3153 } 3154 if (fmt_idx >= nix_hw->mark_format.total) 3155 return -ERANGE; 3156 3157 rvu_write64(rvu, blkaddr, NIX_AF_MARK_FORMATX_CTL(fmt_idx), cfg); 3158 nix_hw->mark_format.cfg[fmt_idx] = cfg; 3159 nix_hw->mark_format.in_use++; 3160 return fmt_idx; 3161 } 3162 3163 static int nix_af_mark_format_setup(struct rvu *rvu, struct nix_hw *nix_hw, 3164 int blkaddr) 3165 { 3166 u64 cfgs[] = { 3167 [NIX_MARK_CFG_IP_DSCP_RED] = 0x10003, 3168 [NIX_MARK_CFG_IP_DSCP_YELLOW] = 0x11200, 3169 [NIX_MARK_CFG_IP_DSCP_YELLOW_RED] = 0x11203, 3170 [NIX_MARK_CFG_IP_ECN_RED] = 0x6000c, 3171 [NIX_MARK_CFG_IP_ECN_YELLOW] = 0x60c00, 3172 [NIX_MARK_CFG_IP_ECN_YELLOW_RED] = 0x60c0c, 3173 [NIX_MARK_CFG_VLAN_DEI_RED] = 0x30008, 3174 [NIX_MARK_CFG_VLAN_DEI_YELLOW] = 0x30800, 3175 [NIX_MARK_CFG_VLAN_DEI_YELLOW_RED] = 0x30808, 3176 }; 3177 int i, rc; 3178 u64 total; 3179 3180 total = (rvu_read64(rvu, blkaddr, NIX_AF_PSE_CONST) & 0xFF00) >> 8; 3181 nix_hw->mark_format.total = (u8)total; 3182 nix_hw->mark_format.cfg = devm_kcalloc(rvu->dev, total, sizeof(u32), 3183 GFP_KERNEL); 3184 if (!nix_hw->mark_format.cfg) 3185 return -ENOMEM; 3186 for (i = 0; i < NIX_MARK_CFG_MAX; i++) { 3187 rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfgs[i]); 3188 if (rc < 0) 3189 dev_err(rvu->dev, "Err %d in setup mark format %d\n", 3190 i, rc); 3191 } 3192 3193 return 0; 3194 } 3195 3196 static void rvu_get_lbk_link_max_frs(struct rvu *rvu, u16 *max_mtu) 3197 { 3198 /* CN10K supports LBK FIFO size 72 KB */ 3199 if (rvu->hw->lbk_bufsize == 0x12000) 3200 *max_mtu = CN10K_LBK_LINK_MAX_FRS; 3201 else 3202 *max_mtu = NIC_HW_MAX_FRS; 3203 } 3204 3205 static void rvu_get_lmac_link_max_frs(struct rvu *rvu, u16 *max_mtu) 3206 { 3207 /* RPM supports FIFO len 128 KB */ 3208 if (rvu_cgx_get_fifolen(rvu) == 0x20000) 3209 *max_mtu = CN10K_LMAC_LINK_MAX_FRS; 3210 else 3211 *max_mtu = NIC_HW_MAX_FRS; 3212 } 3213 3214 int rvu_mbox_handler_nix_get_hw_info(struct rvu *rvu, struct msg_req *req, 3215 struct nix_hw_info *rsp) 3216 { 3217 u16 pcifunc = req->hdr.pcifunc; 3218 u64 dwrr_mtu; 3219 int blkaddr; 3220 3221 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 3222 if (blkaddr < 0) 3223 return NIX_AF_ERR_AF_LF_INVALID; 3224 3225 if (is_afvf(pcifunc)) 3226 rvu_get_lbk_link_max_frs(rvu, &rsp->max_mtu); 3227 else 3228 rvu_get_lmac_link_max_frs(rvu, &rsp->max_mtu); 3229 3230 rsp->min_mtu = NIC_HW_MIN_FRS; 3231 3232 if (!rvu->hw->cap.nix_common_dwrr_mtu) { 3233 /* Return '1' on OTx2 */ 3234 rsp->rpm_dwrr_mtu = 1; 3235 rsp->sdp_dwrr_mtu = 1; 3236 return 0; 3237 } 3238 3239 dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_RPM_MTU); 3240 rsp->rpm_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu); 3241 3242 dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_SDP_MTU); 3243 rsp->sdp_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu); 3244 3245 return 0; 3246 } 3247 3248 int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req, 3249 struct msg_rsp *rsp) 3250 { 3251 u16 pcifunc = req->hdr.pcifunc; 3252 int i, nixlf, blkaddr, err; 3253 u64 stats; 3254 3255 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3256 if (err) 3257 return err; 3258 3259 /* Get stats count supported by HW */ 3260 stats = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 3261 3262 /* Reset tx stats */ 3263 for (i = 0; i < ((stats >> 24) & 0xFF); i++) 3264 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_STATX(nixlf, i), 0); 3265 3266 /* Reset rx stats */ 3267 for (i = 0; i < ((stats >> 32) & 0xFF); i++) 3268 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, i), 0); 3269 3270 return 0; 3271 } 3272 3273 /* Returns the ALG index to be set into NPC_RX_ACTION */ 3274 static int get_flowkey_alg_idx(struct nix_hw *nix_hw, u32 flow_cfg) 3275 { 3276 int i; 3277 3278 /* Scan over exiting algo entries to find a match */ 3279 for (i = 0; i < nix_hw->flowkey.in_use; i++) 3280 if (nix_hw->flowkey.flowkey[i] == flow_cfg) 3281 return i; 3282 3283 return -ERANGE; 3284 } 3285 3286 static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) 3287 { 3288 int idx, nr_field, key_off, field_marker, keyoff_marker; 3289 int max_key_off, max_bit_pos, group_member; 3290 struct nix_rx_flowkey_alg *field; 3291 struct nix_rx_flowkey_alg tmp; 3292 u32 key_type, valid_key; 3293 int l4_key_offset = 0; 3294 3295 if (!alg) 3296 return -EINVAL; 3297 3298 #define FIELDS_PER_ALG 5 3299 #define MAX_KEY_OFF 40 3300 /* Clear all fields */ 3301 memset(alg, 0, sizeof(uint64_t) * FIELDS_PER_ALG); 3302 3303 /* Each of the 32 possible flow key algorithm definitions should 3304 * fall into above incremental config (except ALG0). Otherwise a 3305 * single NPC MCAM entry is not sufficient for supporting RSS. 3306 * 3307 * If a different definition or combination needed then NPC MCAM 3308 * has to be programmed to filter such pkts and it's action should 3309 * point to this definition to calculate flowtag or hash. 3310 * 3311 * The `for loop` goes over _all_ protocol field and the following 3312 * variables depicts the state machine forward progress logic. 3313 * 3314 * keyoff_marker - Enabled when hash byte length needs to be accounted 3315 * in field->key_offset update. 3316 * field_marker - Enabled when a new field needs to be selected. 3317 * group_member - Enabled when protocol is part of a group. 3318 */ 3319 3320 keyoff_marker = 0; max_key_off = 0; group_member = 0; 3321 nr_field = 0; key_off = 0; field_marker = 1; 3322 field = &tmp; max_bit_pos = fls(flow_cfg); 3323 for (idx = 0; 3324 idx < max_bit_pos && nr_field < FIELDS_PER_ALG && 3325 key_off < MAX_KEY_OFF; idx++) { 3326 key_type = BIT(idx); 3327 valid_key = flow_cfg & key_type; 3328 /* Found a field marker, reset the field values */ 3329 if (field_marker) 3330 memset(&tmp, 0, sizeof(tmp)); 3331 3332 field_marker = true; 3333 keyoff_marker = true; 3334 switch (key_type) { 3335 case NIX_FLOW_KEY_TYPE_PORT: 3336 field->sel_chan = true; 3337 /* This should be set to 1, when SEL_CHAN is set */ 3338 field->bytesm1 = 1; 3339 break; 3340 case NIX_FLOW_KEY_TYPE_IPV4_PROTO: 3341 field->lid = NPC_LID_LC; 3342 field->hdr_offset = 9; /* offset */ 3343 field->bytesm1 = 0; /* 1 byte */ 3344 field->ltype_match = NPC_LT_LC_IP; 3345 field->ltype_mask = 0xF; 3346 break; 3347 case NIX_FLOW_KEY_TYPE_IPV4: 3348 case NIX_FLOW_KEY_TYPE_INNR_IPV4: 3349 field->lid = NPC_LID_LC; 3350 field->ltype_match = NPC_LT_LC_IP; 3351 if (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV4) { 3352 field->lid = NPC_LID_LG; 3353 field->ltype_match = NPC_LT_LG_TU_IP; 3354 } 3355 field->hdr_offset = 12; /* SIP offset */ 3356 field->bytesm1 = 7; /* SIP + DIP, 8 bytes */ 3357 field->ltype_mask = 0xF; /* Match only IPv4 */ 3358 keyoff_marker = false; 3359 break; 3360 case NIX_FLOW_KEY_TYPE_IPV6: 3361 case NIX_FLOW_KEY_TYPE_INNR_IPV6: 3362 field->lid = NPC_LID_LC; 3363 field->ltype_match = NPC_LT_LC_IP6; 3364 if (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV6) { 3365 field->lid = NPC_LID_LG; 3366 field->ltype_match = NPC_LT_LG_TU_IP6; 3367 } 3368 field->hdr_offset = 8; /* SIP offset */ 3369 field->bytesm1 = 31; /* SIP + DIP, 32 bytes */ 3370 field->ltype_mask = 0xF; /* Match only IPv6 */ 3371 break; 3372 case NIX_FLOW_KEY_TYPE_TCP: 3373 case NIX_FLOW_KEY_TYPE_UDP: 3374 case NIX_FLOW_KEY_TYPE_SCTP: 3375 case NIX_FLOW_KEY_TYPE_INNR_TCP: 3376 case NIX_FLOW_KEY_TYPE_INNR_UDP: 3377 case NIX_FLOW_KEY_TYPE_INNR_SCTP: 3378 field->lid = NPC_LID_LD; 3379 if (key_type == NIX_FLOW_KEY_TYPE_INNR_TCP || 3380 key_type == NIX_FLOW_KEY_TYPE_INNR_UDP || 3381 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) 3382 field->lid = NPC_LID_LH; 3383 field->bytesm1 = 3; /* Sport + Dport, 4 bytes */ 3384 3385 /* Enum values for NPC_LID_LD and NPC_LID_LG are same, 3386 * so no need to change the ltype_match, just change 3387 * the lid for inner protocols 3388 */ 3389 BUILD_BUG_ON((int)NPC_LT_LD_TCP != 3390 (int)NPC_LT_LH_TU_TCP); 3391 BUILD_BUG_ON((int)NPC_LT_LD_UDP != 3392 (int)NPC_LT_LH_TU_UDP); 3393 BUILD_BUG_ON((int)NPC_LT_LD_SCTP != 3394 (int)NPC_LT_LH_TU_SCTP); 3395 3396 if ((key_type == NIX_FLOW_KEY_TYPE_TCP || 3397 key_type == NIX_FLOW_KEY_TYPE_INNR_TCP) && 3398 valid_key) { 3399 field->ltype_match |= NPC_LT_LD_TCP; 3400 group_member = true; 3401 } else if ((key_type == NIX_FLOW_KEY_TYPE_UDP || 3402 key_type == NIX_FLOW_KEY_TYPE_INNR_UDP) && 3403 valid_key) { 3404 field->ltype_match |= NPC_LT_LD_UDP; 3405 group_member = true; 3406 } else if ((key_type == NIX_FLOW_KEY_TYPE_SCTP || 3407 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) && 3408 valid_key) { 3409 field->ltype_match |= NPC_LT_LD_SCTP; 3410 group_member = true; 3411 } 3412 field->ltype_mask = ~field->ltype_match; 3413 if (key_type == NIX_FLOW_KEY_TYPE_SCTP || 3414 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) { 3415 /* Handle the case where any of the group item 3416 * is enabled in the group but not the final one 3417 */ 3418 if (group_member) { 3419 valid_key = true; 3420 group_member = false; 3421 } 3422 } else { 3423 field_marker = false; 3424 keyoff_marker = false; 3425 } 3426 3427 /* TCP/UDP/SCTP and ESP/AH falls at same offset so 3428 * remember the TCP key offset of 40 byte hash key. 3429 */ 3430 if (key_type == NIX_FLOW_KEY_TYPE_TCP) 3431 l4_key_offset = key_off; 3432 break; 3433 case NIX_FLOW_KEY_TYPE_NVGRE: 3434 field->lid = NPC_LID_LD; 3435 field->hdr_offset = 4; /* VSID offset */ 3436 field->bytesm1 = 2; 3437 field->ltype_match = NPC_LT_LD_NVGRE; 3438 field->ltype_mask = 0xF; 3439 break; 3440 case NIX_FLOW_KEY_TYPE_VXLAN: 3441 case NIX_FLOW_KEY_TYPE_GENEVE: 3442 field->lid = NPC_LID_LE; 3443 field->bytesm1 = 2; 3444 field->hdr_offset = 4; 3445 field->ltype_mask = 0xF; 3446 field_marker = false; 3447 keyoff_marker = false; 3448 3449 if (key_type == NIX_FLOW_KEY_TYPE_VXLAN && valid_key) { 3450 field->ltype_match |= NPC_LT_LE_VXLAN; 3451 group_member = true; 3452 } 3453 3454 if (key_type == NIX_FLOW_KEY_TYPE_GENEVE && valid_key) { 3455 field->ltype_match |= NPC_LT_LE_GENEVE; 3456 group_member = true; 3457 } 3458 3459 if (key_type == NIX_FLOW_KEY_TYPE_GENEVE) { 3460 if (group_member) { 3461 field->ltype_mask = ~field->ltype_match; 3462 field_marker = true; 3463 keyoff_marker = true; 3464 valid_key = true; 3465 group_member = false; 3466 } 3467 } 3468 break; 3469 case NIX_FLOW_KEY_TYPE_ETH_DMAC: 3470 case NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC: 3471 field->lid = NPC_LID_LA; 3472 field->ltype_match = NPC_LT_LA_ETHER; 3473 if (key_type == NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC) { 3474 field->lid = NPC_LID_LF; 3475 field->ltype_match = NPC_LT_LF_TU_ETHER; 3476 } 3477 field->hdr_offset = 0; 3478 field->bytesm1 = 5; /* DMAC 6 Byte */ 3479 field->ltype_mask = 0xF; 3480 break; 3481 case NIX_FLOW_KEY_TYPE_IPV6_EXT: 3482 field->lid = NPC_LID_LC; 3483 field->hdr_offset = 40; /* IPV6 hdr */ 3484 field->bytesm1 = 0; /* 1 Byte ext hdr*/ 3485 field->ltype_match = NPC_LT_LC_IP6_EXT; 3486 field->ltype_mask = 0xF; 3487 break; 3488 case NIX_FLOW_KEY_TYPE_GTPU: 3489 field->lid = NPC_LID_LE; 3490 field->hdr_offset = 4; 3491 field->bytesm1 = 3; /* 4 bytes TID*/ 3492 field->ltype_match = NPC_LT_LE_GTPU; 3493 field->ltype_mask = 0xF; 3494 break; 3495 case NIX_FLOW_KEY_TYPE_VLAN: 3496 field->lid = NPC_LID_LB; 3497 field->hdr_offset = 2; /* Skip TPID (2-bytes) */ 3498 field->bytesm1 = 1; /* 2 Bytes (Actually 12 bits) */ 3499 field->ltype_match = NPC_LT_LB_CTAG; 3500 field->ltype_mask = 0xF; 3501 field->fn_mask = 1; /* Mask out the first nibble */ 3502 break; 3503 case NIX_FLOW_KEY_TYPE_AH: 3504 case NIX_FLOW_KEY_TYPE_ESP: 3505 field->hdr_offset = 0; 3506 field->bytesm1 = 7; /* SPI + sequence number */ 3507 field->ltype_mask = 0xF; 3508 field->lid = NPC_LID_LE; 3509 field->ltype_match = NPC_LT_LE_ESP; 3510 if (key_type == NIX_FLOW_KEY_TYPE_AH) { 3511 field->lid = NPC_LID_LD; 3512 field->ltype_match = NPC_LT_LD_AH; 3513 field->hdr_offset = 4; 3514 keyoff_marker = false; 3515 } 3516 break; 3517 } 3518 field->ena = 1; 3519 3520 /* Found a valid flow key type */ 3521 if (valid_key) { 3522 /* Use the key offset of TCP/UDP/SCTP fields 3523 * for ESP/AH fields. 3524 */ 3525 if (key_type == NIX_FLOW_KEY_TYPE_ESP || 3526 key_type == NIX_FLOW_KEY_TYPE_AH) 3527 key_off = l4_key_offset; 3528 field->key_offset = key_off; 3529 memcpy(&alg[nr_field], field, sizeof(*field)); 3530 max_key_off = max(max_key_off, field->bytesm1 + 1); 3531 3532 /* Found a field marker, get the next field */ 3533 if (field_marker) 3534 nr_field++; 3535 } 3536 3537 /* Found a keyoff marker, update the new key_off */ 3538 if (keyoff_marker) { 3539 key_off += max_key_off; 3540 max_key_off = 0; 3541 } 3542 } 3543 /* Processed all the flow key types */ 3544 if (idx == max_bit_pos && key_off <= MAX_KEY_OFF) 3545 return 0; 3546 else 3547 return NIX_AF_ERR_RSS_NOSPC_FIELD; 3548 } 3549 3550 static int reserve_flowkey_alg_idx(struct rvu *rvu, int blkaddr, u32 flow_cfg) 3551 { 3552 u64 field[FIELDS_PER_ALG]; 3553 struct nix_hw *hw; 3554 int fid, rc; 3555 3556 hw = get_nix_hw(rvu->hw, blkaddr); 3557 if (!hw) 3558 return NIX_AF_ERR_INVALID_NIXBLK; 3559 3560 /* No room to add new flow hash algoritham */ 3561 if (hw->flowkey.in_use >= NIX_FLOW_KEY_ALG_MAX) 3562 return NIX_AF_ERR_RSS_NOSPC_ALGO; 3563 3564 /* Generate algo fields for the given flow_cfg */ 3565 rc = set_flowkey_fields((struct nix_rx_flowkey_alg *)field, flow_cfg); 3566 if (rc) 3567 return rc; 3568 3569 /* Update ALGX_FIELDX register with generated fields */ 3570 for (fid = 0; fid < FIELDS_PER_ALG; fid++) 3571 rvu_write64(rvu, blkaddr, 3572 NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(hw->flowkey.in_use, 3573 fid), field[fid]); 3574 3575 /* Store the flow_cfg for futher lookup */ 3576 rc = hw->flowkey.in_use; 3577 hw->flowkey.flowkey[rc] = flow_cfg; 3578 hw->flowkey.in_use++; 3579 3580 return rc; 3581 } 3582 3583 int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu, 3584 struct nix_rss_flowkey_cfg *req, 3585 struct nix_rss_flowkey_cfg_rsp *rsp) 3586 { 3587 u16 pcifunc = req->hdr.pcifunc; 3588 int alg_idx, nixlf, blkaddr; 3589 struct nix_hw *nix_hw; 3590 int err; 3591 3592 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3593 if (err) 3594 return err; 3595 3596 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3597 if (!nix_hw) 3598 return NIX_AF_ERR_INVALID_NIXBLK; 3599 3600 alg_idx = get_flowkey_alg_idx(nix_hw, req->flowkey_cfg); 3601 /* Failed to get algo index from the exiting list, reserve new */ 3602 if (alg_idx < 0) { 3603 alg_idx = reserve_flowkey_alg_idx(rvu, blkaddr, 3604 req->flowkey_cfg); 3605 if (alg_idx < 0) 3606 return alg_idx; 3607 } 3608 rsp->alg_idx = alg_idx; 3609 rvu_npc_update_flowkey_alg_idx(rvu, pcifunc, nixlf, req->group, 3610 alg_idx, req->mcam_index); 3611 return 0; 3612 } 3613 3614 static int nix_rx_flowkey_alg_cfg(struct rvu *rvu, int blkaddr) 3615 { 3616 u32 flowkey_cfg, minkey_cfg; 3617 int alg, fid, rc; 3618 3619 /* Disable all flow key algx fieldx */ 3620 for (alg = 0; alg < NIX_FLOW_KEY_ALG_MAX; alg++) { 3621 for (fid = 0; fid < FIELDS_PER_ALG; fid++) 3622 rvu_write64(rvu, blkaddr, 3623 NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(alg, fid), 3624 0); 3625 } 3626 3627 /* IPv4/IPv6 SIP/DIPs */ 3628 flowkey_cfg = NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6; 3629 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3630 if (rc < 0) 3631 return rc; 3632 3633 /* TCPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3634 minkey_cfg = flowkey_cfg; 3635 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP; 3636 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3637 if (rc < 0) 3638 return rc; 3639 3640 /* UDPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3641 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_UDP; 3642 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3643 if (rc < 0) 3644 return rc; 3645 3646 /* SCTPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3647 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_SCTP; 3648 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3649 if (rc < 0) 3650 return rc; 3651 3652 /* TCP/UDP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3653 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3654 NIX_FLOW_KEY_TYPE_UDP; 3655 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3656 if (rc < 0) 3657 return rc; 3658 3659 /* TCP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3660 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3661 NIX_FLOW_KEY_TYPE_SCTP; 3662 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3663 if (rc < 0) 3664 return rc; 3665 3666 /* UDP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3667 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_UDP | 3668 NIX_FLOW_KEY_TYPE_SCTP; 3669 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3670 if (rc < 0) 3671 return rc; 3672 3673 /* TCP/UDP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3674 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3675 NIX_FLOW_KEY_TYPE_UDP | NIX_FLOW_KEY_TYPE_SCTP; 3676 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3677 if (rc < 0) 3678 return rc; 3679 3680 return 0; 3681 } 3682 3683 int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu, 3684 struct nix_set_mac_addr *req, 3685 struct msg_rsp *rsp) 3686 { 3687 bool from_vf = req->hdr.pcifunc & RVU_PFVF_FUNC_MASK; 3688 u16 pcifunc = req->hdr.pcifunc; 3689 int blkaddr, nixlf, err; 3690 struct rvu_pfvf *pfvf; 3691 3692 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3693 if (err) 3694 return err; 3695 3696 pfvf = rvu_get_pfvf(rvu, pcifunc); 3697 3698 /* untrusted VF can't overwrite admin(PF) changes */ 3699 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && 3700 (from_vf && test_bit(PF_SET_VF_MAC, &pfvf->flags))) { 3701 dev_warn(rvu->dev, 3702 "MAC address set by admin(PF) cannot be overwritten by untrusted VF"); 3703 return -EPERM; 3704 } 3705 3706 ether_addr_copy(pfvf->mac_addr, req->mac_addr); 3707 3708 rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, 3709 pfvf->rx_chan_base, req->mac_addr); 3710 3711 if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && from_vf) 3712 ether_addr_copy(pfvf->default_mac, req->mac_addr); 3713 3714 rvu_switch_update_rules(rvu, pcifunc); 3715 3716 return 0; 3717 } 3718 3719 int rvu_mbox_handler_nix_get_mac_addr(struct rvu *rvu, 3720 struct msg_req *req, 3721 struct nix_get_mac_addr_rsp *rsp) 3722 { 3723 u16 pcifunc = req->hdr.pcifunc; 3724 struct rvu_pfvf *pfvf; 3725 3726 if (!is_nixlf_attached(rvu, pcifunc)) 3727 return NIX_AF_ERR_AF_LF_INVALID; 3728 3729 pfvf = rvu_get_pfvf(rvu, pcifunc); 3730 3731 ether_addr_copy(rsp->mac_addr, pfvf->mac_addr); 3732 3733 return 0; 3734 } 3735 3736 int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req, 3737 struct msg_rsp *rsp) 3738 { 3739 bool allmulti, promisc, nix_rx_multicast; 3740 u16 pcifunc = req->hdr.pcifunc; 3741 struct rvu_pfvf *pfvf; 3742 int nixlf, err; 3743 3744 pfvf = rvu_get_pfvf(rvu, pcifunc); 3745 promisc = req->mode & NIX_RX_MODE_PROMISC ? true : false; 3746 allmulti = req->mode & NIX_RX_MODE_ALLMULTI ? true : false; 3747 pfvf->use_mce_list = req->mode & NIX_RX_MODE_USE_MCE ? true : false; 3748 3749 nix_rx_multicast = rvu->hw->cap.nix_rx_multicast & pfvf->use_mce_list; 3750 3751 if (is_vf(pcifunc) && !nix_rx_multicast && 3752 (promisc || allmulti)) { 3753 dev_warn_ratelimited(rvu->dev, 3754 "VF promisc/multicast not supported\n"); 3755 return 0; 3756 } 3757 3758 /* untrusted VF can't configure promisc/allmulti */ 3759 if (is_vf(pcifunc) && !test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && 3760 (promisc || allmulti)) 3761 return 0; 3762 3763 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 3764 if (err) 3765 return err; 3766 3767 if (nix_rx_multicast) { 3768 /* add/del this PF_FUNC to/from mcast pkt replication list */ 3769 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_ALLMULTI_ENTRY, 3770 allmulti); 3771 if (err) { 3772 dev_err(rvu->dev, 3773 "Failed to update pcifunc 0x%x to multicast list\n", 3774 pcifunc); 3775 return err; 3776 } 3777 3778 /* add/del this PF_FUNC to/from promisc pkt replication list */ 3779 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_PROMISC_ENTRY, 3780 promisc); 3781 if (err) { 3782 dev_err(rvu->dev, 3783 "Failed to update pcifunc 0x%x to promisc list\n", 3784 pcifunc); 3785 return err; 3786 } 3787 } 3788 3789 /* install/uninstall allmulti entry */ 3790 if (allmulti) { 3791 rvu_npc_install_allmulti_entry(rvu, pcifunc, nixlf, 3792 pfvf->rx_chan_base); 3793 } else { 3794 if (!nix_rx_multicast) 3795 rvu_npc_enable_allmulti_entry(rvu, pcifunc, nixlf, false); 3796 } 3797 3798 /* install/uninstall promisc entry */ 3799 if (promisc) { 3800 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 3801 pfvf->rx_chan_base, 3802 pfvf->rx_chan_cnt); 3803 } else { 3804 if (!nix_rx_multicast) 3805 rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf, false); 3806 } 3807 3808 return 0; 3809 } 3810 3811 static void nix_find_link_frs(struct rvu *rvu, 3812 struct nix_frs_cfg *req, u16 pcifunc) 3813 { 3814 int pf = rvu_get_pf(pcifunc); 3815 struct rvu_pfvf *pfvf; 3816 int maxlen, minlen; 3817 int numvfs, hwvf; 3818 int vf; 3819 3820 /* Update with requester's min/max lengths */ 3821 pfvf = rvu_get_pfvf(rvu, pcifunc); 3822 pfvf->maxlen = req->maxlen; 3823 if (req->update_minlen) 3824 pfvf->minlen = req->minlen; 3825 3826 maxlen = req->maxlen; 3827 minlen = req->update_minlen ? req->minlen : 0; 3828 3829 /* Get this PF's numVFs and starting hwvf */ 3830 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 3831 3832 /* For each VF, compare requested max/minlen */ 3833 for (vf = 0; vf < numvfs; vf++) { 3834 pfvf = &rvu->hwvf[hwvf + vf]; 3835 if (pfvf->maxlen > maxlen) 3836 maxlen = pfvf->maxlen; 3837 if (req->update_minlen && 3838 pfvf->minlen && pfvf->minlen < minlen) 3839 minlen = pfvf->minlen; 3840 } 3841 3842 /* Compare requested max/minlen with PF's max/minlen */ 3843 pfvf = &rvu->pf[pf]; 3844 if (pfvf->maxlen > maxlen) 3845 maxlen = pfvf->maxlen; 3846 if (req->update_minlen && 3847 pfvf->minlen && pfvf->minlen < minlen) 3848 minlen = pfvf->minlen; 3849 3850 /* Update the request with max/min PF's and it's VF's max/min */ 3851 req->maxlen = maxlen; 3852 if (req->update_minlen) 3853 req->minlen = minlen; 3854 } 3855 3856 static int 3857 nix_config_link_credits(struct rvu *rvu, int blkaddr, int link, 3858 u16 pcifunc, u64 tx_credits) 3859 { 3860 struct rvu_hwinfo *hw = rvu->hw; 3861 int pf = rvu_get_pf(pcifunc); 3862 u8 cgx_id = 0, lmac_id = 0; 3863 unsigned long poll_tmo; 3864 bool restore_tx_en = 0; 3865 struct nix_hw *nix_hw; 3866 u64 cfg, sw_xoff = 0; 3867 u32 schq = 0; 3868 u32 credits; 3869 int rc; 3870 3871 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3872 if (!nix_hw) 3873 return NIX_AF_ERR_INVALID_NIXBLK; 3874 3875 if (tx_credits == nix_hw->tx_credits[link]) 3876 return 0; 3877 3878 /* Enable cgx tx if disabled for credits to be back */ 3879 if (is_pf_cgxmapped(rvu, pf)) { 3880 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 3881 restore_tx_en = !cgx_lmac_tx_enable(rvu_cgx_pdata(cgx_id, rvu), 3882 lmac_id, true); 3883 } 3884 3885 mutex_lock(&rvu->rsrc_lock); 3886 /* Disable new traffic to link */ 3887 if (hw->cap.nix_shaping) { 3888 schq = nix_get_tx_link(rvu, pcifunc); 3889 sw_xoff = rvu_read64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq)); 3890 rvu_write64(rvu, blkaddr, 3891 NIX_AF_TL1X_SW_XOFF(schq), BIT_ULL(0)); 3892 } 3893 3894 rc = -EBUSY; 3895 poll_tmo = jiffies + usecs_to_jiffies(10000); 3896 /* Wait for credits to return */ 3897 do { 3898 if (time_after(jiffies, poll_tmo)) 3899 goto exit; 3900 usleep_range(100, 200); 3901 3902 cfg = rvu_read64(rvu, blkaddr, 3903 NIX_AF_TX_LINKX_NORM_CREDIT(link)); 3904 credits = (cfg >> 12) & 0xFFFFFULL; 3905 } while (credits != nix_hw->tx_credits[link]); 3906 3907 cfg &= ~(0xFFFFFULL << 12); 3908 cfg |= (tx_credits << 12); 3909 rvu_write64(rvu, blkaddr, NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg); 3910 rc = 0; 3911 3912 nix_hw->tx_credits[link] = tx_credits; 3913 3914 exit: 3915 /* Enable traffic back */ 3916 if (hw->cap.nix_shaping && !sw_xoff) 3917 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq), 0); 3918 3919 /* Restore state of cgx tx */ 3920 if (restore_tx_en) 3921 cgx_lmac_tx_enable(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false); 3922 3923 mutex_unlock(&rvu->rsrc_lock); 3924 return rc; 3925 } 3926 3927 int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req, 3928 struct msg_rsp *rsp) 3929 { 3930 struct rvu_hwinfo *hw = rvu->hw; 3931 u16 pcifunc = req->hdr.pcifunc; 3932 int pf = rvu_get_pf(pcifunc); 3933 int blkaddr, schq, link = -1; 3934 struct nix_txsch *txsch; 3935 u64 cfg, lmac_fifo_len; 3936 struct nix_hw *nix_hw; 3937 struct rvu_pfvf *pfvf; 3938 u8 cgx = 0, lmac = 0; 3939 u16 max_mtu; 3940 3941 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 3942 if (blkaddr < 0) 3943 return NIX_AF_ERR_AF_LF_INVALID; 3944 3945 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3946 if (!nix_hw) 3947 return NIX_AF_ERR_INVALID_NIXBLK; 3948 3949 if (is_afvf(pcifunc)) 3950 rvu_get_lbk_link_max_frs(rvu, &max_mtu); 3951 else 3952 rvu_get_lmac_link_max_frs(rvu, &max_mtu); 3953 3954 if (!req->sdp_link && req->maxlen > max_mtu) 3955 return NIX_AF_ERR_FRS_INVALID; 3956 3957 if (req->update_minlen && req->minlen < NIC_HW_MIN_FRS) 3958 return NIX_AF_ERR_FRS_INVALID; 3959 3960 /* Check if requester wants to update SMQ's */ 3961 if (!req->update_smq) 3962 goto rx_frscfg; 3963 3964 /* Update min/maxlen in each of the SMQ attached to this PF/VF */ 3965 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 3966 mutex_lock(&rvu->rsrc_lock); 3967 for (schq = 0; schq < txsch->schq.max; schq++) { 3968 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 3969 continue; 3970 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq)); 3971 cfg = (cfg & ~(0xFFFFULL << 8)) | ((u64)req->maxlen << 8); 3972 if (req->update_minlen) 3973 cfg = (cfg & ~0x7FULL) | ((u64)req->minlen & 0x7F); 3974 rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq), cfg); 3975 } 3976 mutex_unlock(&rvu->rsrc_lock); 3977 3978 rx_frscfg: 3979 /* Check if config is for SDP link */ 3980 if (req->sdp_link) { 3981 if (!hw->sdp_links) 3982 return NIX_AF_ERR_RX_LINK_INVALID; 3983 link = hw->cgx_links + hw->lbk_links; 3984 goto linkcfg; 3985 } 3986 3987 /* Check if the request is from CGX mapped RVU PF */ 3988 if (is_pf_cgxmapped(rvu, pf)) { 3989 /* Get CGX and LMAC to which this PF is mapped and find link */ 3990 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac); 3991 link = (cgx * hw->lmac_per_cgx) + lmac; 3992 } else if (pf == 0) { 3993 /* For VFs of PF0 ingress is LBK port, so config LBK link */ 3994 pfvf = rvu_get_pfvf(rvu, pcifunc); 3995 link = hw->cgx_links + pfvf->lbkid; 3996 } 3997 3998 if (link < 0) 3999 return NIX_AF_ERR_RX_LINK_INVALID; 4000 4001 nix_find_link_frs(rvu, req, pcifunc); 4002 4003 linkcfg: 4004 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link)); 4005 cfg = (cfg & ~(0xFFFFULL << 16)) | ((u64)req->maxlen << 16); 4006 if (req->update_minlen) 4007 cfg = (cfg & ~0xFFFFULL) | req->minlen; 4008 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), cfg); 4009 4010 if (req->sdp_link || pf == 0) 4011 return 0; 4012 4013 /* Update transmit credits for CGX links */ 4014 lmac_fifo_len = 4015 rvu_cgx_get_fifolen(rvu) / 4016 cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); 4017 return nix_config_link_credits(rvu, blkaddr, link, pcifunc, 4018 (lmac_fifo_len - req->maxlen) / 16); 4019 } 4020 4021 int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req, 4022 struct msg_rsp *rsp) 4023 { 4024 int nixlf, blkaddr, err; 4025 u64 cfg; 4026 4027 err = nix_get_nixlf(rvu, req->hdr.pcifunc, &nixlf, &blkaddr); 4028 if (err) 4029 return err; 4030 4031 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf)); 4032 /* Set the interface configuration */ 4033 if (req->len_verify & BIT(0)) 4034 cfg |= BIT_ULL(41); 4035 else 4036 cfg &= ~BIT_ULL(41); 4037 4038 if (req->len_verify & BIT(1)) 4039 cfg |= BIT_ULL(40); 4040 else 4041 cfg &= ~BIT_ULL(40); 4042 4043 if (req->csum_verify & BIT(0)) 4044 cfg |= BIT_ULL(37); 4045 else 4046 cfg &= ~BIT_ULL(37); 4047 4048 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), cfg); 4049 4050 return 0; 4051 } 4052 4053 static u64 rvu_get_lbk_link_credits(struct rvu *rvu, u16 lbk_max_frs) 4054 { 4055 /* CN10k supports 72KB FIFO size and max packet size of 64k */ 4056 if (rvu->hw->lbk_bufsize == 0x12000) 4057 return (rvu->hw->lbk_bufsize - lbk_max_frs) / 16; 4058 4059 return 1600; /* 16 * max LBK datarate = 16 * 100Gbps */ 4060 } 4061 4062 static void nix_link_config(struct rvu *rvu, int blkaddr, 4063 struct nix_hw *nix_hw) 4064 { 4065 struct rvu_hwinfo *hw = rvu->hw; 4066 int cgx, lmac_cnt, slink, link; 4067 u16 lbk_max_frs, lmac_max_frs; 4068 u64 tx_credits, cfg; 4069 4070 rvu_get_lbk_link_max_frs(rvu, &lbk_max_frs); 4071 rvu_get_lmac_link_max_frs(rvu, &lmac_max_frs); 4072 4073 /* Set default min/max packet lengths allowed on NIX Rx links. 4074 * 4075 * With HW reset minlen value of 60byte, HW will treat ARP pkts 4076 * as undersize and report them to SW as error pkts, hence 4077 * setting it to 40 bytes. 4078 */ 4079 for (link = 0; link < hw->cgx_links; link++) { 4080 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4081 ((u64)lmac_max_frs << 16) | NIC_HW_MIN_FRS); 4082 } 4083 4084 for (link = hw->cgx_links; link < hw->lbk_links; link++) { 4085 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4086 ((u64)lbk_max_frs << 16) | NIC_HW_MIN_FRS); 4087 } 4088 if (hw->sdp_links) { 4089 link = hw->cgx_links + hw->lbk_links; 4090 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4091 SDP_HW_MAX_FRS << 16 | NIC_HW_MIN_FRS); 4092 } 4093 4094 /* Set credits for Tx links assuming max packet length allowed. 4095 * This will be reconfigured based on MTU set for PF/VF. 4096 */ 4097 for (cgx = 0; cgx < hw->cgx; cgx++) { 4098 lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); 4099 /* Skip when cgx is not available or lmac cnt is zero */ 4100 if (lmac_cnt <= 0) 4101 continue; 4102 tx_credits = ((rvu_cgx_get_fifolen(rvu) / lmac_cnt) - 4103 lmac_max_frs) / 16; 4104 /* Enable credits and set credit pkt count to max allowed */ 4105 cfg = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1); 4106 slink = cgx * hw->lmac_per_cgx; 4107 for (link = slink; link < (slink + lmac_cnt); link++) { 4108 nix_hw->tx_credits[link] = tx_credits; 4109 rvu_write64(rvu, blkaddr, 4110 NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg); 4111 } 4112 } 4113 4114 /* Set Tx credits for LBK link */ 4115 slink = hw->cgx_links; 4116 for (link = slink; link < (slink + hw->lbk_links); link++) { 4117 tx_credits = rvu_get_lbk_link_credits(rvu, lbk_max_frs); 4118 nix_hw->tx_credits[link] = tx_credits; 4119 /* Enable credits and set credit pkt count to max allowed */ 4120 tx_credits = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1); 4121 rvu_write64(rvu, blkaddr, 4122 NIX_AF_TX_LINKX_NORM_CREDIT(link), tx_credits); 4123 } 4124 } 4125 4126 static int nix_calibrate_x2p(struct rvu *rvu, int blkaddr) 4127 { 4128 int idx, err; 4129 u64 status; 4130 4131 /* Start X2P bus calibration */ 4132 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4133 rvu_read64(rvu, blkaddr, NIX_AF_CFG) | BIT_ULL(9)); 4134 /* Wait for calibration to complete */ 4135 err = rvu_poll_reg(rvu, blkaddr, 4136 NIX_AF_STATUS, BIT_ULL(10), false); 4137 if (err) { 4138 dev_err(rvu->dev, "NIX X2P bus calibration failed\n"); 4139 return err; 4140 } 4141 4142 status = rvu_read64(rvu, blkaddr, NIX_AF_STATUS); 4143 /* Check if CGX devices are ready */ 4144 for (idx = 0; idx < rvu->cgx_cnt_max; idx++) { 4145 /* Skip when cgx port is not available */ 4146 if (!rvu_cgx_pdata(idx, rvu) || 4147 (status & (BIT_ULL(16 + idx)))) 4148 continue; 4149 dev_err(rvu->dev, 4150 "CGX%d didn't respond to NIX X2P calibration\n", idx); 4151 err = -EBUSY; 4152 } 4153 4154 /* Check if LBK is ready */ 4155 if (!(status & BIT_ULL(19))) { 4156 dev_err(rvu->dev, 4157 "LBK didn't respond to NIX X2P calibration\n"); 4158 err = -EBUSY; 4159 } 4160 4161 /* Clear 'calibrate_x2p' bit */ 4162 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4163 rvu_read64(rvu, blkaddr, NIX_AF_CFG) & ~BIT_ULL(9)); 4164 if (err || (status & 0x3FFULL)) 4165 dev_err(rvu->dev, 4166 "NIX X2P calibration failed, status 0x%llx\n", status); 4167 if (err) 4168 return err; 4169 return 0; 4170 } 4171 4172 static int nix_aq_init(struct rvu *rvu, struct rvu_block *block) 4173 { 4174 u64 cfg; 4175 int err; 4176 4177 /* Set admin queue endianness */ 4178 cfg = rvu_read64(rvu, block->addr, NIX_AF_CFG); 4179 #ifdef __BIG_ENDIAN 4180 cfg |= BIT_ULL(8); 4181 rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg); 4182 #else 4183 cfg &= ~BIT_ULL(8); 4184 rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg); 4185 #endif 4186 4187 /* Do not bypass NDC cache */ 4188 cfg = rvu_read64(rvu, block->addr, NIX_AF_NDC_CFG); 4189 cfg &= ~0x3FFEULL; 4190 #ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING 4191 /* Disable caching of SQB aka SQEs */ 4192 cfg |= 0x04ULL; 4193 #endif 4194 rvu_write64(rvu, block->addr, NIX_AF_NDC_CFG, cfg); 4195 4196 /* Result structure can be followed by RQ/SQ/CQ context at 4197 * RES + 128bytes and a write mask at RES + 256 bytes, depending on 4198 * operation type. Alloc sufficient result memory for all operations. 4199 */ 4200 err = rvu_aq_alloc(rvu, &block->aq, 4201 Q_COUNT(AQ_SIZE), sizeof(struct nix_aq_inst_s), 4202 ALIGN(sizeof(struct nix_aq_res_s), 128) + 256); 4203 if (err) 4204 return err; 4205 4206 rvu_write64(rvu, block->addr, NIX_AF_AQ_CFG, AQ_SIZE); 4207 rvu_write64(rvu, block->addr, 4208 NIX_AF_AQ_BASE, (u64)block->aq->inst->iova); 4209 return 0; 4210 } 4211 4212 static void rvu_nix_setup_capabilities(struct rvu *rvu, int blkaddr) 4213 { 4214 struct rvu_hwinfo *hw = rvu->hw; 4215 u64 hw_const; 4216 4217 hw_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 4218 4219 /* On OcteonTx2 DWRR quantum is directly configured into each of 4220 * the transmit scheduler queues. And PF/VF drivers were free to 4221 * config any value upto 2^24. 4222 * On CN10K, HW is modified, the quantum configuration at scheduler 4223 * queues is in terms of weight. And SW needs to setup a base DWRR MTU 4224 * at NIX_AF_DWRR_RPM_MTU / NIX_AF_DWRR_SDP_MTU. HW will do 4225 * 'DWRR MTU * weight' to get the quantum. 4226 * 4227 * Check if HW uses a common MTU for all DWRR quantum configs. 4228 * On OcteonTx2 this register field is '0'. 4229 */ 4230 if (((hw_const >> 56) & 0x10) == 0x10) 4231 hw->cap.nix_common_dwrr_mtu = true; 4232 } 4233 4234 static int rvu_nix_block_init(struct rvu *rvu, struct nix_hw *nix_hw) 4235 { 4236 const struct npc_lt_def_cfg *ltdefs; 4237 struct rvu_hwinfo *hw = rvu->hw; 4238 int blkaddr = nix_hw->blkaddr; 4239 struct rvu_block *block; 4240 int err; 4241 u64 cfg; 4242 4243 block = &hw->block[blkaddr]; 4244 4245 if (is_rvu_96xx_B0(rvu)) { 4246 /* As per a HW errata in 96xx A0/B0 silicon, NIX may corrupt 4247 * internal state when conditional clocks are turned off. 4248 * Hence enable them. 4249 */ 4250 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4251 rvu_read64(rvu, blkaddr, NIX_AF_CFG) | 0x40ULL); 4252 4253 /* Set chan/link to backpressure TL3 instead of TL2 */ 4254 rvu_write64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL, 0x01); 4255 4256 /* Disable SQ manager's sticky mode operation (set TM6 = 0) 4257 * This sticky mode is known to cause SQ stalls when multiple 4258 * SQs are mapped to same SMQ and transmitting pkts at a time. 4259 */ 4260 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS); 4261 cfg &= ~BIT_ULL(15); 4262 rvu_write64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS, cfg); 4263 } 4264 4265 ltdefs = rvu->kpu.lt_def; 4266 /* Calibrate X2P bus to check if CGX/LBK links are fine */ 4267 err = nix_calibrate_x2p(rvu, blkaddr); 4268 if (err) 4269 return err; 4270 4271 /* Setup capabilities of the NIX block */ 4272 rvu_nix_setup_capabilities(rvu, blkaddr); 4273 4274 /* Initialize admin queue */ 4275 err = nix_aq_init(rvu, block); 4276 if (err) 4277 return err; 4278 4279 /* Restore CINT timer delay to HW reset values */ 4280 rvu_write64(rvu, blkaddr, NIX_AF_CINT_DELAY, 0x0ULL); 4281 4282 /* For better performance use NDC TX instead of NDC RX for SQ's SQEs" */ 4283 rvu_write64(rvu, blkaddr, NIX_AF_SEB_CFG, 0x1ULL); 4284 4285 if (is_block_implemented(hw, blkaddr)) { 4286 err = nix_setup_txschq(rvu, nix_hw, blkaddr); 4287 if (err) 4288 return err; 4289 4290 err = nix_setup_ipolicers(rvu, nix_hw, blkaddr); 4291 if (err) 4292 return err; 4293 4294 err = nix_af_mark_format_setup(rvu, nix_hw, blkaddr); 4295 if (err) 4296 return err; 4297 4298 err = nix_setup_mcast(rvu, nix_hw, blkaddr); 4299 if (err) 4300 return err; 4301 4302 err = nix_setup_txvlan(rvu, nix_hw); 4303 if (err) 4304 return err; 4305 4306 /* Configure segmentation offload formats */ 4307 nix_setup_lso(rvu, nix_hw, blkaddr); 4308 4309 /* Config Outer/Inner L2, IP, TCP, UDP and SCTP NPC layer info. 4310 * This helps HW protocol checker to identify headers 4311 * and validate length and checksums. 4312 */ 4313 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OL2, 4314 (ltdefs->rx_ol2.lid << 8) | (ltdefs->rx_ol2.ltype_match << 4) | 4315 ltdefs->rx_ol2.ltype_mask); 4316 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4, 4317 (ltdefs->rx_oip4.lid << 8) | (ltdefs->rx_oip4.ltype_match << 4) | 4318 ltdefs->rx_oip4.ltype_mask); 4319 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4, 4320 (ltdefs->rx_iip4.lid << 8) | (ltdefs->rx_iip4.ltype_match << 4) | 4321 ltdefs->rx_iip4.ltype_mask); 4322 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6, 4323 (ltdefs->rx_oip6.lid << 8) | (ltdefs->rx_oip6.ltype_match << 4) | 4324 ltdefs->rx_oip6.ltype_mask); 4325 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6, 4326 (ltdefs->rx_iip6.lid << 8) | (ltdefs->rx_iip6.ltype_match << 4) | 4327 ltdefs->rx_iip6.ltype_mask); 4328 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OTCP, 4329 (ltdefs->rx_otcp.lid << 8) | (ltdefs->rx_otcp.ltype_match << 4) | 4330 ltdefs->rx_otcp.ltype_mask); 4331 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ITCP, 4332 (ltdefs->rx_itcp.lid << 8) | (ltdefs->rx_itcp.ltype_match << 4) | 4333 ltdefs->rx_itcp.ltype_mask); 4334 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OUDP, 4335 (ltdefs->rx_oudp.lid << 8) | (ltdefs->rx_oudp.ltype_match << 4) | 4336 ltdefs->rx_oudp.ltype_mask); 4337 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IUDP, 4338 (ltdefs->rx_iudp.lid << 8) | (ltdefs->rx_iudp.ltype_match << 4) | 4339 ltdefs->rx_iudp.ltype_mask); 4340 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OSCTP, 4341 (ltdefs->rx_osctp.lid << 8) | (ltdefs->rx_osctp.ltype_match << 4) | 4342 ltdefs->rx_osctp.ltype_mask); 4343 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ISCTP, 4344 (ltdefs->rx_isctp.lid << 8) | (ltdefs->rx_isctp.ltype_match << 4) | 4345 ltdefs->rx_isctp.ltype_mask); 4346 4347 if (!is_rvu_otx2(rvu)) { 4348 /* Enable APAD calculation for other protocols 4349 * matching APAD0 and APAD1 lt def registers. 4350 */ 4351 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_CST_APAD0, 4352 (ltdefs->rx_apad0.valid << 11) | 4353 (ltdefs->rx_apad0.lid << 8) | 4354 (ltdefs->rx_apad0.ltype_match << 4) | 4355 ltdefs->rx_apad0.ltype_mask); 4356 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_CST_APAD1, 4357 (ltdefs->rx_apad1.valid << 11) | 4358 (ltdefs->rx_apad1.lid << 8) | 4359 (ltdefs->rx_apad1.ltype_match << 4) | 4360 ltdefs->rx_apad1.ltype_mask); 4361 4362 /* Receive ethertype defination register defines layer 4363 * information in NPC_RESULT_S to identify the Ethertype 4364 * location in L2 header. Used for Ethertype overwriting 4365 * in inline IPsec flow. 4366 */ 4367 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ET(0), 4368 (ltdefs->rx_et[0].offset << 12) | 4369 (ltdefs->rx_et[0].valid << 11) | 4370 (ltdefs->rx_et[0].lid << 8) | 4371 (ltdefs->rx_et[0].ltype_match << 4) | 4372 ltdefs->rx_et[0].ltype_mask); 4373 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ET(1), 4374 (ltdefs->rx_et[1].offset << 12) | 4375 (ltdefs->rx_et[1].valid << 11) | 4376 (ltdefs->rx_et[1].lid << 8) | 4377 (ltdefs->rx_et[1].ltype_match << 4) | 4378 ltdefs->rx_et[1].ltype_mask); 4379 } 4380 4381 err = nix_rx_flowkey_alg_cfg(rvu, blkaddr); 4382 if (err) 4383 return err; 4384 4385 nix_hw->tx_credits = kcalloc(hw->cgx_links + hw->lbk_links, 4386 sizeof(u64), GFP_KERNEL); 4387 if (!nix_hw->tx_credits) 4388 return -ENOMEM; 4389 4390 /* Initialize CGX/LBK/SDP link credits, min/max pkt lengths */ 4391 nix_link_config(rvu, blkaddr, nix_hw); 4392 4393 /* Enable Channel backpressure */ 4394 rvu_write64(rvu, blkaddr, NIX_AF_RX_CFG, BIT_ULL(0)); 4395 } 4396 return 0; 4397 } 4398 4399 int rvu_nix_init(struct rvu *rvu) 4400 { 4401 struct rvu_hwinfo *hw = rvu->hw; 4402 struct nix_hw *nix_hw; 4403 int blkaddr = 0, err; 4404 int i = 0; 4405 4406 hw->nix = devm_kcalloc(rvu->dev, MAX_NIX_BLKS, sizeof(struct nix_hw), 4407 GFP_KERNEL); 4408 if (!hw->nix) 4409 return -ENOMEM; 4410 4411 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4412 while (blkaddr) { 4413 nix_hw = &hw->nix[i]; 4414 nix_hw->rvu = rvu; 4415 nix_hw->blkaddr = blkaddr; 4416 err = rvu_nix_block_init(rvu, nix_hw); 4417 if (err) 4418 return err; 4419 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4420 i++; 4421 } 4422 4423 return 0; 4424 } 4425 4426 static void rvu_nix_block_freemem(struct rvu *rvu, int blkaddr, 4427 struct rvu_block *block) 4428 { 4429 struct nix_txsch *txsch; 4430 struct nix_mcast *mcast; 4431 struct nix_txvlan *vlan; 4432 struct nix_hw *nix_hw; 4433 int lvl; 4434 4435 rvu_aq_free(rvu, block->aq); 4436 4437 if (is_block_implemented(rvu->hw, blkaddr)) { 4438 nix_hw = get_nix_hw(rvu->hw, blkaddr); 4439 if (!nix_hw) 4440 return; 4441 4442 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 4443 txsch = &nix_hw->txsch[lvl]; 4444 kfree(txsch->schq.bmap); 4445 } 4446 4447 kfree(nix_hw->tx_credits); 4448 4449 nix_ipolicer_freemem(rvu, nix_hw); 4450 4451 vlan = &nix_hw->txvlan; 4452 kfree(vlan->rsrc.bmap); 4453 mutex_destroy(&vlan->rsrc_lock); 4454 4455 mcast = &nix_hw->mcast; 4456 qmem_free(rvu->dev, mcast->mce_ctx); 4457 qmem_free(rvu->dev, mcast->mcast_buf); 4458 mutex_destroy(&mcast->mce_lock); 4459 } 4460 } 4461 4462 void rvu_nix_freemem(struct rvu *rvu) 4463 { 4464 struct rvu_hwinfo *hw = rvu->hw; 4465 struct rvu_block *block; 4466 int blkaddr = 0; 4467 4468 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4469 while (blkaddr) { 4470 block = &hw->block[blkaddr]; 4471 rvu_nix_block_freemem(rvu, blkaddr, block); 4472 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4473 } 4474 } 4475 4476 int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req, 4477 struct msg_rsp *rsp) 4478 { 4479 u16 pcifunc = req->hdr.pcifunc; 4480 struct rvu_pfvf *pfvf; 4481 int nixlf, err; 4482 4483 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 4484 if (err) 4485 return err; 4486 4487 rvu_npc_enable_default_entries(rvu, pcifunc, nixlf); 4488 4489 npc_mcam_enable_flows(rvu, pcifunc); 4490 4491 pfvf = rvu_get_pfvf(rvu, pcifunc); 4492 set_bit(NIXLF_INITIALIZED, &pfvf->flags); 4493 4494 rvu_switch_update_rules(rvu, pcifunc); 4495 4496 return rvu_cgx_start_stop_io(rvu, pcifunc, true); 4497 } 4498 4499 int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req, 4500 struct msg_rsp *rsp) 4501 { 4502 u16 pcifunc = req->hdr.pcifunc; 4503 struct rvu_pfvf *pfvf; 4504 int nixlf, err; 4505 4506 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 4507 if (err) 4508 return err; 4509 4510 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 4511 4512 pfvf = rvu_get_pfvf(rvu, pcifunc); 4513 clear_bit(NIXLF_INITIALIZED, &pfvf->flags); 4514 4515 return rvu_cgx_start_stop_io(rvu, pcifunc, false); 4516 } 4517 4518 #define RX_SA_BASE GENMASK_ULL(52, 7) 4519 4520 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int nixlf) 4521 { 4522 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 4523 struct hwctx_disable_req ctx_req; 4524 int pf = rvu_get_pf(pcifunc); 4525 struct mac_ops *mac_ops; 4526 u8 cgx_id, lmac_id; 4527 u64 sa_base; 4528 void *cgxd; 4529 int err; 4530 4531 ctx_req.hdr.pcifunc = pcifunc; 4532 4533 /* Cleanup NPC MCAM entries, free Tx scheduler queues being used */ 4534 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 4535 rvu_npc_free_mcam_entries(rvu, pcifunc, nixlf); 4536 nix_interface_deinit(rvu, pcifunc, nixlf); 4537 nix_rx_sync(rvu, blkaddr); 4538 nix_txschq_free(rvu, pcifunc); 4539 4540 clear_bit(NIXLF_INITIALIZED, &pfvf->flags); 4541 4542 rvu_cgx_start_stop_io(rvu, pcifunc, false); 4543 4544 if (pfvf->sq_ctx) { 4545 ctx_req.ctype = NIX_AQ_CTYPE_SQ; 4546 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4547 if (err) 4548 dev_err(rvu->dev, "SQ ctx disable failed\n"); 4549 } 4550 4551 if (pfvf->rq_ctx) { 4552 ctx_req.ctype = NIX_AQ_CTYPE_RQ; 4553 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4554 if (err) 4555 dev_err(rvu->dev, "RQ ctx disable failed\n"); 4556 } 4557 4558 if (pfvf->cq_ctx) { 4559 ctx_req.ctype = NIX_AQ_CTYPE_CQ; 4560 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4561 if (err) 4562 dev_err(rvu->dev, "CQ ctx disable failed\n"); 4563 } 4564 4565 /* reset HW config done for Switch headers */ 4566 rvu_npc_set_parse_mode(rvu, pcifunc, OTX2_PRIV_FLAGS_DEFAULT, 4567 (PKIND_TX | PKIND_RX), 0, 0, 0, 0); 4568 4569 /* Disabling CGX and NPC config done for PTP */ 4570 if (pfvf->hw_rx_tstamp_en) { 4571 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 4572 cgxd = rvu_cgx_pdata(cgx_id, rvu); 4573 mac_ops = get_mac_ops(cgxd); 4574 mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, false); 4575 /* Undo NPC config done for PTP */ 4576 if (npc_config_ts_kpuaction(rvu, pf, pcifunc, false)) 4577 dev_err(rvu->dev, "NPC config for PTP failed\n"); 4578 pfvf->hw_rx_tstamp_en = false; 4579 } 4580 4581 nix_ctx_free(rvu, pfvf); 4582 4583 nix_free_all_bandprof(rvu, pcifunc); 4584 4585 sa_base = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(nixlf)); 4586 if (FIELD_GET(RX_SA_BASE, sa_base)) { 4587 err = rvu_cpt_ctx_flush(rvu, pcifunc); 4588 if (err) 4589 dev_err(rvu->dev, 4590 "CPT ctx flush failed with error: %d\n", err); 4591 } 4592 } 4593 4594 #define NIX_AF_LFX_TX_CFG_PTP_EN BIT_ULL(32) 4595 4596 static int rvu_nix_lf_ptp_tx_cfg(struct rvu *rvu, u16 pcifunc, bool enable) 4597 { 4598 struct rvu_hwinfo *hw = rvu->hw; 4599 struct rvu_block *block; 4600 int blkaddr, pf; 4601 int nixlf; 4602 u64 cfg; 4603 4604 pf = rvu_get_pf(pcifunc); 4605 if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP)) 4606 return 0; 4607 4608 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 4609 if (blkaddr < 0) 4610 return NIX_AF_ERR_AF_LF_INVALID; 4611 4612 block = &hw->block[blkaddr]; 4613 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 4614 if (nixlf < 0) 4615 return NIX_AF_ERR_AF_LF_INVALID; 4616 4617 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf)); 4618 4619 if (enable) 4620 cfg |= NIX_AF_LFX_TX_CFG_PTP_EN; 4621 else 4622 cfg &= ~NIX_AF_LFX_TX_CFG_PTP_EN; 4623 4624 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg); 4625 4626 return 0; 4627 } 4628 4629 int rvu_mbox_handler_nix_lf_ptp_tx_enable(struct rvu *rvu, struct msg_req *req, 4630 struct msg_rsp *rsp) 4631 { 4632 return rvu_nix_lf_ptp_tx_cfg(rvu, req->hdr.pcifunc, true); 4633 } 4634 4635 int rvu_mbox_handler_nix_lf_ptp_tx_disable(struct rvu *rvu, struct msg_req *req, 4636 struct msg_rsp *rsp) 4637 { 4638 return rvu_nix_lf_ptp_tx_cfg(rvu, req->hdr.pcifunc, false); 4639 } 4640 4641 int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu, 4642 struct nix_lso_format_cfg *req, 4643 struct nix_lso_format_cfg_rsp *rsp) 4644 { 4645 u16 pcifunc = req->hdr.pcifunc; 4646 struct nix_hw *nix_hw; 4647 struct rvu_pfvf *pfvf; 4648 int blkaddr, idx, f; 4649 u64 reg; 4650 4651 pfvf = rvu_get_pfvf(rvu, pcifunc); 4652 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 4653 if (!pfvf->nixlf || blkaddr < 0) 4654 return NIX_AF_ERR_AF_LF_INVALID; 4655 4656 nix_hw = get_nix_hw(rvu->hw, blkaddr); 4657 if (!nix_hw) 4658 return NIX_AF_ERR_INVALID_NIXBLK; 4659 4660 /* Find existing matching LSO format, if any */ 4661 for (idx = 0; idx < nix_hw->lso.in_use; idx++) { 4662 for (f = 0; f < NIX_LSO_FIELD_MAX; f++) { 4663 reg = rvu_read64(rvu, blkaddr, 4664 NIX_AF_LSO_FORMATX_FIELDX(idx, f)); 4665 if (req->fields[f] != (reg & req->field_mask)) 4666 break; 4667 } 4668 4669 if (f == NIX_LSO_FIELD_MAX) 4670 break; 4671 } 4672 4673 if (idx < nix_hw->lso.in_use) { 4674 /* Match found */ 4675 rsp->lso_format_idx = idx; 4676 return 0; 4677 } 4678 4679 if (nix_hw->lso.in_use == nix_hw->lso.total) 4680 return NIX_AF_ERR_LSO_CFG_FAIL; 4681 4682 rsp->lso_format_idx = nix_hw->lso.in_use++; 4683 4684 for (f = 0; f < NIX_LSO_FIELD_MAX; f++) 4685 rvu_write64(rvu, blkaddr, 4686 NIX_AF_LSO_FORMATX_FIELDX(rsp->lso_format_idx, f), 4687 req->fields[f]); 4688 4689 return 0; 4690 } 4691 4692 #define IPSEC_GEN_CFG_EGRP GENMASK_ULL(50, 48) 4693 #define IPSEC_GEN_CFG_OPCODE GENMASK_ULL(47, 32) 4694 #define IPSEC_GEN_CFG_PARAM1 GENMASK_ULL(31, 16) 4695 #define IPSEC_GEN_CFG_PARAM2 GENMASK_ULL(15, 0) 4696 4697 #define CPT_INST_QSEL_BLOCK GENMASK_ULL(28, 24) 4698 #define CPT_INST_QSEL_PF_FUNC GENMASK_ULL(23, 8) 4699 #define CPT_INST_QSEL_SLOT GENMASK_ULL(7, 0) 4700 4701 static void nix_inline_ipsec_cfg(struct rvu *rvu, struct nix_inline_ipsec_cfg *req, 4702 int blkaddr) 4703 { 4704 u8 cpt_idx, cpt_blkaddr; 4705 u64 val; 4706 4707 cpt_idx = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 4708 if (req->enable) { 4709 val = 0; 4710 /* Enable context prefetching */ 4711 if (!is_rvu_otx2(rvu)) 4712 val |= BIT_ULL(51); 4713 4714 /* Set OPCODE and EGRP */ 4715 val |= FIELD_PREP(IPSEC_GEN_CFG_EGRP, req->gen_cfg.egrp); 4716 val |= FIELD_PREP(IPSEC_GEN_CFG_OPCODE, req->gen_cfg.opcode); 4717 val |= FIELD_PREP(IPSEC_GEN_CFG_PARAM1, req->gen_cfg.param1); 4718 val |= FIELD_PREP(IPSEC_GEN_CFG_PARAM2, req->gen_cfg.param2); 4719 4720 rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, val); 4721 4722 /* Set CPT queue for inline IPSec */ 4723 val = FIELD_PREP(CPT_INST_QSEL_SLOT, req->inst_qsel.cpt_slot); 4724 val |= FIELD_PREP(CPT_INST_QSEL_PF_FUNC, 4725 req->inst_qsel.cpt_pf_func); 4726 4727 if (!is_rvu_otx2(rvu)) { 4728 cpt_blkaddr = (cpt_idx == 0) ? BLKADDR_CPT0 : 4729 BLKADDR_CPT1; 4730 val |= FIELD_PREP(CPT_INST_QSEL_BLOCK, cpt_blkaddr); 4731 } 4732 4733 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx), 4734 val); 4735 4736 /* Set CPT credit */ 4737 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), 4738 req->cpt_credit); 4739 } else { 4740 rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, 0x0); 4741 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx), 4742 0x0); 4743 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), 4744 0x3FFFFF); 4745 } 4746 } 4747 4748 int rvu_mbox_handler_nix_inline_ipsec_cfg(struct rvu *rvu, 4749 struct nix_inline_ipsec_cfg *req, 4750 struct msg_rsp *rsp) 4751 { 4752 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) 4753 return 0; 4754 4755 nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX0); 4756 if (is_block_implemented(rvu->hw, BLKADDR_CPT1)) 4757 nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX1); 4758 4759 return 0; 4760 } 4761 4762 int rvu_mbox_handler_nix_inline_ipsec_lf_cfg(struct rvu *rvu, 4763 struct nix_inline_ipsec_lf_cfg *req, 4764 struct msg_rsp *rsp) 4765 { 4766 int lf, blkaddr, err; 4767 u64 val; 4768 4769 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) 4770 return 0; 4771 4772 err = nix_get_nixlf(rvu, req->hdr.pcifunc, &lf, &blkaddr); 4773 if (err) 4774 return err; 4775 4776 if (req->enable) { 4777 /* Set TT, TAG_CONST, SA_POW2_SIZE and LENM1_MAX */ 4778 val = (u64)req->ipsec_cfg0.tt << 44 | 4779 (u64)req->ipsec_cfg0.tag_const << 20 | 4780 (u64)req->ipsec_cfg0.sa_pow2_size << 16 | 4781 req->ipsec_cfg0.lenm1_max; 4782 4783 if (blkaddr == BLKADDR_NIX1) 4784 val |= BIT_ULL(46); 4785 4786 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG0(lf), val); 4787 4788 /* Set SA_IDX_W and SA_IDX_MAX */ 4789 val = (u64)req->ipsec_cfg1.sa_idx_w << 32 | 4790 req->ipsec_cfg1.sa_idx_max; 4791 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(lf), val); 4792 4793 /* Set SA base address */ 4794 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(lf), 4795 req->sa_base_addr); 4796 } else { 4797 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG0(lf), 0x0); 4798 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(lf), 0x0); 4799 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(lf), 4800 0x0); 4801 } 4802 4803 return 0; 4804 } 4805 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc) 4806 { 4807 bool from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK); 4808 4809 /* overwrite vf mac address with default_mac */ 4810 if (from_vf) 4811 ether_addr_copy(pfvf->mac_addr, pfvf->default_mac); 4812 } 4813 4814 /* NIX ingress policers or bandwidth profiles APIs */ 4815 static void nix_config_rx_pkt_policer_precolor(struct rvu *rvu, int blkaddr) 4816 { 4817 struct npc_lt_def_cfg defs, *ltdefs; 4818 4819 ltdefs = &defs; 4820 memcpy(ltdefs, rvu->kpu.lt_def, sizeof(struct npc_lt_def_cfg)); 4821 4822 /* Extract PCP and DEI fields from outer VLAN from byte offset 4823 * 2 from the start of LB_PTR (ie TAG). 4824 * VLAN0 is Outer VLAN and VLAN1 is Inner VLAN. Inner VLAN 4825 * fields are considered when 'Tunnel enable' is set in profile. 4826 */ 4827 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN0_PCP_DEI, 4828 (2UL << 12) | (ltdefs->ovlan.lid << 8) | 4829 (ltdefs->ovlan.ltype_match << 4) | 4830 ltdefs->ovlan.ltype_mask); 4831 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN1_PCP_DEI, 4832 (2UL << 12) | (ltdefs->ivlan.lid << 8) | 4833 (ltdefs->ivlan.ltype_match << 4) | 4834 ltdefs->ivlan.ltype_mask); 4835 4836 /* DSCP field in outer and tunneled IPv4 packets */ 4837 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4_DSCP, 4838 (1UL << 12) | (ltdefs->rx_oip4.lid << 8) | 4839 (ltdefs->rx_oip4.ltype_match << 4) | 4840 ltdefs->rx_oip4.ltype_mask); 4841 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4_DSCP, 4842 (1UL << 12) | (ltdefs->rx_iip4.lid << 8) | 4843 (ltdefs->rx_iip4.ltype_match << 4) | 4844 ltdefs->rx_iip4.ltype_mask); 4845 4846 /* DSCP field (traffic class) in outer and tunneled IPv6 packets */ 4847 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6_DSCP, 4848 (1UL << 11) | (ltdefs->rx_oip6.lid << 8) | 4849 (ltdefs->rx_oip6.ltype_match << 4) | 4850 ltdefs->rx_oip6.ltype_mask); 4851 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6_DSCP, 4852 (1UL << 11) | (ltdefs->rx_iip6.lid << 8) | 4853 (ltdefs->rx_iip6.ltype_match << 4) | 4854 ltdefs->rx_iip6.ltype_mask); 4855 } 4856 4857 static int nix_init_policer_context(struct rvu *rvu, struct nix_hw *nix_hw, 4858 int layer, int prof_idx) 4859 { 4860 struct nix_cn10k_aq_enq_req aq_req; 4861 int rc; 4862 4863 memset(&aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 4864 4865 aq_req.qidx = (prof_idx & 0x3FFF) | (layer << 14); 4866 aq_req.ctype = NIX_AQ_CTYPE_BANDPROF; 4867 aq_req.op = NIX_AQ_INSTOP_INIT; 4868 4869 /* Context is all zeros, submit to AQ */ 4870 rc = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 4871 (struct nix_aq_enq_req *)&aq_req, NULL); 4872 if (rc) 4873 dev_err(rvu->dev, "Failed to INIT bandwidth profile layer %d profile %d\n", 4874 layer, prof_idx); 4875 return rc; 4876 } 4877 4878 static int nix_setup_ipolicers(struct rvu *rvu, 4879 struct nix_hw *nix_hw, int blkaddr) 4880 { 4881 struct rvu_hwinfo *hw = rvu->hw; 4882 struct nix_ipolicer *ipolicer; 4883 int err, layer, prof_idx; 4884 u64 cfg; 4885 4886 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST); 4887 if (!(cfg & BIT_ULL(61))) { 4888 hw->cap.ipolicer = false; 4889 return 0; 4890 } 4891 4892 hw->cap.ipolicer = true; 4893 nix_hw->ipolicer = devm_kcalloc(rvu->dev, BAND_PROF_NUM_LAYERS, 4894 sizeof(*ipolicer), GFP_KERNEL); 4895 if (!nix_hw->ipolicer) 4896 return -ENOMEM; 4897 4898 cfg = rvu_read64(rvu, blkaddr, NIX_AF_PL_CONST); 4899 4900 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 4901 ipolicer = &nix_hw->ipolicer[layer]; 4902 switch (layer) { 4903 case BAND_PROF_LEAF_LAYER: 4904 ipolicer->band_prof.max = cfg & 0XFFFF; 4905 break; 4906 case BAND_PROF_MID_LAYER: 4907 ipolicer->band_prof.max = (cfg >> 16) & 0XFFFF; 4908 break; 4909 case BAND_PROF_TOP_LAYER: 4910 ipolicer->band_prof.max = (cfg >> 32) & 0XFFFF; 4911 break; 4912 } 4913 4914 if (!ipolicer->band_prof.max) 4915 continue; 4916 4917 err = rvu_alloc_bitmap(&ipolicer->band_prof); 4918 if (err) 4919 return err; 4920 4921 ipolicer->pfvf_map = devm_kcalloc(rvu->dev, 4922 ipolicer->band_prof.max, 4923 sizeof(u16), GFP_KERNEL); 4924 if (!ipolicer->pfvf_map) 4925 return -ENOMEM; 4926 4927 ipolicer->match_id = devm_kcalloc(rvu->dev, 4928 ipolicer->band_prof.max, 4929 sizeof(u16), GFP_KERNEL); 4930 if (!ipolicer->match_id) 4931 return -ENOMEM; 4932 4933 for (prof_idx = 0; 4934 prof_idx < ipolicer->band_prof.max; prof_idx++) { 4935 /* Set AF as current owner for INIT ops to succeed */ 4936 ipolicer->pfvf_map[prof_idx] = 0x00; 4937 4938 /* There is no enable bit in the profile context, 4939 * so no context disable. So let's INIT them here 4940 * so that PF/VF later on have to just do WRITE to 4941 * setup policer rates and config. 4942 */ 4943 err = nix_init_policer_context(rvu, nix_hw, 4944 layer, prof_idx); 4945 if (err) 4946 return err; 4947 } 4948 4949 /* Allocate memory for maintaining ref_counts for MID level 4950 * profiles, this will be needed for leaf layer profiles' 4951 * aggregation. 4952 */ 4953 if (layer != BAND_PROF_MID_LAYER) 4954 continue; 4955 4956 ipolicer->ref_count = devm_kcalloc(rvu->dev, 4957 ipolicer->band_prof.max, 4958 sizeof(u16), GFP_KERNEL); 4959 } 4960 4961 /* Set policer timeunit to 2us ie (19 + 1) * 100 nsec = 2us */ 4962 rvu_write64(rvu, blkaddr, NIX_AF_PL_TS, 19); 4963 4964 nix_config_rx_pkt_policer_precolor(rvu, blkaddr); 4965 4966 return 0; 4967 } 4968 4969 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw) 4970 { 4971 struct nix_ipolicer *ipolicer; 4972 int layer; 4973 4974 if (!rvu->hw->cap.ipolicer) 4975 return; 4976 4977 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 4978 ipolicer = &nix_hw->ipolicer[layer]; 4979 4980 if (!ipolicer->band_prof.max) 4981 continue; 4982 4983 kfree(ipolicer->band_prof.bmap); 4984 } 4985 } 4986 4987 static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req, 4988 struct nix_hw *nix_hw, u16 pcifunc) 4989 { 4990 struct nix_ipolicer *ipolicer; 4991 int layer, hi_layer, prof_idx; 4992 4993 /* Bits [15:14] in profile index represent layer */ 4994 layer = (req->qidx >> 14) & 0x03; 4995 prof_idx = req->qidx & 0x3FFF; 4996 4997 ipolicer = &nix_hw->ipolicer[layer]; 4998 if (prof_idx >= ipolicer->band_prof.max) 4999 return -EINVAL; 5000 5001 /* Check if the profile is allocated to the requesting PCIFUNC or not 5002 * with the exception of AF. AF is allowed to read and update contexts. 5003 */ 5004 if (pcifunc && ipolicer->pfvf_map[prof_idx] != pcifunc) 5005 return -EINVAL; 5006 5007 /* If this profile is linked to higher layer profile then check 5008 * if that profile is also allocated to the requesting PCIFUNC 5009 * or not. 5010 */ 5011 if (!req->prof.hl_en) 5012 return 0; 5013 5014 /* Leaf layer profile can link only to mid layer and 5015 * mid layer to top layer. 5016 */ 5017 if (layer == BAND_PROF_LEAF_LAYER) 5018 hi_layer = BAND_PROF_MID_LAYER; 5019 else if (layer == BAND_PROF_MID_LAYER) 5020 hi_layer = BAND_PROF_TOP_LAYER; 5021 else 5022 return -EINVAL; 5023 5024 ipolicer = &nix_hw->ipolicer[hi_layer]; 5025 prof_idx = req->prof.band_prof_id; 5026 if (prof_idx >= ipolicer->band_prof.max || 5027 ipolicer->pfvf_map[prof_idx] != pcifunc) 5028 return -EINVAL; 5029 5030 return 0; 5031 } 5032 5033 int rvu_mbox_handler_nix_bandprof_alloc(struct rvu *rvu, 5034 struct nix_bandprof_alloc_req *req, 5035 struct nix_bandprof_alloc_rsp *rsp) 5036 { 5037 int blkaddr, layer, prof, idx, err; 5038 u16 pcifunc = req->hdr.pcifunc; 5039 struct nix_ipolicer *ipolicer; 5040 struct nix_hw *nix_hw; 5041 5042 if (!rvu->hw->cap.ipolicer) 5043 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5044 5045 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5046 if (err) 5047 return err; 5048 5049 mutex_lock(&rvu->rsrc_lock); 5050 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5051 if (layer == BAND_PROF_INVAL_LAYER) 5052 continue; 5053 if (!req->prof_count[layer]) 5054 continue; 5055 5056 ipolicer = &nix_hw->ipolicer[layer]; 5057 for (idx = 0; idx < req->prof_count[layer]; idx++) { 5058 /* Allocate a max of 'MAX_BANDPROF_PER_PFFUNC' profiles */ 5059 if (idx == MAX_BANDPROF_PER_PFFUNC) 5060 break; 5061 5062 prof = rvu_alloc_rsrc(&ipolicer->band_prof); 5063 if (prof < 0) 5064 break; 5065 rsp->prof_count[layer]++; 5066 rsp->prof_idx[layer][idx] = prof; 5067 ipolicer->pfvf_map[prof] = pcifunc; 5068 } 5069 } 5070 mutex_unlock(&rvu->rsrc_lock); 5071 return 0; 5072 } 5073 5074 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc) 5075 { 5076 int blkaddr, layer, prof_idx, err; 5077 struct nix_ipolicer *ipolicer; 5078 struct nix_hw *nix_hw; 5079 5080 if (!rvu->hw->cap.ipolicer) 5081 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5082 5083 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5084 if (err) 5085 return err; 5086 5087 mutex_lock(&rvu->rsrc_lock); 5088 /* Free all the profiles allocated to the PCIFUNC */ 5089 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5090 if (layer == BAND_PROF_INVAL_LAYER) 5091 continue; 5092 ipolicer = &nix_hw->ipolicer[layer]; 5093 5094 for (prof_idx = 0; prof_idx < ipolicer->band_prof.max; prof_idx++) { 5095 if (ipolicer->pfvf_map[prof_idx] != pcifunc) 5096 continue; 5097 5098 /* Clear ratelimit aggregation, if any */ 5099 if (layer == BAND_PROF_LEAF_LAYER && 5100 ipolicer->match_id[prof_idx]) 5101 nix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx); 5102 5103 ipolicer->pfvf_map[prof_idx] = 0x00; 5104 ipolicer->match_id[prof_idx] = 0; 5105 rvu_free_rsrc(&ipolicer->band_prof, prof_idx); 5106 } 5107 } 5108 mutex_unlock(&rvu->rsrc_lock); 5109 return 0; 5110 } 5111 5112 int rvu_mbox_handler_nix_bandprof_free(struct rvu *rvu, 5113 struct nix_bandprof_free_req *req, 5114 struct msg_rsp *rsp) 5115 { 5116 int blkaddr, layer, prof_idx, idx, err; 5117 u16 pcifunc = req->hdr.pcifunc; 5118 struct nix_ipolicer *ipolicer; 5119 struct nix_hw *nix_hw; 5120 5121 if (req->free_all) 5122 return nix_free_all_bandprof(rvu, pcifunc); 5123 5124 if (!rvu->hw->cap.ipolicer) 5125 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5126 5127 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5128 if (err) 5129 return err; 5130 5131 mutex_lock(&rvu->rsrc_lock); 5132 /* Free the requested profile indices */ 5133 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5134 if (layer == BAND_PROF_INVAL_LAYER) 5135 continue; 5136 if (!req->prof_count[layer]) 5137 continue; 5138 5139 ipolicer = &nix_hw->ipolicer[layer]; 5140 for (idx = 0; idx < req->prof_count[layer]; idx++) { 5141 prof_idx = req->prof_idx[layer][idx]; 5142 if (prof_idx >= ipolicer->band_prof.max || 5143 ipolicer->pfvf_map[prof_idx] != pcifunc) 5144 continue; 5145 5146 /* Clear ratelimit aggregation, if any */ 5147 if (layer == BAND_PROF_LEAF_LAYER && 5148 ipolicer->match_id[prof_idx]) 5149 nix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx); 5150 5151 ipolicer->pfvf_map[prof_idx] = 0x00; 5152 ipolicer->match_id[prof_idx] = 0; 5153 rvu_free_rsrc(&ipolicer->band_prof, prof_idx); 5154 if (idx == MAX_BANDPROF_PER_PFFUNC) 5155 break; 5156 } 5157 } 5158 mutex_unlock(&rvu->rsrc_lock); 5159 return 0; 5160 } 5161 5162 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 5163 struct nix_cn10k_aq_enq_req *aq_req, 5164 struct nix_cn10k_aq_enq_rsp *aq_rsp, 5165 u16 pcifunc, u8 ctype, u32 qidx) 5166 { 5167 memset(aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5168 aq_req->hdr.pcifunc = pcifunc; 5169 aq_req->ctype = ctype; 5170 aq_req->op = NIX_AQ_INSTOP_READ; 5171 aq_req->qidx = qidx; 5172 5173 return rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5174 (struct nix_aq_enq_req *)aq_req, 5175 (struct nix_aq_enq_rsp *)aq_rsp); 5176 } 5177 5178 static int nix_ipolicer_map_leaf_midprofs(struct rvu *rvu, 5179 struct nix_hw *nix_hw, 5180 struct nix_cn10k_aq_enq_req *aq_req, 5181 struct nix_cn10k_aq_enq_rsp *aq_rsp, 5182 u32 leaf_prof, u16 mid_prof) 5183 { 5184 memset(aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5185 aq_req->hdr.pcifunc = 0x00; 5186 aq_req->ctype = NIX_AQ_CTYPE_BANDPROF; 5187 aq_req->op = NIX_AQ_INSTOP_WRITE; 5188 aq_req->qidx = leaf_prof; 5189 5190 aq_req->prof.band_prof_id = mid_prof; 5191 aq_req->prof_mask.band_prof_id = GENMASK(6, 0); 5192 aq_req->prof.hl_en = 1; 5193 aq_req->prof_mask.hl_en = 1; 5194 5195 return rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5196 (struct nix_aq_enq_req *)aq_req, 5197 (struct nix_aq_enq_rsp *)aq_rsp); 5198 } 5199 5200 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 5201 u16 rq_idx, u16 match_id) 5202 { 5203 int leaf_prof, mid_prof, leaf_match; 5204 struct nix_cn10k_aq_enq_req aq_req; 5205 struct nix_cn10k_aq_enq_rsp aq_rsp; 5206 struct nix_ipolicer *ipolicer; 5207 struct nix_hw *nix_hw; 5208 int blkaddr, idx, rc; 5209 5210 if (!rvu->hw->cap.ipolicer) 5211 return 0; 5212 5213 rc = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5214 if (rc) 5215 return rc; 5216 5217 /* Fetch the RQ's context to see if policing is enabled */ 5218 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, pcifunc, 5219 NIX_AQ_CTYPE_RQ, rq_idx); 5220 if (rc) { 5221 dev_err(rvu->dev, 5222 "%s: Failed to fetch RQ%d context of PFFUNC 0x%x\n", 5223 __func__, rq_idx, pcifunc); 5224 return rc; 5225 } 5226 5227 if (!aq_rsp.rq.policer_ena) 5228 return 0; 5229 5230 /* Get the bandwidth profile ID mapped to this RQ */ 5231 leaf_prof = aq_rsp.rq.band_prof_id; 5232 5233 ipolicer = &nix_hw->ipolicer[BAND_PROF_LEAF_LAYER]; 5234 ipolicer->match_id[leaf_prof] = match_id; 5235 5236 /* Check if any other leaf profile is marked with same match_id */ 5237 for (idx = 0; idx < ipolicer->band_prof.max; idx++) { 5238 if (idx == leaf_prof) 5239 continue; 5240 if (ipolicer->match_id[idx] != match_id) 5241 continue; 5242 5243 leaf_match = idx; 5244 break; 5245 } 5246 5247 if (idx == ipolicer->band_prof.max) 5248 return 0; 5249 5250 /* Fetch the matching profile's context to check if it's already 5251 * mapped to a mid level profile. 5252 */ 5253 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5254 NIX_AQ_CTYPE_BANDPROF, leaf_match); 5255 if (rc) { 5256 dev_err(rvu->dev, 5257 "%s: Failed to fetch context of leaf profile %d\n", 5258 __func__, leaf_match); 5259 return rc; 5260 } 5261 5262 ipolicer = &nix_hw->ipolicer[BAND_PROF_MID_LAYER]; 5263 if (aq_rsp.prof.hl_en) { 5264 /* Get Mid layer prof index and map leaf_prof index 5265 * also such that flows that are being steered 5266 * to different RQs and marked with same match_id 5267 * are rate limited in a aggregate fashion 5268 */ 5269 mid_prof = aq_rsp.prof.band_prof_id; 5270 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5271 &aq_req, &aq_rsp, 5272 leaf_prof, mid_prof); 5273 if (rc) { 5274 dev_err(rvu->dev, 5275 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5276 __func__, leaf_prof, mid_prof); 5277 goto exit; 5278 } 5279 5280 mutex_lock(&rvu->rsrc_lock); 5281 ipolicer->ref_count[mid_prof]++; 5282 mutex_unlock(&rvu->rsrc_lock); 5283 goto exit; 5284 } 5285 5286 /* Allocate a mid layer profile and 5287 * map both 'leaf_prof' and 'leaf_match' profiles to it. 5288 */ 5289 mutex_lock(&rvu->rsrc_lock); 5290 mid_prof = rvu_alloc_rsrc(&ipolicer->band_prof); 5291 if (mid_prof < 0) { 5292 dev_err(rvu->dev, 5293 "%s: Unable to allocate mid layer profile\n", __func__); 5294 mutex_unlock(&rvu->rsrc_lock); 5295 goto exit; 5296 } 5297 mutex_unlock(&rvu->rsrc_lock); 5298 ipolicer->pfvf_map[mid_prof] = 0x00; 5299 ipolicer->ref_count[mid_prof] = 0; 5300 5301 /* Initialize mid layer profile same as 'leaf_prof' */ 5302 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5303 NIX_AQ_CTYPE_BANDPROF, leaf_prof); 5304 if (rc) { 5305 dev_err(rvu->dev, 5306 "%s: Failed to fetch context of leaf profile %d\n", 5307 __func__, leaf_prof); 5308 goto exit; 5309 } 5310 5311 memset(&aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5312 aq_req.hdr.pcifunc = 0x00; 5313 aq_req.qidx = (mid_prof & 0x3FFF) | (BAND_PROF_MID_LAYER << 14); 5314 aq_req.ctype = NIX_AQ_CTYPE_BANDPROF; 5315 aq_req.op = NIX_AQ_INSTOP_WRITE; 5316 memcpy(&aq_req.prof, &aq_rsp.prof, sizeof(struct nix_bandprof_s)); 5317 /* Clear higher layer enable bit in the mid profile, just in case */ 5318 aq_req.prof.hl_en = 0; 5319 aq_req.prof_mask.hl_en = 1; 5320 5321 rc = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5322 (struct nix_aq_enq_req *)&aq_req, NULL); 5323 if (rc) { 5324 dev_err(rvu->dev, 5325 "%s: Failed to INIT context of mid layer profile %d\n", 5326 __func__, mid_prof); 5327 goto exit; 5328 } 5329 5330 /* Map both leaf profiles to this mid layer profile */ 5331 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5332 &aq_req, &aq_rsp, 5333 leaf_prof, mid_prof); 5334 if (rc) { 5335 dev_err(rvu->dev, 5336 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5337 __func__, leaf_prof, mid_prof); 5338 goto exit; 5339 } 5340 5341 mutex_lock(&rvu->rsrc_lock); 5342 ipolicer->ref_count[mid_prof]++; 5343 mutex_unlock(&rvu->rsrc_lock); 5344 5345 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5346 &aq_req, &aq_rsp, 5347 leaf_match, mid_prof); 5348 if (rc) { 5349 dev_err(rvu->dev, 5350 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5351 __func__, leaf_match, mid_prof); 5352 ipolicer->ref_count[mid_prof]--; 5353 goto exit; 5354 } 5355 5356 mutex_lock(&rvu->rsrc_lock); 5357 ipolicer->ref_count[mid_prof]++; 5358 mutex_unlock(&rvu->rsrc_lock); 5359 5360 exit: 5361 return rc; 5362 } 5363 5364 /* Called with mutex rsrc_lock */ 5365 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw, 5366 u32 leaf_prof) 5367 { 5368 struct nix_cn10k_aq_enq_req aq_req; 5369 struct nix_cn10k_aq_enq_rsp aq_rsp; 5370 struct nix_ipolicer *ipolicer; 5371 u16 mid_prof; 5372 int rc; 5373 5374 mutex_unlock(&rvu->rsrc_lock); 5375 5376 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5377 NIX_AQ_CTYPE_BANDPROF, leaf_prof); 5378 5379 mutex_lock(&rvu->rsrc_lock); 5380 if (rc) { 5381 dev_err(rvu->dev, 5382 "%s: Failed to fetch context of leaf profile %d\n", 5383 __func__, leaf_prof); 5384 return; 5385 } 5386 5387 if (!aq_rsp.prof.hl_en) 5388 return; 5389 5390 mid_prof = aq_rsp.prof.band_prof_id; 5391 ipolicer = &nix_hw->ipolicer[BAND_PROF_MID_LAYER]; 5392 ipolicer->ref_count[mid_prof]--; 5393 /* If ref_count is zero, free mid layer profile */ 5394 if (!ipolicer->ref_count[mid_prof]) { 5395 ipolicer->pfvf_map[mid_prof] = 0x00; 5396 rvu_free_rsrc(&ipolicer->band_prof, mid_prof); 5397 } 5398 } 5399 5400 int rvu_mbox_handler_nix_bandprof_get_hwinfo(struct rvu *rvu, struct msg_req *req, 5401 struct nix_bandprof_get_hwinfo_rsp *rsp) 5402 { 5403 struct nix_ipolicer *ipolicer; 5404 int blkaddr, layer, err; 5405 struct nix_hw *nix_hw; 5406 u64 tu; 5407 5408 if (!rvu->hw->cap.ipolicer) 5409 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5410 5411 err = nix_get_struct_ptrs(rvu, req->hdr.pcifunc, &nix_hw, &blkaddr); 5412 if (err) 5413 return err; 5414 5415 /* Return number of bandwidth profiles free at each layer */ 5416 mutex_lock(&rvu->rsrc_lock); 5417 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5418 if (layer == BAND_PROF_INVAL_LAYER) 5419 continue; 5420 5421 ipolicer = &nix_hw->ipolicer[layer]; 5422 rsp->prof_count[layer] = rvu_rsrc_free_count(&ipolicer->band_prof); 5423 } 5424 mutex_unlock(&rvu->rsrc_lock); 5425 5426 /* Set the policer timeunit in nanosec */ 5427 tu = rvu_read64(rvu, blkaddr, NIX_AF_PL_TS) & GENMASK_ULL(9, 0); 5428 rsp->policer_timeunit = (tu + 1) * 100; 5429 5430 return 0; 5431 } 5432