1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/pci.h> 10 11 #include "rvu_struct.h" 12 #include "rvu_reg.h" 13 #include "rvu.h" 14 #include "npc.h" 15 #include "cgx.h" 16 #include "lmac_common.h" 17 #include "rvu_npc_hash.h" 18 19 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc); 20 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, 21 int type, int chan_id); 22 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc, 23 int type, bool add); 24 static int nix_setup_ipolicers(struct rvu *rvu, 25 struct nix_hw *nix_hw, int blkaddr); 26 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw); 27 static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req, 28 struct nix_hw *nix_hw, u16 pcifunc); 29 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc); 30 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw, 31 u32 leaf_prof); 32 static const char *nix_get_ctx_name(int ctype); 33 34 enum mc_tbl_sz { 35 MC_TBL_SZ_256, 36 MC_TBL_SZ_512, 37 MC_TBL_SZ_1K, 38 MC_TBL_SZ_2K, 39 MC_TBL_SZ_4K, 40 MC_TBL_SZ_8K, 41 MC_TBL_SZ_16K, 42 MC_TBL_SZ_32K, 43 MC_TBL_SZ_64K, 44 }; 45 46 enum mc_buf_cnt { 47 MC_BUF_CNT_8, 48 MC_BUF_CNT_16, 49 MC_BUF_CNT_32, 50 MC_BUF_CNT_64, 51 MC_BUF_CNT_128, 52 MC_BUF_CNT_256, 53 MC_BUF_CNT_512, 54 MC_BUF_CNT_1024, 55 MC_BUF_CNT_2048, 56 }; 57 58 enum nix_makr_fmt_indexes { 59 NIX_MARK_CFG_IP_DSCP_RED, 60 NIX_MARK_CFG_IP_DSCP_YELLOW, 61 NIX_MARK_CFG_IP_DSCP_YELLOW_RED, 62 NIX_MARK_CFG_IP_ECN_RED, 63 NIX_MARK_CFG_IP_ECN_YELLOW, 64 NIX_MARK_CFG_IP_ECN_YELLOW_RED, 65 NIX_MARK_CFG_VLAN_DEI_RED, 66 NIX_MARK_CFG_VLAN_DEI_YELLOW, 67 NIX_MARK_CFG_VLAN_DEI_YELLOW_RED, 68 NIX_MARK_CFG_MAX, 69 }; 70 71 /* For now considering MC resources needed for broadcast 72 * pkt replication only. i.e 256 HWVFs + 12 PFs. 73 */ 74 #define MC_TBL_SIZE MC_TBL_SZ_512 75 #define MC_BUF_CNT MC_BUF_CNT_128 76 77 struct mce { 78 struct hlist_node node; 79 u16 pcifunc; 80 }; 81 82 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr) 83 { 84 int i = 0; 85 86 /*If blkaddr is 0, return the first nix block address*/ 87 if (blkaddr == 0) 88 return rvu->nix_blkaddr[blkaddr]; 89 90 while (i + 1 < MAX_NIX_BLKS) { 91 if (rvu->nix_blkaddr[i] == blkaddr) 92 return rvu->nix_blkaddr[i + 1]; 93 i++; 94 } 95 96 return 0; 97 } 98 99 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc) 100 { 101 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 102 int blkaddr; 103 104 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 105 if (!pfvf->nixlf || blkaddr < 0) 106 return false; 107 return true; 108 } 109 110 int rvu_get_nixlf_count(struct rvu *rvu) 111 { 112 int blkaddr = 0, max = 0; 113 struct rvu_block *block; 114 115 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 116 while (blkaddr) { 117 block = &rvu->hw->block[blkaddr]; 118 max += block->lf.max; 119 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 120 } 121 return max; 122 } 123 124 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr) 125 { 126 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 127 struct rvu_hwinfo *hw = rvu->hw; 128 int blkaddr; 129 130 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 131 if (!pfvf->nixlf || blkaddr < 0) 132 return NIX_AF_ERR_AF_LF_INVALID; 133 134 *nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 135 if (*nixlf < 0) 136 return NIX_AF_ERR_AF_LF_INVALID; 137 138 if (nix_blkaddr) 139 *nix_blkaddr = blkaddr; 140 141 return 0; 142 } 143 144 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 145 struct nix_hw **nix_hw, int *blkaddr) 146 { 147 struct rvu_pfvf *pfvf; 148 149 pfvf = rvu_get_pfvf(rvu, pcifunc); 150 *blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 151 if (!pfvf->nixlf || *blkaddr < 0) 152 return NIX_AF_ERR_AF_LF_INVALID; 153 154 *nix_hw = get_nix_hw(rvu->hw, *blkaddr); 155 if (!*nix_hw) 156 return NIX_AF_ERR_INVALID_NIXBLK; 157 return 0; 158 } 159 160 static void nix_mce_list_init(struct nix_mce_list *list, int max) 161 { 162 INIT_HLIST_HEAD(&list->head); 163 list->count = 0; 164 list->max = max; 165 } 166 167 static u16 nix_alloc_mce_list(struct nix_mcast *mcast, int count) 168 { 169 int idx; 170 171 if (!mcast) 172 return 0; 173 174 idx = mcast->next_free_mce; 175 mcast->next_free_mce += count; 176 return idx; 177 } 178 179 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr) 180 { 181 int nix_blkaddr = 0, i = 0; 182 struct rvu *rvu = hw->rvu; 183 184 nix_blkaddr = rvu_get_next_nix_blkaddr(rvu, nix_blkaddr); 185 while (nix_blkaddr) { 186 if (blkaddr == nix_blkaddr && hw->nix) 187 return &hw->nix[i]; 188 nix_blkaddr = rvu_get_next_nix_blkaddr(rvu, nix_blkaddr); 189 i++; 190 } 191 return NULL; 192 } 193 194 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu) 195 { 196 dwrr_mtu &= 0x1FULL; 197 198 /* MTU used for DWRR calculation is in power of 2 up until 64K bytes. 199 * Value of 4 is reserved for MTU value of 9728 bytes. 200 * Value of 5 is reserved for MTU value of 10240 bytes. 201 */ 202 switch (dwrr_mtu) { 203 case 4: 204 return 9728; 205 case 5: 206 return 10240; 207 default: 208 return BIT_ULL(dwrr_mtu); 209 } 210 211 return 0; 212 } 213 214 u32 convert_bytes_to_dwrr_mtu(u32 bytes) 215 { 216 /* MTU used for DWRR calculation is in power of 2 up until 64K bytes. 217 * Value of 4 is reserved for MTU value of 9728 bytes. 218 * Value of 5 is reserved for MTU value of 10240 bytes. 219 */ 220 if (bytes > BIT_ULL(16)) 221 return 0; 222 223 switch (bytes) { 224 case 9728: 225 return 4; 226 case 10240: 227 return 5; 228 default: 229 return ilog2(bytes); 230 } 231 232 return 0; 233 } 234 235 static void nix_rx_sync(struct rvu *rvu, int blkaddr) 236 { 237 int err; 238 239 /* Sync all in flight RX packets to LLC/DRAM */ 240 rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); 241 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true); 242 if (err) 243 dev_err(rvu->dev, "SYNC1: NIX RX software sync failed\n"); 244 245 /* SW_SYNC ensures all existing transactions are finished and pkts 246 * are written to LLC/DRAM, queues should be teared down after 247 * successful SW_SYNC. Due to a HW errata, in some rare scenarios 248 * an existing transaction might end after SW_SYNC operation. To 249 * ensure operation is fully done, do the SW_SYNC twice. 250 */ 251 rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); 252 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true); 253 if (err) 254 dev_err(rvu->dev, "SYNC2: NIX RX software sync failed\n"); 255 } 256 257 static bool is_valid_txschq(struct rvu *rvu, int blkaddr, 258 int lvl, u16 pcifunc, u16 schq) 259 { 260 struct rvu_hwinfo *hw = rvu->hw; 261 struct nix_txsch *txsch; 262 struct nix_hw *nix_hw; 263 u16 map_func; 264 265 nix_hw = get_nix_hw(rvu->hw, blkaddr); 266 if (!nix_hw) 267 return false; 268 269 txsch = &nix_hw->txsch[lvl]; 270 /* Check out of bounds */ 271 if (schq >= txsch->schq.max) 272 return false; 273 274 mutex_lock(&rvu->rsrc_lock); 275 map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]); 276 mutex_unlock(&rvu->rsrc_lock); 277 278 /* TLs aggegating traffic are shared across PF and VFs */ 279 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 280 if (rvu_get_pf(map_func) != rvu_get_pf(pcifunc)) 281 return false; 282 else 283 return true; 284 } 285 286 if (map_func != pcifunc) 287 return false; 288 289 return true; 290 } 291 292 static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf, 293 struct nix_lf_alloc_rsp *rsp, bool loop) 294 { 295 struct rvu_pfvf *parent_pf, *pfvf = rvu_get_pfvf(rvu, pcifunc); 296 u16 req_chan_base, req_chan_end, req_chan_cnt; 297 struct rvu_hwinfo *hw = rvu->hw; 298 struct sdp_node_info *sdp_info; 299 int pkind, pf, vf, lbkid, vfid; 300 u8 cgx_id, lmac_id; 301 bool from_vf; 302 int err; 303 304 pf = rvu_get_pf(pcifunc); 305 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK && 306 type != NIX_INTF_TYPE_SDP) 307 return 0; 308 309 switch (type) { 310 case NIX_INTF_TYPE_CGX: 311 pfvf->cgx_lmac = rvu->pf2cgxlmac_map[pf]; 312 rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id); 313 314 pkind = rvu_npc_get_pkind(rvu, pf); 315 if (pkind < 0) { 316 dev_err(rvu->dev, 317 "PF_Func 0x%x: Invalid pkind\n", pcifunc); 318 return -EINVAL; 319 } 320 pfvf->rx_chan_base = rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0); 321 pfvf->tx_chan_base = pfvf->rx_chan_base; 322 pfvf->rx_chan_cnt = 1; 323 pfvf->tx_chan_cnt = 1; 324 rsp->tx_link = cgx_id * hw->lmac_per_cgx + lmac_id; 325 326 cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, pkind); 327 rvu_npc_set_pkind(rvu, pkind, pfvf); 328 329 break; 330 case NIX_INTF_TYPE_LBK: 331 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 332 333 /* If NIX1 block is present on the silicon then NIXes are 334 * assigned alternatively for lbk interfaces. NIX0 should 335 * send packets on lbk link 1 channels and NIX1 should send 336 * on lbk link 0 channels for the communication between 337 * NIX0 and NIX1. 338 */ 339 lbkid = 0; 340 if (rvu->hw->lbk_links > 1) 341 lbkid = vf & 0x1 ? 0 : 1; 342 343 /* By default NIX0 is configured to send packet on lbk link 1 344 * (which corresponds to LBK1), same packet will receive on 345 * NIX1 over lbk link 0. If NIX1 sends packet on lbk link 0 346 * (which corresponds to LBK2) packet will receive on NIX0 lbk 347 * link 1. 348 * But if lbk links for NIX0 and NIX1 are negated, i.e NIX0 349 * transmits and receives on lbk link 0, whick corresponds 350 * to LBK1 block, back to back connectivity between NIX and 351 * LBK can be achieved (which is similar to 96xx) 352 * 353 * RX TX 354 * NIX0 lbk link 1 (LBK2) 1 (LBK1) 355 * NIX0 lbk link 0 (LBK0) 0 (LBK0) 356 * NIX1 lbk link 0 (LBK1) 0 (LBK2) 357 * NIX1 lbk link 1 (LBK3) 1 (LBK3) 358 */ 359 if (loop) 360 lbkid = !lbkid; 361 362 /* Note that AF's VFs work in pairs and talk over consecutive 363 * loopback channels.Therefore if odd number of AF VFs are 364 * enabled then the last VF remains with no pair. 365 */ 366 pfvf->rx_chan_base = rvu_nix_chan_lbk(rvu, lbkid, vf); 367 pfvf->tx_chan_base = vf & 0x1 ? 368 rvu_nix_chan_lbk(rvu, lbkid, vf - 1) : 369 rvu_nix_chan_lbk(rvu, lbkid, vf + 1); 370 pfvf->rx_chan_cnt = 1; 371 pfvf->tx_chan_cnt = 1; 372 rsp->tx_link = hw->cgx_links + lbkid; 373 pfvf->lbkid = lbkid; 374 rvu_npc_set_pkind(rvu, NPC_RX_LBK_PKIND, pfvf); 375 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 376 pfvf->rx_chan_base, 377 pfvf->rx_chan_cnt); 378 379 break; 380 case NIX_INTF_TYPE_SDP: 381 from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK); 382 parent_pf = &rvu->pf[rvu_get_pf(pcifunc)]; 383 sdp_info = parent_pf->sdp_info; 384 if (!sdp_info) { 385 dev_err(rvu->dev, "Invalid sdp_info pointer\n"); 386 return -EINVAL; 387 } 388 if (from_vf) { 389 req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn + 390 sdp_info->num_pf_rings; 391 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 392 for (vfid = 0; vfid < vf; vfid++) 393 req_chan_base += sdp_info->vf_rings[vfid]; 394 req_chan_cnt = sdp_info->vf_rings[vf]; 395 req_chan_end = req_chan_base + req_chan_cnt - 1; 396 if (req_chan_base < rvu_nix_chan_sdp(rvu, 0) || 397 req_chan_end > rvu_nix_chan_sdp(rvu, 255)) { 398 dev_err(rvu->dev, 399 "PF_Func 0x%x: Invalid channel base and count\n", 400 pcifunc); 401 return -EINVAL; 402 } 403 } else { 404 req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn; 405 req_chan_cnt = sdp_info->num_pf_rings; 406 } 407 408 pfvf->rx_chan_base = req_chan_base; 409 pfvf->rx_chan_cnt = req_chan_cnt; 410 pfvf->tx_chan_base = pfvf->rx_chan_base; 411 pfvf->tx_chan_cnt = pfvf->rx_chan_cnt; 412 413 rsp->tx_link = hw->cgx_links + hw->lbk_links; 414 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 415 pfvf->rx_chan_base, 416 pfvf->rx_chan_cnt); 417 break; 418 } 419 420 /* Add a UCAST forwarding rule in MCAM with this NIXLF attached 421 * RVU PF/VF's MAC address. 422 */ 423 rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, 424 pfvf->rx_chan_base, pfvf->mac_addr); 425 426 /* Add this PF_FUNC to bcast pkt replication list */ 427 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, true); 428 if (err) { 429 dev_err(rvu->dev, 430 "Bcast list, failed to enable PF_FUNC 0x%x\n", 431 pcifunc); 432 return err; 433 } 434 /* Install MCAM rule matching Ethernet broadcast mac address */ 435 rvu_npc_install_bcast_match_entry(rvu, pcifunc, 436 nixlf, pfvf->rx_chan_base); 437 438 pfvf->maxlen = NIC_HW_MIN_FRS; 439 pfvf->minlen = NIC_HW_MIN_FRS; 440 441 return 0; 442 } 443 444 static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf) 445 { 446 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 447 int err; 448 449 pfvf->maxlen = 0; 450 pfvf->minlen = 0; 451 452 /* Remove this PF_FUNC from bcast pkt replication list */ 453 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_BCAST_ENTRY, false); 454 if (err) { 455 dev_err(rvu->dev, 456 "Bcast list, failed to disable PF_FUNC 0x%x\n", 457 pcifunc); 458 } 459 460 /* Free and disable any MCAM entries used by this NIX LF */ 461 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 462 463 /* Disable DMAC filters used */ 464 rvu_cgx_disable_dmac_entries(rvu, pcifunc); 465 } 466 467 int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu, 468 struct nix_bp_cfg_req *req, 469 struct msg_rsp *rsp) 470 { 471 u16 pcifunc = req->hdr.pcifunc; 472 struct rvu_pfvf *pfvf; 473 int blkaddr, pf, type; 474 u16 chan_base, chan; 475 u64 cfg; 476 477 pf = rvu_get_pf(pcifunc); 478 type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 479 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK) 480 return 0; 481 482 pfvf = rvu_get_pfvf(rvu, pcifunc); 483 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 484 485 chan_base = pfvf->rx_chan_base + req->chan_base; 486 for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) { 487 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan)); 488 rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan), 489 cfg & ~BIT_ULL(16)); 490 } 491 return 0; 492 } 493 494 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req, 495 int type, int chan_id) 496 { 497 int bpid, blkaddr, lmac_chan_cnt, sdp_chan_cnt; 498 u16 cgx_bpid_cnt, lbk_bpid_cnt, sdp_bpid_cnt; 499 struct rvu_hwinfo *hw = rvu->hw; 500 struct rvu_pfvf *pfvf; 501 u8 cgx_id, lmac_id; 502 u64 cfg; 503 504 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc); 505 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST); 506 lmac_chan_cnt = cfg & 0xFF; 507 508 cgx_bpid_cnt = hw->cgx_links * lmac_chan_cnt; 509 lbk_bpid_cnt = hw->lbk_links * ((cfg >> 16) & 0xFF); 510 511 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 512 sdp_chan_cnt = cfg & 0xFFF; 513 sdp_bpid_cnt = hw->sdp_links * sdp_chan_cnt; 514 515 pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 516 517 /* Backpressure IDs range division 518 * CGX channles are mapped to (0 - 191) BPIDs 519 * LBK channles are mapped to (192 - 255) BPIDs 520 * SDP channles are mapped to (256 - 511) BPIDs 521 * 522 * Lmac channles and bpids mapped as follows 523 * cgx(0)_lmac(0)_chan(0 - 15) = bpid(0 - 15) 524 * cgx(0)_lmac(1)_chan(0 - 15) = bpid(16 - 31) .... 525 * cgx(1)_lmac(0)_chan(0 - 15) = bpid(64 - 79) .... 526 */ 527 switch (type) { 528 case NIX_INTF_TYPE_CGX: 529 if ((req->chan_base + req->chan_cnt) > 16) 530 return -EINVAL; 531 rvu_get_cgx_lmac_id(pfvf->cgx_lmac, &cgx_id, &lmac_id); 532 /* Assign bpid based on cgx, lmac and chan id */ 533 bpid = (cgx_id * hw->lmac_per_cgx * lmac_chan_cnt) + 534 (lmac_id * lmac_chan_cnt) + req->chan_base; 535 536 if (req->bpid_per_chan) 537 bpid += chan_id; 538 if (bpid > cgx_bpid_cnt) 539 return -EINVAL; 540 break; 541 542 case NIX_INTF_TYPE_LBK: 543 if ((req->chan_base + req->chan_cnt) > 63) 544 return -EINVAL; 545 bpid = cgx_bpid_cnt + req->chan_base; 546 if (req->bpid_per_chan) 547 bpid += chan_id; 548 if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt)) 549 return -EINVAL; 550 break; 551 case NIX_INTF_TYPE_SDP: 552 if ((req->chan_base + req->chan_cnt) > 255) 553 return -EINVAL; 554 555 bpid = sdp_bpid_cnt + req->chan_base; 556 if (req->bpid_per_chan) 557 bpid += chan_id; 558 559 if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt + sdp_bpid_cnt)) 560 return -EINVAL; 561 break; 562 default: 563 return -EINVAL; 564 } 565 return bpid; 566 } 567 568 int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu, 569 struct nix_bp_cfg_req *req, 570 struct nix_bp_cfg_rsp *rsp) 571 { 572 int blkaddr, pf, type, chan_id = 0; 573 u16 pcifunc = req->hdr.pcifunc; 574 struct rvu_pfvf *pfvf; 575 u16 chan_base, chan; 576 s16 bpid, bpid_base; 577 u64 cfg; 578 579 pf = rvu_get_pf(pcifunc); 580 type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 581 if (is_sdp_pfvf(pcifunc)) 582 type = NIX_INTF_TYPE_SDP; 583 584 /* Enable backpressure only for CGX mapped PFs and LBK/SDP interface */ 585 if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK && 586 type != NIX_INTF_TYPE_SDP) 587 return 0; 588 589 pfvf = rvu_get_pfvf(rvu, pcifunc); 590 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 591 592 bpid_base = rvu_nix_get_bpid(rvu, req, type, chan_id); 593 chan_base = pfvf->rx_chan_base + req->chan_base; 594 bpid = bpid_base; 595 596 for (chan = chan_base; chan < (chan_base + req->chan_cnt); chan++) { 597 if (bpid < 0) { 598 dev_warn(rvu->dev, "Fail to enable backpressure\n"); 599 return -EINVAL; 600 } 601 602 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan)); 603 cfg &= ~GENMASK_ULL(8, 0); 604 rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan), 605 cfg | (bpid & GENMASK_ULL(8, 0)) | BIT_ULL(16)); 606 chan_id++; 607 bpid = rvu_nix_get_bpid(rvu, req, type, chan_id); 608 } 609 610 for (chan = 0; chan < req->chan_cnt; chan++) { 611 /* Map channel and bpid assign to it */ 612 rsp->chan_bpid[chan] = ((req->chan_base + chan) & 0x7F) << 10 | 613 (bpid_base & 0x3FF); 614 if (req->bpid_per_chan) 615 bpid_base++; 616 } 617 rsp->chan_cnt = req->chan_cnt; 618 619 return 0; 620 } 621 622 static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr, 623 u64 format, bool v4, u64 *fidx) 624 { 625 struct nix_lso_format field = {0}; 626 627 /* IP's Length field */ 628 field.layer = NIX_TXLAYER_OL3; 629 /* In ipv4, length field is at offset 2 bytes, for ipv6 it's 4 */ 630 field.offset = v4 ? 2 : 4; 631 field.sizem1 = 1; /* i.e 2 bytes */ 632 field.alg = NIX_LSOALG_ADD_PAYLEN; 633 rvu_write64(rvu, blkaddr, 634 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 635 *(u64 *)&field); 636 637 /* No ID field in IPv6 header */ 638 if (!v4) 639 return; 640 641 /* IP's ID field */ 642 field.layer = NIX_TXLAYER_OL3; 643 field.offset = 4; 644 field.sizem1 = 1; /* i.e 2 bytes */ 645 field.alg = NIX_LSOALG_ADD_SEGNUM; 646 rvu_write64(rvu, blkaddr, 647 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 648 *(u64 *)&field); 649 } 650 651 static void nix_setup_lso_tso_l4(struct rvu *rvu, int blkaddr, 652 u64 format, u64 *fidx) 653 { 654 struct nix_lso_format field = {0}; 655 656 /* TCP's sequence number field */ 657 field.layer = NIX_TXLAYER_OL4; 658 field.offset = 4; 659 field.sizem1 = 3; /* i.e 4 bytes */ 660 field.alg = NIX_LSOALG_ADD_OFFSET; 661 rvu_write64(rvu, blkaddr, 662 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 663 *(u64 *)&field); 664 665 /* TCP's flags field */ 666 field.layer = NIX_TXLAYER_OL4; 667 field.offset = 12; 668 field.sizem1 = 1; /* 2 bytes */ 669 field.alg = NIX_LSOALG_TCP_FLAGS; 670 rvu_write64(rvu, blkaddr, 671 NIX_AF_LSO_FORMATX_FIELDX(format, (*fidx)++), 672 *(u64 *)&field); 673 } 674 675 static void nix_setup_lso(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 676 { 677 u64 cfg, idx, fidx = 0; 678 679 /* Get max HW supported format indices */ 680 cfg = (rvu_read64(rvu, blkaddr, NIX_AF_CONST1) >> 48) & 0xFF; 681 nix_hw->lso.total = cfg; 682 683 /* Enable LSO */ 684 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LSO_CFG); 685 /* For TSO, set first and middle segment flags to 686 * mask out PSH, RST & FIN flags in TCP packet 687 */ 688 cfg &= ~((0xFFFFULL << 32) | (0xFFFFULL << 16)); 689 cfg |= (0xFFF2ULL << 32) | (0xFFF2ULL << 16); 690 rvu_write64(rvu, blkaddr, NIX_AF_LSO_CFG, cfg | BIT_ULL(63)); 691 692 /* Setup default static LSO formats 693 * 694 * Configure format fields for TCPv4 segmentation offload 695 */ 696 idx = NIX_LSO_FORMAT_IDX_TSOV4; 697 nix_setup_lso_tso_l3(rvu, blkaddr, idx, true, &fidx); 698 nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx); 699 700 /* Set rest of the fields to NOP */ 701 for (; fidx < 8; fidx++) { 702 rvu_write64(rvu, blkaddr, 703 NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL); 704 } 705 nix_hw->lso.in_use++; 706 707 /* Configure format fields for TCPv6 segmentation offload */ 708 idx = NIX_LSO_FORMAT_IDX_TSOV6; 709 fidx = 0; 710 nix_setup_lso_tso_l3(rvu, blkaddr, idx, false, &fidx); 711 nix_setup_lso_tso_l4(rvu, blkaddr, idx, &fidx); 712 713 /* Set rest of the fields to NOP */ 714 for (; fidx < 8; fidx++) { 715 rvu_write64(rvu, blkaddr, 716 NIX_AF_LSO_FORMATX_FIELDX(idx, fidx), 0x0ULL); 717 } 718 nix_hw->lso.in_use++; 719 } 720 721 static void nix_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf) 722 { 723 kfree(pfvf->rq_bmap); 724 kfree(pfvf->sq_bmap); 725 kfree(pfvf->cq_bmap); 726 if (pfvf->rq_ctx) 727 qmem_free(rvu->dev, pfvf->rq_ctx); 728 if (pfvf->sq_ctx) 729 qmem_free(rvu->dev, pfvf->sq_ctx); 730 if (pfvf->cq_ctx) 731 qmem_free(rvu->dev, pfvf->cq_ctx); 732 if (pfvf->rss_ctx) 733 qmem_free(rvu->dev, pfvf->rss_ctx); 734 if (pfvf->nix_qints_ctx) 735 qmem_free(rvu->dev, pfvf->nix_qints_ctx); 736 if (pfvf->cq_ints_ctx) 737 qmem_free(rvu->dev, pfvf->cq_ints_ctx); 738 739 pfvf->rq_bmap = NULL; 740 pfvf->cq_bmap = NULL; 741 pfvf->sq_bmap = NULL; 742 pfvf->rq_ctx = NULL; 743 pfvf->sq_ctx = NULL; 744 pfvf->cq_ctx = NULL; 745 pfvf->rss_ctx = NULL; 746 pfvf->nix_qints_ctx = NULL; 747 pfvf->cq_ints_ctx = NULL; 748 } 749 750 static int nixlf_rss_ctx_init(struct rvu *rvu, int blkaddr, 751 struct rvu_pfvf *pfvf, int nixlf, 752 int rss_sz, int rss_grps, int hwctx_size, 753 u64 way_mask, bool tag_lsb_as_adder) 754 { 755 int err, grp, num_indices; 756 u64 val; 757 758 /* RSS is not requested for this NIXLF */ 759 if (!rss_sz) 760 return 0; 761 num_indices = rss_sz * rss_grps; 762 763 /* Alloc NIX RSS HW context memory and config the base */ 764 err = qmem_alloc(rvu->dev, &pfvf->rss_ctx, num_indices, hwctx_size); 765 if (err) 766 return err; 767 768 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_BASE(nixlf), 769 (u64)pfvf->rss_ctx->iova); 770 771 /* Config full RSS table size, enable RSS and caching */ 772 val = BIT_ULL(36) | BIT_ULL(4) | way_mask << 20 | 773 ilog2(num_indices / MAX_RSS_INDIR_TBL_SIZE); 774 775 if (tag_lsb_as_adder) 776 val |= BIT_ULL(5); 777 778 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf), val); 779 /* Config RSS group offset and sizes */ 780 for (grp = 0; grp < rss_grps; grp++) 781 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RSS_GRPX(nixlf, grp), 782 ((ilog2(rss_sz) - 1) << 16) | (rss_sz * grp)); 783 return 0; 784 } 785 786 static int nix_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block, 787 struct nix_aq_inst_s *inst) 788 { 789 struct admin_queue *aq = block->aq; 790 struct nix_aq_res_s *result; 791 int timeout = 1000; 792 u64 reg, head; 793 794 result = (struct nix_aq_res_s *)aq->res->base; 795 796 /* Get current head pointer where to append this instruction */ 797 reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS); 798 head = (reg >> 4) & AQ_PTR_MASK; 799 800 memcpy((void *)(aq->inst->base + (head * aq->inst->entry_sz)), 801 (void *)inst, aq->inst->entry_sz); 802 memset(result, 0, sizeof(*result)); 803 /* sync into memory */ 804 wmb(); 805 806 /* Ring the doorbell and wait for result */ 807 rvu_write64(rvu, block->addr, NIX_AF_AQ_DOOR, 1); 808 while (result->compcode == NIX_AQ_COMP_NOTDONE) { 809 cpu_relax(); 810 udelay(1); 811 timeout--; 812 if (!timeout) 813 return -EBUSY; 814 } 815 816 if (result->compcode != NIX_AQ_COMP_GOOD) 817 /* TODO: Replace this with some error code */ 818 return -EBUSY; 819 820 return 0; 821 } 822 823 static int rvu_nix_blk_aq_enq_inst(struct rvu *rvu, struct nix_hw *nix_hw, 824 struct nix_aq_enq_req *req, 825 struct nix_aq_enq_rsp *rsp) 826 { 827 struct rvu_hwinfo *hw = rvu->hw; 828 u16 pcifunc = req->hdr.pcifunc; 829 int nixlf, blkaddr, rc = 0; 830 struct nix_aq_inst_s inst; 831 struct rvu_block *block; 832 struct admin_queue *aq; 833 struct rvu_pfvf *pfvf; 834 void *ctx, *mask; 835 bool ena; 836 u64 cfg; 837 838 blkaddr = nix_hw->blkaddr; 839 block = &hw->block[blkaddr]; 840 aq = block->aq; 841 if (!aq) { 842 dev_warn(rvu->dev, "%s: NIX AQ not initialized\n", __func__); 843 return NIX_AF_ERR_AQ_ENQUEUE; 844 } 845 846 pfvf = rvu_get_pfvf(rvu, pcifunc); 847 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 848 849 /* Skip NIXLF check for broadcast MCE entry and bandwidth profile 850 * operations done by AF itself. 851 */ 852 if (!((!rsp && req->ctype == NIX_AQ_CTYPE_MCE) || 853 (req->ctype == NIX_AQ_CTYPE_BANDPROF && !pcifunc))) { 854 if (!pfvf->nixlf || nixlf < 0) 855 return NIX_AF_ERR_AF_LF_INVALID; 856 } 857 858 switch (req->ctype) { 859 case NIX_AQ_CTYPE_RQ: 860 /* Check if index exceeds max no of queues */ 861 if (!pfvf->rq_ctx || req->qidx >= pfvf->rq_ctx->qsize) 862 rc = NIX_AF_ERR_AQ_ENQUEUE; 863 break; 864 case NIX_AQ_CTYPE_SQ: 865 if (!pfvf->sq_ctx || req->qidx >= pfvf->sq_ctx->qsize) 866 rc = NIX_AF_ERR_AQ_ENQUEUE; 867 break; 868 case NIX_AQ_CTYPE_CQ: 869 if (!pfvf->cq_ctx || req->qidx >= pfvf->cq_ctx->qsize) 870 rc = NIX_AF_ERR_AQ_ENQUEUE; 871 break; 872 case NIX_AQ_CTYPE_RSS: 873 /* Check if RSS is enabled and qidx is within range */ 874 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf)); 875 if (!(cfg & BIT_ULL(4)) || !pfvf->rss_ctx || 876 (req->qidx >= (256UL << (cfg & 0xF)))) 877 rc = NIX_AF_ERR_AQ_ENQUEUE; 878 break; 879 case NIX_AQ_CTYPE_MCE: 880 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG); 881 882 /* Check if index exceeds MCE list length */ 883 if (!nix_hw->mcast.mce_ctx || 884 (req->qidx >= (256UL << (cfg & 0xF)))) 885 rc = NIX_AF_ERR_AQ_ENQUEUE; 886 887 /* Adding multicast lists for requests from PF/VFs is not 888 * yet supported, so ignore this. 889 */ 890 if (rsp) 891 rc = NIX_AF_ERR_AQ_ENQUEUE; 892 break; 893 case NIX_AQ_CTYPE_BANDPROF: 894 if (nix_verify_bandprof((struct nix_cn10k_aq_enq_req *)req, 895 nix_hw, pcifunc)) 896 rc = NIX_AF_ERR_INVALID_BANDPROF; 897 break; 898 default: 899 rc = NIX_AF_ERR_AQ_ENQUEUE; 900 } 901 902 if (rc) 903 return rc; 904 905 /* Check if SQ pointed SMQ belongs to this PF/VF or not */ 906 if (req->ctype == NIX_AQ_CTYPE_SQ && 907 ((req->op == NIX_AQ_INSTOP_INIT && req->sq.ena) || 908 (req->op == NIX_AQ_INSTOP_WRITE && 909 req->sq_mask.ena && req->sq_mask.smq && req->sq.ena))) { 910 if (!is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_SMQ, 911 pcifunc, req->sq.smq)) 912 return NIX_AF_ERR_AQ_ENQUEUE; 913 } 914 915 memset(&inst, 0, sizeof(struct nix_aq_inst_s)); 916 inst.lf = nixlf; 917 inst.cindex = req->qidx; 918 inst.ctype = req->ctype; 919 inst.op = req->op; 920 /* Currently we are not supporting enqueuing multiple instructions, 921 * so always choose first entry in result memory. 922 */ 923 inst.res_addr = (u64)aq->res->iova; 924 925 /* Hardware uses same aq->res->base for updating result of 926 * previous instruction hence wait here till it is done. 927 */ 928 spin_lock(&aq->lock); 929 930 /* Clean result + context memory */ 931 memset(aq->res->base, 0, aq->res->entry_sz); 932 /* Context needs to be written at RES_ADDR + 128 */ 933 ctx = aq->res->base + 128; 934 /* Mask needs to be written at RES_ADDR + 256 */ 935 mask = aq->res->base + 256; 936 937 switch (req->op) { 938 case NIX_AQ_INSTOP_WRITE: 939 if (req->ctype == NIX_AQ_CTYPE_RQ) 940 memcpy(mask, &req->rq_mask, 941 sizeof(struct nix_rq_ctx_s)); 942 else if (req->ctype == NIX_AQ_CTYPE_SQ) 943 memcpy(mask, &req->sq_mask, 944 sizeof(struct nix_sq_ctx_s)); 945 else if (req->ctype == NIX_AQ_CTYPE_CQ) 946 memcpy(mask, &req->cq_mask, 947 sizeof(struct nix_cq_ctx_s)); 948 else if (req->ctype == NIX_AQ_CTYPE_RSS) 949 memcpy(mask, &req->rss_mask, 950 sizeof(struct nix_rsse_s)); 951 else if (req->ctype == NIX_AQ_CTYPE_MCE) 952 memcpy(mask, &req->mce_mask, 953 sizeof(struct nix_rx_mce_s)); 954 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 955 memcpy(mask, &req->prof_mask, 956 sizeof(struct nix_bandprof_s)); 957 fallthrough; 958 case NIX_AQ_INSTOP_INIT: 959 if (req->ctype == NIX_AQ_CTYPE_RQ) 960 memcpy(ctx, &req->rq, sizeof(struct nix_rq_ctx_s)); 961 else if (req->ctype == NIX_AQ_CTYPE_SQ) 962 memcpy(ctx, &req->sq, sizeof(struct nix_sq_ctx_s)); 963 else if (req->ctype == NIX_AQ_CTYPE_CQ) 964 memcpy(ctx, &req->cq, sizeof(struct nix_cq_ctx_s)); 965 else if (req->ctype == NIX_AQ_CTYPE_RSS) 966 memcpy(ctx, &req->rss, sizeof(struct nix_rsse_s)); 967 else if (req->ctype == NIX_AQ_CTYPE_MCE) 968 memcpy(ctx, &req->mce, sizeof(struct nix_rx_mce_s)); 969 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 970 memcpy(ctx, &req->prof, sizeof(struct nix_bandprof_s)); 971 break; 972 case NIX_AQ_INSTOP_NOP: 973 case NIX_AQ_INSTOP_READ: 974 case NIX_AQ_INSTOP_LOCK: 975 case NIX_AQ_INSTOP_UNLOCK: 976 break; 977 default: 978 rc = NIX_AF_ERR_AQ_ENQUEUE; 979 spin_unlock(&aq->lock); 980 return rc; 981 } 982 983 /* Submit the instruction to AQ */ 984 rc = nix_aq_enqueue_wait(rvu, block, &inst); 985 if (rc) { 986 spin_unlock(&aq->lock); 987 return rc; 988 } 989 990 /* Set RQ/SQ/CQ bitmap if respective queue hw context is enabled */ 991 if (req->op == NIX_AQ_INSTOP_INIT) { 992 if (req->ctype == NIX_AQ_CTYPE_RQ && req->rq.ena) 993 __set_bit(req->qidx, pfvf->rq_bmap); 994 if (req->ctype == NIX_AQ_CTYPE_SQ && req->sq.ena) 995 __set_bit(req->qidx, pfvf->sq_bmap); 996 if (req->ctype == NIX_AQ_CTYPE_CQ && req->cq.ena) 997 __set_bit(req->qidx, pfvf->cq_bmap); 998 } 999 1000 if (req->op == NIX_AQ_INSTOP_WRITE) { 1001 if (req->ctype == NIX_AQ_CTYPE_RQ) { 1002 ena = (req->rq.ena & req->rq_mask.ena) | 1003 (test_bit(req->qidx, pfvf->rq_bmap) & 1004 ~req->rq_mask.ena); 1005 if (ena) 1006 __set_bit(req->qidx, pfvf->rq_bmap); 1007 else 1008 __clear_bit(req->qidx, pfvf->rq_bmap); 1009 } 1010 if (req->ctype == NIX_AQ_CTYPE_SQ) { 1011 ena = (req->rq.ena & req->sq_mask.ena) | 1012 (test_bit(req->qidx, pfvf->sq_bmap) & 1013 ~req->sq_mask.ena); 1014 if (ena) 1015 __set_bit(req->qidx, pfvf->sq_bmap); 1016 else 1017 __clear_bit(req->qidx, pfvf->sq_bmap); 1018 } 1019 if (req->ctype == NIX_AQ_CTYPE_CQ) { 1020 ena = (req->rq.ena & req->cq_mask.ena) | 1021 (test_bit(req->qidx, pfvf->cq_bmap) & 1022 ~req->cq_mask.ena); 1023 if (ena) 1024 __set_bit(req->qidx, pfvf->cq_bmap); 1025 else 1026 __clear_bit(req->qidx, pfvf->cq_bmap); 1027 } 1028 } 1029 1030 if (rsp) { 1031 /* Copy read context into mailbox */ 1032 if (req->op == NIX_AQ_INSTOP_READ) { 1033 if (req->ctype == NIX_AQ_CTYPE_RQ) 1034 memcpy(&rsp->rq, ctx, 1035 sizeof(struct nix_rq_ctx_s)); 1036 else if (req->ctype == NIX_AQ_CTYPE_SQ) 1037 memcpy(&rsp->sq, ctx, 1038 sizeof(struct nix_sq_ctx_s)); 1039 else if (req->ctype == NIX_AQ_CTYPE_CQ) 1040 memcpy(&rsp->cq, ctx, 1041 sizeof(struct nix_cq_ctx_s)); 1042 else if (req->ctype == NIX_AQ_CTYPE_RSS) 1043 memcpy(&rsp->rss, ctx, 1044 sizeof(struct nix_rsse_s)); 1045 else if (req->ctype == NIX_AQ_CTYPE_MCE) 1046 memcpy(&rsp->mce, ctx, 1047 sizeof(struct nix_rx_mce_s)); 1048 else if (req->ctype == NIX_AQ_CTYPE_BANDPROF) 1049 memcpy(&rsp->prof, ctx, 1050 sizeof(struct nix_bandprof_s)); 1051 } 1052 } 1053 1054 spin_unlock(&aq->lock); 1055 return 0; 1056 } 1057 1058 static int rvu_nix_verify_aq_ctx(struct rvu *rvu, struct nix_hw *nix_hw, 1059 struct nix_aq_enq_req *req, u8 ctype) 1060 { 1061 struct nix_cn10k_aq_enq_req aq_req; 1062 struct nix_cn10k_aq_enq_rsp aq_rsp; 1063 int rc, word; 1064 1065 if (req->ctype != NIX_AQ_CTYPE_CQ) 1066 return 0; 1067 1068 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 1069 req->hdr.pcifunc, ctype, req->qidx); 1070 if (rc) { 1071 dev_err(rvu->dev, 1072 "%s: Failed to fetch %s%d context of PFFUNC 0x%x\n", 1073 __func__, nix_get_ctx_name(ctype), req->qidx, 1074 req->hdr.pcifunc); 1075 return rc; 1076 } 1077 1078 /* Make copy of original context & mask which are required 1079 * for resubmission 1080 */ 1081 memcpy(&aq_req.cq_mask, &req->cq_mask, sizeof(struct nix_cq_ctx_s)); 1082 memcpy(&aq_req.cq, &req->cq, sizeof(struct nix_cq_ctx_s)); 1083 1084 /* exclude fields which HW can update */ 1085 aq_req.cq_mask.cq_err = 0; 1086 aq_req.cq_mask.wrptr = 0; 1087 aq_req.cq_mask.tail = 0; 1088 aq_req.cq_mask.head = 0; 1089 aq_req.cq_mask.avg_level = 0; 1090 aq_req.cq_mask.update_time = 0; 1091 aq_req.cq_mask.substream = 0; 1092 1093 /* Context mask (cq_mask) holds mask value of fields which 1094 * are changed in AQ WRITE operation. 1095 * for example cq.drop = 0xa; 1096 * cq_mask.drop = 0xff; 1097 * Below logic performs '&' between cq and cq_mask so that non 1098 * updated fields are masked out for request and response 1099 * comparison 1100 */ 1101 for (word = 0; word < sizeof(struct nix_cq_ctx_s) / sizeof(u64); 1102 word++) { 1103 *(u64 *)((u8 *)&aq_rsp.cq + word * 8) &= 1104 (*(u64 *)((u8 *)&aq_req.cq_mask + word * 8)); 1105 *(u64 *)((u8 *)&aq_req.cq + word * 8) &= 1106 (*(u64 *)((u8 *)&aq_req.cq_mask + word * 8)); 1107 } 1108 1109 if (memcmp(&aq_req.cq, &aq_rsp.cq, sizeof(struct nix_cq_ctx_s))) 1110 return NIX_AF_ERR_AQ_CTX_RETRY_WRITE; 1111 1112 return 0; 1113 } 1114 1115 static int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req, 1116 struct nix_aq_enq_rsp *rsp) 1117 { 1118 struct nix_hw *nix_hw; 1119 int err, retries = 5; 1120 int blkaddr; 1121 1122 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc); 1123 if (blkaddr < 0) 1124 return NIX_AF_ERR_AF_LF_INVALID; 1125 1126 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1127 if (!nix_hw) 1128 return NIX_AF_ERR_INVALID_NIXBLK; 1129 1130 retry: 1131 err = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, req, rsp); 1132 1133 /* HW errata 'AQ Modification to CQ could be discarded on heavy traffic' 1134 * As a work around perfrom CQ context read after each AQ write. If AQ 1135 * read shows AQ write is not updated perform AQ write again. 1136 */ 1137 if (!err && req->op == NIX_AQ_INSTOP_WRITE) { 1138 err = rvu_nix_verify_aq_ctx(rvu, nix_hw, req, NIX_AQ_CTYPE_CQ); 1139 if (err == NIX_AF_ERR_AQ_CTX_RETRY_WRITE) { 1140 if (retries--) 1141 goto retry; 1142 else 1143 return NIX_AF_ERR_CQ_CTX_WRITE_ERR; 1144 } 1145 } 1146 1147 return err; 1148 } 1149 1150 static const char *nix_get_ctx_name(int ctype) 1151 { 1152 switch (ctype) { 1153 case NIX_AQ_CTYPE_CQ: 1154 return "CQ"; 1155 case NIX_AQ_CTYPE_SQ: 1156 return "SQ"; 1157 case NIX_AQ_CTYPE_RQ: 1158 return "RQ"; 1159 case NIX_AQ_CTYPE_RSS: 1160 return "RSS"; 1161 } 1162 return ""; 1163 } 1164 1165 static int nix_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req *req) 1166 { 1167 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 1168 struct nix_aq_enq_req aq_req; 1169 unsigned long *bmap; 1170 int qidx, q_cnt = 0; 1171 int err = 0, rc; 1172 1173 if (!pfvf->cq_ctx || !pfvf->sq_ctx || !pfvf->rq_ctx) 1174 return NIX_AF_ERR_AQ_ENQUEUE; 1175 1176 memset(&aq_req, 0, sizeof(struct nix_aq_enq_req)); 1177 aq_req.hdr.pcifunc = req->hdr.pcifunc; 1178 1179 if (req->ctype == NIX_AQ_CTYPE_CQ) { 1180 aq_req.cq.ena = 0; 1181 aq_req.cq_mask.ena = 1; 1182 aq_req.cq.bp_ena = 0; 1183 aq_req.cq_mask.bp_ena = 1; 1184 q_cnt = pfvf->cq_ctx->qsize; 1185 bmap = pfvf->cq_bmap; 1186 } 1187 if (req->ctype == NIX_AQ_CTYPE_SQ) { 1188 aq_req.sq.ena = 0; 1189 aq_req.sq_mask.ena = 1; 1190 q_cnt = pfvf->sq_ctx->qsize; 1191 bmap = pfvf->sq_bmap; 1192 } 1193 if (req->ctype == NIX_AQ_CTYPE_RQ) { 1194 aq_req.rq.ena = 0; 1195 aq_req.rq_mask.ena = 1; 1196 q_cnt = pfvf->rq_ctx->qsize; 1197 bmap = pfvf->rq_bmap; 1198 } 1199 1200 aq_req.ctype = req->ctype; 1201 aq_req.op = NIX_AQ_INSTOP_WRITE; 1202 1203 for (qidx = 0; qidx < q_cnt; qidx++) { 1204 if (!test_bit(qidx, bmap)) 1205 continue; 1206 aq_req.qidx = qidx; 1207 rc = rvu_nix_aq_enq_inst(rvu, &aq_req, NULL); 1208 if (rc) { 1209 err = rc; 1210 dev_err(rvu->dev, "Failed to disable %s:%d context\n", 1211 nix_get_ctx_name(req->ctype), qidx); 1212 } 1213 } 1214 1215 return err; 1216 } 1217 1218 #ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING 1219 static int nix_lf_hwctx_lockdown(struct rvu *rvu, struct nix_aq_enq_req *req) 1220 { 1221 struct nix_aq_enq_req lock_ctx_req; 1222 int err; 1223 1224 if (req->op != NIX_AQ_INSTOP_INIT) 1225 return 0; 1226 1227 if (req->ctype == NIX_AQ_CTYPE_MCE || 1228 req->ctype == NIX_AQ_CTYPE_DYNO) 1229 return 0; 1230 1231 memset(&lock_ctx_req, 0, sizeof(struct nix_aq_enq_req)); 1232 lock_ctx_req.hdr.pcifunc = req->hdr.pcifunc; 1233 lock_ctx_req.ctype = req->ctype; 1234 lock_ctx_req.op = NIX_AQ_INSTOP_LOCK; 1235 lock_ctx_req.qidx = req->qidx; 1236 err = rvu_nix_aq_enq_inst(rvu, &lock_ctx_req, NULL); 1237 if (err) 1238 dev_err(rvu->dev, 1239 "PFUNC 0x%x: Failed to lock NIX %s:%d context\n", 1240 req->hdr.pcifunc, 1241 nix_get_ctx_name(req->ctype), req->qidx); 1242 return err; 1243 } 1244 1245 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, 1246 struct nix_aq_enq_req *req, 1247 struct nix_aq_enq_rsp *rsp) 1248 { 1249 int err; 1250 1251 err = rvu_nix_aq_enq_inst(rvu, req, rsp); 1252 if (!err) 1253 err = nix_lf_hwctx_lockdown(rvu, req); 1254 return err; 1255 } 1256 #else 1257 1258 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, 1259 struct nix_aq_enq_req *req, 1260 struct nix_aq_enq_rsp *rsp) 1261 { 1262 return rvu_nix_aq_enq_inst(rvu, req, rsp); 1263 } 1264 #endif 1265 /* CN10K mbox handler */ 1266 int rvu_mbox_handler_nix_cn10k_aq_enq(struct rvu *rvu, 1267 struct nix_cn10k_aq_enq_req *req, 1268 struct nix_cn10k_aq_enq_rsp *rsp) 1269 { 1270 return rvu_nix_aq_enq_inst(rvu, (struct nix_aq_enq_req *)req, 1271 (struct nix_aq_enq_rsp *)rsp); 1272 } 1273 1274 int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu, 1275 struct hwctx_disable_req *req, 1276 struct msg_rsp *rsp) 1277 { 1278 return nix_lf_hwctx_disable(rvu, req); 1279 } 1280 1281 int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, 1282 struct nix_lf_alloc_req *req, 1283 struct nix_lf_alloc_rsp *rsp) 1284 { 1285 int nixlf, qints, hwctx_size, intf, err, rc = 0; 1286 struct rvu_hwinfo *hw = rvu->hw; 1287 u16 pcifunc = req->hdr.pcifunc; 1288 struct rvu_block *block; 1289 struct rvu_pfvf *pfvf; 1290 u64 cfg, ctx_cfg; 1291 int blkaddr; 1292 1293 if (!req->rq_cnt || !req->sq_cnt || !req->cq_cnt) 1294 return NIX_AF_ERR_PARAM; 1295 1296 if (req->way_mask) 1297 req->way_mask &= 0xFFFF; 1298 1299 pfvf = rvu_get_pfvf(rvu, pcifunc); 1300 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1301 if (!pfvf->nixlf || blkaddr < 0) 1302 return NIX_AF_ERR_AF_LF_INVALID; 1303 1304 block = &hw->block[blkaddr]; 1305 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 1306 if (nixlf < 0) 1307 return NIX_AF_ERR_AF_LF_INVALID; 1308 1309 /* Check if requested 'NIXLF <=> NPALF' mapping is valid */ 1310 if (req->npa_func) { 1311 /* If default, use 'this' NIXLF's PFFUNC */ 1312 if (req->npa_func == RVU_DEFAULT_PF_FUNC) 1313 req->npa_func = pcifunc; 1314 if (!is_pffunc_map_valid(rvu, req->npa_func, BLKTYPE_NPA)) 1315 return NIX_AF_INVAL_NPA_PF_FUNC; 1316 } 1317 1318 /* Check if requested 'NIXLF <=> SSOLF' mapping is valid */ 1319 if (req->sso_func) { 1320 /* If default, use 'this' NIXLF's PFFUNC */ 1321 if (req->sso_func == RVU_DEFAULT_PF_FUNC) 1322 req->sso_func = pcifunc; 1323 if (!is_pffunc_map_valid(rvu, req->sso_func, BLKTYPE_SSO)) 1324 return NIX_AF_INVAL_SSO_PF_FUNC; 1325 } 1326 1327 /* If RSS is being enabled, check if requested config is valid. 1328 * RSS table size should be power of two, otherwise 1329 * RSS_GRP::OFFSET + adder might go beyond that group or 1330 * won't be able to use entire table. 1331 */ 1332 if (req->rss_sz && (req->rss_sz > MAX_RSS_INDIR_TBL_SIZE || 1333 !is_power_of_2(req->rss_sz))) 1334 return NIX_AF_ERR_RSS_SIZE_INVALID; 1335 1336 if (req->rss_sz && 1337 (!req->rss_grps || req->rss_grps > MAX_RSS_GROUPS)) 1338 return NIX_AF_ERR_RSS_GRPS_INVALID; 1339 1340 /* Reset this NIX LF */ 1341 err = rvu_lf_reset(rvu, block, nixlf); 1342 if (err) { 1343 dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", 1344 block->addr - BLKADDR_NIX0, nixlf); 1345 return NIX_AF_ERR_LF_RESET; 1346 } 1347 1348 ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3); 1349 1350 /* Alloc NIX RQ HW context memory and config the base */ 1351 hwctx_size = 1UL << ((ctx_cfg >> 4) & 0xF); 1352 err = qmem_alloc(rvu->dev, &pfvf->rq_ctx, req->rq_cnt, hwctx_size); 1353 if (err) 1354 goto free_mem; 1355 1356 pfvf->rq_bmap = kcalloc(req->rq_cnt, sizeof(long), GFP_KERNEL); 1357 if (!pfvf->rq_bmap) 1358 goto free_mem; 1359 1360 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_BASE(nixlf), 1361 (u64)pfvf->rq_ctx->iova); 1362 1363 /* Set caching and queue count in HW */ 1364 cfg = BIT_ULL(36) | (req->rq_cnt - 1) | req->way_mask << 20; 1365 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RQS_CFG(nixlf), cfg); 1366 1367 /* Alloc NIX SQ HW context memory and config the base */ 1368 hwctx_size = 1UL << (ctx_cfg & 0xF); 1369 err = qmem_alloc(rvu->dev, &pfvf->sq_ctx, req->sq_cnt, hwctx_size); 1370 if (err) 1371 goto free_mem; 1372 1373 pfvf->sq_bmap = kcalloc(req->sq_cnt, sizeof(long), GFP_KERNEL); 1374 if (!pfvf->sq_bmap) 1375 goto free_mem; 1376 1377 rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_BASE(nixlf), 1378 (u64)pfvf->sq_ctx->iova); 1379 1380 cfg = BIT_ULL(36) | (req->sq_cnt - 1) | req->way_mask << 20; 1381 rvu_write64(rvu, blkaddr, NIX_AF_LFX_SQS_CFG(nixlf), cfg); 1382 1383 /* Alloc NIX CQ HW context memory and config the base */ 1384 hwctx_size = 1UL << ((ctx_cfg >> 8) & 0xF); 1385 err = qmem_alloc(rvu->dev, &pfvf->cq_ctx, req->cq_cnt, hwctx_size); 1386 if (err) 1387 goto free_mem; 1388 1389 pfvf->cq_bmap = kcalloc(req->cq_cnt, sizeof(long), GFP_KERNEL); 1390 if (!pfvf->cq_bmap) 1391 goto free_mem; 1392 1393 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_BASE(nixlf), 1394 (u64)pfvf->cq_ctx->iova); 1395 1396 cfg = BIT_ULL(36) | (req->cq_cnt - 1) | req->way_mask << 20; 1397 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CQS_CFG(nixlf), cfg); 1398 1399 /* Initialize receive side scaling (RSS) */ 1400 hwctx_size = 1UL << ((ctx_cfg >> 12) & 0xF); 1401 err = nixlf_rss_ctx_init(rvu, blkaddr, pfvf, nixlf, req->rss_sz, 1402 req->rss_grps, hwctx_size, req->way_mask, 1403 !!(req->flags & NIX_LF_RSS_TAG_LSB_AS_ADDER)); 1404 if (err) 1405 goto free_mem; 1406 1407 /* Alloc memory for CQINT's HW contexts */ 1408 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1409 qints = (cfg >> 24) & 0xFFF; 1410 hwctx_size = 1UL << ((ctx_cfg >> 24) & 0xF); 1411 err = qmem_alloc(rvu->dev, &pfvf->cq_ints_ctx, qints, hwctx_size); 1412 if (err) 1413 goto free_mem; 1414 1415 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_BASE(nixlf), 1416 (u64)pfvf->cq_ints_ctx->iova); 1417 1418 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CINTS_CFG(nixlf), 1419 BIT_ULL(36) | req->way_mask << 20); 1420 1421 /* Alloc memory for QINT's HW contexts */ 1422 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1423 qints = (cfg >> 12) & 0xFFF; 1424 hwctx_size = 1UL << ((ctx_cfg >> 20) & 0xF); 1425 err = qmem_alloc(rvu->dev, &pfvf->nix_qints_ctx, qints, hwctx_size); 1426 if (err) 1427 goto free_mem; 1428 1429 rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_BASE(nixlf), 1430 (u64)pfvf->nix_qints_ctx->iova); 1431 rvu_write64(rvu, blkaddr, NIX_AF_LFX_QINTS_CFG(nixlf), 1432 BIT_ULL(36) | req->way_mask << 20); 1433 1434 /* Setup VLANX TPID's. 1435 * Use VLAN1 for 802.1Q 1436 * and VLAN0 for 802.1AD. 1437 */ 1438 cfg = (0x8100ULL << 16) | 0x88A8ULL; 1439 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg); 1440 1441 /* Enable LMTST for this NIX LF */ 1442 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG2(nixlf), BIT_ULL(0)); 1443 1444 /* Set CQE/WQE size, NPA_PF_FUNC for SQBs and also SSO_PF_FUNC */ 1445 if (req->npa_func) 1446 cfg = req->npa_func; 1447 if (req->sso_func) 1448 cfg |= (u64)req->sso_func << 16; 1449 1450 cfg |= (u64)req->xqe_sz << 33; 1451 rvu_write64(rvu, blkaddr, NIX_AF_LFX_CFG(nixlf), cfg); 1452 1453 /* Config Rx pkt length, csum checks and apad enable / disable */ 1454 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), req->rx_cfg); 1455 1456 /* Configure pkind for TX parse config */ 1457 cfg = NPC_TX_DEF_PKIND; 1458 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg); 1459 1460 intf = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; 1461 if (is_sdp_pfvf(pcifunc)) 1462 intf = NIX_INTF_TYPE_SDP; 1463 1464 err = nix_interface_init(rvu, pcifunc, intf, nixlf, rsp, 1465 !!(req->flags & NIX_LF_LBK_BLK_SEL)); 1466 if (err) 1467 goto free_mem; 1468 1469 /* Disable NPC entries as NIXLF's contexts are not initialized yet */ 1470 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 1471 1472 /* Configure RX VTAG Type 7 (strip) for vf vlan */ 1473 rvu_write64(rvu, blkaddr, 1474 NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, NIX_AF_LFX_RX_VTAG_TYPE7), 1475 VTAGSIZE_T4 | VTAG_STRIP); 1476 1477 goto exit; 1478 1479 free_mem: 1480 nix_ctx_free(rvu, pfvf); 1481 rc = -ENOMEM; 1482 1483 exit: 1484 /* Set macaddr of this PF/VF */ 1485 ether_addr_copy(rsp->mac_addr, pfvf->mac_addr); 1486 1487 /* set SQB size info */ 1488 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQ_CONST); 1489 rsp->sqb_size = (cfg >> 34) & 0xFFFF; 1490 rsp->rx_chan_base = pfvf->rx_chan_base; 1491 rsp->tx_chan_base = pfvf->tx_chan_base; 1492 rsp->rx_chan_cnt = pfvf->rx_chan_cnt; 1493 rsp->tx_chan_cnt = pfvf->tx_chan_cnt; 1494 rsp->lso_tsov4_idx = NIX_LSO_FORMAT_IDX_TSOV4; 1495 rsp->lso_tsov6_idx = NIX_LSO_FORMAT_IDX_TSOV6; 1496 /* Get HW supported stat count */ 1497 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 1498 rsp->lf_rx_stats = ((cfg >> 32) & 0xFF); 1499 rsp->lf_tx_stats = ((cfg >> 24) & 0xFF); 1500 /* Get count of CQ IRQs and error IRQs supported per LF */ 1501 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 1502 rsp->qints = ((cfg >> 12) & 0xFFF); 1503 rsp->cints = ((cfg >> 24) & 0xFFF); 1504 rsp->cgx_links = hw->cgx_links; 1505 rsp->lbk_links = hw->lbk_links; 1506 rsp->sdp_links = hw->sdp_links; 1507 1508 return rc; 1509 } 1510 1511 int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct nix_lf_free_req *req, 1512 struct msg_rsp *rsp) 1513 { 1514 struct rvu_hwinfo *hw = rvu->hw; 1515 u16 pcifunc = req->hdr.pcifunc; 1516 struct rvu_block *block; 1517 int blkaddr, nixlf, err; 1518 struct rvu_pfvf *pfvf; 1519 1520 pfvf = rvu_get_pfvf(rvu, pcifunc); 1521 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1522 if (!pfvf->nixlf || blkaddr < 0) 1523 return NIX_AF_ERR_AF_LF_INVALID; 1524 1525 block = &hw->block[blkaddr]; 1526 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 1527 if (nixlf < 0) 1528 return NIX_AF_ERR_AF_LF_INVALID; 1529 1530 if (req->flags & NIX_LF_DISABLE_FLOWS) 1531 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 1532 else 1533 rvu_npc_free_mcam_entries(rvu, pcifunc, nixlf); 1534 1535 /* Free any tx vtag def entries used by this NIX LF */ 1536 if (!(req->flags & NIX_LF_DONT_FREE_TX_VTAG)) 1537 nix_free_tx_vtag_entries(rvu, pcifunc); 1538 1539 nix_interface_deinit(rvu, pcifunc, nixlf); 1540 1541 /* Reset this NIX LF */ 1542 err = rvu_lf_reset(rvu, block, nixlf); 1543 if (err) { 1544 dev_err(rvu->dev, "Failed to reset NIX%d LF%d\n", 1545 block->addr - BLKADDR_NIX0, nixlf); 1546 return NIX_AF_ERR_LF_RESET; 1547 } 1548 1549 nix_ctx_free(rvu, pfvf); 1550 1551 return 0; 1552 } 1553 1554 int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu, 1555 struct nix_mark_format_cfg *req, 1556 struct nix_mark_format_cfg_rsp *rsp) 1557 { 1558 u16 pcifunc = req->hdr.pcifunc; 1559 struct nix_hw *nix_hw; 1560 struct rvu_pfvf *pfvf; 1561 int blkaddr, rc; 1562 u32 cfg; 1563 1564 pfvf = rvu_get_pfvf(rvu, pcifunc); 1565 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1566 if (!pfvf->nixlf || blkaddr < 0) 1567 return NIX_AF_ERR_AF_LF_INVALID; 1568 1569 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1570 if (!nix_hw) 1571 return NIX_AF_ERR_INVALID_NIXBLK; 1572 1573 cfg = (((u32)req->offset & 0x7) << 16) | 1574 (((u32)req->y_mask & 0xF) << 12) | 1575 (((u32)req->y_val & 0xF) << 8) | 1576 (((u32)req->r_mask & 0xF) << 4) | ((u32)req->r_val & 0xF); 1577 1578 rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfg); 1579 if (rc < 0) { 1580 dev_err(rvu->dev, "No mark_format_ctl for (pf:%d, vf:%d)", 1581 rvu_get_pf(pcifunc), pcifunc & RVU_PFVF_FUNC_MASK); 1582 return NIX_AF_ERR_MARK_CFG_FAIL; 1583 } 1584 1585 rsp->mark_format_idx = rc; 1586 return 0; 1587 } 1588 1589 /* Handle shaper update specially for few revisions */ 1590 static bool 1591 handle_txschq_shaper_update(struct rvu *rvu, int blkaddr, int nixlf, 1592 int lvl, u64 reg, u64 regval) 1593 { 1594 u64 regbase, oldval, sw_xoff = 0; 1595 u64 dbgval, md_debug0 = 0; 1596 unsigned long poll_tmo; 1597 bool rate_reg = 0; 1598 u32 schq; 1599 1600 regbase = reg & 0xFFFF; 1601 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 1602 1603 /* Check for rate register */ 1604 switch (lvl) { 1605 case NIX_TXSCH_LVL_TL1: 1606 md_debug0 = NIX_AF_TL1X_MD_DEBUG0(schq); 1607 sw_xoff = NIX_AF_TL1X_SW_XOFF(schq); 1608 1609 rate_reg = !!(regbase == NIX_AF_TL1X_CIR(0)); 1610 break; 1611 case NIX_TXSCH_LVL_TL2: 1612 md_debug0 = NIX_AF_TL2X_MD_DEBUG0(schq); 1613 sw_xoff = NIX_AF_TL2X_SW_XOFF(schq); 1614 1615 rate_reg = (regbase == NIX_AF_TL2X_CIR(0) || 1616 regbase == NIX_AF_TL2X_PIR(0)); 1617 break; 1618 case NIX_TXSCH_LVL_TL3: 1619 md_debug0 = NIX_AF_TL3X_MD_DEBUG0(schq); 1620 sw_xoff = NIX_AF_TL3X_SW_XOFF(schq); 1621 1622 rate_reg = (regbase == NIX_AF_TL3X_CIR(0) || 1623 regbase == NIX_AF_TL3X_PIR(0)); 1624 break; 1625 case NIX_TXSCH_LVL_TL4: 1626 md_debug0 = NIX_AF_TL4X_MD_DEBUG0(schq); 1627 sw_xoff = NIX_AF_TL4X_SW_XOFF(schq); 1628 1629 rate_reg = (regbase == NIX_AF_TL4X_CIR(0) || 1630 regbase == NIX_AF_TL4X_PIR(0)); 1631 break; 1632 case NIX_TXSCH_LVL_MDQ: 1633 sw_xoff = NIX_AF_MDQX_SW_XOFF(schq); 1634 rate_reg = (regbase == NIX_AF_MDQX_CIR(0) || 1635 regbase == NIX_AF_MDQX_PIR(0)); 1636 break; 1637 } 1638 1639 if (!rate_reg) 1640 return false; 1641 1642 /* Nothing special to do when state is not toggled */ 1643 oldval = rvu_read64(rvu, blkaddr, reg); 1644 if ((oldval & 0x1) == (regval & 0x1)) { 1645 rvu_write64(rvu, blkaddr, reg, regval); 1646 return true; 1647 } 1648 1649 /* PIR/CIR disable */ 1650 if (!(regval & 0x1)) { 1651 rvu_write64(rvu, blkaddr, sw_xoff, 1); 1652 rvu_write64(rvu, blkaddr, reg, 0); 1653 udelay(4); 1654 rvu_write64(rvu, blkaddr, sw_xoff, 0); 1655 return true; 1656 } 1657 1658 /* PIR/CIR enable */ 1659 rvu_write64(rvu, blkaddr, sw_xoff, 1); 1660 if (md_debug0) { 1661 poll_tmo = jiffies + usecs_to_jiffies(10000); 1662 /* Wait until VLD(bit32) == 1 or C_CON(bit48) == 0 */ 1663 do { 1664 if (time_after(jiffies, poll_tmo)) { 1665 dev_err(rvu->dev, 1666 "NIXLF%d: TLX%u(lvl %u) CIR/PIR enable failed\n", 1667 nixlf, schq, lvl); 1668 goto exit; 1669 } 1670 usleep_range(1, 5); 1671 dbgval = rvu_read64(rvu, blkaddr, md_debug0); 1672 } while (!(dbgval & BIT_ULL(32)) && (dbgval & BIT_ULL(48))); 1673 } 1674 rvu_write64(rvu, blkaddr, reg, regval); 1675 exit: 1676 rvu_write64(rvu, blkaddr, sw_xoff, 0); 1677 return true; 1678 } 1679 1680 /* Disable shaping of pkts by a scheduler queue 1681 * at a given scheduler level. 1682 */ 1683 static void nix_reset_tx_shaping(struct rvu *rvu, int blkaddr, 1684 int nixlf, int lvl, int schq) 1685 { 1686 struct rvu_hwinfo *hw = rvu->hw; 1687 u64 cir_reg = 0, pir_reg = 0; 1688 u64 cfg; 1689 1690 switch (lvl) { 1691 case NIX_TXSCH_LVL_TL1: 1692 cir_reg = NIX_AF_TL1X_CIR(schq); 1693 pir_reg = 0; /* PIR not available at TL1 */ 1694 break; 1695 case NIX_TXSCH_LVL_TL2: 1696 cir_reg = NIX_AF_TL2X_CIR(schq); 1697 pir_reg = NIX_AF_TL2X_PIR(schq); 1698 break; 1699 case NIX_TXSCH_LVL_TL3: 1700 cir_reg = NIX_AF_TL3X_CIR(schq); 1701 pir_reg = NIX_AF_TL3X_PIR(schq); 1702 break; 1703 case NIX_TXSCH_LVL_TL4: 1704 cir_reg = NIX_AF_TL4X_CIR(schq); 1705 pir_reg = NIX_AF_TL4X_PIR(schq); 1706 break; 1707 case NIX_TXSCH_LVL_MDQ: 1708 cir_reg = NIX_AF_MDQX_CIR(schq); 1709 pir_reg = NIX_AF_MDQX_PIR(schq); 1710 break; 1711 } 1712 1713 /* Shaper state toggle needs wait/poll */ 1714 if (hw->cap.nix_shaper_toggle_wait) { 1715 if (cir_reg) 1716 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 1717 lvl, cir_reg, 0); 1718 if (pir_reg) 1719 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 1720 lvl, pir_reg, 0); 1721 return; 1722 } 1723 1724 if (!cir_reg) 1725 return; 1726 cfg = rvu_read64(rvu, blkaddr, cir_reg); 1727 rvu_write64(rvu, blkaddr, cir_reg, cfg & ~BIT_ULL(0)); 1728 1729 if (!pir_reg) 1730 return; 1731 cfg = rvu_read64(rvu, blkaddr, pir_reg); 1732 rvu_write64(rvu, blkaddr, pir_reg, cfg & ~BIT_ULL(0)); 1733 } 1734 1735 static void nix_reset_tx_linkcfg(struct rvu *rvu, int blkaddr, 1736 int lvl, int schq) 1737 { 1738 struct rvu_hwinfo *hw = rvu->hw; 1739 int link_level; 1740 int link; 1741 1742 if (lvl >= hw->cap.nix_tx_aggr_lvl) 1743 return; 1744 1745 /* Reset TL4's SDP link config */ 1746 if (lvl == NIX_TXSCH_LVL_TL4) 1747 rvu_write64(rvu, blkaddr, NIX_AF_TL4X_SDP_LINK_CFG(schq), 0x00); 1748 1749 link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ? 1750 NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2; 1751 if (lvl != link_level) 1752 return; 1753 1754 /* Reset TL2's CGX or LBK link config */ 1755 for (link = 0; link < (hw->cgx_links + hw->lbk_links); link++) 1756 rvu_write64(rvu, blkaddr, 1757 NIX_AF_TL3_TL2X_LINKX_CFG(schq, link), 0x00); 1758 } 1759 1760 static void nix_clear_tx_xoff(struct rvu *rvu, int blkaddr, 1761 int lvl, int schq) 1762 { 1763 struct rvu_hwinfo *hw = rvu->hw; 1764 u64 reg; 1765 1766 /* Skip this if shaping is not supported */ 1767 if (!hw->cap.nix_shaping) 1768 return; 1769 1770 /* Clear level specific SW_XOFF */ 1771 switch (lvl) { 1772 case NIX_TXSCH_LVL_TL1: 1773 reg = NIX_AF_TL1X_SW_XOFF(schq); 1774 break; 1775 case NIX_TXSCH_LVL_TL2: 1776 reg = NIX_AF_TL2X_SW_XOFF(schq); 1777 break; 1778 case NIX_TXSCH_LVL_TL3: 1779 reg = NIX_AF_TL3X_SW_XOFF(schq); 1780 break; 1781 case NIX_TXSCH_LVL_TL4: 1782 reg = NIX_AF_TL4X_SW_XOFF(schq); 1783 break; 1784 case NIX_TXSCH_LVL_MDQ: 1785 reg = NIX_AF_MDQX_SW_XOFF(schq); 1786 break; 1787 default: 1788 return; 1789 } 1790 1791 rvu_write64(rvu, blkaddr, reg, 0x0); 1792 } 1793 1794 static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc) 1795 { 1796 struct rvu_hwinfo *hw = rvu->hw; 1797 int pf = rvu_get_pf(pcifunc); 1798 u8 cgx_id = 0, lmac_id = 0; 1799 1800 if (is_afvf(pcifunc)) {/* LBK links */ 1801 return hw->cgx_links; 1802 } else if (is_pf_cgxmapped(rvu, pf)) { 1803 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1804 return (cgx_id * hw->lmac_per_cgx) + lmac_id; 1805 } 1806 1807 /* SDP link */ 1808 return hw->cgx_links + hw->lbk_links; 1809 } 1810 1811 static void nix_get_txschq_range(struct rvu *rvu, u16 pcifunc, 1812 int link, int *start, int *end) 1813 { 1814 struct rvu_hwinfo *hw = rvu->hw; 1815 int pf = rvu_get_pf(pcifunc); 1816 1817 if (is_afvf(pcifunc)) { /* LBK links */ 1818 *start = hw->cap.nix_txsch_per_cgx_lmac * link; 1819 *end = *start + hw->cap.nix_txsch_per_lbk_lmac; 1820 } else if (is_pf_cgxmapped(rvu, pf)) { /* CGX links */ 1821 *start = hw->cap.nix_txsch_per_cgx_lmac * link; 1822 *end = *start + hw->cap.nix_txsch_per_cgx_lmac; 1823 } else { /* SDP link */ 1824 *start = (hw->cap.nix_txsch_per_cgx_lmac * hw->cgx_links) + 1825 (hw->cap.nix_txsch_per_lbk_lmac * hw->lbk_links); 1826 *end = *start + hw->cap.nix_txsch_per_sdp_lmac; 1827 } 1828 } 1829 1830 static int nix_check_txschq_alloc_req(struct rvu *rvu, int lvl, u16 pcifunc, 1831 struct nix_hw *nix_hw, 1832 struct nix_txsch_alloc_req *req) 1833 { 1834 struct rvu_hwinfo *hw = rvu->hw; 1835 int schq, req_schq, free_cnt; 1836 struct nix_txsch *txsch; 1837 int link, start, end; 1838 1839 txsch = &nix_hw->txsch[lvl]; 1840 req_schq = req->schq_contig[lvl] + req->schq[lvl]; 1841 1842 if (!req_schq) 1843 return 0; 1844 1845 link = nix_get_tx_link(rvu, pcifunc); 1846 1847 /* For traffic aggregating scheduler level, one queue is enough */ 1848 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 1849 if (req_schq != 1) 1850 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1851 return 0; 1852 } 1853 1854 /* Get free SCHQ count and check if request can be accomodated */ 1855 if (hw->cap.nix_fixed_txschq_mapping) { 1856 nix_get_txschq_range(rvu, pcifunc, link, &start, &end); 1857 schq = start + (pcifunc & RVU_PFVF_FUNC_MASK); 1858 if (end <= txsch->schq.max && schq < end && 1859 !test_bit(schq, txsch->schq.bmap)) 1860 free_cnt = 1; 1861 else 1862 free_cnt = 0; 1863 } else { 1864 free_cnt = rvu_rsrc_free_count(&txsch->schq); 1865 } 1866 1867 if (free_cnt < req_schq || req_schq > MAX_TXSCHQ_PER_FUNC) 1868 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1869 1870 /* If contiguous queues are needed, check for availability */ 1871 if (!hw->cap.nix_fixed_txschq_mapping && req->schq_contig[lvl] && 1872 !rvu_rsrc_check_contig(&txsch->schq, req->schq_contig[lvl])) 1873 return NIX_AF_ERR_TLX_ALLOC_FAIL; 1874 1875 return 0; 1876 } 1877 1878 static void nix_txsch_alloc(struct rvu *rvu, struct nix_txsch *txsch, 1879 struct nix_txsch_alloc_rsp *rsp, 1880 int lvl, int start, int end) 1881 { 1882 struct rvu_hwinfo *hw = rvu->hw; 1883 u16 pcifunc = rsp->hdr.pcifunc; 1884 int idx, schq; 1885 1886 /* For traffic aggregating levels, queue alloc is based 1887 * on transmit link to which PF_FUNC is mapped to. 1888 */ 1889 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 1890 /* A single TL queue is allocated */ 1891 if (rsp->schq_contig[lvl]) { 1892 rsp->schq_contig[lvl] = 1; 1893 rsp->schq_contig_list[lvl][0] = start; 1894 } 1895 1896 /* Both contig and non-contig reqs doesn't make sense here */ 1897 if (rsp->schq_contig[lvl]) 1898 rsp->schq[lvl] = 0; 1899 1900 if (rsp->schq[lvl]) { 1901 rsp->schq[lvl] = 1; 1902 rsp->schq_list[lvl][0] = start; 1903 } 1904 return; 1905 } 1906 1907 /* Adjust the queue request count if HW supports 1908 * only one queue per level configuration. 1909 */ 1910 if (hw->cap.nix_fixed_txschq_mapping) { 1911 idx = pcifunc & RVU_PFVF_FUNC_MASK; 1912 schq = start + idx; 1913 if (idx >= (end - start) || test_bit(schq, txsch->schq.bmap)) { 1914 rsp->schq_contig[lvl] = 0; 1915 rsp->schq[lvl] = 0; 1916 return; 1917 } 1918 1919 if (rsp->schq_contig[lvl]) { 1920 rsp->schq_contig[lvl] = 1; 1921 set_bit(schq, txsch->schq.bmap); 1922 rsp->schq_contig_list[lvl][0] = schq; 1923 rsp->schq[lvl] = 0; 1924 } else if (rsp->schq[lvl]) { 1925 rsp->schq[lvl] = 1; 1926 set_bit(schq, txsch->schq.bmap); 1927 rsp->schq_list[lvl][0] = schq; 1928 } 1929 return; 1930 } 1931 1932 /* Allocate contiguous queue indices requesty first */ 1933 if (rsp->schq_contig[lvl]) { 1934 schq = bitmap_find_next_zero_area(txsch->schq.bmap, 1935 txsch->schq.max, start, 1936 rsp->schq_contig[lvl], 0); 1937 if (schq >= end) 1938 rsp->schq_contig[lvl] = 0; 1939 for (idx = 0; idx < rsp->schq_contig[lvl]; idx++) { 1940 set_bit(schq, txsch->schq.bmap); 1941 rsp->schq_contig_list[lvl][idx] = schq; 1942 schq++; 1943 } 1944 } 1945 1946 /* Allocate non-contiguous queue indices */ 1947 if (rsp->schq[lvl]) { 1948 idx = 0; 1949 for (schq = start; schq < end; schq++) { 1950 if (!test_bit(schq, txsch->schq.bmap)) { 1951 set_bit(schq, txsch->schq.bmap); 1952 rsp->schq_list[lvl][idx++] = schq; 1953 } 1954 if (idx == rsp->schq[lvl]) 1955 break; 1956 } 1957 /* Update how many were allocated */ 1958 rsp->schq[lvl] = idx; 1959 } 1960 } 1961 1962 int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu, 1963 struct nix_txsch_alloc_req *req, 1964 struct nix_txsch_alloc_rsp *rsp) 1965 { 1966 struct rvu_hwinfo *hw = rvu->hw; 1967 u16 pcifunc = req->hdr.pcifunc; 1968 int link, blkaddr, rc = 0; 1969 int lvl, idx, start, end; 1970 struct nix_txsch *txsch; 1971 struct nix_hw *nix_hw; 1972 u32 *pfvf_map; 1973 int nixlf; 1974 u16 schq; 1975 1976 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 1977 if (rc) 1978 return rc; 1979 1980 nix_hw = get_nix_hw(rvu->hw, blkaddr); 1981 if (!nix_hw) 1982 return NIX_AF_ERR_INVALID_NIXBLK; 1983 1984 mutex_lock(&rvu->rsrc_lock); 1985 1986 /* Check if request is valid as per HW capabilities 1987 * and can be accomodated. 1988 */ 1989 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1990 rc = nix_check_txschq_alloc_req(rvu, lvl, pcifunc, nix_hw, req); 1991 if (rc) 1992 goto err; 1993 } 1994 1995 /* Allocate requested Tx scheduler queues */ 1996 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1997 txsch = &nix_hw->txsch[lvl]; 1998 pfvf_map = txsch->pfvf_map; 1999 2000 if (!req->schq[lvl] && !req->schq_contig[lvl]) 2001 continue; 2002 2003 rsp->schq[lvl] = req->schq[lvl]; 2004 rsp->schq_contig[lvl] = req->schq_contig[lvl]; 2005 2006 link = nix_get_tx_link(rvu, pcifunc); 2007 2008 if (lvl >= hw->cap.nix_tx_aggr_lvl) { 2009 start = link; 2010 end = link; 2011 } else if (hw->cap.nix_fixed_txschq_mapping) { 2012 nix_get_txschq_range(rvu, pcifunc, link, &start, &end); 2013 } else { 2014 start = 0; 2015 end = txsch->schq.max; 2016 } 2017 2018 nix_txsch_alloc(rvu, txsch, rsp, lvl, start, end); 2019 2020 /* Reset queue config */ 2021 for (idx = 0; idx < req->schq_contig[lvl]; idx++) { 2022 schq = rsp->schq_contig_list[lvl][idx]; 2023 if (!(TXSCH_MAP_FLAGS(pfvf_map[schq]) & 2024 NIX_TXSCHQ_CFG_DONE)) 2025 pfvf_map[schq] = TXSCH_MAP(pcifunc, 0); 2026 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2027 nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq); 2028 } 2029 2030 for (idx = 0; idx < req->schq[lvl]; idx++) { 2031 schq = rsp->schq_list[lvl][idx]; 2032 if (!(TXSCH_MAP_FLAGS(pfvf_map[schq]) & 2033 NIX_TXSCHQ_CFG_DONE)) 2034 pfvf_map[schq] = TXSCH_MAP(pcifunc, 0); 2035 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2036 nix_reset_tx_shaping(rvu, blkaddr, nixlf, lvl, schq); 2037 } 2038 } 2039 2040 rsp->aggr_level = hw->cap.nix_tx_aggr_lvl; 2041 rsp->aggr_lvl_rr_prio = TXSCH_TL1_DFLT_RR_PRIO; 2042 rsp->link_cfg_lvl = rvu_read64(rvu, blkaddr, 2043 NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ? 2044 NIX_TXSCH_LVL_TL3 : NIX_TXSCH_LVL_TL2; 2045 goto exit; 2046 err: 2047 rc = NIX_AF_ERR_TLX_ALLOC_FAIL; 2048 exit: 2049 mutex_unlock(&rvu->rsrc_lock); 2050 return rc; 2051 } 2052 2053 static int nix_smq_flush(struct rvu *rvu, int blkaddr, 2054 int smq, u16 pcifunc, int nixlf) 2055 { 2056 int pf = rvu_get_pf(pcifunc); 2057 u8 cgx_id = 0, lmac_id = 0; 2058 int err, restore_tx_en = 0; 2059 u64 cfg; 2060 2061 /* enable cgx tx if disabled */ 2062 if (is_pf_cgxmapped(rvu, pf)) { 2063 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 2064 restore_tx_en = !rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), 2065 lmac_id, true); 2066 } 2067 2068 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq)); 2069 /* Do SMQ flush and set enqueue xoff */ 2070 cfg |= BIT_ULL(50) | BIT_ULL(49); 2071 rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq), cfg); 2072 2073 /* Disable backpressure from physical link, 2074 * otherwise SMQ flush may stall. 2075 */ 2076 rvu_cgx_enadis_rx_bp(rvu, pf, false); 2077 2078 /* Wait for flush to complete */ 2079 err = rvu_poll_reg(rvu, blkaddr, 2080 NIX_AF_SMQX_CFG(smq), BIT_ULL(49), true); 2081 if (err) 2082 dev_err(rvu->dev, 2083 "NIXLF%d: SMQ%d flush failed\n", nixlf, smq); 2084 2085 rvu_cgx_enadis_rx_bp(rvu, pf, true); 2086 /* restore cgx tx state */ 2087 if (restore_tx_en) 2088 rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false); 2089 return err; 2090 } 2091 2092 static int nix_txschq_free(struct rvu *rvu, u16 pcifunc) 2093 { 2094 int blkaddr, nixlf, lvl, schq, err; 2095 struct rvu_hwinfo *hw = rvu->hw; 2096 struct nix_txsch *txsch; 2097 struct nix_hw *nix_hw; 2098 u16 map_func; 2099 2100 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2101 if (blkaddr < 0) 2102 return NIX_AF_ERR_AF_LF_INVALID; 2103 2104 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2105 if (!nix_hw) 2106 return NIX_AF_ERR_INVALID_NIXBLK; 2107 2108 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2109 if (nixlf < 0) 2110 return NIX_AF_ERR_AF_LF_INVALID; 2111 2112 /* Disable TL2/3 queue links and all XOFF's before SMQ flush*/ 2113 mutex_lock(&rvu->rsrc_lock); 2114 for (lvl = NIX_TXSCH_LVL_MDQ; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2115 txsch = &nix_hw->txsch[lvl]; 2116 2117 if (lvl >= hw->cap.nix_tx_aggr_lvl) 2118 continue; 2119 2120 for (schq = 0; schq < txsch->schq.max; schq++) { 2121 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2122 continue; 2123 nix_reset_tx_linkcfg(rvu, blkaddr, lvl, schq); 2124 nix_clear_tx_xoff(rvu, blkaddr, lvl, schq); 2125 } 2126 } 2127 nix_clear_tx_xoff(rvu, blkaddr, NIX_TXSCH_LVL_TL1, 2128 nix_get_tx_link(rvu, pcifunc)); 2129 2130 /* On PF cleanup, clear cfg done flag as 2131 * PF would have changed default config. 2132 */ 2133 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) { 2134 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL1]; 2135 schq = nix_get_tx_link(rvu, pcifunc); 2136 /* Do not clear pcifunc in txsch->pfvf_map[schq] because 2137 * VF might be using this TL1 queue 2138 */ 2139 map_func = TXSCH_MAP_FUNC(txsch->pfvf_map[schq]); 2140 txsch->pfvf_map[schq] = TXSCH_SET_FLAG(map_func, 0x0); 2141 } 2142 2143 /* Flush SMQs */ 2144 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 2145 for (schq = 0; schq < txsch->schq.max; schq++) { 2146 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2147 continue; 2148 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf); 2149 } 2150 2151 /* Now free scheduler queues to free pool */ 2152 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 2153 /* TLs above aggregation level are shared across all PF 2154 * and it's VFs, hence skip freeing them. 2155 */ 2156 if (lvl >= hw->cap.nix_tx_aggr_lvl) 2157 continue; 2158 2159 txsch = &nix_hw->txsch[lvl]; 2160 for (schq = 0; schq < txsch->schq.max; schq++) { 2161 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2162 continue; 2163 rvu_free_rsrc(&txsch->schq, schq); 2164 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 2165 } 2166 } 2167 mutex_unlock(&rvu->rsrc_lock); 2168 2169 /* Sync cached info for this LF in NDC-TX to LLC/DRAM */ 2170 rvu_write64(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12) | nixlf); 2171 err = rvu_poll_reg(rvu, blkaddr, NIX_AF_NDC_TX_SYNC, BIT_ULL(12), true); 2172 if (err) 2173 dev_err(rvu->dev, "NDC-TX sync failed for NIXLF %d\n", nixlf); 2174 2175 return 0; 2176 } 2177 2178 static int nix_txschq_free_one(struct rvu *rvu, 2179 struct nix_txsch_free_req *req) 2180 { 2181 struct rvu_hwinfo *hw = rvu->hw; 2182 u16 pcifunc = req->hdr.pcifunc; 2183 int lvl, schq, nixlf, blkaddr; 2184 struct nix_txsch *txsch; 2185 struct nix_hw *nix_hw; 2186 u32 *pfvf_map; 2187 int rc; 2188 2189 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2190 if (blkaddr < 0) 2191 return NIX_AF_ERR_AF_LF_INVALID; 2192 2193 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2194 if (!nix_hw) 2195 return NIX_AF_ERR_INVALID_NIXBLK; 2196 2197 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2198 if (nixlf < 0) 2199 return NIX_AF_ERR_AF_LF_INVALID; 2200 2201 lvl = req->schq_lvl; 2202 schq = req->schq; 2203 txsch = &nix_hw->txsch[lvl]; 2204 2205 if (lvl >= hw->cap.nix_tx_aggr_lvl || schq >= txsch->schq.max) 2206 return 0; 2207 2208 pfvf_map = txsch->pfvf_map; 2209 mutex_lock(&rvu->rsrc_lock); 2210 2211 if (TXSCH_MAP_FUNC(pfvf_map[schq]) != pcifunc) { 2212 rc = NIX_AF_ERR_TLX_INVALID; 2213 goto err; 2214 } 2215 2216 /* Clear SW_XOFF of this resource only. 2217 * For SMQ level, all path XOFF's 2218 * need to be made clear by user 2219 */ 2220 nix_clear_tx_xoff(rvu, blkaddr, lvl, schq); 2221 2222 /* Flush if it is a SMQ. Onus of disabling 2223 * TL2/3 queue links before SMQ flush is on user 2224 */ 2225 if (lvl == NIX_TXSCH_LVL_SMQ && 2226 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf)) { 2227 rc = NIX_AF_SMQ_FLUSH_FAILED; 2228 goto err; 2229 } 2230 2231 /* Free the resource */ 2232 rvu_free_rsrc(&txsch->schq, schq); 2233 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 2234 mutex_unlock(&rvu->rsrc_lock); 2235 return 0; 2236 err: 2237 mutex_unlock(&rvu->rsrc_lock); 2238 return rc; 2239 } 2240 2241 int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu, 2242 struct nix_txsch_free_req *req, 2243 struct msg_rsp *rsp) 2244 { 2245 if (req->flags & TXSCHQ_FREE_ALL) 2246 return nix_txschq_free(rvu, req->hdr.pcifunc); 2247 else 2248 return nix_txschq_free_one(rvu, req); 2249 } 2250 2251 static bool is_txschq_hierarchy_valid(struct rvu *rvu, u16 pcifunc, int blkaddr, 2252 int lvl, u64 reg, u64 regval) 2253 { 2254 u64 regbase = reg & 0xFFFF; 2255 u16 schq, parent; 2256 2257 if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, lvl, reg)) 2258 return false; 2259 2260 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2261 /* Check if this schq belongs to this PF/VF or not */ 2262 if (!is_valid_txschq(rvu, blkaddr, lvl, pcifunc, schq)) 2263 return false; 2264 2265 parent = (regval >> 16) & 0x1FF; 2266 /* Validate MDQ's TL4 parent */ 2267 if (regbase == NIX_AF_MDQX_PARENT(0) && 2268 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL4, pcifunc, parent)) 2269 return false; 2270 2271 /* Validate TL4's TL3 parent */ 2272 if (regbase == NIX_AF_TL4X_PARENT(0) && 2273 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL3, pcifunc, parent)) 2274 return false; 2275 2276 /* Validate TL3's TL2 parent */ 2277 if (regbase == NIX_AF_TL3X_PARENT(0) && 2278 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL2, pcifunc, parent)) 2279 return false; 2280 2281 /* Validate TL2's TL1 parent */ 2282 if (regbase == NIX_AF_TL2X_PARENT(0) && 2283 !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL1, pcifunc, parent)) 2284 return false; 2285 2286 return true; 2287 } 2288 2289 static bool is_txschq_shaping_valid(struct rvu_hwinfo *hw, int lvl, u64 reg) 2290 { 2291 u64 regbase; 2292 2293 if (hw->cap.nix_shaping) 2294 return true; 2295 2296 /* If shaping and coloring is not supported, then 2297 * *_CIR and *_PIR registers should not be configured. 2298 */ 2299 regbase = reg & 0xFFFF; 2300 2301 switch (lvl) { 2302 case NIX_TXSCH_LVL_TL1: 2303 if (regbase == NIX_AF_TL1X_CIR(0)) 2304 return false; 2305 break; 2306 case NIX_TXSCH_LVL_TL2: 2307 if (regbase == NIX_AF_TL2X_CIR(0) || 2308 regbase == NIX_AF_TL2X_PIR(0)) 2309 return false; 2310 break; 2311 case NIX_TXSCH_LVL_TL3: 2312 if (regbase == NIX_AF_TL3X_CIR(0) || 2313 regbase == NIX_AF_TL3X_PIR(0)) 2314 return false; 2315 break; 2316 case NIX_TXSCH_LVL_TL4: 2317 if (regbase == NIX_AF_TL4X_CIR(0) || 2318 regbase == NIX_AF_TL4X_PIR(0)) 2319 return false; 2320 break; 2321 case NIX_TXSCH_LVL_MDQ: 2322 if (regbase == NIX_AF_MDQX_CIR(0) || 2323 regbase == NIX_AF_MDQX_PIR(0)) 2324 return false; 2325 break; 2326 } 2327 return true; 2328 } 2329 2330 static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw, 2331 u16 pcifunc, int blkaddr) 2332 { 2333 u32 *pfvf_map; 2334 int schq; 2335 2336 schq = nix_get_tx_link(rvu, pcifunc); 2337 pfvf_map = nix_hw->txsch[NIX_TXSCH_LVL_TL1].pfvf_map; 2338 /* Skip if PF has already done the config */ 2339 if (TXSCH_MAP_FLAGS(pfvf_map[schq]) & NIX_TXSCHQ_CFG_DONE) 2340 return; 2341 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_TOPOLOGY(schq), 2342 (TXSCH_TL1_DFLT_RR_PRIO << 1)); 2343 2344 /* On OcteonTx2 the config was in bytes and newer silcons 2345 * it's changed to weight. 2346 */ 2347 if (!rvu->hw->cap.nix_common_dwrr_mtu) 2348 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq), 2349 TXSCH_TL1_DFLT_RR_QTM); 2350 else 2351 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq), 2352 CN10K_MAX_DWRR_WEIGHT); 2353 2354 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_CIR(schq), 0x00); 2355 pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], NIX_TXSCHQ_CFG_DONE); 2356 } 2357 2358 /* Register offset - [15:0] 2359 * Scheduler Queue number - [25:16] 2360 */ 2361 #define NIX_TX_SCHQ_MASK GENMASK_ULL(25, 0) 2362 2363 static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw, 2364 int blkaddr, struct nix_txschq_config *req, 2365 struct nix_txschq_config *rsp) 2366 { 2367 u16 pcifunc = req->hdr.pcifunc; 2368 int idx, schq; 2369 u64 reg; 2370 2371 for (idx = 0; idx < req->num_regs; idx++) { 2372 reg = req->reg[idx]; 2373 reg &= NIX_TX_SCHQ_MASK; 2374 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2375 if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, req->lvl, reg) || 2376 !is_valid_txschq(rvu, blkaddr, req->lvl, pcifunc, schq)) 2377 return NIX_AF_INVAL_TXSCHQ_CFG; 2378 rsp->regval[idx] = rvu_read64(rvu, blkaddr, reg); 2379 } 2380 rsp->lvl = req->lvl; 2381 rsp->num_regs = req->num_regs; 2382 return 0; 2383 } 2384 2385 static void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, 2386 u16 pcifunc, struct nix_txsch *txsch) 2387 { 2388 struct rvu_hwinfo *hw = rvu->hw; 2389 int lbk_link_start, lbk_links; 2390 u8 pf = rvu_get_pf(pcifunc); 2391 int schq; 2392 2393 if (!is_pf_cgxmapped(rvu, pf)) 2394 return; 2395 2396 lbk_link_start = hw->cgx_links; 2397 2398 for (schq = 0; schq < txsch->schq.max; schq++) { 2399 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 2400 continue; 2401 /* Enable all LBK links with channel 63 by default so that 2402 * packets can be sent to LBK with a NPC TX MCAM rule 2403 */ 2404 lbk_links = hw->lbk_links; 2405 while (lbk_links--) 2406 rvu_write64(rvu, blkaddr, 2407 NIX_AF_TL3_TL2X_LINKX_CFG(schq, 2408 lbk_link_start + 2409 lbk_links), 2410 BIT_ULL(12) | RVU_SWITCH_LBK_CHAN); 2411 } 2412 } 2413 2414 int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu, 2415 struct nix_txschq_config *req, 2416 struct nix_txschq_config *rsp) 2417 { 2418 u64 reg, val, regval, schq_regbase, val_mask; 2419 struct rvu_hwinfo *hw = rvu->hw; 2420 u16 pcifunc = req->hdr.pcifunc; 2421 struct nix_txsch *txsch; 2422 struct nix_hw *nix_hw; 2423 int blkaddr, idx, err; 2424 int nixlf, schq; 2425 u32 *pfvf_map; 2426 2427 if (req->lvl >= NIX_TXSCH_LVL_CNT || 2428 req->num_regs > MAX_REGS_PER_MBOX_MSG) 2429 return NIX_AF_INVAL_TXSCHQ_CFG; 2430 2431 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 2432 if (err) 2433 return err; 2434 2435 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2436 if (!nix_hw) 2437 return NIX_AF_ERR_INVALID_NIXBLK; 2438 2439 if (req->read) 2440 return nix_txschq_cfg_read(rvu, nix_hw, blkaddr, req, rsp); 2441 2442 txsch = &nix_hw->txsch[req->lvl]; 2443 pfvf_map = txsch->pfvf_map; 2444 2445 if (req->lvl >= hw->cap.nix_tx_aggr_lvl && 2446 pcifunc & RVU_PFVF_FUNC_MASK) { 2447 mutex_lock(&rvu->rsrc_lock); 2448 if (req->lvl == NIX_TXSCH_LVL_TL1) 2449 nix_tl1_default_cfg(rvu, nix_hw, pcifunc, blkaddr); 2450 mutex_unlock(&rvu->rsrc_lock); 2451 return 0; 2452 } 2453 2454 for (idx = 0; idx < req->num_regs; idx++) { 2455 reg = req->reg[idx]; 2456 reg &= NIX_TX_SCHQ_MASK; 2457 regval = req->regval[idx]; 2458 schq_regbase = reg & 0xFFFF; 2459 val_mask = req->regval_mask[idx]; 2460 2461 if (!is_txschq_hierarchy_valid(rvu, pcifunc, blkaddr, 2462 txsch->lvl, reg, regval)) 2463 return NIX_AF_INVAL_TXSCHQ_CFG; 2464 2465 /* Check if shaping and coloring is supported */ 2466 if (!is_txschq_shaping_valid(hw, req->lvl, reg)) 2467 continue; 2468 2469 val = rvu_read64(rvu, blkaddr, reg); 2470 regval = (val & val_mask) | (regval & ~val_mask); 2471 2472 /* Handle shaping state toggle specially */ 2473 if (hw->cap.nix_shaper_toggle_wait && 2474 handle_txschq_shaper_update(rvu, blkaddr, nixlf, 2475 req->lvl, reg, regval)) 2476 continue; 2477 2478 /* Replace PF/VF visible NIXLF slot with HW NIXLF id */ 2479 if (schq_regbase == NIX_AF_SMQX_CFG(0)) { 2480 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 2481 pcifunc, 0); 2482 regval &= ~(0x7FULL << 24); 2483 regval |= ((u64)nixlf << 24); 2484 } 2485 2486 /* Clear 'BP_ENA' config, if it's not allowed */ 2487 if (!hw->cap.nix_tx_link_bp) { 2488 if (schq_regbase == NIX_AF_TL4X_SDP_LINK_CFG(0) || 2489 (schq_regbase & 0xFF00) == 2490 NIX_AF_TL3_TL2X_LINKX_CFG(0, 0)) 2491 regval &= ~BIT_ULL(13); 2492 } 2493 2494 /* Mark config as done for TL1 by PF */ 2495 if (schq_regbase >= NIX_AF_TL1X_SCHEDULE(0) && 2496 schq_regbase <= NIX_AF_TL1X_GREEN_BYTES(0)) { 2497 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2498 mutex_lock(&rvu->rsrc_lock); 2499 pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], 2500 NIX_TXSCHQ_CFG_DONE); 2501 mutex_unlock(&rvu->rsrc_lock); 2502 } 2503 2504 /* SMQ flush is special hence split register writes such 2505 * that flush first and write rest of the bits later. 2506 */ 2507 if (schq_regbase == NIX_AF_SMQX_CFG(0) && 2508 (regval & BIT_ULL(49))) { 2509 schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); 2510 nix_smq_flush(rvu, blkaddr, schq, pcifunc, nixlf); 2511 regval &= ~BIT_ULL(49); 2512 } 2513 rvu_write64(rvu, blkaddr, reg, regval); 2514 } 2515 2516 rvu_nix_tx_tl2_cfg(rvu, blkaddr, pcifunc, 2517 &nix_hw->txsch[NIX_TXSCH_LVL_TL2]); 2518 return 0; 2519 } 2520 2521 static int nix_rx_vtag_cfg(struct rvu *rvu, int nixlf, int blkaddr, 2522 struct nix_vtag_config *req) 2523 { 2524 u64 regval = req->vtag_size; 2525 2526 if (req->rx.vtag_type > NIX_AF_LFX_RX_VTAG_TYPE7 || 2527 req->vtag_size > VTAGSIZE_T8) 2528 return -EINVAL; 2529 2530 /* RX VTAG Type 7 reserved for vf vlan */ 2531 if (req->rx.vtag_type == NIX_AF_LFX_RX_VTAG_TYPE7) 2532 return NIX_AF_ERR_RX_VTAG_INUSE; 2533 2534 if (req->rx.capture_vtag) 2535 regval |= BIT_ULL(5); 2536 if (req->rx.strip_vtag) 2537 regval |= BIT_ULL(4); 2538 2539 rvu_write64(rvu, blkaddr, 2540 NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, req->rx.vtag_type), regval); 2541 return 0; 2542 } 2543 2544 static int nix_tx_vtag_free(struct rvu *rvu, int blkaddr, 2545 u16 pcifunc, int index) 2546 { 2547 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2548 struct nix_txvlan *vlan; 2549 2550 if (!nix_hw) 2551 return NIX_AF_ERR_INVALID_NIXBLK; 2552 2553 vlan = &nix_hw->txvlan; 2554 if (vlan->entry2pfvf_map[index] != pcifunc) 2555 return NIX_AF_ERR_PARAM; 2556 2557 rvu_write64(rvu, blkaddr, 2558 NIX_AF_TX_VTAG_DEFX_DATA(index), 0x0ull); 2559 rvu_write64(rvu, blkaddr, 2560 NIX_AF_TX_VTAG_DEFX_CTL(index), 0x0ull); 2561 2562 vlan->entry2pfvf_map[index] = 0; 2563 rvu_free_rsrc(&vlan->rsrc, index); 2564 2565 return 0; 2566 } 2567 2568 static void nix_free_tx_vtag_entries(struct rvu *rvu, u16 pcifunc) 2569 { 2570 struct nix_txvlan *vlan; 2571 struct nix_hw *nix_hw; 2572 int index, blkaddr; 2573 2574 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2575 if (blkaddr < 0) 2576 return; 2577 2578 nix_hw = get_nix_hw(rvu->hw, blkaddr); 2579 if (!nix_hw) 2580 return; 2581 2582 vlan = &nix_hw->txvlan; 2583 2584 mutex_lock(&vlan->rsrc_lock); 2585 /* Scan all the entries and free the ones mapped to 'pcifunc' */ 2586 for (index = 0; index < vlan->rsrc.max; index++) { 2587 if (vlan->entry2pfvf_map[index] == pcifunc) 2588 nix_tx_vtag_free(rvu, blkaddr, pcifunc, index); 2589 } 2590 mutex_unlock(&vlan->rsrc_lock); 2591 } 2592 2593 static int nix_tx_vtag_alloc(struct rvu *rvu, int blkaddr, 2594 u64 vtag, u8 size) 2595 { 2596 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2597 struct nix_txvlan *vlan; 2598 u64 regval; 2599 int index; 2600 2601 if (!nix_hw) 2602 return NIX_AF_ERR_INVALID_NIXBLK; 2603 2604 vlan = &nix_hw->txvlan; 2605 2606 mutex_lock(&vlan->rsrc_lock); 2607 2608 index = rvu_alloc_rsrc(&vlan->rsrc); 2609 if (index < 0) { 2610 mutex_unlock(&vlan->rsrc_lock); 2611 return index; 2612 } 2613 2614 mutex_unlock(&vlan->rsrc_lock); 2615 2616 regval = size ? vtag : vtag << 32; 2617 2618 rvu_write64(rvu, blkaddr, 2619 NIX_AF_TX_VTAG_DEFX_DATA(index), regval); 2620 rvu_write64(rvu, blkaddr, 2621 NIX_AF_TX_VTAG_DEFX_CTL(index), size); 2622 2623 return index; 2624 } 2625 2626 static int nix_tx_vtag_decfg(struct rvu *rvu, int blkaddr, 2627 struct nix_vtag_config *req) 2628 { 2629 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2630 u16 pcifunc = req->hdr.pcifunc; 2631 int idx0 = req->tx.vtag0_idx; 2632 int idx1 = req->tx.vtag1_idx; 2633 struct nix_txvlan *vlan; 2634 int err = 0; 2635 2636 if (!nix_hw) 2637 return NIX_AF_ERR_INVALID_NIXBLK; 2638 2639 vlan = &nix_hw->txvlan; 2640 if (req->tx.free_vtag0 && req->tx.free_vtag1) 2641 if (vlan->entry2pfvf_map[idx0] != pcifunc || 2642 vlan->entry2pfvf_map[idx1] != pcifunc) 2643 return NIX_AF_ERR_PARAM; 2644 2645 mutex_lock(&vlan->rsrc_lock); 2646 2647 if (req->tx.free_vtag0) { 2648 err = nix_tx_vtag_free(rvu, blkaddr, pcifunc, idx0); 2649 if (err) 2650 goto exit; 2651 } 2652 2653 if (req->tx.free_vtag1) 2654 err = nix_tx_vtag_free(rvu, blkaddr, pcifunc, idx1); 2655 2656 exit: 2657 mutex_unlock(&vlan->rsrc_lock); 2658 return err; 2659 } 2660 2661 static int nix_tx_vtag_cfg(struct rvu *rvu, int blkaddr, 2662 struct nix_vtag_config *req, 2663 struct nix_vtag_config_rsp *rsp) 2664 { 2665 struct nix_hw *nix_hw = get_nix_hw(rvu->hw, blkaddr); 2666 struct nix_txvlan *vlan; 2667 u16 pcifunc = req->hdr.pcifunc; 2668 2669 if (!nix_hw) 2670 return NIX_AF_ERR_INVALID_NIXBLK; 2671 2672 vlan = &nix_hw->txvlan; 2673 if (req->tx.cfg_vtag0) { 2674 rsp->vtag0_idx = 2675 nix_tx_vtag_alloc(rvu, blkaddr, 2676 req->tx.vtag0, req->vtag_size); 2677 2678 if (rsp->vtag0_idx < 0) 2679 return NIX_AF_ERR_TX_VTAG_NOSPC; 2680 2681 vlan->entry2pfvf_map[rsp->vtag0_idx] = pcifunc; 2682 } 2683 2684 if (req->tx.cfg_vtag1) { 2685 rsp->vtag1_idx = 2686 nix_tx_vtag_alloc(rvu, blkaddr, 2687 req->tx.vtag1, req->vtag_size); 2688 2689 if (rsp->vtag1_idx < 0) 2690 goto err_free; 2691 2692 vlan->entry2pfvf_map[rsp->vtag1_idx] = pcifunc; 2693 } 2694 2695 return 0; 2696 2697 err_free: 2698 if (req->tx.cfg_vtag0) 2699 nix_tx_vtag_free(rvu, blkaddr, pcifunc, rsp->vtag0_idx); 2700 2701 return NIX_AF_ERR_TX_VTAG_NOSPC; 2702 } 2703 2704 int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu, 2705 struct nix_vtag_config *req, 2706 struct nix_vtag_config_rsp *rsp) 2707 { 2708 u16 pcifunc = req->hdr.pcifunc; 2709 int blkaddr, nixlf, err; 2710 2711 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 2712 if (err) 2713 return err; 2714 2715 if (req->cfg_type) { 2716 /* rx vtag configuration */ 2717 err = nix_rx_vtag_cfg(rvu, nixlf, blkaddr, req); 2718 if (err) 2719 return NIX_AF_ERR_PARAM; 2720 } else { 2721 /* tx vtag configuration */ 2722 if ((req->tx.cfg_vtag0 || req->tx.cfg_vtag1) && 2723 (req->tx.free_vtag0 || req->tx.free_vtag1)) 2724 return NIX_AF_ERR_PARAM; 2725 2726 if (req->tx.cfg_vtag0 || req->tx.cfg_vtag1) 2727 return nix_tx_vtag_cfg(rvu, blkaddr, req, rsp); 2728 2729 if (req->tx.free_vtag0 || req->tx.free_vtag1) 2730 return nix_tx_vtag_decfg(rvu, blkaddr, req); 2731 } 2732 2733 return 0; 2734 } 2735 2736 static int nix_blk_setup_mce(struct rvu *rvu, struct nix_hw *nix_hw, 2737 int mce, u8 op, u16 pcifunc, int next, bool eol) 2738 { 2739 struct nix_aq_enq_req aq_req; 2740 int err; 2741 2742 aq_req.hdr.pcifunc = 0; 2743 aq_req.ctype = NIX_AQ_CTYPE_MCE; 2744 aq_req.op = op; 2745 aq_req.qidx = mce; 2746 2747 /* Use RSS with RSS index 0 */ 2748 aq_req.mce.op = 1; 2749 aq_req.mce.index = 0; 2750 aq_req.mce.eol = eol; 2751 aq_req.mce.pf_func = pcifunc; 2752 aq_req.mce.next = next; 2753 2754 /* All fields valid */ 2755 *(u64 *)(&aq_req.mce_mask) = ~0ULL; 2756 2757 err = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, &aq_req, NULL); 2758 if (err) { 2759 dev_err(rvu->dev, "Failed to setup Bcast MCE for PF%d:VF%d\n", 2760 rvu_get_pf(pcifunc), pcifunc & RVU_PFVF_FUNC_MASK); 2761 return err; 2762 } 2763 return 0; 2764 } 2765 2766 static int nix_update_mce_list_entry(struct nix_mce_list *mce_list, 2767 u16 pcifunc, bool add) 2768 { 2769 struct mce *mce, *tail = NULL; 2770 bool delete = false; 2771 2772 /* Scan through the current list */ 2773 hlist_for_each_entry(mce, &mce_list->head, node) { 2774 /* If already exists, then delete */ 2775 if (mce->pcifunc == pcifunc && !add) { 2776 delete = true; 2777 break; 2778 } else if (mce->pcifunc == pcifunc && add) { 2779 /* entry already exists */ 2780 return 0; 2781 } 2782 tail = mce; 2783 } 2784 2785 if (delete) { 2786 hlist_del(&mce->node); 2787 kfree(mce); 2788 mce_list->count--; 2789 return 0; 2790 } 2791 2792 if (!add) 2793 return 0; 2794 2795 /* Add a new one to the list, at the tail */ 2796 mce = kzalloc(sizeof(*mce), GFP_KERNEL); 2797 if (!mce) 2798 return -ENOMEM; 2799 mce->pcifunc = pcifunc; 2800 if (!tail) 2801 hlist_add_head(&mce->node, &mce_list->head); 2802 else 2803 hlist_add_behind(&mce->node, &tail->node); 2804 mce_list->count++; 2805 return 0; 2806 } 2807 2808 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 2809 struct nix_mce_list *mce_list, 2810 int mce_idx, int mcam_index, bool add) 2811 { 2812 int err = 0, idx, next_idx, last_idx, blkaddr, npc_blkaddr; 2813 struct npc_mcam *mcam = &rvu->hw->mcam; 2814 struct nix_mcast *mcast; 2815 struct nix_hw *nix_hw; 2816 struct mce *mce; 2817 2818 if (!mce_list) 2819 return -EINVAL; 2820 2821 /* Get this PF/VF func's MCE index */ 2822 idx = mce_idx + (pcifunc & RVU_PFVF_FUNC_MASK); 2823 2824 if (idx > (mce_idx + mce_list->max)) { 2825 dev_err(rvu->dev, 2826 "%s: Idx %d > max MCE idx %d, for PF%d bcast list\n", 2827 __func__, idx, mce_list->max, 2828 pcifunc >> RVU_PFVF_PF_SHIFT); 2829 return -EINVAL; 2830 } 2831 2832 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 2833 if (err) 2834 return err; 2835 2836 mcast = &nix_hw->mcast; 2837 mutex_lock(&mcast->mce_lock); 2838 2839 err = nix_update_mce_list_entry(mce_list, pcifunc, add); 2840 if (err) 2841 goto end; 2842 2843 /* Disable MCAM entry in NPC */ 2844 if (!mce_list->count) { 2845 npc_blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2846 npc_enable_mcam_entry(rvu, mcam, npc_blkaddr, mcam_index, false); 2847 goto end; 2848 } 2849 2850 /* Dump the updated list to HW */ 2851 idx = mce_idx; 2852 last_idx = idx + mce_list->count - 1; 2853 hlist_for_each_entry(mce, &mce_list->head, node) { 2854 if (idx > last_idx) 2855 break; 2856 2857 next_idx = idx + 1; 2858 /* EOL should be set in last MCE */ 2859 err = nix_blk_setup_mce(rvu, nix_hw, idx, NIX_AQ_INSTOP_WRITE, 2860 mce->pcifunc, next_idx, 2861 (next_idx > last_idx) ? true : false); 2862 if (err) 2863 goto end; 2864 idx++; 2865 } 2866 2867 end: 2868 mutex_unlock(&mcast->mce_lock); 2869 return err; 2870 } 2871 2872 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 2873 struct nix_mce_list **mce_list, int *mce_idx) 2874 { 2875 struct rvu_hwinfo *hw = rvu->hw; 2876 struct rvu_pfvf *pfvf; 2877 2878 if (!hw->cap.nix_rx_multicast || 2879 !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc & ~RVU_PFVF_FUNC_MASK))) { 2880 *mce_list = NULL; 2881 *mce_idx = 0; 2882 return; 2883 } 2884 2885 /* Get this PF/VF func's MCE index */ 2886 pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 2887 2888 if (type == NIXLF_BCAST_ENTRY) { 2889 *mce_list = &pfvf->bcast_mce_list; 2890 *mce_idx = pfvf->bcast_mce_idx; 2891 } else if (type == NIXLF_ALLMULTI_ENTRY) { 2892 *mce_list = &pfvf->mcast_mce_list; 2893 *mce_idx = pfvf->mcast_mce_idx; 2894 } else if (type == NIXLF_PROMISC_ENTRY) { 2895 *mce_list = &pfvf->promisc_mce_list; 2896 *mce_idx = pfvf->promisc_mce_idx; 2897 } else { 2898 *mce_list = NULL; 2899 *mce_idx = 0; 2900 } 2901 } 2902 2903 static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc, 2904 int type, bool add) 2905 { 2906 int err = 0, nixlf, blkaddr, mcam_index, mce_idx; 2907 struct npc_mcam *mcam = &rvu->hw->mcam; 2908 struct rvu_hwinfo *hw = rvu->hw; 2909 struct nix_mce_list *mce_list; 2910 int pf; 2911 2912 /* skip multicast pkt replication for AF's VFs & SDP links */ 2913 if (is_afvf(pcifunc) || is_sdp_pfvf(pcifunc)) 2914 return 0; 2915 2916 if (!hw->cap.nix_rx_multicast) 2917 return 0; 2918 2919 pf = rvu_get_pf(pcifunc); 2920 if (!is_pf_cgxmapped(rvu, pf)) 2921 return 0; 2922 2923 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 2924 if (blkaddr < 0) 2925 return -EINVAL; 2926 2927 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 2928 if (nixlf < 0) 2929 return -EINVAL; 2930 2931 nix_get_mce_list(rvu, pcifunc, type, &mce_list, &mce_idx); 2932 2933 mcam_index = npc_get_nixlf_mcam_index(mcam, 2934 pcifunc & ~RVU_PFVF_FUNC_MASK, 2935 nixlf, type); 2936 err = nix_update_mce_list(rvu, pcifunc, mce_list, 2937 mce_idx, mcam_index, add); 2938 return err; 2939 } 2940 2941 static int nix_setup_mce_tables(struct rvu *rvu, struct nix_hw *nix_hw) 2942 { 2943 struct nix_mcast *mcast = &nix_hw->mcast; 2944 int err, pf, numvfs, idx; 2945 struct rvu_pfvf *pfvf; 2946 u16 pcifunc; 2947 u64 cfg; 2948 2949 /* Skip PF0 (i.e AF) */ 2950 for (pf = 1; pf < (rvu->cgx_mapped_pfs + 1); pf++) { 2951 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2952 /* If PF is not enabled, nothing to do */ 2953 if (!((cfg >> 20) & 0x01)) 2954 continue; 2955 /* Get numVFs attached to this PF */ 2956 numvfs = (cfg >> 12) & 0xFF; 2957 2958 pfvf = &rvu->pf[pf]; 2959 2960 /* This NIX0/1 block mapped to PF ? */ 2961 if (pfvf->nix_blkaddr != nix_hw->blkaddr) 2962 continue; 2963 2964 /* save start idx of broadcast mce list */ 2965 pfvf->bcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2966 nix_mce_list_init(&pfvf->bcast_mce_list, numvfs + 1); 2967 2968 /* save start idx of multicast mce list */ 2969 pfvf->mcast_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2970 nix_mce_list_init(&pfvf->mcast_mce_list, numvfs + 1); 2971 2972 /* save the start idx of promisc mce list */ 2973 pfvf->promisc_mce_idx = nix_alloc_mce_list(mcast, numvfs + 1); 2974 nix_mce_list_init(&pfvf->promisc_mce_list, numvfs + 1); 2975 2976 for (idx = 0; idx < (numvfs + 1); idx++) { 2977 /* idx-0 is for PF, followed by VFs */ 2978 pcifunc = (pf << RVU_PFVF_PF_SHIFT); 2979 pcifunc |= idx; 2980 /* Add dummy entries now, so that we don't have to check 2981 * for whether AQ_OP should be INIT/WRITE later on. 2982 * Will be updated when a NIXLF is attached/detached to 2983 * these PF/VFs. 2984 */ 2985 err = nix_blk_setup_mce(rvu, nix_hw, 2986 pfvf->bcast_mce_idx + idx, 2987 NIX_AQ_INSTOP_INIT, 2988 pcifunc, 0, true); 2989 if (err) 2990 return err; 2991 2992 /* add dummy entries to multicast mce list */ 2993 err = nix_blk_setup_mce(rvu, nix_hw, 2994 pfvf->mcast_mce_idx + idx, 2995 NIX_AQ_INSTOP_INIT, 2996 pcifunc, 0, true); 2997 if (err) 2998 return err; 2999 3000 /* add dummy entries to promisc mce list */ 3001 err = nix_blk_setup_mce(rvu, nix_hw, 3002 pfvf->promisc_mce_idx + idx, 3003 NIX_AQ_INSTOP_INIT, 3004 pcifunc, 0, true); 3005 if (err) 3006 return err; 3007 } 3008 } 3009 return 0; 3010 } 3011 3012 static int nix_setup_mcast(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 3013 { 3014 struct nix_mcast *mcast = &nix_hw->mcast; 3015 struct rvu_hwinfo *hw = rvu->hw; 3016 int err, size; 3017 3018 size = (rvu_read64(rvu, blkaddr, NIX_AF_CONST3) >> 16) & 0x0F; 3019 size = (1ULL << size); 3020 3021 /* Alloc memory for multicast/mirror replication entries */ 3022 err = qmem_alloc(rvu->dev, &mcast->mce_ctx, 3023 (256UL << MC_TBL_SIZE), size); 3024 if (err) 3025 return -ENOMEM; 3026 3027 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BASE, 3028 (u64)mcast->mce_ctx->iova); 3029 3030 /* Set max list length equal to max no of VFs per PF + PF itself */ 3031 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG, 3032 BIT_ULL(36) | (hw->max_vfs_per_pf << 4) | MC_TBL_SIZE); 3033 3034 /* Alloc memory for multicast replication buffers */ 3035 size = rvu_read64(rvu, blkaddr, NIX_AF_MC_MIRROR_CONST) & 0xFFFF; 3036 err = qmem_alloc(rvu->dev, &mcast->mcast_buf, 3037 (8UL << MC_BUF_CNT), size); 3038 if (err) 3039 return -ENOMEM; 3040 3041 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_BASE, 3042 (u64)mcast->mcast_buf->iova); 3043 3044 /* Alloc pkind for NIX internal RX multicast/mirror replay */ 3045 mcast->replay_pkind = rvu_alloc_rsrc(&hw->pkind.rsrc); 3046 3047 rvu_write64(rvu, blkaddr, NIX_AF_RX_MCAST_BUF_CFG, 3048 BIT_ULL(63) | (mcast->replay_pkind << 24) | 3049 BIT_ULL(20) | MC_BUF_CNT); 3050 3051 mutex_init(&mcast->mce_lock); 3052 3053 return nix_setup_mce_tables(rvu, nix_hw); 3054 } 3055 3056 static int nix_setup_txvlan(struct rvu *rvu, struct nix_hw *nix_hw) 3057 { 3058 struct nix_txvlan *vlan = &nix_hw->txvlan; 3059 int err; 3060 3061 /* Allocate resource bimap for tx vtag def registers*/ 3062 vlan->rsrc.max = NIX_TX_VTAG_DEF_MAX; 3063 err = rvu_alloc_bitmap(&vlan->rsrc); 3064 if (err) 3065 return -ENOMEM; 3066 3067 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */ 3068 vlan->entry2pfvf_map = devm_kcalloc(rvu->dev, vlan->rsrc.max, 3069 sizeof(u16), GFP_KERNEL); 3070 if (!vlan->entry2pfvf_map) 3071 goto free_mem; 3072 3073 mutex_init(&vlan->rsrc_lock); 3074 return 0; 3075 3076 free_mem: 3077 kfree(vlan->rsrc.bmap); 3078 return -ENOMEM; 3079 } 3080 3081 static int nix_setup_txschq(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr) 3082 { 3083 struct nix_txsch *txsch; 3084 int err, lvl, schq; 3085 u64 cfg, reg; 3086 3087 /* Get scheduler queue count of each type and alloc 3088 * bitmap for each for alloc/free/attach operations. 3089 */ 3090 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 3091 txsch = &nix_hw->txsch[lvl]; 3092 txsch->lvl = lvl; 3093 switch (lvl) { 3094 case NIX_TXSCH_LVL_SMQ: 3095 reg = NIX_AF_MDQ_CONST; 3096 break; 3097 case NIX_TXSCH_LVL_TL4: 3098 reg = NIX_AF_TL4_CONST; 3099 break; 3100 case NIX_TXSCH_LVL_TL3: 3101 reg = NIX_AF_TL3_CONST; 3102 break; 3103 case NIX_TXSCH_LVL_TL2: 3104 reg = NIX_AF_TL2_CONST; 3105 break; 3106 case NIX_TXSCH_LVL_TL1: 3107 reg = NIX_AF_TL1_CONST; 3108 break; 3109 } 3110 cfg = rvu_read64(rvu, blkaddr, reg); 3111 txsch->schq.max = cfg & 0xFFFF; 3112 err = rvu_alloc_bitmap(&txsch->schq); 3113 if (err) 3114 return err; 3115 3116 /* Allocate memory for scheduler queues to 3117 * PF/VF pcifunc mapping info. 3118 */ 3119 txsch->pfvf_map = devm_kcalloc(rvu->dev, txsch->schq.max, 3120 sizeof(u32), GFP_KERNEL); 3121 if (!txsch->pfvf_map) 3122 return -ENOMEM; 3123 for (schq = 0; schq < txsch->schq.max; schq++) 3124 txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE); 3125 } 3126 3127 /* Setup a default value of 8192 as DWRR MTU */ 3128 if (rvu->hw->cap.nix_common_dwrr_mtu) { 3129 rvu_write64(rvu, blkaddr, NIX_AF_DWRR_RPM_MTU, 3130 convert_bytes_to_dwrr_mtu(8192)); 3131 rvu_write64(rvu, blkaddr, NIX_AF_DWRR_SDP_MTU, 3132 convert_bytes_to_dwrr_mtu(8192)); 3133 } 3134 3135 return 0; 3136 } 3137 3138 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 3139 int blkaddr, u32 cfg) 3140 { 3141 int fmt_idx; 3142 3143 for (fmt_idx = 0; fmt_idx < nix_hw->mark_format.in_use; fmt_idx++) { 3144 if (nix_hw->mark_format.cfg[fmt_idx] == cfg) 3145 return fmt_idx; 3146 } 3147 if (fmt_idx >= nix_hw->mark_format.total) 3148 return -ERANGE; 3149 3150 rvu_write64(rvu, blkaddr, NIX_AF_MARK_FORMATX_CTL(fmt_idx), cfg); 3151 nix_hw->mark_format.cfg[fmt_idx] = cfg; 3152 nix_hw->mark_format.in_use++; 3153 return fmt_idx; 3154 } 3155 3156 static int nix_af_mark_format_setup(struct rvu *rvu, struct nix_hw *nix_hw, 3157 int blkaddr) 3158 { 3159 u64 cfgs[] = { 3160 [NIX_MARK_CFG_IP_DSCP_RED] = 0x10003, 3161 [NIX_MARK_CFG_IP_DSCP_YELLOW] = 0x11200, 3162 [NIX_MARK_CFG_IP_DSCP_YELLOW_RED] = 0x11203, 3163 [NIX_MARK_CFG_IP_ECN_RED] = 0x6000c, 3164 [NIX_MARK_CFG_IP_ECN_YELLOW] = 0x60c00, 3165 [NIX_MARK_CFG_IP_ECN_YELLOW_RED] = 0x60c0c, 3166 [NIX_MARK_CFG_VLAN_DEI_RED] = 0x30008, 3167 [NIX_MARK_CFG_VLAN_DEI_YELLOW] = 0x30800, 3168 [NIX_MARK_CFG_VLAN_DEI_YELLOW_RED] = 0x30808, 3169 }; 3170 int i, rc; 3171 u64 total; 3172 3173 total = (rvu_read64(rvu, blkaddr, NIX_AF_PSE_CONST) & 0xFF00) >> 8; 3174 nix_hw->mark_format.total = (u8)total; 3175 nix_hw->mark_format.cfg = devm_kcalloc(rvu->dev, total, sizeof(u32), 3176 GFP_KERNEL); 3177 if (!nix_hw->mark_format.cfg) 3178 return -ENOMEM; 3179 for (i = 0; i < NIX_MARK_CFG_MAX; i++) { 3180 rc = rvu_nix_reserve_mark_format(rvu, nix_hw, blkaddr, cfgs[i]); 3181 if (rc < 0) 3182 dev_err(rvu->dev, "Err %d in setup mark format %d\n", 3183 i, rc); 3184 } 3185 3186 return 0; 3187 } 3188 3189 static void rvu_get_lbk_link_max_frs(struct rvu *rvu, u16 *max_mtu) 3190 { 3191 /* CN10K supports LBK FIFO size 72 KB */ 3192 if (rvu->hw->lbk_bufsize == 0x12000) 3193 *max_mtu = CN10K_LBK_LINK_MAX_FRS; 3194 else 3195 *max_mtu = NIC_HW_MAX_FRS; 3196 } 3197 3198 static void rvu_get_lmac_link_max_frs(struct rvu *rvu, u16 *max_mtu) 3199 { 3200 int fifo_size = rvu_cgx_get_fifolen(rvu); 3201 3202 /* RPM supports FIFO len 128 KB and RPM2 supports double the 3203 * FIFO len to accommodate 8 LMACS 3204 */ 3205 if (fifo_size == 0x20000 || fifo_size == 0x40000) 3206 *max_mtu = CN10K_LMAC_LINK_MAX_FRS; 3207 else 3208 *max_mtu = NIC_HW_MAX_FRS; 3209 } 3210 3211 int rvu_mbox_handler_nix_get_hw_info(struct rvu *rvu, struct msg_req *req, 3212 struct nix_hw_info *rsp) 3213 { 3214 u16 pcifunc = req->hdr.pcifunc; 3215 u64 dwrr_mtu; 3216 int blkaddr; 3217 3218 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 3219 if (blkaddr < 0) 3220 return NIX_AF_ERR_AF_LF_INVALID; 3221 3222 if (is_afvf(pcifunc)) 3223 rvu_get_lbk_link_max_frs(rvu, &rsp->max_mtu); 3224 else 3225 rvu_get_lmac_link_max_frs(rvu, &rsp->max_mtu); 3226 3227 rsp->min_mtu = NIC_HW_MIN_FRS; 3228 3229 if (!rvu->hw->cap.nix_common_dwrr_mtu) { 3230 /* Return '1' on OTx2 */ 3231 rsp->rpm_dwrr_mtu = 1; 3232 rsp->sdp_dwrr_mtu = 1; 3233 return 0; 3234 } 3235 3236 dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_RPM_MTU); 3237 rsp->rpm_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu); 3238 3239 dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_SDP_MTU); 3240 rsp->sdp_dwrr_mtu = convert_dwrr_mtu_to_bytes(dwrr_mtu); 3241 3242 return 0; 3243 } 3244 3245 int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req, 3246 struct msg_rsp *rsp) 3247 { 3248 u16 pcifunc = req->hdr.pcifunc; 3249 int i, nixlf, blkaddr, err; 3250 u64 stats; 3251 3252 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3253 if (err) 3254 return err; 3255 3256 /* Get stats count supported by HW */ 3257 stats = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 3258 3259 /* Reset tx stats */ 3260 for (i = 0; i < ((stats >> 24) & 0xFF); i++) 3261 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_STATX(nixlf, i), 0); 3262 3263 /* Reset rx stats */ 3264 for (i = 0; i < ((stats >> 32) & 0xFF); i++) 3265 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, i), 0); 3266 3267 return 0; 3268 } 3269 3270 /* Returns the ALG index to be set into NPC_RX_ACTION */ 3271 static int get_flowkey_alg_idx(struct nix_hw *nix_hw, u32 flow_cfg) 3272 { 3273 int i; 3274 3275 /* Scan over exiting algo entries to find a match */ 3276 for (i = 0; i < nix_hw->flowkey.in_use; i++) 3277 if (nix_hw->flowkey.flowkey[i] == flow_cfg) 3278 return i; 3279 3280 return -ERANGE; 3281 } 3282 3283 static int set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg) 3284 { 3285 int idx, nr_field, key_off, field_marker, keyoff_marker; 3286 int max_key_off, max_bit_pos, group_member; 3287 struct nix_rx_flowkey_alg *field; 3288 struct nix_rx_flowkey_alg tmp; 3289 u32 key_type, valid_key; 3290 int l4_key_offset = 0; 3291 3292 if (!alg) 3293 return -EINVAL; 3294 3295 #define FIELDS_PER_ALG 5 3296 #define MAX_KEY_OFF 40 3297 /* Clear all fields */ 3298 memset(alg, 0, sizeof(uint64_t) * FIELDS_PER_ALG); 3299 3300 /* Each of the 32 possible flow key algorithm definitions should 3301 * fall into above incremental config (except ALG0). Otherwise a 3302 * single NPC MCAM entry is not sufficient for supporting RSS. 3303 * 3304 * If a different definition or combination needed then NPC MCAM 3305 * has to be programmed to filter such pkts and it's action should 3306 * point to this definition to calculate flowtag or hash. 3307 * 3308 * The `for loop` goes over _all_ protocol field and the following 3309 * variables depicts the state machine forward progress logic. 3310 * 3311 * keyoff_marker - Enabled when hash byte length needs to be accounted 3312 * in field->key_offset update. 3313 * field_marker - Enabled when a new field needs to be selected. 3314 * group_member - Enabled when protocol is part of a group. 3315 */ 3316 3317 keyoff_marker = 0; max_key_off = 0; group_member = 0; 3318 nr_field = 0; key_off = 0; field_marker = 1; 3319 field = &tmp; max_bit_pos = fls(flow_cfg); 3320 for (idx = 0; 3321 idx < max_bit_pos && nr_field < FIELDS_PER_ALG && 3322 key_off < MAX_KEY_OFF; idx++) { 3323 key_type = BIT(idx); 3324 valid_key = flow_cfg & key_type; 3325 /* Found a field marker, reset the field values */ 3326 if (field_marker) 3327 memset(&tmp, 0, sizeof(tmp)); 3328 3329 field_marker = true; 3330 keyoff_marker = true; 3331 switch (key_type) { 3332 case NIX_FLOW_KEY_TYPE_PORT: 3333 field->sel_chan = true; 3334 /* This should be set to 1, when SEL_CHAN is set */ 3335 field->bytesm1 = 1; 3336 break; 3337 case NIX_FLOW_KEY_TYPE_IPV4_PROTO: 3338 field->lid = NPC_LID_LC; 3339 field->hdr_offset = 9; /* offset */ 3340 field->bytesm1 = 0; /* 1 byte */ 3341 field->ltype_match = NPC_LT_LC_IP; 3342 field->ltype_mask = 0xF; 3343 break; 3344 case NIX_FLOW_KEY_TYPE_IPV4: 3345 case NIX_FLOW_KEY_TYPE_INNR_IPV4: 3346 field->lid = NPC_LID_LC; 3347 field->ltype_match = NPC_LT_LC_IP; 3348 if (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV4) { 3349 field->lid = NPC_LID_LG; 3350 field->ltype_match = NPC_LT_LG_TU_IP; 3351 } 3352 field->hdr_offset = 12; /* SIP offset */ 3353 field->bytesm1 = 7; /* SIP + DIP, 8 bytes */ 3354 field->ltype_mask = 0xF; /* Match only IPv4 */ 3355 keyoff_marker = false; 3356 break; 3357 case NIX_FLOW_KEY_TYPE_IPV6: 3358 case NIX_FLOW_KEY_TYPE_INNR_IPV6: 3359 field->lid = NPC_LID_LC; 3360 field->ltype_match = NPC_LT_LC_IP6; 3361 if (key_type == NIX_FLOW_KEY_TYPE_INNR_IPV6) { 3362 field->lid = NPC_LID_LG; 3363 field->ltype_match = NPC_LT_LG_TU_IP6; 3364 } 3365 field->hdr_offset = 8; /* SIP offset */ 3366 field->bytesm1 = 31; /* SIP + DIP, 32 bytes */ 3367 field->ltype_mask = 0xF; /* Match only IPv6 */ 3368 break; 3369 case NIX_FLOW_KEY_TYPE_TCP: 3370 case NIX_FLOW_KEY_TYPE_UDP: 3371 case NIX_FLOW_KEY_TYPE_SCTP: 3372 case NIX_FLOW_KEY_TYPE_INNR_TCP: 3373 case NIX_FLOW_KEY_TYPE_INNR_UDP: 3374 case NIX_FLOW_KEY_TYPE_INNR_SCTP: 3375 field->lid = NPC_LID_LD; 3376 if (key_type == NIX_FLOW_KEY_TYPE_INNR_TCP || 3377 key_type == NIX_FLOW_KEY_TYPE_INNR_UDP || 3378 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) 3379 field->lid = NPC_LID_LH; 3380 field->bytesm1 = 3; /* Sport + Dport, 4 bytes */ 3381 3382 /* Enum values for NPC_LID_LD and NPC_LID_LG are same, 3383 * so no need to change the ltype_match, just change 3384 * the lid for inner protocols 3385 */ 3386 BUILD_BUG_ON((int)NPC_LT_LD_TCP != 3387 (int)NPC_LT_LH_TU_TCP); 3388 BUILD_BUG_ON((int)NPC_LT_LD_UDP != 3389 (int)NPC_LT_LH_TU_UDP); 3390 BUILD_BUG_ON((int)NPC_LT_LD_SCTP != 3391 (int)NPC_LT_LH_TU_SCTP); 3392 3393 if ((key_type == NIX_FLOW_KEY_TYPE_TCP || 3394 key_type == NIX_FLOW_KEY_TYPE_INNR_TCP) && 3395 valid_key) { 3396 field->ltype_match |= NPC_LT_LD_TCP; 3397 group_member = true; 3398 } else if ((key_type == NIX_FLOW_KEY_TYPE_UDP || 3399 key_type == NIX_FLOW_KEY_TYPE_INNR_UDP) && 3400 valid_key) { 3401 field->ltype_match |= NPC_LT_LD_UDP; 3402 group_member = true; 3403 } else if ((key_type == NIX_FLOW_KEY_TYPE_SCTP || 3404 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) && 3405 valid_key) { 3406 field->ltype_match |= NPC_LT_LD_SCTP; 3407 group_member = true; 3408 } 3409 field->ltype_mask = ~field->ltype_match; 3410 if (key_type == NIX_FLOW_KEY_TYPE_SCTP || 3411 key_type == NIX_FLOW_KEY_TYPE_INNR_SCTP) { 3412 /* Handle the case where any of the group item 3413 * is enabled in the group but not the final one 3414 */ 3415 if (group_member) { 3416 valid_key = true; 3417 group_member = false; 3418 } 3419 } else { 3420 field_marker = false; 3421 keyoff_marker = false; 3422 } 3423 3424 /* TCP/UDP/SCTP and ESP/AH falls at same offset so 3425 * remember the TCP key offset of 40 byte hash key. 3426 */ 3427 if (key_type == NIX_FLOW_KEY_TYPE_TCP) 3428 l4_key_offset = key_off; 3429 break; 3430 case NIX_FLOW_KEY_TYPE_NVGRE: 3431 field->lid = NPC_LID_LD; 3432 field->hdr_offset = 4; /* VSID offset */ 3433 field->bytesm1 = 2; 3434 field->ltype_match = NPC_LT_LD_NVGRE; 3435 field->ltype_mask = 0xF; 3436 break; 3437 case NIX_FLOW_KEY_TYPE_VXLAN: 3438 case NIX_FLOW_KEY_TYPE_GENEVE: 3439 field->lid = NPC_LID_LE; 3440 field->bytesm1 = 2; 3441 field->hdr_offset = 4; 3442 field->ltype_mask = 0xF; 3443 field_marker = false; 3444 keyoff_marker = false; 3445 3446 if (key_type == NIX_FLOW_KEY_TYPE_VXLAN && valid_key) { 3447 field->ltype_match |= NPC_LT_LE_VXLAN; 3448 group_member = true; 3449 } 3450 3451 if (key_type == NIX_FLOW_KEY_TYPE_GENEVE && valid_key) { 3452 field->ltype_match |= NPC_LT_LE_GENEVE; 3453 group_member = true; 3454 } 3455 3456 if (key_type == NIX_FLOW_KEY_TYPE_GENEVE) { 3457 if (group_member) { 3458 field->ltype_mask = ~field->ltype_match; 3459 field_marker = true; 3460 keyoff_marker = true; 3461 valid_key = true; 3462 group_member = false; 3463 } 3464 } 3465 break; 3466 case NIX_FLOW_KEY_TYPE_ETH_DMAC: 3467 case NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC: 3468 field->lid = NPC_LID_LA; 3469 field->ltype_match = NPC_LT_LA_ETHER; 3470 if (key_type == NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC) { 3471 field->lid = NPC_LID_LF; 3472 field->ltype_match = NPC_LT_LF_TU_ETHER; 3473 } 3474 field->hdr_offset = 0; 3475 field->bytesm1 = 5; /* DMAC 6 Byte */ 3476 field->ltype_mask = 0xF; 3477 break; 3478 case NIX_FLOW_KEY_TYPE_IPV6_EXT: 3479 field->lid = NPC_LID_LC; 3480 field->hdr_offset = 40; /* IPV6 hdr */ 3481 field->bytesm1 = 0; /* 1 Byte ext hdr*/ 3482 field->ltype_match = NPC_LT_LC_IP6_EXT; 3483 field->ltype_mask = 0xF; 3484 break; 3485 case NIX_FLOW_KEY_TYPE_GTPU: 3486 field->lid = NPC_LID_LE; 3487 field->hdr_offset = 4; 3488 field->bytesm1 = 3; /* 4 bytes TID*/ 3489 field->ltype_match = NPC_LT_LE_GTPU; 3490 field->ltype_mask = 0xF; 3491 break; 3492 case NIX_FLOW_KEY_TYPE_VLAN: 3493 field->lid = NPC_LID_LB; 3494 field->hdr_offset = 2; /* Skip TPID (2-bytes) */ 3495 field->bytesm1 = 1; /* 2 Bytes (Actually 12 bits) */ 3496 field->ltype_match = NPC_LT_LB_CTAG; 3497 field->ltype_mask = 0xF; 3498 field->fn_mask = 1; /* Mask out the first nibble */ 3499 break; 3500 case NIX_FLOW_KEY_TYPE_AH: 3501 case NIX_FLOW_KEY_TYPE_ESP: 3502 field->hdr_offset = 0; 3503 field->bytesm1 = 7; /* SPI + sequence number */ 3504 field->ltype_mask = 0xF; 3505 field->lid = NPC_LID_LE; 3506 field->ltype_match = NPC_LT_LE_ESP; 3507 if (key_type == NIX_FLOW_KEY_TYPE_AH) { 3508 field->lid = NPC_LID_LD; 3509 field->ltype_match = NPC_LT_LD_AH; 3510 field->hdr_offset = 4; 3511 keyoff_marker = false; 3512 } 3513 break; 3514 } 3515 field->ena = 1; 3516 3517 /* Found a valid flow key type */ 3518 if (valid_key) { 3519 /* Use the key offset of TCP/UDP/SCTP fields 3520 * for ESP/AH fields. 3521 */ 3522 if (key_type == NIX_FLOW_KEY_TYPE_ESP || 3523 key_type == NIX_FLOW_KEY_TYPE_AH) 3524 key_off = l4_key_offset; 3525 field->key_offset = key_off; 3526 memcpy(&alg[nr_field], field, sizeof(*field)); 3527 max_key_off = max(max_key_off, field->bytesm1 + 1); 3528 3529 /* Found a field marker, get the next field */ 3530 if (field_marker) 3531 nr_field++; 3532 } 3533 3534 /* Found a keyoff marker, update the new key_off */ 3535 if (keyoff_marker) { 3536 key_off += max_key_off; 3537 max_key_off = 0; 3538 } 3539 } 3540 /* Processed all the flow key types */ 3541 if (idx == max_bit_pos && key_off <= MAX_KEY_OFF) 3542 return 0; 3543 else 3544 return NIX_AF_ERR_RSS_NOSPC_FIELD; 3545 } 3546 3547 static int reserve_flowkey_alg_idx(struct rvu *rvu, int blkaddr, u32 flow_cfg) 3548 { 3549 u64 field[FIELDS_PER_ALG]; 3550 struct nix_hw *hw; 3551 int fid, rc; 3552 3553 hw = get_nix_hw(rvu->hw, blkaddr); 3554 if (!hw) 3555 return NIX_AF_ERR_INVALID_NIXBLK; 3556 3557 /* No room to add new flow hash algoritham */ 3558 if (hw->flowkey.in_use >= NIX_FLOW_KEY_ALG_MAX) 3559 return NIX_AF_ERR_RSS_NOSPC_ALGO; 3560 3561 /* Generate algo fields for the given flow_cfg */ 3562 rc = set_flowkey_fields((struct nix_rx_flowkey_alg *)field, flow_cfg); 3563 if (rc) 3564 return rc; 3565 3566 /* Update ALGX_FIELDX register with generated fields */ 3567 for (fid = 0; fid < FIELDS_PER_ALG; fid++) 3568 rvu_write64(rvu, blkaddr, 3569 NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(hw->flowkey.in_use, 3570 fid), field[fid]); 3571 3572 /* Store the flow_cfg for futher lookup */ 3573 rc = hw->flowkey.in_use; 3574 hw->flowkey.flowkey[rc] = flow_cfg; 3575 hw->flowkey.in_use++; 3576 3577 return rc; 3578 } 3579 3580 int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu, 3581 struct nix_rss_flowkey_cfg *req, 3582 struct nix_rss_flowkey_cfg_rsp *rsp) 3583 { 3584 u16 pcifunc = req->hdr.pcifunc; 3585 int alg_idx, nixlf, blkaddr; 3586 struct nix_hw *nix_hw; 3587 int err; 3588 3589 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3590 if (err) 3591 return err; 3592 3593 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3594 if (!nix_hw) 3595 return NIX_AF_ERR_INVALID_NIXBLK; 3596 3597 alg_idx = get_flowkey_alg_idx(nix_hw, req->flowkey_cfg); 3598 /* Failed to get algo index from the exiting list, reserve new */ 3599 if (alg_idx < 0) { 3600 alg_idx = reserve_flowkey_alg_idx(rvu, blkaddr, 3601 req->flowkey_cfg); 3602 if (alg_idx < 0) 3603 return alg_idx; 3604 } 3605 rsp->alg_idx = alg_idx; 3606 rvu_npc_update_flowkey_alg_idx(rvu, pcifunc, nixlf, req->group, 3607 alg_idx, req->mcam_index); 3608 return 0; 3609 } 3610 3611 static int nix_rx_flowkey_alg_cfg(struct rvu *rvu, int blkaddr) 3612 { 3613 u32 flowkey_cfg, minkey_cfg; 3614 int alg, fid, rc; 3615 3616 /* Disable all flow key algx fieldx */ 3617 for (alg = 0; alg < NIX_FLOW_KEY_ALG_MAX; alg++) { 3618 for (fid = 0; fid < FIELDS_PER_ALG; fid++) 3619 rvu_write64(rvu, blkaddr, 3620 NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(alg, fid), 3621 0); 3622 } 3623 3624 /* IPv4/IPv6 SIP/DIPs */ 3625 flowkey_cfg = NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6; 3626 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3627 if (rc < 0) 3628 return rc; 3629 3630 /* TCPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3631 minkey_cfg = flowkey_cfg; 3632 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP; 3633 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3634 if (rc < 0) 3635 return rc; 3636 3637 /* UDPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3638 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_UDP; 3639 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3640 if (rc < 0) 3641 return rc; 3642 3643 /* SCTPv4/v6 4-tuple, SIP, DIP, Sport, Dport */ 3644 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_SCTP; 3645 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3646 if (rc < 0) 3647 return rc; 3648 3649 /* TCP/UDP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3650 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3651 NIX_FLOW_KEY_TYPE_UDP; 3652 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3653 if (rc < 0) 3654 return rc; 3655 3656 /* TCP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3657 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3658 NIX_FLOW_KEY_TYPE_SCTP; 3659 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3660 if (rc < 0) 3661 return rc; 3662 3663 /* UDP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3664 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_UDP | 3665 NIX_FLOW_KEY_TYPE_SCTP; 3666 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3667 if (rc < 0) 3668 return rc; 3669 3670 /* TCP/UDP/SCTP v4/v6 4-tuple, rest IP pkts 2-tuple */ 3671 flowkey_cfg = minkey_cfg | NIX_FLOW_KEY_TYPE_TCP | 3672 NIX_FLOW_KEY_TYPE_UDP | NIX_FLOW_KEY_TYPE_SCTP; 3673 rc = reserve_flowkey_alg_idx(rvu, blkaddr, flowkey_cfg); 3674 if (rc < 0) 3675 return rc; 3676 3677 return 0; 3678 } 3679 3680 int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu, 3681 struct nix_set_mac_addr *req, 3682 struct msg_rsp *rsp) 3683 { 3684 bool from_vf = req->hdr.pcifunc & RVU_PFVF_FUNC_MASK; 3685 u16 pcifunc = req->hdr.pcifunc; 3686 int blkaddr, nixlf, err; 3687 struct rvu_pfvf *pfvf; 3688 3689 err = nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); 3690 if (err) 3691 return err; 3692 3693 pfvf = rvu_get_pfvf(rvu, pcifunc); 3694 3695 /* untrusted VF can't overwrite admin(PF) changes */ 3696 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && 3697 (from_vf && test_bit(PF_SET_VF_MAC, &pfvf->flags))) { 3698 dev_warn(rvu->dev, 3699 "MAC address set by admin(PF) cannot be overwritten by untrusted VF"); 3700 return -EPERM; 3701 } 3702 3703 ether_addr_copy(pfvf->mac_addr, req->mac_addr); 3704 3705 rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf, 3706 pfvf->rx_chan_base, req->mac_addr); 3707 3708 if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && from_vf) 3709 ether_addr_copy(pfvf->default_mac, req->mac_addr); 3710 3711 rvu_switch_update_rules(rvu, pcifunc); 3712 3713 return 0; 3714 } 3715 3716 int rvu_mbox_handler_nix_get_mac_addr(struct rvu *rvu, 3717 struct msg_req *req, 3718 struct nix_get_mac_addr_rsp *rsp) 3719 { 3720 u16 pcifunc = req->hdr.pcifunc; 3721 struct rvu_pfvf *pfvf; 3722 3723 if (!is_nixlf_attached(rvu, pcifunc)) 3724 return NIX_AF_ERR_AF_LF_INVALID; 3725 3726 pfvf = rvu_get_pfvf(rvu, pcifunc); 3727 3728 ether_addr_copy(rsp->mac_addr, pfvf->mac_addr); 3729 3730 return 0; 3731 } 3732 3733 int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req, 3734 struct msg_rsp *rsp) 3735 { 3736 bool allmulti, promisc, nix_rx_multicast; 3737 u16 pcifunc = req->hdr.pcifunc; 3738 struct rvu_pfvf *pfvf; 3739 int nixlf, err; 3740 3741 pfvf = rvu_get_pfvf(rvu, pcifunc); 3742 promisc = req->mode & NIX_RX_MODE_PROMISC ? true : false; 3743 allmulti = req->mode & NIX_RX_MODE_ALLMULTI ? true : false; 3744 pfvf->use_mce_list = req->mode & NIX_RX_MODE_USE_MCE ? true : false; 3745 3746 nix_rx_multicast = rvu->hw->cap.nix_rx_multicast & pfvf->use_mce_list; 3747 3748 if (is_vf(pcifunc) && !nix_rx_multicast && 3749 (promisc || allmulti)) { 3750 dev_warn_ratelimited(rvu->dev, 3751 "VF promisc/multicast not supported\n"); 3752 return 0; 3753 } 3754 3755 /* untrusted VF can't configure promisc/allmulti */ 3756 if (is_vf(pcifunc) && !test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && 3757 (promisc || allmulti)) 3758 return 0; 3759 3760 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 3761 if (err) 3762 return err; 3763 3764 if (nix_rx_multicast) { 3765 /* add/del this PF_FUNC to/from mcast pkt replication list */ 3766 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_ALLMULTI_ENTRY, 3767 allmulti); 3768 if (err) { 3769 dev_err(rvu->dev, 3770 "Failed to update pcifunc 0x%x to multicast list\n", 3771 pcifunc); 3772 return err; 3773 } 3774 3775 /* add/del this PF_FUNC to/from promisc pkt replication list */ 3776 err = nix_update_mce_rule(rvu, pcifunc, NIXLF_PROMISC_ENTRY, 3777 promisc); 3778 if (err) { 3779 dev_err(rvu->dev, 3780 "Failed to update pcifunc 0x%x to promisc list\n", 3781 pcifunc); 3782 return err; 3783 } 3784 } 3785 3786 /* install/uninstall allmulti entry */ 3787 if (allmulti) { 3788 rvu_npc_install_allmulti_entry(rvu, pcifunc, nixlf, 3789 pfvf->rx_chan_base); 3790 } else { 3791 if (!nix_rx_multicast) 3792 rvu_npc_enable_allmulti_entry(rvu, pcifunc, nixlf, false); 3793 } 3794 3795 /* install/uninstall promisc entry */ 3796 if (promisc) { 3797 rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf, 3798 pfvf->rx_chan_base, 3799 pfvf->rx_chan_cnt); 3800 3801 if (rvu_npc_exact_has_match_table(rvu)) 3802 rvu_npc_exact_promisc_enable(rvu, pcifunc); 3803 } else { 3804 if (!nix_rx_multicast) 3805 rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf, false); 3806 3807 if (rvu_npc_exact_has_match_table(rvu)) 3808 rvu_npc_exact_promisc_disable(rvu, pcifunc); 3809 } 3810 3811 return 0; 3812 } 3813 3814 static void nix_find_link_frs(struct rvu *rvu, 3815 struct nix_frs_cfg *req, u16 pcifunc) 3816 { 3817 int pf = rvu_get_pf(pcifunc); 3818 struct rvu_pfvf *pfvf; 3819 int maxlen, minlen; 3820 int numvfs, hwvf; 3821 int vf; 3822 3823 /* Update with requester's min/max lengths */ 3824 pfvf = rvu_get_pfvf(rvu, pcifunc); 3825 pfvf->maxlen = req->maxlen; 3826 if (req->update_minlen) 3827 pfvf->minlen = req->minlen; 3828 3829 maxlen = req->maxlen; 3830 minlen = req->update_minlen ? req->minlen : 0; 3831 3832 /* Get this PF's numVFs and starting hwvf */ 3833 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 3834 3835 /* For each VF, compare requested max/minlen */ 3836 for (vf = 0; vf < numvfs; vf++) { 3837 pfvf = &rvu->hwvf[hwvf + vf]; 3838 if (pfvf->maxlen > maxlen) 3839 maxlen = pfvf->maxlen; 3840 if (req->update_minlen && 3841 pfvf->minlen && pfvf->minlen < minlen) 3842 minlen = pfvf->minlen; 3843 } 3844 3845 /* Compare requested max/minlen with PF's max/minlen */ 3846 pfvf = &rvu->pf[pf]; 3847 if (pfvf->maxlen > maxlen) 3848 maxlen = pfvf->maxlen; 3849 if (req->update_minlen && 3850 pfvf->minlen && pfvf->minlen < minlen) 3851 minlen = pfvf->minlen; 3852 3853 /* Update the request with max/min PF's and it's VF's max/min */ 3854 req->maxlen = maxlen; 3855 if (req->update_minlen) 3856 req->minlen = minlen; 3857 } 3858 3859 static int 3860 nix_config_link_credits(struct rvu *rvu, int blkaddr, int link, 3861 u16 pcifunc, u64 tx_credits) 3862 { 3863 struct rvu_hwinfo *hw = rvu->hw; 3864 int pf = rvu_get_pf(pcifunc); 3865 u8 cgx_id = 0, lmac_id = 0; 3866 unsigned long poll_tmo; 3867 bool restore_tx_en = 0; 3868 struct nix_hw *nix_hw; 3869 u64 cfg, sw_xoff = 0; 3870 u32 schq = 0; 3871 u32 credits; 3872 int rc; 3873 3874 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3875 if (!nix_hw) 3876 return NIX_AF_ERR_INVALID_NIXBLK; 3877 3878 if (tx_credits == nix_hw->tx_credits[link]) 3879 return 0; 3880 3881 /* Enable cgx tx if disabled for credits to be back */ 3882 if (is_pf_cgxmapped(rvu, pf)) { 3883 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 3884 restore_tx_en = !rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), 3885 lmac_id, true); 3886 } 3887 3888 mutex_lock(&rvu->rsrc_lock); 3889 /* Disable new traffic to link */ 3890 if (hw->cap.nix_shaping) { 3891 schq = nix_get_tx_link(rvu, pcifunc); 3892 sw_xoff = rvu_read64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq)); 3893 rvu_write64(rvu, blkaddr, 3894 NIX_AF_TL1X_SW_XOFF(schq), BIT_ULL(0)); 3895 } 3896 3897 rc = NIX_AF_ERR_LINK_CREDITS; 3898 poll_tmo = jiffies + usecs_to_jiffies(200000); 3899 /* Wait for credits to return */ 3900 do { 3901 if (time_after(jiffies, poll_tmo)) 3902 goto exit; 3903 usleep_range(100, 200); 3904 3905 cfg = rvu_read64(rvu, blkaddr, 3906 NIX_AF_TX_LINKX_NORM_CREDIT(link)); 3907 credits = (cfg >> 12) & 0xFFFFFULL; 3908 } while (credits != nix_hw->tx_credits[link]); 3909 3910 cfg &= ~(0xFFFFFULL << 12); 3911 cfg |= (tx_credits << 12); 3912 rvu_write64(rvu, blkaddr, NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg); 3913 rc = 0; 3914 3915 nix_hw->tx_credits[link] = tx_credits; 3916 3917 exit: 3918 /* Enable traffic back */ 3919 if (hw->cap.nix_shaping && !sw_xoff) 3920 rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SW_XOFF(schq), 0); 3921 3922 /* Restore state of cgx tx */ 3923 if (restore_tx_en) 3924 rvu_cgx_config_tx(rvu_cgx_pdata(cgx_id, rvu), lmac_id, false); 3925 3926 mutex_unlock(&rvu->rsrc_lock); 3927 return rc; 3928 } 3929 3930 int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req, 3931 struct msg_rsp *rsp) 3932 { 3933 struct rvu_hwinfo *hw = rvu->hw; 3934 u16 pcifunc = req->hdr.pcifunc; 3935 int pf = rvu_get_pf(pcifunc); 3936 int blkaddr, schq, link = -1; 3937 struct nix_txsch *txsch; 3938 u64 cfg, lmac_fifo_len; 3939 struct nix_hw *nix_hw; 3940 struct rvu_pfvf *pfvf; 3941 u8 cgx = 0, lmac = 0; 3942 u16 max_mtu; 3943 3944 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 3945 if (blkaddr < 0) 3946 return NIX_AF_ERR_AF_LF_INVALID; 3947 3948 nix_hw = get_nix_hw(rvu->hw, blkaddr); 3949 if (!nix_hw) 3950 return NIX_AF_ERR_INVALID_NIXBLK; 3951 3952 if (is_afvf(pcifunc)) 3953 rvu_get_lbk_link_max_frs(rvu, &max_mtu); 3954 else 3955 rvu_get_lmac_link_max_frs(rvu, &max_mtu); 3956 3957 if (!req->sdp_link && req->maxlen > max_mtu) 3958 return NIX_AF_ERR_FRS_INVALID; 3959 3960 if (req->update_minlen && req->minlen < NIC_HW_MIN_FRS) 3961 return NIX_AF_ERR_FRS_INVALID; 3962 3963 /* Check if requester wants to update SMQ's */ 3964 if (!req->update_smq) 3965 goto rx_frscfg; 3966 3967 /* Update min/maxlen in each of the SMQ attached to this PF/VF */ 3968 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 3969 mutex_lock(&rvu->rsrc_lock); 3970 for (schq = 0; schq < txsch->schq.max; schq++) { 3971 if (TXSCH_MAP_FUNC(txsch->pfvf_map[schq]) != pcifunc) 3972 continue; 3973 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq)); 3974 cfg = (cfg & ~(0xFFFFULL << 8)) | ((u64)req->maxlen << 8); 3975 if (req->update_minlen) 3976 cfg = (cfg & ~0x7FULL) | ((u64)req->minlen & 0x7F); 3977 rvu_write64(rvu, blkaddr, NIX_AF_SMQX_CFG(schq), cfg); 3978 } 3979 mutex_unlock(&rvu->rsrc_lock); 3980 3981 rx_frscfg: 3982 /* Check if config is for SDP link */ 3983 if (req->sdp_link) { 3984 if (!hw->sdp_links) 3985 return NIX_AF_ERR_RX_LINK_INVALID; 3986 link = hw->cgx_links + hw->lbk_links; 3987 goto linkcfg; 3988 } 3989 3990 /* Check if the request is from CGX mapped RVU PF */ 3991 if (is_pf_cgxmapped(rvu, pf)) { 3992 /* Get CGX and LMAC to which this PF is mapped and find link */ 3993 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac); 3994 link = (cgx * hw->lmac_per_cgx) + lmac; 3995 } else if (pf == 0) { 3996 /* For VFs of PF0 ingress is LBK port, so config LBK link */ 3997 pfvf = rvu_get_pfvf(rvu, pcifunc); 3998 link = hw->cgx_links + pfvf->lbkid; 3999 } 4000 4001 if (link < 0) 4002 return NIX_AF_ERR_RX_LINK_INVALID; 4003 4004 nix_find_link_frs(rvu, req, pcifunc); 4005 4006 linkcfg: 4007 cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link)); 4008 cfg = (cfg & ~(0xFFFFULL << 16)) | ((u64)req->maxlen << 16); 4009 if (req->update_minlen) 4010 cfg = (cfg & ~0xFFFFULL) | req->minlen; 4011 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), cfg); 4012 4013 if (req->sdp_link || pf == 0) 4014 return 0; 4015 4016 /* Update transmit credits for CGX links */ 4017 lmac_fifo_len = rvu_cgx_get_lmac_fifolen(rvu, cgx, lmac); 4018 if (!lmac_fifo_len) { 4019 dev_err(rvu->dev, 4020 "%s: Failed to get CGX/RPM%d:LMAC%d FIFO size\n", 4021 __func__, cgx, lmac); 4022 return 0; 4023 } 4024 return nix_config_link_credits(rvu, blkaddr, link, pcifunc, 4025 (lmac_fifo_len - req->maxlen) / 16); 4026 } 4027 4028 int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req, 4029 struct msg_rsp *rsp) 4030 { 4031 int nixlf, blkaddr, err; 4032 u64 cfg; 4033 4034 err = nix_get_nixlf(rvu, req->hdr.pcifunc, &nixlf, &blkaddr); 4035 if (err) 4036 return err; 4037 4038 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf)); 4039 /* Set the interface configuration */ 4040 if (req->len_verify & BIT(0)) 4041 cfg |= BIT_ULL(41); 4042 else 4043 cfg &= ~BIT_ULL(41); 4044 4045 if (req->len_verify & BIT(1)) 4046 cfg |= BIT_ULL(40); 4047 else 4048 cfg &= ~BIT_ULL(40); 4049 4050 if (req->csum_verify & BIT(0)) 4051 cfg |= BIT_ULL(37); 4052 else 4053 cfg &= ~BIT_ULL(37); 4054 4055 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf), cfg); 4056 4057 return 0; 4058 } 4059 4060 static u64 rvu_get_lbk_link_credits(struct rvu *rvu, u16 lbk_max_frs) 4061 { 4062 /* CN10k supports 72KB FIFO size and max packet size of 64k */ 4063 if (rvu->hw->lbk_bufsize == 0x12000) 4064 return (rvu->hw->lbk_bufsize - lbk_max_frs) / 16; 4065 4066 return 1600; /* 16 * max LBK datarate = 16 * 100Gbps */ 4067 } 4068 4069 static void nix_link_config(struct rvu *rvu, int blkaddr, 4070 struct nix_hw *nix_hw) 4071 { 4072 struct rvu_hwinfo *hw = rvu->hw; 4073 int cgx, lmac_cnt, slink, link; 4074 u16 lbk_max_frs, lmac_max_frs; 4075 unsigned long lmac_bmap; 4076 u64 tx_credits, cfg; 4077 u64 lmac_fifo_len; 4078 int iter; 4079 4080 rvu_get_lbk_link_max_frs(rvu, &lbk_max_frs); 4081 rvu_get_lmac_link_max_frs(rvu, &lmac_max_frs); 4082 4083 /* Set default min/max packet lengths allowed on NIX Rx links. 4084 * 4085 * With HW reset minlen value of 60byte, HW will treat ARP pkts 4086 * as undersize and report them to SW as error pkts, hence 4087 * setting it to 40 bytes. 4088 */ 4089 for (link = 0; link < hw->cgx_links; link++) { 4090 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4091 ((u64)lmac_max_frs << 16) | NIC_HW_MIN_FRS); 4092 } 4093 4094 for (link = hw->cgx_links; link < hw->lbk_links; link++) { 4095 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4096 ((u64)lbk_max_frs << 16) | NIC_HW_MIN_FRS); 4097 } 4098 if (hw->sdp_links) { 4099 link = hw->cgx_links + hw->lbk_links; 4100 rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), 4101 SDP_HW_MAX_FRS << 16 | NIC_HW_MIN_FRS); 4102 } 4103 4104 /* Set credits for Tx links assuming max packet length allowed. 4105 * This will be reconfigured based on MTU set for PF/VF. 4106 */ 4107 for (cgx = 0; cgx < hw->cgx; cgx++) { 4108 lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); 4109 /* Skip when cgx is not available or lmac cnt is zero */ 4110 if (lmac_cnt <= 0) 4111 continue; 4112 slink = cgx * hw->lmac_per_cgx; 4113 4114 /* Get LMAC id's from bitmap */ 4115 lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu)); 4116 for_each_set_bit(iter, &lmac_bmap, rvu->hw->lmac_per_cgx) { 4117 lmac_fifo_len = rvu_cgx_get_lmac_fifolen(rvu, cgx, iter); 4118 if (!lmac_fifo_len) { 4119 dev_err(rvu->dev, 4120 "%s: Failed to get CGX/RPM%d:LMAC%d FIFO size\n", 4121 __func__, cgx, iter); 4122 continue; 4123 } 4124 tx_credits = (lmac_fifo_len - lmac_max_frs) / 16; 4125 /* Enable credits and set credit pkt count to max allowed */ 4126 cfg = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1); 4127 4128 link = iter + slink; 4129 nix_hw->tx_credits[link] = tx_credits; 4130 rvu_write64(rvu, blkaddr, 4131 NIX_AF_TX_LINKX_NORM_CREDIT(link), cfg); 4132 } 4133 } 4134 4135 /* Set Tx credits for LBK link */ 4136 slink = hw->cgx_links; 4137 for (link = slink; link < (slink + hw->lbk_links); link++) { 4138 tx_credits = rvu_get_lbk_link_credits(rvu, lbk_max_frs); 4139 nix_hw->tx_credits[link] = tx_credits; 4140 /* Enable credits and set credit pkt count to max allowed */ 4141 tx_credits = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1); 4142 rvu_write64(rvu, blkaddr, 4143 NIX_AF_TX_LINKX_NORM_CREDIT(link), tx_credits); 4144 } 4145 } 4146 4147 static int nix_calibrate_x2p(struct rvu *rvu, int blkaddr) 4148 { 4149 int idx, err; 4150 u64 status; 4151 4152 /* Start X2P bus calibration */ 4153 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4154 rvu_read64(rvu, blkaddr, NIX_AF_CFG) | BIT_ULL(9)); 4155 /* Wait for calibration to complete */ 4156 err = rvu_poll_reg(rvu, blkaddr, 4157 NIX_AF_STATUS, BIT_ULL(10), false); 4158 if (err) { 4159 dev_err(rvu->dev, "NIX X2P bus calibration failed\n"); 4160 return err; 4161 } 4162 4163 status = rvu_read64(rvu, blkaddr, NIX_AF_STATUS); 4164 /* Check if CGX devices are ready */ 4165 for (idx = 0; idx < rvu->cgx_cnt_max; idx++) { 4166 /* Skip when cgx port is not available */ 4167 if (!rvu_cgx_pdata(idx, rvu) || 4168 (status & (BIT_ULL(16 + idx)))) 4169 continue; 4170 dev_err(rvu->dev, 4171 "CGX%d didn't respond to NIX X2P calibration\n", idx); 4172 err = -EBUSY; 4173 } 4174 4175 /* Check if LBK is ready */ 4176 if (!(status & BIT_ULL(19))) { 4177 dev_err(rvu->dev, 4178 "LBK didn't respond to NIX X2P calibration\n"); 4179 err = -EBUSY; 4180 } 4181 4182 /* Clear 'calibrate_x2p' bit */ 4183 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4184 rvu_read64(rvu, blkaddr, NIX_AF_CFG) & ~BIT_ULL(9)); 4185 if (err || (status & 0x3FFULL)) 4186 dev_err(rvu->dev, 4187 "NIX X2P calibration failed, status 0x%llx\n", status); 4188 if (err) 4189 return err; 4190 return 0; 4191 } 4192 4193 static int nix_aq_init(struct rvu *rvu, struct rvu_block *block) 4194 { 4195 u64 cfg; 4196 int err; 4197 4198 /* Set admin queue endianness */ 4199 cfg = rvu_read64(rvu, block->addr, NIX_AF_CFG); 4200 #ifdef __BIG_ENDIAN 4201 cfg |= BIT_ULL(8); 4202 rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg); 4203 #else 4204 cfg &= ~BIT_ULL(8); 4205 rvu_write64(rvu, block->addr, NIX_AF_CFG, cfg); 4206 #endif 4207 4208 /* Do not bypass NDC cache */ 4209 cfg = rvu_read64(rvu, block->addr, NIX_AF_NDC_CFG); 4210 cfg &= ~0x3FFEULL; 4211 #ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING 4212 /* Disable caching of SQB aka SQEs */ 4213 cfg |= 0x04ULL; 4214 #endif 4215 rvu_write64(rvu, block->addr, NIX_AF_NDC_CFG, cfg); 4216 4217 /* Result structure can be followed by RQ/SQ/CQ context at 4218 * RES + 128bytes and a write mask at RES + 256 bytes, depending on 4219 * operation type. Alloc sufficient result memory for all operations. 4220 */ 4221 err = rvu_aq_alloc(rvu, &block->aq, 4222 Q_COUNT(AQ_SIZE), sizeof(struct nix_aq_inst_s), 4223 ALIGN(sizeof(struct nix_aq_res_s), 128) + 256); 4224 if (err) 4225 return err; 4226 4227 rvu_write64(rvu, block->addr, NIX_AF_AQ_CFG, AQ_SIZE); 4228 rvu_write64(rvu, block->addr, 4229 NIX_AF_AQ_BASE, (u64)block->aq->inst->iova); 4230 return 0; 4231 } 4232 4233 static void rvu_nix_setup_capabilities(struct rvu *rvu, int blkaddr) 4234 { 4235 struct rvu_hwinfo *hw = rvu->hw; 4236 u64 hw_const; 4237 4238 hw_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); 4239 4240 /* On OcteonTx2 DWRR quantum is directly configured into each of 4241 * the transmit scheduler queues. And PF/VF drivers were free to 4242 * config any value upto 2^24. 4243 * On CN10K, HW is modified, the quantum configuration at scheduler 4244 * queues is in terms of weight. And SW needs to setup a base DWRR MTU 4245 * at NIX_AF_DWRR_RPM_MTU / NIX_AF_DWRR_SDP_MTU. HW will do 4246 * 'DWRR MTU * weight' to get the quantum. 4247 * 4248 * Check if HW uses a common MTU for all DWRR quantum configs. 4249 * On OcteonTx2 this register field is '0'. 4250 */ 4251 if (((hw_const >> 56) & 0x10) == 0x10) 4252 hw->cap.nix_common_dwrr_mtu = true; 4253 } 4254 4255 static int rvu_nix_block_init(struct rvu *rvu, struct nix_hw *nix_hw) 4256 { 4257 const struct npc_lt_def_cfg *ltdefs; 4258 struct rvu_hwinfo *hw = rvu->hw; 4259 int blkaddr = nix_hw->blkaddr; 4260 struct rvu_block *block; 4261 int err; 4262 u64 cfg; 4263 4264 block = &hw->block[blkaddr]; 4265 4266 if (is_rvu_96xx_B0(rvu)) { 4267 /* As per a HW errata in 96xx A0/B0 silicon, NIX may corrupt 4268 * internal state when conditional clocks are turned off. 4269 * Hence enable them. 4270 */ 4271 rvu_write64(rvu, blkaddr, NIX_AF_CFG, 4272 rvu_read64(rvu, blkaddr, NIX_AF_CFG) | 0x40ULL); 4273 4274 /* Set chan/link to backpressure TL3 instead of TL2 */ 4275 rvu_write64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL, 0x01); 4276 4277 /* Disable SQ manager's sticky mode operation (set TM6 = 0) 4278 * This sticky mode is known to cause SQ stalls when multiple 4279 * SQs are mapped to same SMQ and transmitting pkts at a time. 4280 */ 4281 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS); 4282 cfg &= ~BIT_ULL(15); 4283 rvu_write64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS, cfg); 4284 } 4285 4286 ltdefs = rvu->kpu.lt_def; 4287 /* Calibrate X2P bus to check if CGX/LBK links are fine */ 4288 err = nix_calibrate_x2p(rvu, blkaddr); 4289 if (err) 4290 return err; 4291 4292 /* Setup capabilities of the NIX block */ 4293 rvu_nix_setup_capabilities(rvu, blkaddr); 4294 4295 /* Initialize admin queue */ 4296 err = nix_aq_init(rvu, block); 4297 if (err) 4298 return err; 4299 4300 /* Restore CINT timer delay to HW reset values */ 4301 rvu_write64(rvu, blkaddr, NIX_AF_CINT_DELAY, 0x0ULL); 4302 4303 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SEB_CFG); 4304 4305 /* For better performance use NDC TX instead of NDC RX for SQ's SQEs" */ 4306 cfg |= 1ULL; 4307 if (!is_rvu_otx2(rvu)) 4308 cfg |= NIX_PTP_1STEP_EN; 4309 4310 rvu_write64(rvu, blkaddr, NIX_AF_SEB_CFG, cfg); 4311 4312 if (is_block_implemented(hw, blkaddr)) { 4313 err = nix_setup_txschq(rvu, nix_hw, blkaddr); 4314 if (err) 4315 return err; 4316 4317 err = nix_setup_ipolicers(rvu, nix_hw, blkaddr); 4318 if (err) 4319 return err; 4320 4321 err = nix_af_mark_format_setup(rvu, nix_hw, blkaddr); 4322 if (err) 4323 return err; 4324 4325 err = nix_setup_mcast(rvu, nix_hw, blkaddr); 4326 if (err) 4327 return err; 4328 4329 err = nix_setup_txvlan(rvu, nix_hw); 4330 if (err) 4331 return err; 4332 4333 /* Configure segmentation offload formats */ 4334 nix_setup_lso(rvu, nix_hw, blkaddr); 4335 4336 /* Config Outer/Inner L2, IP, TCP, UDP and SCTP NPC layer info. 4337 * This helps HW protocol checker to identify headers 4338 * and validate length and checksums. 4339 */ 4340 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OL2, 4341 (ltdefs->rx_ol2.lid << 8) | (ltdefs->rx_ol2.ltype_match << 4) | 4342 ltdefs->rx_ol2.ltype_mask); 4343 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4, 4344 (ltdefs->rx_oip4.lid << 8) | (ltdefs->rx_oip4.ltype_match << 4) | 4345 ltdefs->rx_oip4.ltype_mask); 4346 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4, 4347 (ltdefs->rx_iip4.lid << 8) | (ltdefs->rx_iip4.ltype_match << 4) | 4348 ltdefs->rx_iip4.ltype_mask); 4349 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6, 4350 (ltdefs->rx_oip6.lid << 8) | (ltdefs->rx_oip6.ltype_match << 4) | 4351 ltdefs->rx_oip6.ltype_mask); 4352 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6, 4353 (ltdefs->rx_iip6.lid << 8) | (ltdefs->rx_iip6.ltype_match << 4) | 4354 ltdefs->rx_iip6.ltype_mask); 4355 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OTCP, 4356 (ltdefs->rx_otcp.lid << 8) | (ltdefs->rx_otcp.ltype_match << 4) | 4357 ltdefs->rx_otcp.ltype_mask); 4358 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ITCP, 4359 (ltdefs->rx_itcp.lid << 8) | (ltdefs->rx_itcp.ltype_match << 4) | 4360 ltdefs->rx_itcp.ltype_mask); 4361 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OUDP, 4362 (ltdefs->rx_oudp.lid << 8) | (ltdefs->rx_oudp.ltype_match << 4) | 4363 ltdefs->rx_oudp.ltype_mask); 4364 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IUDP, 4365 (ltdefs->rx_iudp.lid << 8) | (ltdefs->rx_iudp.ltype_match << 4) | 4366 ltdefs->rx_iudp.ltype_mask); 4367 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OSCTP, 4368 (ltdefs->rx_osctp.lid << 8) | (ltdefs->rx_osctp.ltype_match << 4) | 4369 ltdefs->rx_osctp.ltype_mask); 4370 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ISCTP, 4371 (ltdefs->rx_isctp.lid << 8) | (ltdefs->rx_isctp.ltype_match << 4) | 4372 ltdefs->rx_isctp.ltype_mask); 4373 4374 if (!is_rvu_otx2(rvu)) { 4375 /* Enable APAD calculation for other protocols 4376 * matching APAD0 and APAD1 lt def registers. 4377 */ 4378 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_CST_APAD0, 4379 (ltdefs->rx_apad0.valid << 11) | 4380 (ltdefs->rx_apad0.lid << 8) | 4381 (ltdefs->rx_apad0.ltype_match << 4) | 4382 ltdefs->rx_apad0.ltype_mask); 4383 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_CST_APAD1, 4384 (ltdefs->rx_apad1.valid << 11) | 4385 (ltdefs->rx_apad1.lid << 8) | 4386 (ltdefs->rx_apad1.ltype_match << 4) | 4387 ltdefs->rx_apad1.ltype_mask); 4388 4389 /* Receive ethertype defination register defines layer 4390 * information in NPC_RESULT_S to identify the Ethertype 4391 * location in L2 header. Used for Ethertype overwriting 4392 * in inline IPsec flow. 4393 */ 4394 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ET(0), 4395 (ltdefs->rx_et[0].offset << 12) | 4396 (ltdefs->rx_et[0].valid << 11) | 4397 (ltdefs->rx_et[0].lid << 8) | 4398 (ltdefs->rx_et[0].ltype_match << 4) | 4399 ltdefs->rx_et[0].ltype_mask); 4400 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_ET(1), 4401 (ltdefs->rx_et[1].offset << 12) | 4402 (ltdefs->rx_et[1].valid << 11) | 4403 (ltdefs->rx_et[1].lid << 8) | 4404 (ltdefs->rx_et[1].ltype_match << 4) | 4405 ltdefs->rx_et[1].ltype_mask); 4406 } 4407 4408 err = nix_rx_flowkey_alg_cfg(rvu, blkaddr); 4409 if (err) 4410 return err; 4411 4412 nix_hw->tx_credits = kcalloc(hw->cgx_links + hw->lbk_links, 4413 sizeof(u64), GFP_KERNEL); 4414 if (!nix_hw->tx_credits) 4415 return -ENOMEM; 4416 4417 /* Initialize CGX/LBK/SDP link credits, min/max pkt lengths */ 4418 nix_link_config(rvu, blkaddr, nix_hw); 4419 4420 /* Enable Channel backpressure */ 4421 rvu_write64(rvu, blkaddr, NIX_AF_RX_CFG, BIT_ULL(0)); 4422 } 4423 return 0; 4424 } 4425 4426 int rvu_nix_init(struct rvu *rvu) 4427 { 4428 struct rvu_hwinfo *hw = rvu->hw; 4429 struct nix_hw *nix_hw; 4430 int blkaddr = 0, err; 4431 int i = 0; 4432 4433 hw->nix = devm_kcalloc(rvu->dev, MAX_NIX_BLKS, sizeof(struct nix_hw), 4434 GFP_KERNEL); 4435 if (!hw->nix) 4436 return -ENOMEM; 4437 4438 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4439 while (blkaddr) { 4440 nix_hw = &hw->nix[i]; 4441 nix_hw->rvu = rvu; 4442 nix_hw->blkaddr = blkaddr; 4443 err = rvu_nix_block_init(rvu, nix_hw); 4444 if (err) 4445 return err; 4446 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4447 i++; 4448 } 4449 4450 return 0; 4451 } 4452 4453 static void rvu_nix_block_freemem(struct rvu *rvu, int blkaddr, 4454 struct rvu_block *block) 4455 { 4456 struct nix_txsch *txsch; 4457 struct nix_mcast *mcast; 4458 struct nix_txvlan *vlan; 4459 struct nix_hw *nix_hw; 4460 int lvl; 4461 4462 rvu_aq_free(rvu, block->aq); 4463 4464 if (is_block_implemented(rvu->hw, blkaddr)) { 4465 nix_hw = get_nix_hw(rvu->hw, blkaddr); 4466 if (!nix_hw) 4467 return; 4468 4469 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 4470 txsch = &nix_hw->txsch[lvl]; 4471 kfree(txsch->schq.bmap); 4472 } 4473 4474 kfree(nix_hw->tx_credits); 4475 4476 nix_ipolicer_freemem(rvu, nix_hw); 4477 4478 vlan = &nix_hw->txvlan; 4479 kfree(vlan->rsrc.bmap); 4480 mutex_destroy(&vlan->rsrc_lock); 4481 4482 mcast = &nix_hw->mcast; 4483 qmem_free(rvu->dev, mcast->mce_ctx); 4484 qmem_free(rvu->dev, mcast->mcast_buf); 4485 mutex_destroy(&mcast->mce_lock); 4486 } 4487 } 4488 4489 void rvu_nix_freemem(struct rvu *rvu) 4490 { 4491 struct rvu_hwinfo *hw = rvu->hw; 4492 struct rvu_block *block; 4493 int blkaddr = 0; 4494 4495 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4496 while (blkaddr) { 4497 block = &hw->block[blkaddr]; 4498 rvu_nix_block_freemem(rvu, blkaddr, block); 4499 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 4500 } 4501 } 4502 4503 int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req, 4504 struct msg_rsp *rsp) 4505 { 4506 u16 pcifunc = req->hdr.pcifunc; 4507 struct rvu_pfvf *pfvf; 4508 int nixlf, err; 4509 4510 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 4511 if (err) 4512 return err; 4513 4514 rvu_npc_enable_default_entries(rvu, pcifunc, nixlf); 4515 4516 npc_mcam_enable_flows(rvu, pcifunc); 4517 4518 pfvf = rvu_get_pfvf(rvu, pcifunc); 4519 set_bit(NIXLF_INITIALIZED, &pfvf->flags); 4520 4521 rvu_switch_update_rules(rvu, pcifunc); 4522 4523 return rvu_cgx_start_stop_io(rvu, pcifunc, true); 4524 } 4525 4526 int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req, 4527 struct msg_rsp *rsp) 4528 { 4529 u16 pcifunc = req->hdr.pcifunc; 4530 struct rvu_pfvf *pfvf; 4531 int nixlf, err; 4532 4533 err = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); 4534 if (err) 4535 return err; 4536 4537 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 4538 4539 pfvf = rvu_get_pfvf(rvu, pcifunc); 4540 clear_bit(NIXLF_INITIALIZED, &pfvf->flags); 4541 4542 return rvu_cgx_start_stop_io(rvu, pcifunc, false); 4543 } 4544 4545 #define RX_SA_BASE GENMASK_ULL(52, 7) 4546 4547 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int nixlf) 4548 { 4549 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 4550 struct hwctx_disable_req ctx_req; 4551 int pf = rvu_get_pf(pcifunc); 4552 struct mac_ops *mac_ops; 4553 u8 cgx_id, lmac_id; 4554 u64 sa_base; 4555 void *cgxd; 4556 int err; 4557 4558 ctx_req.hdr.pcifunc = pcifunc; 4559 4560 /* Cleanup NPC MCAM entries, free Tx scheduler queues being used */ 4561 rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); 4562 rvu_npc_free_mcam_entries(rvu, pcifunc, nixlf); 4563 nix_interface_deinit(rvu, pcifunc, nixlf); 4564 nix_rx_sync(rvu, blkaddr); 4565 nix_txschq_free(rvu, pcifunc); 4566 4567 clear_bit(NIXLF_INITIALIZED, &pfvf->flags); 4568 4569 rvu_cgx_start_stop_io(rvu, pcifunc, false); 4570 4571 if (pfvf->sq_ctx) { 4572 ctx_req.ctype = NIX_AQ_CTYPE_SQ; 4573 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4574 if (err) 4575 dev_err(rvu->dev, "SQ ctx disable failed\n"); 4576 } 4577 4578 if (pfvf->rq_ctx) { 4579 ctx_req.ctype = NIX_AQ_CTYPE_RQ; 4580 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4581 if (err) 4582 dev_err(rvu->dev, "RQ ctx disable failed\n"); 4583 } 4584 4585 if (pfvf->cq_ctx) { 4586 ctx_req.ctype = NIX_AQ_CTYPE_CQ; 4587 err = nix_lf_hwctx_disable(rvu, &ctx_req); 4588 if (err) 4589 dev_err(rvu->dev, "CQ ctx disable failed\n"); 4590 } 4591 4592 /* reset HW config done for Switch headers */ 4593 rvu_npc_set_parse_mode(rvu, pcifunc, OTX2_PRIV_FLAGS_DEFAULT, 4594 (PKIND_TX | PKIND_RX), 0, 0, 0, 0); 4595 4596 /* Disabling CGX and NPC config done for PTP */ 4597 if (pfvf->hw_rx_tstamp_en) { 4598 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 4599 cgxd = rvu_cgx_pdata(cgx_id, rvu); 4600 mac_ops = get_mac_ops(cgxd); 4601 mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, false); 4602 /* Undo NPC config done for PTP */ 4603 if (npc_config_ts_kpuaction(rvu, pf, pcifunc, false)) 4604 dev_err(rvu->dev, "NPC config for PTP failed\n"); 4605 pfvf->hw_rx_tstamp_en = false; 4606 } 4607 4608 /* reset priority flow control config */ 4609 rvu_cgx_prio_flow_ctrl_cfg(rvu, pcifunc, 0, 0, 0); 4610 4611 /* reset 802.3x flow control config */ 4612 rvu_cgx_cfg_pause_frm(rvu, pcifunc, 0, 0); 4613 4614 nix_ctx_free(rvu, pfvf); 4615 4616 nix_free_all_bandprof(rvu, pcifunc); 4617 4618 sa_base = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(nixlf)); 4619 if (FIELD_GET(RX_SA_BASE, sa_base)) { 4620 err = rvu_cpt_ctx_flush(rvu, pcifunc); 4621 if (err) 4622 dev_err(rvu->dev, 4623 "CPT ctx flush failed with error: %d\n", err); 4624 } 4625 } 4626 4627 #define NIX_AF_LFX_TX_CFG_PTP_EN BIT_ULL(32) 4628 4629 static int rvu_nix_lf_ptp_tx_cfg(struct rvu *rvu, u16 pcifunc, bool enable) 4630 { 4631 struct rvu_hwinfo *hw = rvu->hw; 4632 struct rvu_block *block; 4633 int blkaddr, pf; 4634 int nixlf; 4635 u64 cfg; 4636 4637 pf = rvu_get_pf(pcifunc); 4638 if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP)) 4639 return 0; 4640 4641 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 4642 if (blkaddr < 0) 4643 return NIX_AF_ERR_AF_LF_INVALID; 4644 4645 block = &hw->block[blkaddr]; 4646 nixlf = rvu_get_lf(rvu, block, pcifunc, 0); 4647 if (nixlf < 0) 4648 return NIX_AF_ERR_AF_LF_INVALID; 4649 4650 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf)); 4651 4652 if (enable) 4653 cfg |= NIX_AF_LFX_TX_CFG_PTP_EN; 4654 else 4655 cfg &= ~NIX_AF_LFX_TX_CFG_PTP_EN; 4656 4657 rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf), cfg); 4658 4659 return 0; 4660 } 4661 4662 int rvu_mbox_handler_nix_lf_ptp_tx_enable(struct rvu *rvu, struct msg_req *req, 4663 struct msg_rsp *rsp) 4664 { 4665 return rvu_nix_lf_ptp_tx_cfg(rvu, req->hdr.pcifunc, true); 4666 } 4667 4668 int rvu_mbox_handler_nix_lf_ptp_tx_disable(struct rvu *rvu, struct msg_req *req, 4669 struct msg_rsp *rsp) 4670 { 4671 return rvu_nix_lf_ptp_tx_cfg(rvu, req->hdr.pcifunc, false); 4672 } 4673 4674 int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu, 4675 struct nix_lso_format_cfg *req, 4676 struct nix_lso_format_cfg_rsp *rsp) 4677 { 4678 u16 pcifunc = req->hdr.pcifunc; 4679 struct nix_hw *nix_hw; 4680 struct rvu_pfvf *pfvf; 4681 int blkaddr, idx, f; 4682 u64 reg; 4683 4684 pfvf = rvu_get_pfvf(rvu, pcifunc); 4685 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 4686 if (!pfvf->nixlf || blkaddr < 0) 4687 return NIX_AF_ERR_AF_LF_INVALID; 4688 4689 nix_hw = get_nix_hw(rvu->hw, blkaddr); 4690 if (!nix_hw) 4691 return NIX_AF_ERR_INVALID_NIXBLK; 4692 4693 /* Find existing matching LSO format, if any */ 4694 for (idx = 0; idx < nix_hw->lso.in_use; idx++) { 4695 for (f = 0; f < NIX_LSO_FIELD_MAX; f++) { 4696 reg = rvu_read64(rvu, blkaddr, 4697 NIX_AF_LSO_FORMATX_FIELDX(idx, f)); 4698 if (req->fields[f] != (reg & req->field_mask)) 4699 break; 4700 } 4701 4702 if (f == NIX_LSO_FIELD_MAX) 4703 break; 4704 } 4705 4706 if (idx < nix_hw->lso.in_use) { 4707 /* Match found */ 4708 rsp->lso_format_idx = idx; 4709 return 0; 4710 } 4711 4712 if (nix_hw->lso.in_use == nix_hw->lso.total) 4713 return NIX_AF_ERR_LSO_CFG_FAIL; 4714 4715 rsp->lso_format_idx = nix_hw->lso.in_use++; 4716 4717 for (f = 0; f < NIX_LSO_FIELD_MAX; f++) 4718 rvu_write64(rvu, blkaddr, 4719 NIX_AF_LSO_FORMATX_FIELDX(rsp->lso_format_idx, f), 4720 req->fields[f]); 4721 4722 return 0; 4723 } 4724 4725 #define IPSEC_GEN_CFG_EGRP GENMASK_ULL(50, 48) 4726 #define IPSEC_GEN_CFG_OPCODE GENMASK_ULL(47, 32) 4727 #define IPSEC_GEN_CFG_PARAM1 GENMASK_ULL(31, 16) 4728 #define IPSEC_GEN_CFG_PARAM2 GENMASK_ULL(15, 0) 4729 4730 #define CPT_INST_QSEL_BLOCK GENMASK_ULL(28, 24) 4731 #define CPT_INST_QSEL_PF_FUNC GENMASK_ULL(23, 8) 4732 #define CPT_INST_QSEL_SLOT GENMASK_ULL(7, 0) 4733 4734 static void nix_inline_ipsec_cfg(struct rvu *rvu, struct nix_inline_ipsec_cfg *req, 4735 int blkaddr) 4736 { 4737 u8 cpt_idx, cpt_blkaddr; 4738 u64 val; 4739 4740 cpt_idx = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 4741 if (req->enable) { 4742 val = 0; 4743 /* Enable context prefetching */ 4744 if (!is_rvu_otx2(rvu)) 4745 val |= BIT_ULL(51); 4746 4747 /* Set OPCODE and EGRP */ 4748 val |= FIELD_PREP(IPSEC_GEN_CFG_EGRP, req->gen_cfg.egrp); 4749 val |= FIELD_PREP(IPSEC_GEN_CFG_OPCODE, req->gen_cfg.opcode); 4750 val |= FIELD_PREP(IPSEC_GEN_CFG_PARAM1, req->gen_cfg.param1); 4751 val |= FIELD_PREP(IPSEC_GEN_CFG_PARAM2, req->gen_cfg.param2); 4752 4753 rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, val); 4754 4755 /* Set CPT queue for inline IPSec */ 4756 val = FIELD_PREP(CPT_INST_QSEL_SLOT, req->inst_qsel.cpt_slot); 4757 val |= FIELD_PREP(CPT_INST_QSEL_PF_FUNC, 4758 req->inst_qsel.cpt_pf_func); 4759 4760 if (!is_rvu_otx2(rvu)) { 4761 cpt_blkaddr = (cpt_idx == 0) ? BLKADDR_CPT0 : 4762 BLKADDR_CPT1; 4763 val |= FIELD_PREP(CPT_INST_QSEL_BLOCK, cpt_blkaddr); 4764 } 4765 4766 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx), 4767 val); 4768 4769 /* Set CPT credit */ 4770 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), 4771 req->cpt_credit); 4772 } else { 4773 rvu_write64(rvu, blkaddr, NIX_AF_RX_IPSEC_GEN_CFG, 0x0); 4774 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_INST_QSEL(cpt_idx), 4775 0x0); 4776 rvu_write64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx), 4777 0x3FFFFF); 4778 } 4779 } 4780 4781 int rvu_mbox_handler_nix_inline_ipsec_cfg(struct rvu *rvu, 4782 struct nix_inline_ipsec_cfg *req, 4783 struct msg_rsp *rsp) 4784 { 4785 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) 4786 return 0; 4787 4788 nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX0); 4789 if (is_block_implemented(rvu->hw, BLKADDR_CPT1)) 4790 nix_inline_ipsec_cfg(rvu, req, BLKADDR_NIX1); 4791 4792 return 0; 4793 } 4794 4795 int rvu_mbox_handler_nix_inline_ipsec_lf_cfg(struct rvu *rvu, 4796 struct nix_inline_ipsec_lf_cfg *req, 4797 struct msg_rsp *rsp) 4798 { 4799 int lf, blkaddr, err; 4800 u64 val; 4801 4802 if (!is_block_implemented(rvu->hw, BLKADDR_CPT0)) 4803 return 0; 4804 4805 err = nix_get_nixlf(rvu, req->hdr.pcifunc, &lf, &blkaddr); 4806 if (err) 4807 return err; 4808 4809 if (req->enable) { 4810 /* Set TT, TAG_CONST, SA_POW2_SIZE and LENM1_MAX */ 4811 val = (u64)req->ipsec_cfg0.tt << 44 | 4812 (u64)req->ipsec_cfg0.tag_const << 20 | 4813 (u64)req->ipsec_cfg0.sa_pow2_size << 16 | 4814 req->ipsec_cfg0.lenm1_max; 4815 4816 if (blkaddr == BLKADDR_NIX1) 4817 val |= BIT_ULL(46); 4818 4819 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG0(lf), val); 4820 4821 /* Set SA_IDX_W and SA_IDX_MAX */ 4822 val = (u64)req->ipsec_cfg1.sa_idx_w << 32 | 4823 req->ipsec_cfg1.sa_idx_max; 4824 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(lf), val); 4825 4826 /* Set SA base address */ 4827 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(lf), 4828 req->sa_base_addr); 4829 } else { 4830 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG0(lf), 0x0); 4831 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_CFG1(lf), 0x0); 4832 rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(lf), 4833 0x0); 4834 } 4835 4836 return 0; 4837 } 4838 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc) 4839 { 4840 bool from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK); 4841 4842 /* overwrite vf mac address with default_mac */ 4843 if (from_vf) 4844 ether_addr_copy(pfvf->mac_addr, pfvf->default_mac); 4845 } 4846 4847 /* NIX ingress policers or bandwidth profiles APIs */ 4848 static void nix_config_rx_pkt_policer_precolor(struct rvu *rvu, int blkaddr) 4849 { 4850 struct npc_lt_def_cfg defs, *ltdefs; 4851 4852 ltdefs = &defs; 4853 memcpy(ltdefs, rvu->kpu.lt_def, sizeof(struct npc_lt_def_cfg)); 4854 4855 /* Extract PCP and DEI fields from outer VLAN from byte offset 4856 * 2 from the start of LB_PTR (ie TAG). 4857 * VLAN0 is Outer VLAN and VLAN1 is Inner VLAN. Inner VLAN 4858 * fields are considered when 'Tunnel enable' is set in profile. 4859 */ 4860 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN0_PCP_DEI, 4861 (2UL << 12) | (ltdefs->ovlan.lid << 8) | 4862 (ltdefs->ovlan.ltype_match << 4) | 4863 ltdefs->ovlan.ltype_mask); 4864 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_VLAN1_PCP_DEI, 4865 (2UL << 12) | (ltdefs->ivlan.lid << 8) | 4866 (ltdefs->ivlan.ltype_match << 4) | 4867 ltdefs->ivlan.ltype_mask); 4868 4869 /* DSCP field in outer and tunneled IPv4 packets */ 4870 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4_DSCP, 4871 (1UL << 12) | (ltdefs->rx_oip4.lid << 8) | 4872 (ltdefs->rx_oip4.ltype_match << 4) | 4873 ltdefs->rx_oip4.ltype_mask); 4874 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP4_DSCP, 4875 (1UL << 12) | (ltdefs->rx_iip4.lid << 8) | 4876 (ltdefs->rx_iip4.ltype_match << 4) | 4877 ltdefs->rx_iip4.ltype_mask); 4878 4879 /* DSCP field (traffic class) in outer and tunneled IPv6 packets */ 4880 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP6_DSCP, 4881 (1UL << 11) | (ltdefs->rx_oip6.lid << 8) | 4882 (ltdefs->rx_oip6.ltype_match << 4) | 4883 ltdefs->rx_oip6.ltype_mask); 4884 rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_IIP6_DSCP, 4885 (1UL << 11) | (ltdefs->rx_iip6.lid << 8) | 4886 (ltdefs->rx_iip6.ltype_match << 4) | 4887 ltdefs->rx_iip6.ltype_mask); 4888 } 4889 4890 static int nix_init_policer_context(struct rvu *rvu, struct nix_hw *nix_hw, 4891 int layer, int prof_idx) 4892 { 4893 struct nix_cn10k_aq_enq_req aq_req; 4894 int rc; 4895 4896 memset(&aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 4897 4898 aq_req.qidx = (prof_idx & 0x3FFF) | (layer << 14); 4899 aq_req.ctype = NIX_AQ_CTYPE_BANDPROF; 4900 aq_req.op = NIX_AQ_INSTOP_INIT; 4901 4902 /* Context is all zeros, submit to AQ */ 4903 rc = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 4904 (struct nix_aq_enq_req *)&aq_req, NULL); 4905 if (rc) 4906 dev_err(rvu->dev, "Failed to INIT bandwidth profile layer %d profile %d\n", 4907 layer, prof_idx); 4908 return rc; 4909 } 4910 4911 static int nix_setup_ipolicers(struct rvu *rvu, 4912 struct nix_hw *nix_hw, int blkaddr) 4913 { 4914 struct rvu_hwinfo *hw = rvu->hw; 4915 struct nix_ipolicer *ipolicer; 4916 int err, layer, prof_idx; 4917 u64 cfg; 4918 4919 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST); 4920 if (!(cfg & BIT_ULL(61))) { 4921 hw->cap.ipolicer = false; 4922 return 0; 4923 } 4924 4925 hw->cap.ipolicer = true; 4926 nix_hw->ipolicer = devm_kcalloc(rvu->dev, BAND_PROF_NUM_LAYERS, 4927 sizeof(*ipolicer), GFP_KERNEL); 4928 if (!nix_hw->ipolicer) 4929 return -ENOMEM; 4930 4931 cfg = rvu_read64(rvu, blkaddr, NIX_AF_PL_CONST); 4932 4933 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 4934 ipolicer = &nix_hw->ipolicer[layer]; 4935 switch (layer) { 4936 case BAND_PROF_LEAF_LAYER: 4937 ipolicer->band_prof.max = cfg & 0XFFFF; 4938 break; 4939 case BAND_PROF_MID_LAYER: 4940 ipolicer->band_prof.max = (cfg >> 16) & 0XFFFF; 4941 break; 4942 case BAND_PROF_TOP_LAYER: 4943 ipolicer->band_prof.max = (cfg >> 32) & 0XFFFF; 4944 break; 4945 } 4946 4947 if (!ipolicer->band_prof.max) 4948 continue; 4949 4950 err = rvu_alloc_bitmap(&ipolicer->band_prof); 4951 if (err) 4952 return err; 4953 4954 ipolicer->pfvf_map = devm_kcalloc(rvu->dev, 4955 ipolicer->band_prof.max, 4956 sizeof(u16), GFP_KERNEL); 4957 if (!ipolicer->pfvf_map) 4958 return -ENOMEM; 4959 4960 ipolicer->match_id = devm_kcalloc(rvu->dev, 4961 ipolicer->band_prof.max, 4962 sizeof(u16), GFP_KERNEL); 4963 if (!ipolicer->match_id) 4964 return -ENOMEM; 4965 4966 for (prof_idx = 0; 4967 prof_idx < ipolicer->band_prof.max; prof_idx++) { 4968 /* Set AF as current owner for INIT ops to succeed */ 4969 ipolicer->pfvf_map[prof_idx] = 0x00; 4970 4971 /* There is no enable bit in the profile context, 4972 * so no context disable. So let's INIT them here 4973 * so that PF/VF later on have to just do WRITE to 4974 * setup policer rates and config. 4975 */ 4976 err = nix_init_policer_context(rvu, nix_hw, 4977 layer, prof_idx); 4978 if (err) 4979 return err; 4980 } 4981 4982 /* Allocate memory for maintaining ref_counts for MID level 4983 * profiles, this will be needed for leaf layer profiles' 4984 * aggregation. 4985 */ 4986 if (layer != BAND_PROF_MID_LAYER) 4987 continue; 4988 4989 ipolicer->ref_count = devm_kcalloc(rvu->dev, 4990 ipolicer->band_prof.max, 4991 sizeof(u16), GFP_KERNEL); 4992 if (!ipolicer->ref_count) 4993 return -ENOMEM; 4994 } 4995 4996 /* Set policer timeunit to 2us ie (19 + 1) * 100 nsec = 2us */ 4997 rvu_write64(rvu, blkaddr, NIX_AF_PL_TS, 19); 4998 4999 nix_config_rx_pkt_policer_precolor(rvu, blkaddr); 5000 5001 return 0; 5002 } 5003 5004 static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw) 5005 { 5006 struct nix_ipolicer *ipolicer; 5007 int layer; 5008 5009 if (!rvu->hw->cap.ipolicer) 5010 return; 5011 5012 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5013 ipolicer = &nix_hw->ipolicer[layer]; 5014 5015 if (!ipolicer->band_prof.max) 5016 continue; 5017 5018 kfree(ipolicer->band_prof.bmap); 5019 } 5020 } 5021 5022 static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req, 5023 struct nix_hw *nix_hw, u16 pcifunc) 5024 { 5025 struct nix_ipolicer *ipolicer; 5026 int layer, hi_layer, prof_idx; 5027 5028 /* Bits [15:14] in profile index represent layer */ 5029 layer = (req->qidx >> 14) & 0x03; 5030 prof_idx = req->qidx & 0x3FFF; 5031 5032 ipolicer = &nix_hw->ipolicer[layer]; 5033 if (prof_idx >= ipolicer->band_prof.max) 5034 return -EINVAL; 5035 5036 /* Check if the profile is allocated to the requesting PCIFUNC or not 5037 * with the exception of AF. AF is allowed to read and update contexts. 5038 */ 5039 if (pcifunc && ipolicer->pfvf_map[prof_idx] != pcifunc) 5040 return -EINVAL; 5041 5042 /* If this profile is linked to higher layer profile then check 5043 * if that profile is also allocated to the requesting PCIFUNC 5044 * or not. 5045 */ 5046 if (!req->prof.hl_en) 5047 return 0; 5048 5049 /* Leaf layer profile can link only to mid layer and 5050 * mid layer to top layer. 5051 */ 5052 if (layer == BAND_PROF_LEAF_LAYER) 5053 hi_layer = BAND_PROF_MID_LAYER; 5054 else if (layer == BAND_PROF_MID_LAYER) 5055 hi_layer = BAND_PROF_TOP_LAYER; 5056 else 5057 return -EINVAL; 5058 5059 ipolicer = &nix_hw->ipolicer[hi_layer]; 5060 prof_idx = req->prof.band_prof_id; 5061 if (prof_idx >= ipolicer->band_prof.max || 5062 ipolicer->pfvf_map[prof_idx] != pcifunc) 5063 return -EINVAL; 5064 5065 return 0; 5066 } 5067 5068 int rvu_mbox_handler_nix_bandprof_alloc(struct rvu *rvu, 5069 struct nix_bandprof_alloc_req *req, 5070 struct nix_bandprof_alloc_rsp *rsp) 5071 { 5072 int blkaddr, layer, prof, idx, err; 5073 u16 pcifunc = req->hdr.pcifunc; 5074 struct nix_ipolicer *ipolicer; 5075 struct nix_hw *nix_hw; 5076 5077 if (!rvu->hw->cap.ipolicer) 5078 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5079 5080 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5081 if (err) 5082 return err; 5083 5084 mutex_lock(&rvu->rsrc_lock); 5085 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5086 if (layer == BAND_PROF_INVAL_LAYER) 5087 continue; 5088 if (!req->prof_count[layer]) 5089 continue; 5090 5091 ipolicer = &nix_hw->ipolicer[layer]; 5092 for (idx = 0; idx < req->prof_count[layer]; idx++) { 5093 /* Allocate a max of 'MAX_BANDPROF_PER_PFFUNC' profiles */ 5094 if (idx == MAX_BANDPROF_PER_PFFUNC) 5095 break; 5096 5097 prof = rvu_alloc_rsrc(&ipolicer->band_prof); 5098 if (prof < 0) 5099 break; 5100 rsp->prof_count[layer]++; 5101 rsp->prof_idx[layer][idx] = prof; 5102 ipolicer->pfvf_map[prof] = pcifunc; 5103 } 5104 } 5105 mutex_unlock(&rvu->rsrc_lock); 5106 return 0; 5107 } 5108 5109 static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc) 5110 { 5111 int blkaddr, layer, prof_idx, err; 5112 struct nix_ipolicer *ipolicer; 5113 struct nix_hw *nix_hw; 5114 5115 if (!rvu->hw->cap.ipolicer) 5116 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5117 5118 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5119 if (err) 5120 return err; 5121 5122 mutex_lock(&rvu->rsrc_lock); 5123 /* Free all the profiles allocated to the PCIFUNC */ 5124 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5125 if (layer == BAND_PROF_INVAL_LAYER) 5126 continue; 5127 ipolicer = &nix_hw->ipolicer[layer]; 5128 5129 for (prof_idx = 0; prof_idx < ipolicer->band_prof.max; prof_idx++) { 5130 if (ipolicer->pfvf_map[prof_idx] != pcifunc) 5131 continue; 5132 5133 /* Clear ratelimit aggregation, if any */ 5134 if (layer == BAND_PROF_LEAF_LAYER && 5135 ipolicer->match_id[prof_idx]) 5136 nix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx); 5137 5138 ipolicer->pfvf_map[prof_idx] = 0x00; 5139 ipolicer->match_id[prof_idx] = 0; 5140 rvu_free_rsrc(&ipolicer->band_prof, prof_idx); 5141 } 5142 } 5143 mutex_unlock(&rvu->rsrc_lock); 5144 return 0; 5145 } 5146 5147 int rvu_mbox_handler_nix_bandprof_free(struct rvu *rvu, 5148 struct nix_bandprof_free_req *req, 5149 struct msg_rsp *rsp) 5150 { 5151 int blkaddr, layer, prof_idx, idx, err; 5152 u16 pcifunc = req->hdr.pcifunc; 5153 struct nix_ipolicer *ipolicer; 5154 struct nix_hw *nix_hw; 5155 5156 if (req->free_all) 5157 return nix_free_all_bandprof(rvu, pcifunc); 5158 5159 if (!rvu->hw->cap.ipolicer) 5160 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5161 5162 err = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5163 if (err) 5164 return err; 5165 5166 mutex_lock(&rvu->rsrc_lock); 5167 /* Free the requested profile indices */ 5168 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5169 if (layer == BAND_PROF_INVAL_LAYER) 5170 continue; 5171 if (!req->prof_count[layer]) 5172 continue; 5173 5174 ipolicer = &nix_hw->ipolicer[layer]; 5175 for (idx = 0; idx < req->prof_count[layer]; idx++) { 5176 prof_idx = req->prof_idx[layer][idx]; 5177 if (prof_idx >= ipolicer->band_prof.max || 5178 ipolicer->pfvf_map[prof_idx] != pcifunc) 5179 continue; 5180 5181 /* Clear ratelimit aggregation, if any */ 5182 if (layer == BAND_PROF_LEAF_LAYER && 5183 ipolicer->match_id[prof_idx]) 5184 nix_clear_ratelimit_aggr(rvu, nix_hw, prof_idx); 5185 5186 ipolicer->pfvf_map[prof_idx] = 0x00; 5187 ipolicer->match_id[prof_idx] = 0; 5188 rvu_free_rsrc(&ipolicer->band_prof, prof_idx); 5189 if (idx == MAX_BANDPROF_PER_PFFUNC) 5190 break; 5191 } 5192 } 5193 mutex_unlock(&rvu->rsrc_lock); 5194 return 0; 5195 } 5196 5197 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 5198 struct nix_cn10k_aq_enq_req *aq_req, 5199 struct nix_cn10k_aq_enq_rsp *aq_rsp, 5200 u16 pcifunc, u8 ctype, u32 qidx) 5201 { 5202 memset(aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5203 aq_req->hdr.pcifunc = pcifunc; 5204 aq_req->ctype = ctype; 5205 aq_req->op = NIX_AQ_INSTOP_READ; 5206 aq_req->qidx = qidx; 5207 5208 return rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5209 (struct nix_aq_enq_req *)aq_req, 5210 (struct nix_aq_enq_rsp *)aq_rsp); 5211 } 5212 5213 static int nix_ipolicer_map_leaf_midprofs(struct rvu *rvu, 5214 struct nix_hw *nix_hw, 5215 struct nix_cn10k_aq_enq_req *aq_req, 5216 struct nix_cn10k_aq_enq_rsp *aq_rsp, 5217 u32 leaf_prof, u16 mid_prof) 5218 { 5219 memset(aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5220 aq_req->hdr.pcifunc = 0x00; 5221 aq_req->ctype = NIX_AQ_CTYPE_BANDPROF; 5222 aq_req->op = NIX_AQ_INSTOP_WRITE; 5223 aq_req->qidx = leaf_prof; 5224 5225 aq_req->prof.band_prof_id = mid_prof; 5226 aq_req->prof_mask.band_prof_id = GENMASK(6, 0); 5227 aq_req->prof.hl_en = 1; 5228 aq_req->prof_mask.hl_en = 1; 5229 5230 return rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5231 (struct nix_aq_enq_req *)aq_req, 5232 (struct nix_aq_enq_rsp *)aq_rsp); 5233 } 5234 5235 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 5236 u16 rq_idx, u16 match_id) 5237 { 5238 int leaf_prof, mid_prof, leaf_match; 5239 struct nix_cn10k_aq_enq_req aq_req; 5240 struct nix_cn10k_aq_enq_rsp aq_rsp; 5241 struct nix_ipolicer *ipolicer; 5242 struct nix_hw *nix_hw; 5243 int blkaddr, idx, rc; 5244 5245 if (!rvu->hw->cap.ipolicer) 5246 return 0; 5247 5248 rc = nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); 5249 if (rc) 5250 return rc; 5251 5252 /* Fetch the RQ's context to see if policing is enabled */ 5253 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, pcifunc, 5254 NIX_AQ_CTYPE_RQ, rq_idx); 5255 if (rc) { 5256 dev_err(rvu->dev, 5257 "%s: Failed to fetch RQ%d context of PFFUNC 0x%x\n", 5258 __func__, rq_idx, pcifunc); 5259 return rc; 5260 } 5261 5262 if (!aq_rsp.rq.policer_ena) 5263 return 0; 5264 5265 /* Get the bandwidth profile ID mapped to this RQ */ 5266 leaf_prof = aq_rsp.rq.band_prof_id; 5267 5268 ipolicer = &nix_hw->ipolicer[BAND_PROF_LEAF_LAYER]; 5269 ipolicer->match_id[leaf_prof] = match_id; 5270 5271 /* Check if any other leaf profile is marked with same match_id */ 5272 for (idx = 0; idx < ipolicer->band_prof.max; idx++) { 5273 if (idx == leaf_prof) 5274 continue; 5275 if (ipolicer->match_id[idx] != match_id) 5276 continue; 5277 5278 leaf_match = idx; 5279 break; 5280 } 5281 5282 if (idx == ipolicer->band_prof.max) 5283 return 0; 5284 5285 /* Fetch the matching profile's context to check if it's already 5286 * mapped to a mid level profile. 5287 */ 5288 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5289 NIX_AQ_CTYPE_BANDPROF, leaf_match); 5290 if (rc) { 5291 dev_err(rvu->dev, 5292 "%s: Failed to fetch context of leaf profile %d\n", 5293 __func__, leaf_match); 5294 return rc; 5295 } 5296 5297 ipolicer = &nix_hw->ipolicer[BAND_PROF_MID_LAYER]; 5298 if (aq_rsp.prof.hl_en) { 5299 /* Get Mid layer prof index and map leaf_prof index 5300 * also such that flows that are being steered 5301 * to different RQs and marked with same match_id 5302 * are rate limited in a aggregate fashion 5303 */ 5304 mid_prof = aq_rsp.prof.band_prof_id; 5305 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5306 &aq_req, &aq_rsp, 5307 leaf_prof, mid_prof); 5308 if (rc) { 5309 dev_err(rvu->dev, 5310 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5311 __func__, leaf_prof, mid_prof); 5312 goto exit; 5313 } 5314 5315 mutex_lock(&rvu->rsrc_lock); 5316 ipolicer->ref_count[mid_prof]++; 5317 mutex_unlock(&rvu->rsrc_lock); 5318 goto exit; 5319 } 5320 5321 /* Allocate a mid layer profile and 5322 * map both 'leaf_prof' and 'leaf_match' profiles to it. 5323 */ 5324 mutex_lock(&rvu->rsrc_lock); 5325 mid_prof = rvu_alloc_rsrc(&ipolicer->band_prof); 5326 if (mid_prof < 0) { 5327 dev_err(rvu->dev, 5328 "%s: Unable to allocate mid layer profile\n", __func__); 5329 mutex_unlock(&rvu->rsrc_lock); 5330 goto exit; 5331 } 5332 mutex_unlock(&rvu->rsrc_lock); 5333 ipolicer->pfvf_map[mid_prof] = 0x00; 5334 ipolicer->ref_count[mid_prof] = 0; 5335 5336 /* Initialize mid layer profile same as 'leaf_prof' */ 5337 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5338 NIX_AQ_CTYPE_BANDPROF, leaf_prof); 5339 if (rc) { 5340 dev_err(rvu->dev, 5341 "%s: Failed to fetch context of leaf profile %d\n", 5342 __func__, leaf_prof); 5343 goto exit; 5344 } 5345 5346 memset(&aq_req, 0, sizeof(struct nix_cn10k_aq_enq_req)); 5347 aq_req.hdr.pcifunc = 0x00; 5348 aq_req.qidx = (mid_prof & 0x3FFF) | (BAND_PROF_MID_LAYER << 14); 5349 aq_req.ctype = NIX_AQ_CTYPE_BANDPROF; 5350 aq_req.op = NIX_AQ_INSTOP_WRITE; 5351 memcpy(&aq_req.prof, &aq_rsp.prof, sizeof(struct nix_bandprof_s)); 5352 memset((char *)&aq_req.prof_mask, 0xff, sizeof(struct nix_bandprof_s)); 5353 /* Clear higher layer enable bit in the mid profile, just in case */ 5354 aq_req.prof.hl_en = 0; 5355 aq_req.prof_mask.hl_en = 1; 5356 5357 rc = rvu_nix_blk_aq_enq_inst(rvu, nix_hw, 5358 (struct nix_aq_enq_req *)&aq_req, NULL); 5359 if (rc) { 5360 dev_err(rvu->dev, 5361 "%s: Failed to INIT context of mid layer profile %d\n", 5362 __func__, mid_prof); 5363 goto exit; 5364 } 5365 5366 /* Map both leaf profiles to this mid layer profile */ 5367 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5368 &aq_req, &aq_rsp, 5369 leaf_prof, mid_prof); 5370 if (rc) { 5371 dev_err(rvu->dev, 5372 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5373 __func__, leaf_prof, mid_prof); 5374 goto exit; 5375 } 5376 5377 mutex_lock(&rvu->rsrc_lock); 5378 ipolicer->ref_count[mid_prof]++; 5379 mutex_unlock(&rvu->rsrc_lock); 5380 5381 rc = nix_ipolicer_map_leaf_midprofs(rvu, nix_hw, 5382 &aq_req, &aq_rsp, 5383 leaf_match, mid_prof); 5384 if (rc) { 5385 dev_err(rvu->dev, 5386 "%s: Failed to map leaf(%d) and mid(%d) profiles\n", 5387 __func__, leaf_match, mid_prof); 5388 ipolicer->ref_count[mid_prof]--; 5389 goto exit; 5390 } 5391 5392 mutex_lock(&rvu->rsrc_lock); 5393 ipolicer->ref_count[mid_prof]++; 5394 mutex_unlock(&rvu->rsrc_lock); 5395 5396 exit: 5397 return rc; 5398 } 5399 5400 /* Called with mutex rsrc_lock */ 5401 static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_hw, 5402 u32 leaf_prof) 5403 { 5404 struct nix_cn10k_aq_enq_req aq_req; 5405 struct nix_cn10k_aq_enq_rsp aq_rsp; 5406 struct nix_ipolicer *ipolicer; 5407 u16 mid_prof; 5408 int rc; 5409 5410 mutex_unlock(&rvu->rsrc_lock); 5411 5412 rc = nix_aq_context_read(rvu, nix_hw, &aq_req, &aq_rsp, 0x00, 5413 NIX_AQ_CTYPE_BANDPROF, leaf_prof); 5414 5415 mutex_lock(&rvu->rsrc_lock); 5416 if (rc) { 5417 dev_err(rvu->dev, 5418 "%s: Failed to fetch context of leaf profile %d\n", 5419 __func__, leaf_prof); 5420 return; 5421 } 5422 5423 if (!aq_rsp.prof.hl_en) 5424 return; 5425 5426 mid_prof = aq_rsp.prof.band_prof_id; 5427 ipolicer = &nix_hw->ipolicer[BAND_PROF_MID_LAYER]; 5428 ipolicer->ref_count[mid_prof]--; 5429 /* If ref_count is zero, free mid layer profile */ 5430 if (!ipolicer->ref_count[mid_prof]) { 5431 ipolicer->pfvf_map[mid_prof] = 0x00; 5432 rvu_free_rsrc(&ipolicer->band_prof, mid_prof); 5433 } 5434 } 5435 5436 int rvu_mbox_handler_nix_bandprof_get_hwinfo(struct rvu *rvu, struct msg_req *req, 5437 struct nix_bandprof_get_hwinfo_rsp *rsp) 5438 { 5439 struct nix_ipolicer *ipolicer; 5440 int blkaddr, layer, err; 5441 struct nix_hw *nix_hw; 5442 u64 tu; 5443 5444 if (!rvu->hw->cap.ipolicer) 5445 return NIX_AF_ERR_IPOLICER_NOTSUPP; 5446 5447 err = nix_get_struct_ptrs(rvu, req->hdr.pcifunc, &nix_hw, &blkaddr); 5448 if (err) 5449 return err; 5450 5451 /* Return number of bandwidth profiles free at each layer */ 5452 mutex_lock(&rvu->rsrc_lock); 5453 for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { 5454 if (layer == BAND_PROF_INVAL_LAYER) 5455 continue; 5456 5457 ipolicer = &nix_hw->ipolicer[layer]; 5458 rsp->prof_count[layer] = rvu_rsrc_free_count(&ipolicer->band_prof); 5459 } 5460 mutex_unlock(&rvu->rsrc_lock); 5461 5462 /* Set the policer timeunit in nanosec */ 5463 tu = rvu_read64(rvu, blkaddr, NIX_AF_PL_TS) & GENMASK_ULL(9, 0); 5464 rsp->policer_timeunit = (tu + 1) * 100; 5465 5466 return 0; 5467 } 5468