1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2020 Marvell. */ 3 4 #include <linux/pci.h> 5 #include "rvu_struct.h" 6 #include "rvu_reg.h" 7 #include "mbox.h" 8 #include "rvu.h" 9 10 /* CPT PF device id */ 11 #define PCI_DEVID_OTX2_CPT_PF 0xA0FD 12 13 static int get_cpt_pf_num(struct rvu *rvu) 14 { 15 int i, domain_nr, cpt_pf_num = -1; 16 struct pci_dev *pdev; 17 18 domain_nr = pci_domain_nr(rvu->pdev->bus); 19 for (i = 0; i < rvu->hw->total_pfs; i++) { 20 pdev = pci_get_domain_bus_and_slot(domain_nr, i + 1, 0); 21 if (!pdev) 22 continue; 23 24 if (pdev->device == PCI_DEVID_OTX2_CPT_PF) { 25 cpt_pf_num = i; 26 put_device(&pdev->dev); 27 break; 28 } 29 put_device(&pdev->dev); 30 } 31 return cpt_pf_num; 32 } 33 34 static bool is_cpt_pf(struct rvu *rvu, u16 pcifunc) 35 { 36 int cpt_pf_num = get_cpt_pf_num(rvu); 37 38 if (rvu_get_pf(pcifunc) != cpt_pf_num) 39 return false; 40 if (pcifunc & RVU_PFVF_FUNC_MASK) 41 return false; 42 43 return true; 44 } 45 46 static bool is_cpt_vf(struct rvu *rvu, u16 pcifunc) 47 { 48 int cpt_pf_num = get_cpt_pf_num(rvu); 49 50 if (rvu_get_pf(pcifunc) != cpt_pf_num) 51 return false; 52 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 53 return false; 54 55 return true; 56 } 57 58 int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu, 59 struct cpt_lf_alloc_req_msg *req, 60 struct msg_rsp *rsp) 61 { 62 u16 pcifunc = req->hdr.pcifunc; 63 struct rvu_block *block; 64 int cptlf, blkaddr; 65 int num_lfs, slot; 66 u64 val; 67 68 if (req->eng_grpmsk == 0x0) 69 return CPT_AF_ERR_GRP_INVALID; 70 71 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, 0); 72 if (blkaddr < 0) 73 return blkaddr; 74 75 block = &rvu->hw->block[blkaddr]; 76 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 77 block->addr); 78 if (!num_lfs) 79 return CPT_AF_ERR_LF_INVALID; 80 81 /* Check if requested 'CPTLF <=> NIXLF' mapping is valid */ 82 if (req->nix_pf_func) { 83 /* If default, use 'this' CPTLF's PFFUNC */ 84 if (req->nix_pf_func == RVU_DEFAULT_PF_FUNC) 85 req->nix_pf_func = pcifunc; 86 if (!is_pffunc_map_valid(rvu, req->nix_pf_func, BLKTYPE_NIX)) 87 return CPT_AF_ERR_NIX_PF_FUNC_INVALID; 88 } 89 90 /* Check if requested 'CPTLF <=> SSOLF' mapping is valid */ 91 if (req->sso_pf_func) { 92 /* If default, use 'this' CPTLF's PFFUNC */ 93 if (req->sso_pf_func == RVU_DEFAULT_PF_FUNC) 94 req->sso_pf_func = pcifunc; 95 if (!is_pffunc_map_valid(rvu, req->sso_pf_func, BLKTYPE_SSO)) 96 return CPT_AF_ERR_SSO_PF_FUNC_INVALID; 97 } 98 99 for (slot = 0; slot < num_lfs; slot++) { 100 cptlf = rvu_get_lf(rvu, block, pcifunc, slot); 101 if (cptlf < 0) 102 return CPT_AF_ERR_LF_INVALID; 103 104 /* Set CPT LF group and priority */ 105 val = (u64)req->eng_grpmsk << 48 | 1; 106 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); 107 108 /* Set CPT LF NIX_PF_FUNC and SSO_PF_FUNC */ 109 val = (u64)req->nix_pf_func << 48 | 110 (u64)req->sso_pf_func << 32; 111 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val); 112 } 113 114 return 0; 115 } 116 117 int rvu_mbox_handler_cpt_lf_free(struct rvu *rvu, struct msg_req *req, 118 struct msg_rsp *rsp) 119 { 120 u16 pcifunc = req->hdr.pcifunc; 121 struct rvu_block *block; 122 int cptlf, blkaddr; 123 int num_lfs, slot; 124 125 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, 0); 126 if (blkaddr < 0) 127 return blkaddr; 128 129 block = &rvu->hw->block[blkaddr]; 130 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 131 block->addr); 132 if (!num_lfs) 133 return CPT_AF_ERR_LF_INVALID; 134 135 for (slot = 0; slot < num_lfs; slot++) { 136 cptlf = rvu_get_lf(rvu, block, pcifunc, slot); 137 if (cptlf < 0) 138 return CPT_AF_ERR_LF_INVALID; 139 140 /* Reset CPT LF group and priority */ 141 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), 0x0); 142 /* Reset CPT LF NIX_PF_FUNC and SSO_PF_FUNC */ 143 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), 0x0); 144 } 145 146 return 0; 147 } 148 149 static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req) 150 { 151 u64 offset = req->reg_offset; 152 int blkaddr, num_lfs, lf; 153 struct rvu_block *block; 154 struct rvu_pfvf *pfvf; 155 156 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, 0); 157 158 /* Registers that can be accessed from PF/VF */ 159 if ((offset & 0xFF000) == CPT_AF_LFX_CTL(0) || 160 (offset & 0xFF000) == CPT_AF_LFX_CTL2(0)) { 161 if (offset & 7) 162 return false; 163 164 lf = (offset & 0xFFF) >> 3; 165 block = &rvu->hw->block[blkaddr]; 166 pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 167 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 168 if (lf >= num_lfs) 169 /* Slot is not valid for that PF/VF */ 170 return false; 171 172 /* Translate local LF used by VFs to global CPT LF */ 173 lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr], 174 req->hdr.pcifunc, lf); 175 if (lf < 0) 176 return false; 177 178 return true; 179 } else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) { 180 /* Registers that can be accessed from PF */ 181 switch (offset) { 182 case CPT_AF_CTL: 183 case CPT_AF_PF_FUNC: 184 case CPT_AF_BLK_RST: 185 case CPT_AF_CONSTANTS1: 186 return true; 187 } 188 189 switch (offset & 0xFF000) { 190 case CPT_AF_EXEX_STS(0): 191 case CPT_AF_EXEX_CTL(0): 192 case CPT_AF_EXEX_CTL2(0): 193 case CPT_AF_EXEX_UCODE_BASE(0): 194 if (offset & 7) 195 return false; 196 break; 197 default: 198 return false; 199 } 200 return true; 201 } 202 return false; 203 } 204 205 int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, 206 struct cpt_rd_wr_reg_msg *req, 207 struct cpt_rd_wr_reg_msg *rsp) 208 { 209 int blkaddr; 210 211 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, 0); 212 if (blkaddr < 0) 213 return blkaddr; 214 215 /* This message is accepted only if sent from CPT PF/VF */ 216 if (!is_cpt_pf(rvu, req->hdr.pcifunc) && 217 !is_cpt_vf(rvu, req->hdr.pcifunc)) 218 return CPT_AF_ERR_ACCESS_DENIED; 219 220 rsp->reg_offset = req->reg_offset; 221 rsp->ret_val = req->ret_val; 222 rsp->is_write = req->is_write; 223 224 if (!is_valid_offset(rvu, req)) 225 return CPT_AF_ERR_ACCESS_DENIED; 226 227 if (req->is_write) 228 rvu_write64(rvu, blkaddr, req->reg_offset, req->val); 229 else 230 rsp->val = rvu_read64(rvu, blkaddr, req->reg_offset); 231 232 return 0; 233 } 234