1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/pci.h> 10 #include "rvu_struct.h" 11 #include "rvu_reg.h" 12 #include "mbox.h" 13 #include "rvu.h" 14 15 /* CPT PF device id */ 16 #define PCI_DEVID_OTX2_CPT_PF 0xA0FD 17 #define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2 18 19 /* Length of initial context fetch in 128 byte words */ 20 #define CPT_CTX_ILEN 2 21 22 #define cpt_get_eng_sts(e_min, e_max, rsp, etype) \ 23 ({ \ 24 u64 free_sts = 0, busy_sts = 0; \ 25 typeof(rsp) _rsp = rsp; \ 26 u32 e, i; \ 27 \ 28 for (e = (e_min), i = 0; e < (e_max); e++, i++) { \ 29 reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(e)); \ 30 if (reg & 0x1) \ 31 busy_sts |= 1ULL << i; \ 32 \ 33 if (reg & 0x2) \ 34 free_sts |= 1ULL << i; \ 35 } \ 36 (_rsp)->busy_sts_##etype = busy_sts; \ 37 (_rsp)->free_sts_##etype = free_sts; \ 38 }) 39 40 static int get_cpt_pf_num(struct rvu *rvu) 41 { 42 int i, domain_nr, cpt_pf_num = -1; 43 struct pci_dev *pdev; 44 45 domain_nr = pci_domain_nr(rvu->pdev->bus); 46 for (i = 0; i < rvu->hw->total_pfs; i++) { 47 pdev = pci_get_domain_bus_and_slot(domain_nr, i + 1, 0); 48 if (!pdev) 49 continue; 50 51 if (pdev->device == PCI_DEVID_OTX2_CPT_PF || 52 pdev->device == PCI_DEVID_OTX2_CPT10K_PF) { 53 cpt_pf_num = i; 54 put_device(&pdev->dev); 55 break; 56 } 57 put_device(&pdev->dev); 58 } 59 return cpt_pf_num; 60 } 61 62 static bool is_cpt_pf(struct rvu *rvu, u16 pcifunc) 63 { 64 int cpt_pf_num = get_cpt_pf_num(rvu); 65 66 if (rvu_get_pf(pcifunc) != cpt_pf_num) 67 return false; 68 if (pcifunc & RVU_PFVF_FUNC_MASK) 69 return false; 70 71 return true; 72 } 73 74 static bool is_cpt_vf(struct rvu *rvu, u16 pcifunc) 75 { 76 int cpt_pf_num = get_cpt_pf_num(rvu); 77 78 if (rvu_get_pf(pcifunc) != cpt_pf_num) 79 return false; 80 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 81 return false; 82 83 return true; 84 } 85 86 static int validate_and_get_cpt_blkaddr(int req_blkaddr) 87 { 88 int blkaddr; 89 90 blkaddr = req_blkaddr ? req_blkaddr : BLKADDR_CPT0; 91 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 92 return -EINVAL; 93 94 return blkaddr; 95 } 96 97 int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu, 98 struct cpt_lf_alloc_req_msg *req, 99 struct msg_rsp *rsp) 100 { 101 u16 pcifunc = req->hdr.pcifunc; 102 struct rvu_block *block; 103 int cptlf, blkaddr; 104 int num_lfs, slot; 105 u64 val; 106 107 blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); 108 if (blkaddr < 0) 109 return blkaddr; 110 111 if (req->eng_grpmsk == 0x0) 112 return CPT_AF_ERR_GRP_INVALID; 113 114 block = &rvu->hw->block[blkaddr]; 115 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 116 block->addr); 117 if (!num_lfs) 118 return CPT_AF_ERR_LF_INVALID; 119 120 /* Check if requested 'CPTLF <=> NIXLF' mapping is valid */ 121 if (req->nix_pf_func) { 122 /* If default, use 'this' CPTLF's PFFUNC */ 123 if (req->nix_pf_func == RVU_DEFAULT_PF_FUNC) 124 req->nix_pf_func = pcifunc; 125 if (!is_pffunc_map_valid(rvu, req->nix_pf_func, BLKTYPE_NIX)) 126 return CPT_AF_ERR_NIX_PF_FUNC_INVALID; 127 } 128 129 /* Check if requested 'CPTLF <=> SSOLF' mapping is valid */ 130 if (req->sso_pf_func) { 131 /* If default, use 'this' CPTLF's PFFUNC */ 132 if (req->sso_pf_func == RVU_DEFAULT_PF_FUNC) 133 req->sso_pf_func = pcifunc; 134 if (!is_pffunc_map_valid(rvu, req->sso_pf_func, BLKTYPE_SSO)) 135 return CPT_AF_ERR_SSO_PF_FUNC_INVALID; 136 } 137 138 for (slot = 0; slot < num_lfs; slot++) { 139 cptlf = rvu_get_lf(rvu, block, pcifunc, slot); 140 if (cptlf < 0) 141 return CPT_AF_ERR_LF_INVALID; 142 143 /* Set CPT LF group and priority */ 144 val = (u64)req->eng_grpmsk << 48 | 1; 145 if (!is_rvu_otx2(rvu)) 146 val |= (CPT_CTX_ILEN << 17); 147 148 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); 149 150 /* Set CPT LF NIX_PF_FUNC and SSO_PF_FUNC */ 151 val = (u64)req->nix_pf_func << 48 | 152 (u64)req->sso_pf_func << 32; 153 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val); 154 } 155 156 return 0; 157 } 158 159 static int cpt_lf_free(struct rvu *rvu, struct msg_req *req, int blkaddr) 160 { 161 u16 pcifunc = req->hdr.pcifunc; 162 int num_lfs, cptlf, slot; 163 struct rvu_block *block; 164 165 block = &rvu->hw->block[blkaddr]; 166 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 167 block->addr); 168 if (!num_lfs) 169 return 0; 170 171 for (slot = 0; slot < num_lfs; slot++) { 172 cptlf = rvu_get_lf(rvu, block, pcifunc, slot); 173 if (cptlf < 0) 174 return CPT_AF_ERR_LF_INVALID; 175 176 /* Reset CPT LF group and priority */ 177 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), 0x0); 178 /* Reset CPT LF NIX_PF_FUNC and SSO_PF_FUNC */ 179 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), 0x0); 180 } 181 182 return 0; 183 } 184 185 int rvu_mbox_handler_cpt_lf_free(struct rvu *rvu, struct msg_req *req, 186 struct msg_rsp *rsp) 187 { 188 int ret; 189 190 ret = cpt_lf_free(rvu, req, BLKADDR_CPT0); 191 if (ret) 192 return ret; 193 194 if (is_block_implemented(rvu->hw, BLKADDR_CPT1)) 195 ret = cpt_lf_free(rvu, req, BLKADDR_CPT1); 196 197 return ret; 198 } 199 200 static int cpt_inline_ipsec_cfg_inbound(struct rvu *rvu, int blkaddr, u8 cptlf, 201 struct cpt_inline_ipsec_cfg_msg *req) 202 { 203 u16 sso_pf_func = req->sso_pf_func; 204 u8 nix_sel; 205 u64 val; 206 207 val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf)); 208 if (req->enable && (val & BIT_ULL(16))) { 209 /* IPSec inline outbound path is already enabled for a given 210 * CPT LF, HRM states that inline inbound & outbound paths 211 * must not be enabled at the same time for a given CPT LF 212 */ 213 return CPT_AF_ERR_INLINE_IPSEC_INB_ENA; 214 } 215 /* Check if requested 'CPTLF <=> SSOLF' mapping is valid */ 216 if (sso_pf_func && !is_pffunc_map_valid(rvu, sso_pf_func, BLKTYPE_SSO)) 217 return CPT_AF_ERR_SSO_PF_FUNC_INVALID; 218 219 nix_sel = (blkaddr == BLKADDR_CPT1) ? 1 : 0; 220 /* Enable CPT LF for IPsec inline inbound operations */ 221 if (req->enable) 222 val |= BIT_ULL(9); 223 else 224 val &= ~BIT_ULL(9); 225 226 val |= (u64)nix_sel << 8; 227 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); 228 229 if (sso_pf_func) { 230 /* Set SSO_PF_FUNC */ 231 val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf)); 232 val |= (u64)sso_pf_func << 32; 233 val |= (u64)req->nix_pf_func << 48; 234 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val); 235 } 236 if (req->sso_pf_func_ovrd) 237 /* Set SSO_PF_FUNC_OVRD for inline IPSec */ 238 rvu_write64(rvu, blkaddr, CPT_AF_ECO, 0x1); 239 240 /* Configure the X2P Link register with the cpt base channel number and 241 * range of channels it should propagate to X2P 242 */ 243 if (!is_rvu_otx2(rvu)) { 244 val = (ilog2(NIX_CHAN_CPT_X2P_MASK + 1) << 16); 245 val |= rvu->hw->cpt_chan_base; 246 247 rvu_write64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0), val); 248 rvu_write64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(1), val); 249 } 250 251 return 0; 252 } 253 254 static int cpt_inline_ipsec_cfg_outbound(struct rvu *rvu, int blkaddr, u8 cptlf, 255 struct cpt_inline_ipsec_cfg_msg *req) 256 { 257 u16 nix_pf_func = req->nix_pf_func; 258 int nix_blkaddr; 259 u8 nix_sel; 260 u64 val; 261 262 val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf)); 263 if (req->enable && (val & BIT_ULL(9))) { 264 /* IPSec inline inbound path is already enabled for a given 265 * CPT LF, HRM states that inline inbound & outbound paths 266 * must not be enabled at the same time for a given CPT LF 267 */ 268 return CPT_AF_ERR_INLINE_IPSEC_OUT_ENA; 269 } 270 271 /* Check if requested 'CPTLF <=> NIXLF' mapping is valid */ 272 if (nix_pf_func && !is_pffunc_map_valid(rvu, nix_pf_func, BLKTYPE_NIX)) 273 return CPT_AF_ERR_NIX_PF_FUNC_INVALID; 274 275 /* Enable CPT LF for IPsec inline outbound operations */ 276 if (req->enable) 277 val |= BIT_ULL(16); 278 else 279 val &= ~BIT_ULL(16); 280 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); 281 282 if (nix_pf_func) { 283 /* Set NIX_PF_FUNC */ 284 val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf)); 285 val |= (u64)nix_pf_func << 48; 286 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val); 287 288 nix_blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, nix_pf_func); 289 nix_sel = (nix_blkaddr == BLKADDR_NIX0) ? 0 : 1; 290 291 val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf)); 292 val |= (u64)nix_sel << 8; 293 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); 294 } 295 296 return 0; 297 } 298 299 int rvu_mbox_handler_cpt_inline_ipsec_cfg(struct rvu *rvu, 300 struct cpt_inline_ipsec_cfg_msg *req, 301 struct msg_rsp *rsp) 302 { 303 u16 pcifunc = req->hdr.pcifunc; 304 struct rvu_block *block; 305 int cptlf, blkaddr, ret; 306 u16 actual_slot; 307 308 blkaddr = rvu_get_blkaddr_from_slot(rvu, BLKTYPE_CPT, pcifunc, 309 req->slot, &actual_slot); 310 if (blkaddr < 0) 311 return CPT_AF_ERR_LF_INVALID; 312 313 block = &rvu->hw->block[blkaddr]; 314 315 cptlf = rvu_get_lf(rvu, block, pcifunc, actual_slot); 316 if (cptlf < 0) 317 return CPT_AF_ERR_LF_INVALID; 318 319 switch (req->dir) { 320 case CPT_INLINE_INBOUND: 321 ret = cpt_inline_ipsec_cfg_inbound(rvu, blkaddr, cptlf, req); 322 break; 323 324 case CPT_INLINE_OUTBOUND: 325 ret = cpt_inline_ipsec_cfg_outbound(rvu, blkaddr, cptlf, req); 326 break; 327 328 default: 329 return CPT_AF_ERR_PARAM; 330 } 331 332 return ret; 333 } 334 335 static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req) 336 { 337 u64 offset = req->reg_offset; 338 int blkaddr, num_lfs, lf; 339 struct rvu_block *block; 340 struct rvu_pfvf *pfvf; 341 342 blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); 343 if (blkaddr < 0) 344 return blkaddr; 345 346 /* Registers that can be accessed from PF/VF */ 347 if ((offset & 0xFF000) == CPT_AF_LFX_CTL(0) || 348 (offset & 0xFF000) == CPT_AF_LFX_CTL2(0)) { 349 if (offset & 7) 350 return false; 351 352 lf = (offset & 0xFFF) >> 3; 353 block = &rvu->hw->block[blkaddr]; 354 pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 355 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 356 if (lf >= num_lfs) 357 /* Slot is not valid for that PF/VF */ 358 return false; 359 360 /* Translate local LF used by VFs to global CPT LF */ 361 lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr], 362 req->hdr.pcifunc, lf); 363 if (lf < 0) 364 return false; 365 366 return true; 367 } else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) { 368 /* Registers that can be accessed from PF */ 369 switch (offset) { 370 case CPT_AF_CTL: 371 case CPT_AF_PF_FUNC: 372 case CPT_AF_BLK_RST: 373 case CPT_AF_CONSTANTS1: 374 case CPT_AF_CTX_FLUSH_TIMER: 375 return true; 376 } 377 378 switch (offset & 0xFF000) { 379 case CPT_AF_EXEX_STS(0): 380 case CPT_AF_EXEX_CTL(0): 381 case CPT_AF_EXEX_CTL2(0): 382 case CPT_AF_EXEX_UCODE_BASE(0): 383 if (offset & 7) 384 return false; 385 break; 386 default: 387 return false; 388 } 389 return true; 390 } 391 return false; 392 } 393 394 int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, 395 struct cpt_rd_wr_reg_msg *req, 396 struct cpt_rd_wr_reg_msg *rsp) 397 { 398 int blkaddr; 399 400 blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); 401 if (blkaddr < 0) 402 return blkaddr; 403 404 /* This message is accepted only if sent from CPT PF/VF */ 405 if (!is_cpt_pf(rvu, req->hdr.pcifunc) && 406 !is_cpt_vf(rvu, req->hdr.pcifunc)) 407 return CPT_AF_ERR_ACCESS_DENIED; 408 409 rsp->reg_offset = req->reg_offset; 410 rsp->ret_val = req->ret_val; 411 rsp->is_write = req->is_write; 412 413 if (!is_valid_offset(rvu, req)) 414 return CPT_AF_ERR_ACCESS_DENIED; 415 416 if (req->is_write) 417 rvu_write64(rvu, blkaddr, req->reg_offset, req->val); 418 else 419 rsp->val = rvu_read64(rvu, blkaddr, req->reg_offset); 420 421 return 0; 422 } 423 424 static void get_ctx_pc(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr) 425 { 426 if (is_rvu_otx2(rvu)) 427 return; 428 429 rsp->ctx_mis_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_MIS_PC); 430 rsp->ctx_hit_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_HIT_PC); 431 rsp->ctx_aop_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_AOP_PC); 432 rsp->ctx_aop_lat_pc = rvu_read64(rvu, blkaddr, 433 CPT_AF_CTX_AOP_LATENCY_PC); 434 rsp->ctx_ifetch_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_IFETCH_PC); 435 rsp->ctx_ifetch_lat_pc = rvu_read64(rvu, blkaddr, 436 CPT_AF_CTX_IFETCH_LATENCY_PC); 437 rsp->ctx_ffetch_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC); 438 rsp->ctx_ffetch_lat_pc = rvu_read64(rvu, blkaddr, 439 CPT_AF_CTX_FFETCH_LATENCY_PC); 440 rsp->ctx_wback_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC); 441 rsp->ctx_wback_lat_pc = rvu_read64(rvu, blkaddr, 442 CPT_AF_CTX_FFETCH_LATENCY_PC); 443 rsp->ctx_psh_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC); 444 rsp->ctx_psh_lat_pc = rvu_read64(rvu, blkaddr, 445 CPT_AF_CTX_FFETCH_LATENCY_PC); 446 rsp->ctx_err = rvu_read64(rvu, blkaddr, CPT_AF_CTX_ERR); 447 rsp->ctx_enc_id = rvu_read64(rvu, blkaddr, CPT_AF_CTX_ENC_ID); 448 rsp->ctx_flush_timer = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FLUSH_TIMER); 449 450 rsp->rxc_time = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME); 451 rsp->rxc_time_cfg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG); 452 rsp->rxc_active_sts = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ACTIVE_STS); 453 rsp->rxc_zombie_sts = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ZOMBIE_STS); 454 rsp->rxc_dfrg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_DFRG); 455 rsp->x2p_link_cfg0 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0)); 456 rsp->x2p_link_cfg1 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(1)); 457 } 458 459 static void get_eng_sts(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr) 460 { 461 u16 max_ses, max_ies, max_aes; 462 u32 e_min = 0, e_max = 0; 463 u64 reg; 464 465 reg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS1); 466 max_ses = reg & 0xffff; 467 max_ies = (reg >> 16) & 0xffff; 468 max_aes = (reg >> 32) & 0xffff; 469 470 /* Get AE status */ 471 e_min = max_ses + max_ies; 472 e_max = max_ses + max_ies + max_aes; 473 cpt_get_eng_sts(e_min, e_max, rsp, ae); 474 /* Get SE status */ 475 e_min = 0; 476 e_max = max_ses; 477 cpt_get_eng_sts(e_min, e_max, rsp, se); 478 /* Get IE status */ 479 e_min = max_ses; 480 e_max = max_ses + max_ies; 481 cpt_get_eng_sts(e_min, e_max, rsp, ie); 482 } 483 484 int rvu_mbox_handler_cpt_sts(struct rvu *rvu, struct cpt_sts_req *req, 485 struct cpt_sts_rsp *rsp) 486 { 487 int blkaddr; 488 489 blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); 490 if (blkaddr < 0) 491 return blkaddr; 492 493 /* This message is accepted only if sent from CPT PF/VF */ 494 if (!is_cpt_pf(rvu, req->hdr.pcifunc) && 495 !is_cpt_vf(rvu, req->hdr.pcifunc)) 496 return CPT_AF_ERR_ACCESS_DENIED; 497 498 get_ctx_pc(rvu, rsp, blkaddr); 499 500 /* Get CPT engines status */ 501 get_eng_sts(rvu, rsp, blkaddr); 502 503 /* Read CPT instruction PC registers */ 504 rsp->inst_req_pc = rvu_read64(rvu, blkaddr, CPT_AF_INST_REQ_PC); 505 rsp->inst_lat_pc = rvu_read64(rvu, blkaddr, CPT_AF_INST_LATENCY_PC); 506 rsp->rd_req_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_REQ_PC); 507 rsp->rd_lat_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_LATENCY_PC); 508 rsp->rd_uc_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_UC_PC); 509 rsp->active_cycles_pc = rvu_read64(rvu, blkaddr, 510 CPT_AF_ACTIVE_CYCLES_PC); 511 rsp->exe_err_info = rvu_read64(rvu, blkaddr, CPT_AF_EXE_ERR_INFO); 512 rsp->cptclk_cnt = rvu_read64(rvu, blkaddr, CPT_AF_CPTCLK_CNT); 513 rsp->diag = rvu_read64(rvu, blkaddr, CPT_AF_DIAG); 514 515 return 0; 516 } 517 518 #define RXC_ZOMBIE_THRES GENMASK_ULL(59, 48) 519 #define RXC_ZOMBIE_LIMIT GENMASK_ULL(43, 32) 520 #define RXC_ACTIVE_THRES GENMASK_ULL(27, 16) 521 #define RXC_ACTIVE_LIMIT GENMASK_ULL(11, 0) 522 #define RXC_ACTIVE_COUNT GENMASK_ULL(60, 48) 523 #define RXC_ZOMBIE_COUNT GENMASK_ULL(60, 48) 524 525 static void cpt_rxc_time_cfg(struct rvu *rvu, struct cpt_rxc_time_cfg_req *req, 526 int blkaddr) 527 { 528 u64 dfrg_reg; 529 530 dfrg_reg = FIELD_PREP(RXC_ZOMBIE_THRES, req->zombie_thres); 531 dfrg_reg |= FIELD_PREP(RXC_ZOMBIE_LIMIT, req->zombie_limit); 532 dfrg_reg |= FIELD_PREP(RXC_ACTIVE_THRES, req->active_thres); 533 dfrg_reg |= FIELD_PREP(RXC_ACTIVE_LIMIT, req->active_limit); 534 535 rvu_write64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG, req->step); 536 rvu_write64(rvu, blkaddr, CPT_AF_RXC_DFRG, dfrg_reg); 537 } 538 539 int rvu_mbox_handler_cpt_rxc_time_cfg(struct rvu *rvu, 540 struct cpt_rxc_time_cfg_req *req, 541 struct msg_rsp *rsp) 542 { 543 int blkaddr; 544 545 blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); 546 if (blkaddr < 0) 547 return blkaddr; 548 549 /* This message is accepted only if sent from CPT PF/VF */ 550 if (!is_cpt_pf(rvu, req->hdr.pcifunc) && 551 !is_cpt_vf(rvu, req->hdr.pcifunc)) 552 return CPT_AF_ERR_ACCESS_DENIED; 553 554 cpt_rxc_time_cfg(rvu, req, blkaddr); 555 556 return 0; 557 } 558 559 #define INPROG_INFLIGHT(reg) ((reg) & 0x1FF) 560 #define INPROG_GRB_PARTIAL(reg) ((reg) & BIT_ULL(31)) 561 #define INPROG_GRB(reg) (((reg) >> 32) & 0xFF) 562 #define INPROG_GWB(reg) (((reg) >> 40) & 0xFF) 563 564 static void cpt_lf_disable_iqueue(struct rvu *rvu, int blkaddr, int slot) 565 { 566 int i = 0, hard_lp_ctr = 100000; 567 u64 inprog, grp_ptr; 568 u16 nq_ptr, dq_ptr; 569 570 /* Disable instructions enqueuing */ 571 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_CTL), 0x0); 572 573 /* Disable executions in the LF's queue */ 574 inprog = rvu_read64(rvu, blkaddr, 575 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 576 inprog &= ~BIT_ULL(16); 577 rvu_write64(rvu, blkaddr, 578 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG), inprog); 579 580 /* Wait for CPT queue to become execution-quiescent */ 581 do { 582 inprog = rvu_read64(rvu, blkaddr, 583 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 584 if (INPROG_GRB_PARTIAL(inprog)) { 585 i = 0; 586 hard_lp_ctr--; 587 } else { 588 i++; 589 } 590 591 grp_ptr = rvu_read64(rvu, blkaddr, 592 CPT_AF_BAR2_ALIASX(slot, 593 CPT_LF_Q_GRP_PTR)); 594 nq_ptr = (grp_ptr >> 32) & 0x7FFF; 595 dq_ptr = grp_ptr & 0x7FFF; 596 597 } while (hard_lp_ctr && (i < 10) && (nq_ptr != dq_ptr)); 598 599 if (hard_lp_ctr == 0) 600 dev_warn(rvu->dev, "CPT FLR hits hard loop counter\n"); 601 602 i = 0; 603 hard_lp_ctr = 100000; 604 do { 605 inprog = rvu_read64(rvu, blkaddr, 606 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 607 608 if ((INPROG_INFLIGHT(inprog) == 0) && 609 (INPROG_GWB(inprog) < 40) && 610 ((INPROG_GRB(inprog) == 0) || 611 (INPROG_GRB((inprog)) == 40))) { 612 i++; 613 } else { 614 i = 0; 615 hard_lp_ctr--; 616 } 617 } while (hard_lp_ctr && (i < 10)); 618 619 if (hard_lp_ctr == 0) 620 dev_warn(rvu->dev, "CPT FLR hits hard loop counter\n"); 621 } 622 623 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot) 624 { 625 int blkaddr; 626 u64 reg; 627 628 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, pcifunc); 629 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 630 return -EINVAL; 631 632 /* Enable BAR2 ALIAS for this pcifunc. */ 633 reg = BIT_ULL(16) | pcifunc; 634 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, reg); 635 636 cpt_lf_disable_iqueue(rvu, blkaddr, slot); 637 638 /* Set group drop to help clear out hardware */ 639 reg = rvu_read64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 640 reg |= BIT_ULL(17); 641 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG), reg); 642 643 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0); 644 645 return 0; 646 } 647