1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/pci.h> 10 #include "rvu_struct.h" 11 #include "rvu_reg.h" 12 #include "mbox.h" 13 #include "rvu.h" 14 15 /* CPT PF device id */ 16 #define PCI_DEVID_OTX2_CPT_PF 0xA0FD 17 #define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2 18 19 /* Length of initial context fetch in 128 byte words */ 20 #define CPT_CTX_ILEN 2 21 22 #define cpt_get_eng_sts(e_min, e_max, rsp, etype) \ 23 ({ \ 24 u64 free_sts = 0, busy_sts = 0; \ 25 typeof(rsp) _rsp = rsp; \ 26 u32 e, i; \ 27 \ 28 for (e = (e_min), i = 0; e < (e_max); e++, i++) { \ 29 reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(e)); \ 30 if (reg & 0x1) \ 31 busy_sts |= 1ULL << i; \ 32 \ 33 if (reg & 0x2) \ 34 free_sts |= 1ULL << i; \ 35 } \ 36 (_rsp)->busy_sts_##etype = busy_sts; \ 37 (_rsp)->free_sts_##etype = free_sts; \ 38 }) 39 40 static int get_cpt_pf_num(struct rvu *rvu) 41 { 42 int i, domain_nr, cpt_pf_num = -1; 43 struct pci_dev *pdev; 44 45 domain_nr = pci_domain_nr(rvu->pdev->bus); 46 for (i = 0; i < rvu->hw->total_pfs; i++) { 47 pdev = pci_get_domain_bus_and_slot(domain_nr, i + 1, 0); 48 if (!pdev) 49 continue; 50 51 if (pdev->device == PCI_DEVID_OTX2_CPT_PF || 52 pdev->device == PCI_DEVID_OTX2_CPT10K_PF) { 53 cpt_pf_num = i; 54 put_device(&pdev->dev); 55 break; 56 } 57 put_device(&pdev->dev); 58 } 59 return cpt_pf_num; 60 } 61 62 static bool is_cpt_pf(struct rvu *rvu, u16 pcifunc) 63 { 64 int cpt_pf_num = get_cpt_pf_num(rvu); 65 66 if (rvu_get_pf(pcifunc) != cpt_pf_num) 67 return false; 68 if (pcifunc & RVU_PFVF_FUNC_MASK) 69 return false; 70 71 return true; 72 } 73 74 static bool is_cpt_vf(struct rvu *rvu, u16 pcifunc) 75 { 76 int cpt_pf_num = get_cpt_pf_num(rvu); 77 78 if (rvu_get_pf(pcifunc) != cpt_pf_num) 79 return false; 80 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 81 return false; 82 83 return true; 84 } 85 86 static int validate_and_get_cpt_blkaddr(int req_blkaddr) 87 { 88 int blkaddr; 89 90 blkaddr = req_blkaddr ? req_blkaddr : BLKADDR_CPT0; 91 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 92 return -EINVAL; 93 94 return blkaddr; 95 } 96 97 int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu, 98 struct cpt_lf_alloc_req_msg *req, 99 struct msg_rsp *rsp) 100 { 101 u16 pcifunc = req->hdr.pcifunc; 102 struct rvu_block *block; 103 int cptlf, blkaddr; 104 int num_lfs, slot; 105 u64 val; 106 107 blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); 108 if (blkaddr < 0) 109 return blkaddr; 110 111 if (req->eng_grpmsk == 0x0) 112 return CPT_AF_ERR_GRP_INVALID; 113 114 block = &rvu->hw->block[blkaddr]; 115 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 116 block->addr); 117 if (!num_lfs) 118 return CPT_AF_ERR_LF_INVALID; 119 120 /* Check if requested 'CPTLF <=> NIXLF' mapping is valid */ 121 if (req->nix_pf_func) { 122 /* If default, use 'this' CPTLF's PFFUNC */ 123 if (req->nix_pf_func == RVU_DEFAULT_PF_FUNC) 124 req->nix_pf_func = pcifunc; 125 if (!is_pffunc_map_valid(rvu, req->nix_pf_func, BLKTYPE_NIX)) 126 return CPT_AF_ERR_NIX_PF_FUNC_INVALID; 127 } 128 129 /* Check if requested 'CPTLF <=> SSOLF' mapping is valid */ 130 if (req->sso_pf_func) { 131 /* If default, use 'this' CPTLF's PFFUNC */ 132 if (req->sso_pf_func == RVU_DEFAULT_PF_FUNC) 133 req->sso_pf_func = pcifunc; 134 if (!is_pffunc_map_valid(rvu, req->sso_pf_func, BLKTYPE_SSO)) 135 return CPT_AF_ERR_SSO_PF_FUNC_INVALID; 136 } 137 138 for (slot = 0; slot < num_lfs; slot++) { 139 cptlf = rvu_get_lf(rvu, block, pcifunc, slot); 140 if (cptlf < 0) 141 return CPT_AF_ERR_LF_INVALID; 142 143 /* Set CPT LF group and priority */ 144 val = (u64)req->eng_grpmsk << 48 | 1; 145 if (!is_rvu_otx2(rvu)) 146 val |= (CPT_CTX_ILEN << 17); 147 148 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); 149 150 /* Set CPT LF NIX_PF_FUNC and SSO_PF_FUNC */ 151 val = (u64)req->nix_pf_func << 48 | 152 (u64)req->sso_pf_func << 32; 153 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val); 154 } 155 156 return 0; 157 } 158 159 static int cpt_lf_free(struct rvu *rvu, struct msg_req *req, int blkaddr) 160 { 161 u16 pcifunc = req->hdr.pcifunc; 162 int num_lfs, cptlf, slot; 163 struct rvu_block *block; 164 165 block = &rvu->hw->block[blkaddr]; 166 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 167 block->addr); 168 if (!num_lfs) 169 return 0; 170 171 for (slot = 0; slot < num_lfs; slot++) { 172 cptlf = rvu_get_lf(rvu, block, pcifunc, slot); 173 if (cptlf < 0) 174 return CPT_AF_ERR_LF_INVALID; 175 176 /* Reset CPT LF group and priority */ 177 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), 0x0); 178 /* Reset CPT LF NIX_PF_FUNC and SSO_PF_FUNC */ 179 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), 0x0); 180 } 181 182 return 0; 183 } 184 185 int rvu_mbox_handler_cpt_lf_free(struct rvu *rvu, struct msg_req *req, 186 struct msg_rsp *rsp) 187 { 188 int ret; 189 190 ret = cpt_lf_free(rvu, req, BLKADDR_CPT0); 191 if (ret) 192 return ret; 193 194 if (is_block_implemented(rvu->hw, BLKADDR_CPT1)) 195 ret = cpt_lf_free(rvu, req, BLKADDR_CPT1); 196 197 return ret; 198 } 199 200 static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req) 201 { 202 u64 offset = req->reg_offset; 203 int blkaddr, num_lfs, lf; 204 struct rvu_block *block; 205 struct rvu_pfvf *pfvf; 206 207 blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); 208 if (blkaddr < 0) 209 return blkaddr; 210 211 /* Registers that can be accessed from PF/VF */ 212 if ((offset & 0xFF000) == CPT_AF_LFX_CTL(0) || 213 (offset & 0xFF000) == CPT_AF_LFX_CTL2(0)) { 214 if (offset & 7) 215 return false; 216 217 lf = (offset & 0xFFF) >> 3; 218 block = &rvu->hw->block[blkaddr]; 219 pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 220 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 221 if (lf >= num_lfs) 222 /* Slot is not valid for that PF/VF */ 223 return false; 224 225 /* Translate local LF used by VFs to global CPT LF */ 226 lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr], 227 req->hdr.pcifunc, lf); 228 if (lf < 0) 229 return false; 230 231 return true; 232 } else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) { 233 /* Registers that can be accessed from PF */ 234 switch (offset) { 235 case CPT_AF_CTL: 236 case CPT_AF_PF_FUNC: 237 case CPT_AF_BLK_RST: 238 case CPT_AF_CONSTANTS1: 239 case CPT_AF_CTX_FLUSH_TIMER: 240 return true; 241 } 242 243 switch (offset & 0xFF000) { 244 case CPT_AF_EXEX_STS(0): 245 case CPT_AF_EXEX_CTL(0): 246 case CPT_AF_EXEX_CTL2(0): 247 case CPT_AF_EXEX_UCODE_BASE(0): 248 if (offset & 7) 249 return false; 250 break; 251 default: 252 return false; 253 } 254 return true; 255 } 256 return false; 257 } 258 259 int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, 260 struct cpt_rd_wr_reg_msg *req, 261 struct cpt_rd_wr_reg_msg *rsp) 262 { 263 int blkaddr; 264 265 blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); 266 if (blkaddr < 0) 267 return blkaddr; 268 269 /* This message is accepted only if sent from CPT PF/VF */ 270 if (!is_cpt_pf(rvu, req->hdr.pcifunc) && 271 !is_cpt_vf(rvu, req->hdr.pcifunc)) 272 return CPT_AF_ERR_ACCESS_DENIED; 273 274 rsp->reg_offset = req->reg_offset; 275 rsp->ret_val = req->ret_val; 276 rsp->is_write = req->is_write; 277 278 if (!is_valid_offset(rvu, req)) 279 return CPT_AF_ERR_ACCESS_DENIED; 280 281 if (req->is_write) 282 rvu_write64(rvu, blkaddr, req->reg_offset, req->val); 283 else 284 rsp->val = rvu_read64(rvu, blkaddr, req->reg_offset); 285 286 return 0; 287 } 288 289 static void get_ctx_pc(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr) 290 { 291 if (is_rvu_otx2(rvu)) 292 return; 293 294 rsp->ctx_mis_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_MIS_PC); 295 rsp->ctx_hit_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_HIT_PC); 296 rsp->ctx_aop_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_AOP_PC); 297 rsp->ctx_aop_lat_pc = rvu_read64(rvu, blkaddr, 298 CPT_AF_CTX_AOP_LATENCY_PC); 299 rsp->ctx_ifetch_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_IFETCH_PC); 300 rsp->ctx_ifetch_lat_pc = rvu_read64(rvu, blkaddr, 301 CPT_AF_CTX_IFETCH_LATENCY_PC); 302 rsp->ctx_ffetch_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC); 303 rsp->ctx_ffetch_lat_pc = rvu_read64(rvu, blkaddr, 304 CPT_AF_CTX_FFETCH_LATENCY_PC); 305 rsp->ctx_wback_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC); 306 rsp->ctx_wback_lat_pc = rvu_read64(rvu, blkaddr, 307 CPT_AF_CTX_FFETCH_LATENCY_PC); 308 rsp->ctx_psh_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC); 309 rsp->ctx_psh_lat_pc = rvu_read64(rvu, blkaddr, 310 CPT_AF_CTX_FFETCH_LATENCY_PC); 311 rsp->ctx_err = rvu_read64(rvu, blkaddr, CPT_AF_CTX_ERR); 312 rsp->ctx_enc_id = rvu_read64(rvu, blkaddr, CPT_AF_CTX_ENC_ID); 313 rsp->ctx_flush_timer = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FLUSH_TIMER); 314 315 rsp->rxc_time = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME); 316 rsp->rxc_time_cfg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG); 317 rsp->rxc_active_sts = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ACTIVE_STS); 318 rsp->rxc_zombie_sts = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ZOMBIE_STS); 319 rsp->rxc_dfrg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_DFRG); 320 rsp->x2p_link_cfg0 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0)); 321 rsp->x2p_link_cfg1 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(1)); 322 } 323 324 static void get_eng_sts(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr) 325 { 326 u16 max_ses, max_ies, max_aes; 327 u32 e_min = 0, e_max = 0; 328 u64 reg; 329 330 reg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS1); 331 max_ses = reg & 0xffff; 332 max_ies = (reg >> 16) & 0xffff; 333 max_aes = (reg >> 32) & 0xffff; 334 335 /* Get AE status */ 336 e_min = max_ses + max_ies; 337 e_max = max_ses + max_ies + max_aes; 338 cpt_get_eng_sts(e_min, e_max, rsp, ae); 339 /* Get SE status */ 340 e_min = 0; 341 e_max = max_ses; 342 cpt_get_eng_sts(e_min, e_max, rsp, se); 343 /* Get IE status */ 344 e_min = max_ses; 345 e_max = max_ses + max_ies; 346 cpt_get_eng_sts(e_min, e_max, rsp, ie); 347 } 348 349 int rvu_mbox_handler_cpt_sts(struct rvu *rvu, struct cpt_sts_req *req, 350 struct cpt_sts_rsp *rsp) 351 { 352 int blkaddr; 353 354 blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); 355 if (blkaddr < 0) 356 return blkaddr; 357 358 /* This message is accepted only if sent from CPT PF/VF */ 359 if (!is_cpt_pf(rvu, req->hdr.pcifunc) && 360 !is_cpt_vf(rvu, req->hdr.pcifunc)) 361 return CPT_AF_ERR_ACCESS_DENIED; 362 363 get_ctx_pc(rvu, rsp, blkaddr); 364 365 /* Get CPT engines status */ 366 get_eng_sts(rvu, rsp, blkaddr); 367 368 /* Read CPT instruction PC registers */ 369 rsp->inst_req_pc = rvu_read64(rvu, blkaddr, CPT_AF_INST_REQ_PC); 370 rsp->inst_lat_pc = rvu_read64(rvu, blkaddr, CPT_AF_INST_LATENCY_PC); 371 rsp->rd_req_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_REQ_PC); 372 rsp->rd_lat_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_LATENCY_PC); 373 rsp->rd_uc_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_UC_PC); 374 rsp->active_cycles_pc = rvu_read64(rvu, blkaddr, 375 CPT_AF_ACTIVE_CYCLES_PC); 376 rsp->exe_err_info = rvu_read64(rvu, blkaddr, CPT_AF_EXE_ERR_INFO); 377 rsp->cptclk_cnt = rvu_read64(rvu, blkaddr, CPT_AF_CPTCLK_CNT); 378 rsp->diag = rvu_read64(rvu, blkaddr, CPT_AF_DIAG); 379 380 return 0; 381 } 382 383 #define RXC_ZOMBIE_THRES GENMASK_ULL(59, 48) 384 #define RXC_ZOMBIE_LIMIT GENMASK_ULL(43, 32) 385 #define RXC_ACTIVE_THRES GENMASK_ULL(27, 16) 386 #define RXC_ACTIVE_LIMIT GENMASK_ULL(11, 0) 387 #define RXC_ACTIVE_COUNT GENMASK_ULL(60, 48) 388 #define RXC_ZOMBIE_COUNT GENMASK_ULL(60, 48) 389 390 static void cpt_rxc_time_cfg(struct rvu *rvu, struct cpt_rxc_time_cfg_req *req, 391 int blkaddr) 392 { 393 u64 dfrg_reg; 394 395 dfrg_reg = FIELD_PREP(RXC_ZOMBIE_THRES, req->zombie_thres); 396 dfrg_reg |= FIELD_PREP(RXC_ZOMBIE_LIMIT, req->zombie_limit); 397 dfrg_reg |= FIELD_PREP(RXC_ACTIVE_THRES, req->active_thres); 398 dfrg_reg |= FIELD_PREP(RXC_ACTIVE_LIMIT, req->active_limit); 399 400 rvu_write64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG, req->step); 401 rvu_write64(rvu, blkaddr, CPT_AF_RXC_DFRG, dfrg_reg); 402 } 403 404 int rvu_mbox_handler_cpt_rxc_time_cfg(struct rvu *rvu, 405 struct cpt_rxc_time_cfg_req *req, 406 struct msg_rsp *rsp) 407 { 408 int blkaddr; 409 410 blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr); 411 if (blkaddr < 0) 412 return blkaddr; 413 414 /* This message is accepted only if sent from CPT PF/VF */ 415 if (!is_cpt_pf(rvu, req->hdr.pcifunc) && 416 !is_cpt_vf(rvu, req->hdr.pcifunc)) 417 return CPT_AF_ERR_ACCESS_DENIED; 418 419 cpt_rxc_time_cfg(rvu, req, blkaddr); 420 421 return 0; 422 } 423 424 #define INPROG_INFLIGHT(reg) ((reg) & 0x1FF) 425 #define INPROG_GRB_PARTIAL(reg) ((reg) & BIT_ULL(31)) 426 #define INPROG_GRB(reg) (((reg) >> 32) & 0xFF) 427 #define INPROG_GWB(reg) (((reg) >> 40) & 0xFF) 428 429 static void cpt_lf_disable_iqueue(struct rvu *rvu, int blkaddr, int slot) 430 { 431 int i = 0, hard_lp_ctr = 100000; 432 u64 inprog, grp_ptr; 433 u16 nq_ptr, dq_ptr; 434 435 /* Disable instructions enqueuing */ 436 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_CTL), 0x0); 437 438 /* Disable executions in the LF's queue */ 439 inprog = rvu_read64(rvu, blkaddr, 440 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 441 inprog &= ~BIT_ULL(16); 442 rvu_write64(rvu, blkaddr, 443 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG), inprog); 444 445 /* Wait for CPT queue to become execution-quiescent */ 446 do { 447 inprog = rvu_read64(rvu, blkaddr, 448 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 449 if (INPROG_GRB_PARTIAL(inprog)) { 450 i = 0; 451 hard_lp_ctr--; 452 } else { 453 i++; 454 } 455 456 grp_ptr = rvu_read64(rvu, blkaddr, 457 CPT_AF_BAR2_ALIASX(slot, 458 CPT_LF_Q_GRP_PTR)); 459 nq_ptr = (grp_ptr >> 32) & 0x7FFF; 460 dq_ptr = grp_ptr & 0x7FFF; 461 462 } while (hard_lp_ctr && (i < 10) && (nq_ptr != dq_ptr)); 463 464 if (hard_lp_ctr == 0) 465 dev_warn(rvu->dev, "CPT FLR hits hard loop counter\n"); 466 467 i = 0; 468 hard_lp_ctr = 100000; 469 do { 470 inprog = rvu_read64(rvu, blkaddr, 471 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 472 473 if ((INPROG_INFLIGHT(inprog) == 0) && 474 (INPROG_GWB(inprog) < 40) && 475 ((INPROG_GRB(inprog) == 0) || 476 (INPROG_GRB((inprog)) == 40))) { 477 i++; 478 } else { 479 i = 0; 480 hard_lp_ctr--; 481 } 482 } while (hard_lp_ctr && (i < 10)); 483 484 if (hard_lp_ctr == 0) 485 dev_warn(rvu->dev, "CPT FLR hits hard loop counter\n"); 486 } 487 488 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot) 489 { 490 int blkaddr; 491 u64 reg; 492 493 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, pcifunc); 494 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 495 return -EINVAL; 496 497 /* Enable BAR2 ALIAS for this pcifunc. */ 498 reg = BIT_ULL(16) | pcifunc; 499 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, reg); 500 501 cpt_lf_disable_iqueue(rvu, blkaddr, slot); 502 503 /* Set group drop to help clear out hardware */ 504 reg = rvu_read64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 505 reg |= BIT_ULL(17); 506 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG), reg); 507 508 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0); 509 510 return 0; 511 } 512