1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2020 Marvell. */ 3 4 #include <linux/pci.h> 5 #include "rvu_struct.h" 6 #include "rvu_reg.h" 7 #include "mbox.h" 8 #include "rvu.h" 9 10 /* CPT PF device id */ 11 #define PCI_DEVID_OTX2_CPT_PF 0xA0FD 12 13 static int get_cpt_pf_num(struct rvu *rvu) 14 { 15 int i, domain_nr, cpt_pf_num = -1; 16 struct pci_dev *pdev; 17 18 domain_nr = pci_domain_nr(rvu->pdev->bus); 19 for (i = 0; i < rvu->hw->total_pfs; i++) { 20 pdev = pci_get_domain_bus_and_slot(domain_nr, i + 1, 0); 21 if (!pdev) 22 continue; 23 24 if (pdev->device == PCI_DEVID_OTX2_CPT_PF) { 25 cpt_pf_num = i; 26 put_device(&pdev->dev); 27 break; 28 } 29 put_device(&pdev->dev); 30 } 31 return cpt_pf_num; 32 } 33 34 static bool is_cpt_pf(struct rvu *rvu, u16 pcifunc) 35 { 36 int cpt_pf_num = get_cpt_pf_num(rvu); 37 38 if (rvu_get_pf(pcifunc) != cpt_pf_num) 39 return false; 40 if (pcifunc & RVU_PFVF_FUNC_MASK) 41 return false; 42 43 return true; 44 } 45 46 static bool is_cpt_vf(struct rvu *rvu, u16 pcifunc) 47 { 48 int cpt_pf_num = get_cpt_pf_num(rvu); 49 50 if (rvu_get_pf(pcifunc) != cpt_pf_num) 51 return false; 52 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 53 return false; 54 55 return true; 56 } 57 58 int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu, 59 struct cpt_lf_alloc_req_msg *req, 60 struct msg_rsp *rsp) 61 { 62 u16 pcifunc = req->hdr.pcifunc; 63 struct rvu_block *block; 64 int cptlf, blkaddr; 65 int num_lfs, slot; 66 u64 val; 67 68 blkaddr = req->blkaddr ? req->blkaddr : BLKADDR_CPT0; 69 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 70 return -ENODEV; 71 72 if (req->eng_grpmsk == 0x0) 73 return CPT_AF_ERR_GRP_INVALID; 74 75 block = &rvu->hw->block[blkaddr]; 76 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 77 block->addr); 78 if (!num_lfs) 79 return CPT_AF_ERR_LF_INVALID; 80 81 /* Check if requested 'CPTLF <=> NIXLF' mapping is valid */ 82 if (req->nix_pf_func) { 83 /* If default, use 'this' CPTLF's PFFUNC */ 84 if (req->nix_pf_func == RVU_DEFAULT_PF_FUNC) 85 req->nix_pf_func = pcifunc; 86 if (!is_pffunc_map_valid(rvu, req->nix_pf_func, BLKTYPE_NIX)) 87 return CPT_AF_ERR_NIX_PF_FUNC_INVALID; 88 } 89 90 /* Check if requested 'CPTLF <=> SSOLF' mapping is valid */ 91 if (req->sso_pf_func) { 92 /* If default, use 'this' CPTLF's PFFUNC */ 93 if (req->sso_pf_func == RVU_DEFAULT_PF_FUNC) 94 req->sso_pf_func = pcifunc; 95 if (!is_pffunc_map_valid(rvu, req->sso_pf_func, BLKTYPE_SSO)) 96 return CPT_AF_ERR_SSO_PF_FUNC_INVALID; 97 } 98 99 for (slot = 0; slot < num_lfs; slot++) { 100 cptlf = rvu_get_lf(rvu, block, pcifunc, slot); 101 if (cptlf < 0) 102 return CPT_AF_ERR_LF_INVALID; 103 104 /* Set CPT LF group and priority */ 105 val = (u64)req->eng_grpmsk << 48 | 1; 106 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val); 107 108 /* Set CPT LF NIX_PF_FUNC and SSO_PF_FUNC */ 109 val = (u64)req->nix_pf_func << 48 | 110 (u64)req->sso_pf_func << 32; 111 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val); 112 } 113 114 return 0; 115 } 116 117 static int cpt_lf_free(struct rvu *rvu, struct msg_req *req, int blkaddr) 118 { 119 u16 pcifunc = req->hdr.pcifunc; 120 int num_lfs, cptlf, slot; 121 struct rvu_block *block; 122 123 block = &rvu->hw->block[blkaddr]; 124 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 125 block->addr); 126 if (!num_lfs) 127 return 0; 128 129 for (slot = 0; slot < num_lfs; slot++) { 130 cptlf = rvu_get_lf(rvu, block, pcifunc, slot); 131 if (cptlf < 0) 132 return CPT_AF_ERR_LF_INVALID; 133 134 /* Reset CPT LF group and priority */ 135 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), 0x0); 136 /* Reset CPT LF NIX_PF_FUNC and SSO_PF_FUNC */ 137 rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), 0x0); 138 } 139 140 return 0; 141 } 142 143 int rvu_mbox_handler_cpt_lf_free(struct rvu *rvu, struct msg_req *req, 144 struct msg_rsp *rsp) 145 { 146 int ret; 147 148 ret = cpt_lf_free(rvu, req, BLKADDR_CPT0); 149 if (ret) 150 return ret; 151 152 if (is_block_implemented(rvu->hw, BLKADDR_CPT1)) 153 ret = cpt_lf_free(rvu, req, BLKADDR_CPT1); 154 155 return ret; 156 } 157 158 static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req) 159 { 160 u64 offset = req->reg_offset; 161 int blkaddr, num_lfs, lf; 162 struct rvu_block *block; 163 struct rvu_pfvf *pfvf; 164 165 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, 0); 166 167 /* Registers that can be accessed from PF/VF */ 168 if ((offset & 0xFF000) == CPT_AF_LFX_CTL(0) || 169 (offset & 0xFF000) == CPT_AF_LFX_CTL2(0)) { 170 if (offset & 7) 171 return false; 172 173 lf = (offset & 0xFFF) >> 3; 174 block = &rvu->hw->block[blkaddr]; 175 pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); 176 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 177 if (lf >= num_lfs) 178 /* Slot is not valid for that PF/VF */ 179 return false; 180 181 /* Translate local LF used by VFs to global CPT LF */ 182 lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr], 183 req->hdr.pcifunc, lf); 184 if (lf < 0) 185 return false; 186 187 return true; 188 } else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) { 189 /* Registers that can be accessed from PF */ 190 switch (offset) { 191 case CPT_AF_CTL: 192 case CPT_AF_PF_FUNC: 193 case CPT_AF_BLK_RST: 194 case CPT_AF_CONSTANTS1: 195 return true; 196 } 197 198 switch (offset & 0xFF000) { 199 case CPT_AF_EXEX_STS(0): 200 case CPT_AF_EXEX_CTL(0): 201 case CPT_AF_EXEX_CTL2(0): 202 case CPT_AF_EXEX_UCODE_BASE(0): 203 if (offset & 7) 204 return false; 205 break; 206 default: 207 return false; 208 } 209 return true; 210 } 211 return false; 212 } 213 214 int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu, 215 struct cpt_rd_wr_reg_msg *req, 216 struct cpt_rd_wr_reg_msg *rsp) 217 { 218 int blkaddr; 219 220 blkaddr = req->blkaddr ? req->blkaddr : BLKADDR_CPT0; 221 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 222 return -ENODEV; 223 224 /* This message is accepted only if sent from CPT PF/VF */ 225 if (!is_cpt_pf(rvu, req->hdr.pcifunc) && 226 !is_cpt_vf(rvu, req->hdr.pcifunc)) 227 return CPT_AF_ERR_ACCESS_DENIED; 228 229 rsp->reg_offset = req->reg_offset; 230 rsp->ret_val = req->ret_val; 231 rsp->is_write = req->is_write; 232 233 if (!is_valid_offset(rvu, req)) 234 return CPT_AF_ERR_ACCESS_DENIED; 235 236 if (req->is_write) 237 rvu_write64(rvu, blkaddr, req->reg_offset, req->val); 238 else 239 rsp->val = rvu_read64(rvu, blkaddr, req->reg_offset); 240 241 return 0; 242 } 243 244 #define INPROG_INFLIGHT(reg) ((reg) & 0x1FF) 245 #define INPROG_GRB_PARTIAL(reg) ((reg) & BIT_ULL(31)) 246 #define INPROG_GRB(reg) (((reg) >> 32) & 0xFF) 247 #define INPROG_GWB(reg) (((reg) >> 40) & 0xFF) 248 249 static void cpt_lf_disable_iqueue(struct rvu *rvu, int blkaddr, int slot) 250 { 251 int i = 0, hard_lp_ctr = 100000; 252 u64 inprog, grp_ptr; 253 u16 nq_ptr, dq_ptr; 254 255 /* Disable instructions enqueuing */ 256 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_CTL), 0x0); 257 258 /* Disable executions in the LF's queue */ 259 inprog = rvu_read64(rvu, blkaddr, 260 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 261 inprog &= ~BIT_ULL(16); 262 rvu_write64(rvu, blkaddr, 263 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG), inprog); 264 265 /* Wait for CPT queue to become execution-quiescent */ 266 do { 267 inprog = rvu_read64(rvu, blkaddr, 268 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 269 if (INPROG_GRB_PARTIAL(inprog)) { 270 i = 0; 271 hard_lp_ctr--; 272 } else { 273 i++; 274 } 275 276 grp_ptr = rvu_read64(rvu, blkaddr, 277 CPT_AF_BAR2_ALIASX(slot, 278 CPT_LF_Q_GRP_PTR)); 279 nq_ptr = (grp_ptr >> 32) & 0x7FFF; 280 dq_ptr = grp_ptr & 0x7FFF; 281 282 } while (hard_lp_ctr && (i < 10) && (nq_ptr != dq_ptr)); 283 284 if (hard_lp_ctr == 0) 285 dev_warn(rvu->dev, "CPT FLR hits hard loop counter\n"); 286 287 i = 0; 288 hard_lp_ctr = 100000; 289 do { 290 inprog = rvu_read64(rvu, blkaddr, 291 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 292 293 if ((INPROG_INFLIGHT(inprog) == 0) && 294 (INPROG_GWB(inprog) < 40) && 295 ((INPROG_GRB(inprog) == 0) || 296 (INPROG_GRB((inprog)) == 40))) { 297 i++; 298 } else { 299 i = 0; 300 hard_lp_ctr--; 301 } 302 } while (hard_lp_ctr && (i < 10)); 303 304 if (hard_lp_ctr == 0) 305 dev_warn(rvu->dev, "CPT FLR hits hard loop counter\n"); 306 } 307 308 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot) 309 { 310 int blkaddr; 311 u64 reg; 312 313 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, pcifunc); 314 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 315 return -EINVAL; 316 317 /* Enable BAR2 ALIAS for this pcifunc. */ 318 reg = BIT_ULL(16) | pcifunc; 319 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, reg); 320 321 cpt_lf_disable_iqueue(rvu, blkaddr, slot); 322 323 /* Set group drop to help clear out hardware */ 324 reg = rvu_read64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG)); 325 reg |= BIT_ULL(17); 326 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG), reg); 327 328 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0); 329 330 return 0; 331 } 332