1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RPM CN10K driver 3 * 4 * Copyright (C) 2020 Marvell. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/pci.h> 9 #include "rvu.h" 10 #include "cgx.h" 11 #include "rvu_reg.h" 12 13 /* RVU LMTST */ 14 #define LMT_TBL_OP_READ 0 15 #define LMT_TBL_OP_WRITE 1 16 #define LMT_MAP_TABLE_SIZE (128 * 1024) 17 #define LMT_MAPTBL_ENTRY_SIZE 16 18 19 /* Function to perform operations (read/write) on lmtst map table */ 20 static int lmtst_map_table_ops(struct rvu *rvu, u32 index, u64 *val, 21 int lmt_tbl_op) 22 { 23 void __iomem *lmt_map_base; 24 u64 tbl_base; 25 26 tbl_base = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_MAP_BASE); 27 28 lmt_map_base = ioremap_wc(tbl_base, LMT_MAP_TABLE_SIZE); 29 if (!lmt_map_base) { 30 dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n"); 31 return -ENOMEM; 32 } 33 34 if (lmt_tbl_op == LMT_TBL_OP_READ) { 35 *val = readq(lmt_map_base + index); 36 } else { 37 writeq((*val), (lmt_map_base + index)); 38 /* Flushing the AP interceptor cache to make APR_LMT_MAP_ENTRY_S 39 * changes effective. Write 1 for flush and read is being used as a 40 * barrier and sets up a data dependency. Write to 0 after a write 41 * to 1 to complete the flush. 42 */ 43 rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, BIT_ULL(0)); 44 rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CTL); 45 rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CTL, 0x00); 46 } 47 48 iounmap(lmt_map_base); 49 return 0; 50 } 51 52 static u32 rvu_get_lmtst_tbl_index(struct rvu *rvu, u16 pcifunc) 53 { 54 return ((rvu_get_pf(pcifunc) * rvu->hw->total_vfs) + 55 (pcifunc & RVU_PFVF_FUNC_MASK)) * LMT_MAPTBL_ENTRY_SIZE; 56 } 57 58 static int rvu_get_lmtaddr(struct rvu *rvu, u16 pcifunc, 59 u64 iova, u64 *lmt_addr) 60 { 61 u64 pa, val, pf; 62 int err; 63 64 if (!iova) { 65 dev_err(rvu->dev, "%s Requested Null address for transulation\n", __func__); 66 return -EINVAL; 67 } 68 69 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_REQ, iova); 70 pf = rvu_get_pf(pcifunc) & 0x1F; 71 val = BIT_ULL(63) | BIT_ULL(14) | BIT_ULL(13) | pf << 8 | 72 ((pcifunc & RVU_PFVF_FUNC_MASK) & 0xFF); 73 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TXN_REQ, val); 74 75 err = rvu_poll_reg(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS, BIT_ULL(0), false); 76 if (err) { 77 dev_err(rvu->dev, "%s LMTLINE iova transulation failed\n", __func__); 78 return err; 79 } 80 val = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_ADDR_RSP_STS); 81 if (val & ~0x1ULL) { 82 dev_err(rvu->dev, "%s LMTLINE iova transulation failed err:%llx\n", __func__, val); 83 return -EIO; 84 } 85 /* PA[51:12] = RVU_AF_SMMU_TLN_FLIT1[60:21] 86 * PA[11:0] = IOVA[11:0] 87 */ 88 pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT1) >> 21; 89 pa &= GENMASK_ULL(39, 0); 90 *lmt_addr = (pa << 12) | (iova & 0xFFF); 91 92 return 0; 93 } 94 95 static int rvu_update_lmtaddr(struct rvu *rvu, u16 pcifunc, u64 lmt_addr) 96 { 97 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 98 u32 tbl_idx; 99 int err = 0; 100 u64 val; 101 102 /* Read the current lmt addr of pcifunc */ 103 tbl_idx = rvu_get_lmtst_tbl_index(rvu, pcifunc); 104 err = lmtst_map_table_ops(rvu, tbl_idx, &val, LMT_TBL_OP_READ); 105 if (err) { 106 dev_err(rvu->dev, 107 "Failed to read LMT map table: index 0x%x err %d\n", 108 tbl_idx, err); 109 return err; 110 } 111 112 /* Storing the seondary's lmt base address as this needs to be 113 * reverted in FLR. Also making sure this default value doesn't 114 * get overwritten on multiple calls to this mailbox. 115 */ 116 if (!pfvf->lmt_base_addr) 117 pfvf->lmt_base_addr = val; 118 119 /* Update the LMT table with new addr */ 120 err = lmtst_map_table_ops(rvu, tbl_idx, &lmt_addr, LMT_TBL_OP_WRITE); 121 if (err) { 122 dev_err(rvu->dev, 123 "Failed to update LMT map table: index 0x%x err %d\n", 124 tbl_idx, err); 125 return err; 126 } 127 return 0; 128 } 129 130 int rvu_mbox_handler_lmtst_tbl_setup(struct rvu *rvu, 131 struct lmtst_tbl_setup_req *req, 132 struct msg_rsp *rsp) 133 { 134 u64 lmt_addr, val; 135 u32 pri_tbl_idx; 136 int err = 0; 137 138 /* Check if PF_FUNC wants to use it's own local memory as LMTLINE 139 * region, if so, convert that IOVA to physical address and 140 * populate LMT table with that address 141 */ 142 if (req->use_local_lmt_region) { 143 err = rvu_get_lmtaddr(rvu, req->hdr.pcifunc, 144 req->lmt_iova, &lmt_addr); 145 if (err < 0) 146 return err; 147 148 /* Update the lmt addr for this PFFUNC in the LMT table */ 149 err = rvu_update_lmtaddr(rvu, req->hdr.pcifunc, lmt_addr); 150 if (err) 151 return err; 152 } 153 154 /* Reconfiguring lmtst map table in lmt region shared mode i.e. make 155 * multiple PF_FUNCs to share an LMTLINE region, so primary/base 156 * pcifunc (which is passed as an argument to mailbox) is the one 157 * whose lmt base address will be shared among other secondary 158 * pcifunc (will be the one who is calling this mailbox). 159 */ 160 if (req->base_pcifunc) { 161 /* Calculating the LMT table index equivalent to primary 162 * pcifunc. 163 */ 164 pri_tbl_idx = rvu_get_lmtst_tbl_index(rvu, req->base_pcifunc); 165 166 /* Read the base lmt addr of the primary pcifunc */ 167 err = lmtst_map_table_ops(rvu, pri_tbl_idx, &val, 168 LMT_TBL_OP_READ); 169 if (err) { 170 dev_err(rvu->dev, 171 "Failed to read LMT map table: index 0x%x err %d\n", 172 pri_tbl_idx, err); 173 return err; 174 } 175 176 /* Update the base lmt addr of secondary with primary's base 177 * lmt addr. 178 */ 179 err = rvu_update_lmtaddr(rvu, req->hdr.pcifunc, val); 180 if (err) 181 return err; 182 } 183 184 return 0; 185 } 186 187 /* Resetting the lmtst map table to original base addresses */ 188 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc) 189 { 190 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 191 u32 tbl_idx; 192 int err; 193 194 if (is_rvu_otx2(rvu)) 195 return; 196 197 if (pfvf->lmt_base_addr) { 198 /* This corresponds to lmt map table index */ 199 tbl_idx = rvu_get_lmtst_tbl_index(rvu, pcifunc); 200 /* Reverting back original lmt base addr for respective 201 * pcifunc. 202 */ 203 err = lmtst_map_table_ops(rvu, tbl_idx, &pfvf->lmt_base_addr, 204 LMT_TBL_OP_WRITE); 205 if (err) 206 dev_err(rvu->dev, 207 "Failed to update LMT map table: index 0x%x err %d\n", 208 tbl_idx, err); 209 pfvf->lmt_base_addr = 0; 210 } 211 } 212 213 int rvu_set_channels_base(struct rvu *rvu) 214 { 215 struct rvu_hwinfo *hw = rvu->hw; 216 u16 cpt_chan_base; 217 u64 nix_const; 218 int blkaddr; 219 220 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0); 221 if (blkaddr < 0) 222 return blkaddr; 223 224 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST); 225 226 hw->cgx = (nix_const >> 12) & 0xFULL; 227 hw->lmac_per_cgx = (nix_const >> 8) & 0xFULL; 228 hw->cgx_links = hw->cgx * hw->lmac_per_cgx; 229 hw->lbk_links = (nix_const >> 24) & 0xFULL; 230 hw->cpt_links = (nix_const >> 44) & 0xFULL; 231 hw->sdp_links = 1; 232 233 hw->cgx_chan_base = NIX_CHAN_CGX_LMAC_CHX(0, 0, 0); 234 hw->lbk_chan_base = NIX_CHAN_LBK_CHX(0, 0); 235 hw->sdp_chan_base = NIX_CHAN_SDP_CH_START; 236 237 /* No Programmable channels */ 238 if (!(nix_const & BIT_ULL(60))) 239 return 0; 240 241 hw->cap.programmable_chans = true; 242 243 /* If programmable channels are present then configure 244 * channels such that all channel numbers are contiguous 245 * leaving no holes. This way the new CPT channels can be 246 * accomodated. The order of channel numbers assigned is 247 * LBK, SDP, CGX and CPT. 248 */ 249 hw->sdp_chan_base = hw->lbk_chan_base + hw->lbk_links * 250 ((nix_const >> 16) & 0xFFULL); 251 hw->cgx_chan_base = hw->sdp_chan_base + hw->sdp_links * SDP_CHANNELS; 252 253 cpt_chan_base = hw->cgx_chan_base + hw->cgx_links * 254 (nix_const & 0xFFULL); 255 256 /* Out of 4096 channels start CPT from 2048 so 257 * that MSB for CPT channels is always set 258 */ 259 if (cpt_chan_base <= 0x800) { 260 hw->cpt_chan_base = 0x800; 261 } else { 262 dev_err(rvu->dev, 263 "CPT channels could not fit in the range 2048-4095\n"); 264 return -EINVAL; 265 } 266 267 return 0; 268 } 269 270 #define LBK_CONNECT_NIXX(a) (0x0 + (a)) 271 272 static void __rvu_lbk_set_chans(struct rvu *rvu, void __iomem *base, 273 u64 offset, int lbkid, u16 chans) 274 { 275 struct rvu_hwinfo *hw = rvu->hw; 276 u64 cfg; 277 278 cfg = readq(base + offset); 279 cfg &= ~(LBK_LINK_CFG_RANGE_MASK | 280 LBK_LINK_CFG_ID_MASK | LBK_LINK_CFG_BASE_MASK); 281 cfg |= FIELD_PREP(LBK_LINK_CFG_RANGE_MASK, ilog2(chans)); 282 cfg |= FIELD_PREP(LBK_LINK_CFG_ID_MASK, lbkid); 283 cfg |= FIELD_PREP(LBK_LINK_CFG_BASE_MASK, hw->lbk_chan_base); 284 285 writeq(cfg, base + offset); 286 } 287 288 static void rvu_lbk_set_channels(struct rvu *rvu) 289 { 290 struct pci_dev *pdev = NULL; 291 void __iomem *base; 292 u64 lbk_const; 293 u8 src, dst; 294 u16 chans; 295 296 /* To loopback packets between multiple NIX blocks 297 * mutliple LBK blocks are needed. With two NIX blocks, 298 * four LBK blocks are needed and each LBK block 299 * source and destination are as follows: 300 * LBK0 - source NIX0 and destination NIX1 301 * LBK1 - source NIX0 and destination NIX1 302 * LBK2 - source NIX1 and destination NIX0 303 * LBK3 - source NIX1 and destination NIX1 304 * As per the HRM channel numbers should be programmed as: 305 * P2X and X2P of LBK0 as same 306 * P2X and X2P of LBK3 as same 307 * P2X of LBK1 and X2P of LBK2 as same 308 * P2X of LBK2 and X2P of LBK1 as same 309 */ 310 while (true) { 311 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 312 PCI_DEVID_OCTEONTX2_LBK, pdev); 313 if (!pdev) 314 return; 315 316 base = pci_ioremap_bar(pdev, 0); 317 if (!base) 318 goto err_put; 319 320 lbk_const = readq(base + LBK_CONST); 321 chans = FIELD_GET(LBK_CONST_CHANS, lbk_const); 322 dst = FIELD_GET(LBK_CONST_DST, lbk_const); 323 src = FIELD_GET(LBK_CONST_SRC, lbk_const); 324 325 if (src == dst) { 326 if (src == LBK_CONNECT_NIXX(0)) { /* LBK0 */ 327 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P, 328 0, chans); 329 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X, 330 0, chans); 331 } else if (src == LBK_CONNECT_NIXX(1)) { /* LBK3 */ 332 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P, 333 1, chans); 334 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X, 335 1, chans); 336 } 337 } else { 338 if (src == LBK_CONNECT_NIXX(0)) { /* LBK1 */ 339 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P, 340 0, chans); 341 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X, 342 1, chans); 343 } else if (src == LBK_CONNECT_NIXX(1)) { /* LBK2 */ 344 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_X2P, 345 1, chans); 346 __rvu_lbk_set_chans(rvu, base, LBK_LINK_CFG_P2X, 347 0, chans); 348 } 349 } 350 iounmap(base); 351 } 352 err_put: 353 pci_dev_put(pdev); 354 } 355 356 static void __rvu_nix_set_channels(struct rvu *rvu, int blkaddr) 357 { 358 u64 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST); 359 u16 cgx_chans, lbk_chans, sdp_chans, cpt_chans; 360 struct rvu_hwinfo *hw = rvu->hw; 361 int link, nix_link = 0; 362 u16 start; 363 u64 cfg; 364 365 cgx_chans = nix_const & 0xFFULL; 366 lbk_chans = (nix_const >> 16) & 0xFFULL; 367 sdp_chans = SDP_CHANNELS; 368 cpt_chans = (nix_const >> 32) & 0xFFFULL; 369 370 start = hw->cgx_chan_base; 371 for (link = 0; link < hw->cgx_links; link++, nix_link++) { 372 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link)); 373 cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK); 374 cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(cgx_chans)); 375 cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start); 376 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg); 377 start += cgx_chans; 378 } 379 380 start = hw->lbk_chan_base; 381 for (link = 0; link < hw->lbk_links; link++, nix_link++) { 382 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link)); 383 cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK); 384 cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(lbk_chans)); 385 cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start); 386 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg); 387 start += lbk_chans; 388 } 389 390 start = hw->sdp_chan_base; 391 for (link = 0; link < hw->sdp_links; link++, nix_link++) { 392 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link)); 393 cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK); 394 cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(sdp_chans)); 395 cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start); 396 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg); 397 start += sdp_chans; 398 } 399 400 start = hw->cpt_chan_base; 401 for (link = 0; link < hw->cpt_links; link++, nix_link++) { 402 cfg = rvu_read64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link)); 403 cfg &= ~(NIX_AF_LINKX_BASE_MASK | NIX_AF_LINKX_RANGE_MASK); 404 cfg |= FIELD_PREP(NIX_AF_LINKX_RANGE_MASK, ilog2(cpt_chans)); 405 cfg |= FIELD_PREP(NIX_AF_LINKX_BASE_MASK, start); 406 rvu_write64(rvu, blkaddr, NIX_AF_LINKX_CFG(nix_link), cfg); 407 start += cpt_chans; 408 } 409 } 410 411 static void rvu_nix_set_channels(struct rvu *rvu) 412 { 413 int blkaddr = 0; 414 415 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 416 while (blkaddr) { 417 __rvu_nix_set_channels(rvu, blkaddr); 418 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); 419 } 420 } 421 422 static void __rvu_rpm_set_channels(int cgxid, int lmacid, u16 base) 423 { 424 u64 cfg; 425 426 cfg = cgx_lmac_read(cgxid, lmacid, RPMX_CMRX_LINK_CFG); 427 cfg &= ~(RPMX_CMRX_LINK_BASE_MASK | RPMX_CMRX_LINK_RANGE_MASK); 428 429 /* There is no read-only constant register to read 430 * the number of channels for LMAC and it is always 16. 431 */ 432 cfg |= FIELD_PREP(RPMX_CMRX_LINK_RANGE_MASK, ilog2(16)); 433 cfg |= FIELD_PREP(RPMX_CMRX_LINK_BASE_MASK, base); 434 cgx_lmac_write(cgxid, lmacid, RPMX_CMRX_LINK_CFG, cfg); 435 } 436 437 static void rvu_rpm_set_channels(struct rvu *rvu) 438 { 439 struct rvu_hwinfo *hw = rvu->hw; 440 u16 base = hw->cgx_chan_base; 441 int cgx, lmac; 442 443 for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++) { 444 for (lmac = 0; lmac < hw->lmac_per_cgx; lmac++) { 445 __rvu_rpm_set_channels(cgx, lmac, base); 446 base += 16; 447 } 448 } 449 } 450 451 void rvu_program_channels(struct rvu *rvu) 452 { 453 struct rvu_hwinfo *hw = rvu->hw; 454 455 if (!hw->cap.programmable_chans) 456 return; 457 458 rvu_nix_set_channels(rvu); 459 rvu_lbk_set_channels(rvu); 460 rvu_rpm_set_channels(rvu); 461 } 462