1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #include <linux/types.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 
12 #include "rvu.h"
13 #include "cgx.h"
14 #include "lmac_common.h"
15 #include "rvu_reg.h"
16 #include "rvu_trace.h"
17 
18 struct cgx_evq_entry {
19 	struct list_head evq_node;
20 	struct cgx_link_event link_event;
21 };
22 
23 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
24 static struct _req_type __maybe_unused					\
25 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid)		\
26 {									\
27 	struct _req_type *req;						\
28 									\
29 	req = (struct _req_type *)otx2_mbox_alloc_msg_rsp(		\
30 		&rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
31 		sizeof(struct _rsp_type));				\
32 	if (!req)							\
33 		return NULL;						\
34 	req->hdr.sig = OTX2_MBOX_REQ_SIG;				\
35 	req->hdr.id = _id;						\
36 	trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req));		\
37 	return req;							\
38 }
39 
40 MBOX_UP_CGX_MESSAGES
41 #undef M
42 
43 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature)
44 {
45 	u8 cgx_id, lmac_id;
46 	void *cgxd;
47 
48 	if (!is_pf_cgxmapped(rvu, pf))
49 		return 0;
50 
51 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
52 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
53 
54 	return  (cgx_features_get(cgxd) & feature);
55 }
56 
57 /* Returns bitmap of mapped PFs */
58 static u16 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id)
59 {
60 	return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id];
61 }
62 
63 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id)
64 {
65 	unsigned long pfmap;
66 
67 	pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id);
68 
69 	/* Assumes only one pf mapped to a cgx lmac port */
70 	if (!pfmap)
71 		return -ENODEV;
72 	else
73 		return find_first_bit(&pfmap, 16);
74 }
75 
76 static u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
77 {
78 	return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);
79 }
80 
81 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
82 {
83 	if (cgx_id >= rvu->cgx_cnt_max)
84 		return NULL;
85 
86 	return rvu->cgx_idmap[cgx_id];
87 }
88 
89 /* Return first enabled CGX instance if none are enabled then return NULL */
90 void *rvu_first_cgx_pdata(struct rvu *rvu)
91 {
92 	int first_enabled_cgx = 0;
93 	void *cgxd = NULL;
94 
95 	for (; first_enabled_cgx < rvu->cgx_cnt_max; first_enabled_cgx++) {
96 		cgxd = rvu_cgx_pdata(first_enabled_cgx, rvu);
97 		if (cgxd)
98 			break;
99 	}
100 
101 	return cgxd;
102 }
103 
104 /* Based on P2X connectivity find mapped NIX block for a PF */
105 static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf,
106 				  int cgx_id, int lmac_id)
107 {
108 	struct rvu_pfvf *pfvf = &rvu->pf[pf];
109 	u8 p2x;
110 
111 	p2x = cgx_lmac_get_p2x(cgx_id, lmac_id);
112 	/* Firmware sets P2X_SELECT as either NIX0 or NIX1 */
113 	pfvf->nix_blkaddr = BLKADDR_NIX0;
114 	if (p2x == CMR_P2X_SEL_NIX1)
115 		pfvf->nix_blkaddr = BLKADDR_NIX1;
116 }
117 
118 static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
119 {
120 	struct npc_pkind *pkind = &rvu->hw->pkind;
121 	int cgx_cnt_max = rvu->cgx_cnt_max;
122 	int pf = PF_CGXMAP_BASE;
123 	unsigned long lmac_bmap;
124 	int size, free_pkind;
125 	int cgx, lmac, iter;
126 	int numvfs, hwvfs;
127 
128 	if (!cgx_cnt_max)
129 		return 0;
130 
131 	if (cgx_cnt_max > 0xF || MAX_LMAC_PER_CGX > 0xF)
132 		return -EINVAL;
133 
134 	/* Alloc map table
135 	 * An additional entry is required since PF id starts from 1 and
136 	 * hence entry at offset 0 is invalid.
137 	 */
138 	size = (cgx_cnt_max * MAX_LMAC_PER_CGX + 1) * sizeof(u8);
139 	rvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL);
140 	if (!rvu->pf2cgxlmac_map)
141 		return -ENOMEM;
142 
143 	/* Initialize all entries with an invalid cgx and lmac id */
144 	memset(rvu->pf2cgxlmac_map, 0xFF, size);
145 
146 	/* Reverse map table */
147 	rvu->cgxlmac2pf_map = devm_kzalloc(rvu->dev,
148 				  cgx_cnt_max * MAX_LMAC_PER_CGX * sizeof(u16),
149 				  GFP_KERNEL);
150 	if (!rvu->cgxlmac2pf_map)
151 		return -ENOMEM;
152 
153 	rvu->cgx_mapped_pfs = 0;
154 	for (cgx = 0; cgx < cgx_cnt_max; cgx++) {
155 		if (!rvu_cgx_pdata(cgx, rvu))
156 			continue;
157 		lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu));
158 		for_each_set_bit(iter, &lmac_bmap, MAX_LMAC_PER_CGX) {
159 			lmac = cgx_get_lmacid(rvu_cgx_pdata(cgx, rvu),
160 					      iter);
161 			rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);
162 			rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;
163 			free_pkind = rvu_alloc_rsrc(&pkind->rsrc);
164 			pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16;
165 			rvu_map_cgx_nix_block(rvu, pf, cgx, lmac);
166 			rvu->cgx_mapped_pfs++;
167 			rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvfs);
168 			rvu->cgx_mapped_vfs += numvfs;
169 			pf++;
170 		}
171 	}
172 	return 0;
173 }
174 
175 static int rvu_cgx_send_link_info(int cgx_id, int lmac_id, struct rvu *rvu)
176 {
177 	struct cgx_evq_entry *qentry;
178 	unsigned long flags;
179 	int err;
180 
181 	qentry = kmalloc(sizeof(*qentry), GFP_KERNEL);
182 	if (!qentry)
183 		return -ENOMEM;
184 
185 	/* Lock the event queue before we read the local link status */
186 	spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
187 	err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
188 				&qentry->link_event.link_uinfo);
189 	qentry->link_event.cgx_id = cgx_id;
190 	qentry->link_event.lmac_id = lmac_id;
191 	if (err) {
192 		kfree(qentry);
193 		goto skip_add;
194 	}
195 	list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
196 skip_add:
197 	spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
198 
199 	/* start worker to process the events */
200 	queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
201 
202 	return 0;
203 }
204 
205 /* This is called from interrupt context and is expected to be atomic */
206 static int cgx_lmac_postevent(struct cgx_link_event *event, void *data)
207 {
208 	struct cgx_evq_entry *qentry;
209 	struct rvu *rvu = data;
210 
211 	/* post event to the event queue */
212 	qentry = kmalloc(sizeof(*qentry), GFP_ATOMIC);
213 	if (!qentry)
214 		return -ENOMEM;
215 	qentry->link_event = *event;
216 	spin_lock(&rvu->cgx_evq_lock);
217 	list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
218 	spin_unlock(&rvu->cgx_evq_lock);
219 
220 	/* start worker to process the events */
221 	queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
222 
223 	return 0;
224 }
225 
226 static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu)
227 {
228 	struct cgx_link_user_info *linfo;
229 	struct cgx_link_info_msg *msg;
230 	unsigned long pfmap;
231 	int err, pfid;
232 
233 	linfo = &event->link_uinfo;
234 	pfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id);
235 
236 	do {
237 		pfid = find_first_bit(&pfmap, 16);
238 		clear_bit(pfid, &pfmap);
239 
240 		/* check if notification is enabled */
241 		if (!test_bit(pfid, &rvu->pf_notify_bmap)) {
242 			dev_info(rvu->dev, "cgx %d: lmac %d Link status %s\n",
243 				 event->cgx_id, event->lmac_id,
244 				 linfo->link_up ? "UP" : "DOWN");
245 			continue;
246 		}
247 
248 		/* Send mbox message to PF */
249 		msg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid);
250 		if (!msg)
251 			continue;
252 		msg->link_info = *linfo;
253 		otx2_mbox_msg_send(&rvu->afpf_wq_info.mbox_up, pfid);
254 		err = otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, pfid);
255 		if (err)
256 			dev_warn(rvu->dev, "notification to pf %d failed\n",
257 				 pfid);
258 	} while (pfmap);
259 }
260 
261 static void cgx_evhandler_task(struct work_struct *work)
262 {
263 	struct rvu *rvu = container_of(work, struct rvu, cgx_evh_work);
264 	struct cgx_evq_entry *qentry;
265 	struct cgx_link_event *event;
266 	unsigned long flags;
267 
268 	do {
269 		/* Dequeue an event */
270 		spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
271 		qentry = list_first_entry_or_null(&rvu->cgx_evq_head,
272 						  struct cgx_evq_entry,
273 						  evq_node);
274 		if (qentry)
275 			list_del(&qentry->evq_node);
276 		spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
277 		if (!qentry)
278 			break; /* nothing more to process */
279 
280 		event = &qentry->link_event;
281 
282 		/* process event */
283 		cgx_notify_pfs(event, rvu);
284 		kfree(qentry);
285 	} while (1);
286 }
287 
288 static int cgx_lmac_event_handler_init(struct rvu *rvu)
289 {
290 	unsigned long lmac_bmap;
291 	struct cgx_event_cb cb;
292 	int cgx, lmac, err;
293 	void *cgxd;
294 
295 	spin_lock_init(&rvu->cgx_evq_lock);
296 	INIT_LIST_HEAD(&rvu->cgx_evq_head);
297 	INIT_WORK(&rvu->cgx_evh_work, cgx_evhandler_task);
298 	rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0);
299 	if (!rvu->cgx_evh_wq) {
300 		dev_err(rvu->dev, "alloc workqueue failed");
301 		return -ENOMEM;
302 	}
303 
304 	cb.notify_link_chg = cgx_lmac_postevent; /* link change call back */
305 	cb.data = rvu;
306 
307 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
308 		cgxd = rvu_cgx_pdata(cgx, rvu);
309 		if (!cgxd)
310 			continue;
311 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
312 		for_each_set_bit(lmac, &lmac_bmap, MAX_LMAC_PER_CGX) {
313 			err = cgx_lmac_evh_register(&cb, cgxd, lmac);
314 			if (err)
315 				dev_err(rvu->dev,
316 					"%d:%d handler register failed\n",
317 					cgx, lmac);
318 		}
319 	}
320 
321 	return 0;
322 }
323 
324 static void rvu_cgx_wq_destroy(struct rvu *rvu)
325 {
326 	if (rvu->cgx_evh_wq) {
327 		flush_workqueue(rvu->cgx_evh_wq);
328 		destroy_workqueue(rvu->cgx_evh_wq);
329 		rvu->cgx_evh_wq = NULL;
330 	}
331 }
332 
333 int rvu_cgx_init(struct rvu *rvu)
334 {
335 	int cgx, err;
336 	void *cgxd;
337 
338 	/* CGX port id starts from 0 and are not necessarily contiguous
339 	 * Hence we allocate resources based on the maximum port id value.
340 	 */
341 	rvu->cgx_cnt_max = cgx_get_cgxcnt_max();
342 	if (!rvu->cgx_cnt_max) {
343 		dev_info(rvu->dev, "No CGX devices found!\n");
344 		return -ENODEV;
345 	}
346 
347 	rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt_max *
348 				      sizeof(void *), GFP_KERNEL);
349 	if (!rvu->cgx_idmap)
350 		return -ENOMEM;
351 
352 	/* Initialize the cgxdata table */
353 	for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++)
354 		rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx);
355 
356 	/* Map CGX LMAC interfaces to RVU PFs */
357 	err = rvu_map_cgx_lmac_pf(rvu);
358 	if (err)
359 		return err;
360 
361 	/* Register for CGX events */
362 	err = cgx_lmac_event_handler_init(rvu);
363 	if (err)
364 		return err;
365 
366 	mutex_init(&rvu->cgx_cfg_lock);
367 
368 	/* Ensure event handler registration is completed, before
369 	 * we turn on the links
370 	 */
371 	mb();
372 
373 	/* Do link up for all CGX ports */
374 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
375 		cgxd = rvu_cgx_pdata(cgx, rvu);
376 		if (!cgxd)
377 			continue;
378 		err = cgx_lmac_linkup_start(cgxd);
379 		if (err)
380 			dev_err(rvu->dev,
381 				"Link up process failed to start on cgx %d\n",
382 				cgx);
383 	}
384 
385 	return 0;
386 }
387 
388 int rvu_cgx_exit(struct rvu *rvu)
389 {
390 	unsigned long lmac_bmap;
391 	int cgx, lmac;
392 	void *cgxd;
393 
394 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
395 		cgxd = rvu_cgx_pdata(cgx, rvu);
396 		if (!cgxd)
397 			continue;
398 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
399 		for_each_set_bit(lmac, &lmac_bmap, MAX_LMAC_PER_CGX)
400 			cgx_lmac_evh_unregister(cgxd, lmac);
401 	}
402 
403 	/* Ensure event handler unregister is completed */
404 	mb();
405 
406 	rvu_cgx_wq_destroy(rvu);
407 	return 0;
408 }
409 
410 /* Most of the CGX configuration is restricted to the mapped PF only,
411  * VF's of mapped PF and other PFs are not allowed. This fn() checks
412  * whether a PFFUNC is permitted to do the config or not.
413  */
414 inline bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc)
415 {
416 	if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
417 	    !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
418 		return false;
419 	return true;
420 }
421 
422 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable)
423 {
424 	struct mac_ops *mac_ops;
425 	u8 cgx_id, lmac_id;
426 	void *cgxd;
427 
428 	if (!is_pf_cgxmapped(rvu, pf))
429 		return;
430 
431 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
432 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
433 
434 	mac_ops = get_mac_ops(cgxd);
435 	/* Set / clear CTL_BCK to control pause frame forwarding to NIX */
436 	if (enable)
437 		mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, true);
438 	else
439 		mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, false);
440 }
441 
442 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start)
443 {
444 	int pf = rvu_get_pf(pcifunc);
445 	u8 cgx_id, lmac_id;
446 
447 	if (!is_cgx_config_permitted(rvu, pcifunc))
448 		return LMAC_AF_ERR_PERM_DENIED;
449 
450 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
451 
452 	cgx_lmac_rx_tx_enable(rvu_cgx_pdata(cgx_id, rvu), lmac_id, start);
453 
454 	return 0;
455 }
456 
457 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc)
458 {
459 	int pf = rvu_get_pf(pcifunc);
460 	int i = 0, lmac_count = 0;
461 	u8 max_dmac_filters;
462 	u8 cgx_id, lmac_id;
463 	void *cgx_dev;
464 
465 	if (!is_cgx_config_permitted(rvu, pcifunc))
466 		return;
467 
468 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
469 	cgx_dev = cgx_get_pdata(cgx_id);
470 	lmac_count = cgx_get_lmac_cnt(cgx_dev);
471 	max_dmac_filters = MAX_DMAC_ENTRIES_PER_CGX / lmac_count;
472 
473 	for (i = 0; i < max_dmac_filters; i++)
474 		cgx_lmac_addr_del(cgx_id, lmac_id, i);
475 
476 	/* As cgx_lmac_addr_del does not clear entry for index 0
477 	 * so it needs to be done explicitly
478 	 */
479 	cgx_lmac_addr_reset(cgx_id, lmac_id);
480 }
481 
482 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req,
483 				    struct msg_rsp *rsp)
484 {
485 	rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, true);
486 	return 0;
487 }
488 
489 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req,
490 				   struct msg_rsp *rsp)
491 {
492 	rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false);
493 	return 0;
494 }
495 
496 static int rvu_lmac_get_stats(struct rvu *rvu, struct msg_req *req,
497 			      void *rsp)
498 {
499 	int pf = rvu_get_pf(req->hdr.pcifunc);
500 	struct mac_ops *mac_ops;
501 	int stat = 0, err = 0;
502 	u64 tx_stat, rx_stat;
503 	u8 cgx_idx, lmac;
504 	void *cgxd;
505 
506 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
507 		return LMAC_AF_ERR_PERM_DENIED;
508 
509 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
510 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
511 	mac_ops = get_mac_ops(cgxd);
512 
513 	/* Rx stats */
514 	while (stat < mac_ops->rx_stats_cnt) {
515 		err = mac_ops->mac_get_rx_stats(cgxd, lmac, stat, &rx_stat);
516 		if (err)
517 			return err;
518 		if (mac_ops->rx_stats_cnt == RPM_RX_STATS_COUNT)
519 			((struct rpm_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
520 		else
521 			((struct cgx_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
522 		stat++;
523 	}
524 
525 	/* Tx stats */
526 	stat = 0;
527 	while (stat < mac_ops->tx_stats_cnt) {
528 		err = mac_ops->mac_get_tx_stats(cgxd, lmac, stat, &tx_stat);
529 		if (err)
530 			return err;
531 		if (mac_ops->tx_stats_cnt == RPM_TX_STATS_COUNT)
532 			((struct rpm_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
533 		else
534 			((struct cgx_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
535 		stat++;
536 	}
537 	return 0;
538 }
539 
540 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req,
541 			       struct cgx_stats_rsp *rsp)
542 {
543 	return rvu_lmac_get_stats(rvu, req, (void *)rsp);
544 }
545 
546 int rvu_mbox_handler_rpm_stats(struct rvu *rvu, struct msg_req *req,
547 			       struct rpm_stats_rsp *rsp)
548 {
549 	return rvu_lmac_get_stats(rvu, req, (void *)rsp);
550 }
551 
552 int rvu_mbox_handler_cgx_fec_stats(struct rvu *rvu,
553 				   struct msg_req *req,
554 				   struct cgx_fec_stats_rsp *rsp)
555 {
556 	int pf = rvu_get_pf(req->hdr.pcifunc);
557 	u8 cgx_idx, lmac;
558 	void *cgxd;
559 
560 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
561 		return LMAC_AF_ERR_PERM_DENIED;
562 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
563 
564 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
565 	return cgx_get_fec_stats(cgxd, lmac, rsp);
566 }
567 
568 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu,
569 				      struct cgx_mac_addr_set_or_get *req,
570 				      struct cgx_mac_addr_set_or_get *rsp)
571 {
572 	int pf = rvu_get_pf(req->hdr.pcifunc);
573 	u8 cgx_id, lmac_id;
574 
575 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
576 		return -EPERM;
577 
578 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
579 
580 	cgx_lmac_addr_set(cgx_id, lmac_id, req->mac_addr);
581 
582 	return 0;
583 }
584 
585 int rvu_mbox_handler_cgx_mac_addr_add(struct rvu *rvu,
586 				      struct cgx_mac_addr_add_req *req,
587 				      struct cgx_mac_addr_add_rsp *rsp)
588 {
589 	int pf = rvu_get_pf(req->hdr.pcifunc);
590 	u8 cgx_id, lmac_id;
591 	int rc = 0;
592 
593 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
594 		return -EPERM;
595 
596 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
597 	rc = cgx_lmac_addr_add(cgx_id, lmac_id, req->mac_addr);
598 	if (rc >= 0) {
599 		rsp->index = rc;
600 		return 0;
601 	}
602 
603 	return rc;
604 }
605 
606 int rvu_mbox_handler_cgx_mac_addr_del(struct rvu *rvu,
607 				      struct cgx_mac_addr_del_req *req,
608 				      struct msg_rsp *rsp)
609 {
610 	int pf = rvu_get_pf(req->hdr.pcifunc);
611 	u8 cgx_id, lmac_id;
612 
613 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
614 		return -EPERM;
615 
616 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
617 	return cgx_lmac_addr_del(cgx_id, lmac_id, req->index);
618 }
619 
620 int rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu *rvu,
621 					     struct msg_req *req,
622 					     struct cgx_max_dmac_entries_get_rsp
623 					     *rsp)
624 {
625 	int pf = rvu_get_pf(req->hdr.pcifunc);
626 	u8 cgx_id, lmac_id;
627 
628 	/* If msg is received from PFs(which are not mapped to CGX LMACs)
629 	 * or VF then no entries are allocated for DMAC filters at CGX level.
630 	 * So returning zero.
631 	 */
632 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) {
633 		rsp->max_dmac_filters = 0;
634 		return 0;
635 	}
636 
637 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
638 	rsp->max_dmac_filters = cgx_lmac_addr_max_entries_get(cgx_id, lmac_id);
639 	return 0;
640 }
641 
642 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu,
643 				      struct cgx_mac_addr_set_or_get *req,
644 				      struct cgx_mac_addr_set_or_get *rsp)
645 {
646 	int pf = rvu_get_pf(req->hdr.pcifunc);
647 	u8 cgx_id, lmac_id;
648 	int rc = 0, i;
649 	u64 cfg;
650 
651 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
652 		return -EPERM;
653 
654 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
655 
656 	rsp->hdr.rc = rc;
657 	cfg = cgx_lmac_addr_get(cgx_id, lmac_id);
658 	/* copy 48 bit mac address to req->mac_addr */
659 	for (i = 0; i < ETH_ALEN; i++)
660 		rsp->mac_addr[i] = cfg >> (ETH_ALEN - 1 - i) * 8;
661 	return 0;
662 }
663 
664 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req,
665 					struct msg_rsp *rsp)
666 {
667 	u16 pcifunc = req->hdr.pcifunc;
668 	int pf = rvu_get_pf(pcifunc);
669 	u8 cgx_id, lmac_id;
670 
671 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
672 		return -EPERM;
673 
674 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
675 
676 	cgx_lmac_promisc_config(cgx_id, lmac_id, true);
677 	return 0;
678 }
679 
680 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req,
681 					 struct msg_rsp *rsp)
682 {
683 	int pf = rvu_get_pf(req->hdr.pcifunc);
684 	u8 cgx_id, lmac_id;
685 
686 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
687 		return -EPERM;
688 
689 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
690 
691 	cgx_lmac_promisc_config(cgx_id, lmac_id, false);
692 	return 0;
693 }
694 
695 static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcifunc, bool enable)
696 {
697 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
698 	int pf = rvu_get_pf(pcifunc);
699 	struct mac_ops *mac_ops;
700 	u8 cgx_id, lmac_id;
701 	void *cgxd;
702 
703 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP))
704 		return 0;
705 
706 	/* This msg is expected only from PFs that are mapped to CGX LMACs,
707 	 * if received from other PF/VF simply ACK, nothing to do.
708 	 */
709 	if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
710 	    !is_pf_cgxmapped(rvu, pf))
711 		return -ENODEV;
712 
713 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
714 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
715 
716 	mac_ops = get_mac_ops(cgxd);
717 	mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, true);
718 	/* If PTP is enabled then inform NPC that packets to be
719 	 * parsed by this PF will have their data shifted by 8 bytes
720 	 * and if PTP is disabled then no shift is required
721 	 */
722 	if (npc_config_ts_kpuaction(rvu, pf, pcifunc, enable))
723 		return -EINVAL;
724 	/* This flag is required to clean up CGX conf if app gets killed */
725 	pfvf->hw_rx_tstamp_en = enable;
726 
727 	return 0;
728 }
729 
730 int rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu *rvu, struct msg_req *req,
731 				       struct msg_rsp *rsp)
732 {
733 	if (!is_pf_cgxmapped(rvu, rvu_get_pf(req->hdr.pcifunc)))
734 		return -EPERM;
735 
736 	return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, true);
737 }
738 
739 int rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu *rvu, struct msg_req *req,
740 					struct msg_rsp *rsp)
741 {
742 	return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, false);
743 }
744 
745 static int rvu_cgx_config_linkevents(struct rvu *rvu, u16 pcifunc, bool en)
746 {
747 	int pf = rvu_get_pf(pcifunc);
748 	u8 cgx_id, lmac_id;
749 
750 	if (!is_cgx_config_permitted(rvu, pcifunc))
751 		return -EPERM;
752 
753 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
754 
755 	if (en) {
756 		set_bit(pf, &rvu->pf_notify_bmap);
757 		/* Send the current link status to PF */
758 		rvu_cgx_send_link_info(cgx_id, lmac_id, rvu);
759 	} else {
760 		clear_bit(pf, &rvu->pf_notify_bmap);
761 	}
762 
763 	return 0;
764 }
765 
766 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req,
767 					  struct msg_rsp *rsp)
768 {
769 	rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, true);
770 	return 0;
771 }
772 
773 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req,
774 					 struct msg_rsp *rsp)
775 {
776 	rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, false);
777 	return 0;
778 }
779 
780 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req,
781 				      struct cgx_link_info_msg *rsp)
782 {
783 	u8 cgx_id, lmac_id;
784 	int pf, err;
785 
786 	pf = rvu_get_pf(req->hdr.pcifunc);
787 
788 	if (!is_pf_cgxmapped(rvu, pf))
789 		return -ENODEV;
790 
791 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
792 
793 	err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
794 				&rsp->link_info);
795 	return err;
796 }
797 
798 int rvu_mbox_handler_cgx_features_get(struct rvu *rvu,
799 				      struct msg_req *req,
800 				      struct cgx_features_info_msg *rsp)
801 {
802 	int pf = rvu_get_pf(req->hdr.pcifunc);
803 	u8 cgx_idx, lmac;
804 	void *cgxd;
805 
806 	if (!is_pf_cgxmapped(rvu, pf))
807 		return 0;
808 
809 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
810 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
811 	rsp->lmac_features = cgx_features_get(cgxd);
812 
813 	return 0;
814 }
815 
816 u32 rvu_cgx_get_fifolen(struct rvu *rvu)
817 {
818 	struct mac_ops *mac_ops;
819 	u32 fifo_len;
820 
821 	mac_ops = get_mac_ops(rvu_first_cgx_pdata(rvu));
822 	fifo_len = mac_ops ? mac_ops->fifo_len : 0;
823 
824 	return fifo_len;
825 }
826 
827 static int rvu_cgx_config_intlbk(struct rvu *rvu, u16 pcifunc, bool en)
828 {
829 	int pf = rvu_get_pf(pcifunc);
830 	struct mac_ops *mac_ops;
831 	u8 cgx_id, lmac_id;
832 
833 	if (!is_cgx_config_permitted(rvu, pcifunc))
834 		return -EPERM;
835 
836 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
837 	mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu));
838 
839 	return mac_ops->mac_lmac_intl_lbk(rvu_cgx_pdata(cgx_id, rvu),
840 					  lmac_id, en);
841 }
842 
843 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req,
844 				       struct msg_rsp *rsp)
845 {
846 	rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, true);
847 	return 0;
848 }
849 
850 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req,
851 					struct msg_rsp *rsp)
852 {
853 	rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, false);
854 	return 0;
855 }
856 
857 int rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu *rvu,
858 				       struct cgx_pause_frm_cfg *req,
859 				       struct cgx_pause_frm_cfg *rsp)
860 {
861 	int pf = rvu_get_pf(req->hdr.pcifunc);
862 	struct mac_ops *mac_ops;
863 	u8 cgx_id, lmac_id;
864 	void *cgxd;
865 
866 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_FC))
867 		return 0;
868 
869 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
870 	 * if received from other PF/VF simply ACK, nothing to do.
871 	 */
872 	if (!is_pf_cgxmapped(rvu, pf))
873 		return -ENODEV;
874 
875 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
876 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
877 	mac_ops = get_mac_ops(cgxd);
878 
879 	if (req->set)
880 		mac_ops->mac_enadis_pause_frm(cgxd, lmac_id,
881 					      req->tx_pause, req->rx_pause);
882 	else
883 		mac_ops->mac_get_pause_frm_status(cgxd, lmac_id,
884 						  &rsp->tx_pause,
885 						  &rsp->rx_pause);
886 	return 0;
887 }
888 
889 int rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu *rvu, struct msg_req *req,
890 					   struct msg_rsp *rsp)
891 {
892 	int pf = rvu_get_pf(req->hdr.pcifunc);
893 	u8 cgx_id, lmac_id;
894 
895 	if (!is_pf_cgxmapped(rvu, pf))
896 		return LMAC_AF_ERR_PF_NOT_MAPPED;
897 
898 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
899 	return cgx_get_phy_fec_stats(rvu_cgx_pdata(cgx_id, rvu), lmac_id);
900 }
901 
902 /* Finds cumulative status of NIX rx/tx counters from LF of a PF and those
903  * from its VFs as well. ie. NIX rx/tx counters at the CGX port level
904  */
905 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id,
906 			   int index, int rxtxflag, u64 *stat)
907 {
908 	struct rvu_block *block;
909 	int blkaddr;
910 	u16 pcifunc;
911 	int pf, lf;
912 
913 	*stat = 0;
914 
915 	if (!cgxd || !rvu)
916 		return -EINVAL;
917 
918 	pf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id);
919 	if (pf < 0)
920 		return pf;
921 
922 	/* Assumes LF of a PF and all of its VF belongs to the same
923 	 * NIX block
924 	 */
925 	pcifunc = pf << RVU_PFVF_PF_SHIFT;
926 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
927 	if (blkaddr < 0)
928 		return 0;
929 	block = &rvu->hw->block[blkaddr];
930 
931 	for (lf = 0; lf < block->lf.max; lf++) {
932 		/* Check if a lf is attached to this PF or one of its VFs */
933 		if (!((block->fn_map[lf] & ~RVU_PFVF_FUNC_MASK) == (pcifunc &
934 			 ~RVU_PFVF_FUNC_MASK)))
935 			continue;
936 		if (rxtxflag == NIX_STATS_RX)
937 			*stat += rvu_read64(rvu, blkaddr,
938 					    NIX_AF_LFX_RX_STATX(lf, index));
939 		else
940 			*stat += rvu_read64(rvu, blkaddr,
941 					    NIX_AF_LFX_TX_STATX(lf, index));
942 	}
943 
944 	return 0;
945 }
946 
947 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start)
948 {
949 	struct rvu_pfvf *parent_pf, *pfvf;
950 	int cgx_users, err = 0;
951 
952 	if (!is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
953 		return 0;
954 
955 	parent_pf = &rvu->pf[rvu_get_pf(pcifunc)];
956 	pfvf = rvu_get_pfvf(rvu, pcifunc);
957 
958 	mutex_lock(&rvu->cgx_cfg_lock);
959 
960 	if (start && pfvf->cgx_in_use)
961 		goto exit;  /* CGX is already started hence nothing to do */
962 	if (!start && !pfvf->cgx_in_use)
963 		goto exit; /* CGX is already stopped hence nothing to do */
964 
965 	if (start) {
966 		cgx_users = parent_pf->cgx_users;
967 		parent_pf->cgx_users++;
968 	} else {
969 		parent_pf->cgx_users--;
970 		cgx_users = parent_pf->cgx_users;
971 	}
972 
973 	/* Start CGX when first of all NIXLFs is started.
974 	 * Stop CGX when last of all NIXLFs is stopped.
975 	 */
976 	if (!cgx_users) {
977 		err = rvu_cgx_config_rxtx(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK,
978 					  start);
979 		if (err) {
980 			dev_err(rvu->dev, "Unable to %s CGX\n",
981 				start ? "start" : "stop");
982 			/* Revert the usage count in case of error */
983 			parent_pf->cgx_users = start ? parent_pf->cgx_users  - 1
984 					       : parent_pf->cgx_users  + 1;
985 			goto exit;
986 		}
987 	}
988 	pfvf->cgx_in_use = start;
989 exit:
990 	mutex_unlock(&rvu->cgx_cfg_lock);
991 	return err;
992 }
993 
994 int rvu_mbox_handler_cgx_set_fec_param(struct rvu *rvu,
995 				       struct fec_mode *req,
996 				       struct fec_mode *rsp)
997 {
998 	int pf = rvu_get_pf(req->hdr.pcifunc);
999 	u8 cgx_id, lmac_id;
1000 
1001 	if (!is_pf_cgxmapped(rvu, pf))
1002 		return -EPERM;
1003 
1004 	if (req->fec == OTX2_FEC_OFF)
1005 		req->fec = OTX2_FEC_NONE;
1006 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1007 	rsp->fec = cgx_set_fec(req->fec, cgx_id, lmac_id);
1008 	return 0;
1009 }
1010 
1011 int rvu_mbox_handler_cgx_get_aux_link_info(struct rvu *rvu, struct msg_req *req,
1012 					   struct cgx_fw_data *rsp)
1013 {
1014 	int pf = rvu_get_pf(req->hdr.pcifunc);
1015 	u8 cgx_id, lmac_id;
1016 
1017 	if (!rvu->fwdata)
1018 		return -ENXIO;
1019 
1020 	if (!is_pf_cgxmapped(rvu, pf))
1021 		return -EPERM;
1022 
1023 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1024 
1025 	memcpy(&rsp->fwdata, &rvu->fwdata->cgx_fw_data[cgx_id][lmac_id],
1026 	       sizeof(struct cgx_lmac_fwdata_s));
1027 	return 0;
1028 }
1029 
1030 int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu,
1031 				       struct cgx_set_link_mode_req *req,
1032 				       struct cgx_set_link_mode_rsp *rsp)
1033 {
1034 	int pf = rvu_get_pf(req->hdr.pcifunc);
1035 	u8 cgx_idx, lmac;
1036 	void *cgxd;
1037 
1038 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1039 		return -EPERM;
1040 
1041 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
1042 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
1043 	rsp->status = cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac);
1044 	return 0;
1045 }
1046 
1047 int rvu_mbox_handler_cgx_mac_addr_reset(struct rvu *rvu, struct msg_req *req,
1048 					struct msg_rsp *rsp)
1049 {
1050 	int pf = rvu_get_pf(req->hdr.pcifunc);
1051 	u8 cgx_id, lmac_id;
1052 
1053 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1054 		return LMAC_AF_ERR_PERM_DENIED;
1055 
1056 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1057 	return cgx_lmac_addr_reset(cgx_id, lmac_id);
1058 }
1059 
1060 int rvu_mbox_handler_cgx_mac_addr_update(struct rvu *rvu,
1061 					 struct cgx_mac_addr_update_req *req,
1062 					 struct msg_rsp *rsp)
1063 {
1064 	int pf = rvu_get_pf(req->hdr.pcifunc);
1065 	u8 cgx_id, lmac_id;
1066 
1067 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1068 		return LMAC_AF_ERR_PERM_DENIED;
1069 
1070 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1071 	return cgx_lmac_addr_update(cgx_id, lmac_id, req->mac_addr, req->index);
1072 }
1073