1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/types.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 12 #include "rvu.h" 13 #include "cgx.h" 14 #include "lmac_common.h" 15 #include "rvu_reg.h" 16 #include "rvu_trace.h" 17 #include "rvu_npc_hash.h" 18 19 struct cgx_evq_entry { 20 struct list_head evq_node; 21 struct cgx_link_event link_event; 22 }; 23 24 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 25 static struct _req_type __maybe_unused \ 26 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \ 27 { \ 28 struct _req_type *req; \ 29 \ 30 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 31 &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \ 32 sizeof(struct _rsp_type)); \ 33 if (!req) \ 34 return NULL; \ 35 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 36 req->hdr.id = _id; \ 37 trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req)); \ 38 return req; \ 39 } 40 41 MBOX_UP_CGX_MESSAGES 42 #undef M 43 44 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature) 45 { 46 u8 cgx_id, lmac_id; 47 void *cgxd; 48 49 if (!is_pf_cgxmapped(rvu, pf)) 50 return 0; 51 52 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 53 cgxd = rvu_cgx_pdata(cgx_id, rvu); 54 55 return (cgx_features_get(cgxd) & feature); 56 } 57 58 #define CGX_OFFSET(x) ((x) * rvu->hw->lmac_per_cgx) 59 /* Returns bitmap of mapped PFs */ 60 static u64 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id) 61 { 62 return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id]; 63 } 64 65 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id) 66 { 67 unsigned long pfmap; 68 69 pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id); 70 71 /* Assumes only one pf mapped to a cgx lmac port */ 72 if (!pfmap) 73 return -ENODEV; 74 else 75 return find_first_bit(&pfmap, 76 rvu->cgx_cnt_max * rvu->hw->lmac_per_cgx); 77 } 78 79 static u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id) 80 { 81 return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF); 82 } 83 84 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu) 85 { 86 if (cgx_id >= rvu->cgx_cnt_max) 87 return NULL; 88 89 return rvu->cgx_idmap[cgx_id]; 90 } 91 92 /* Return first enabled CGX instance if none are enabled then return NULL */ 93 void *rvu_first_cgx_pdata(struct rvu *rvu) 94 { 95 int first_enabled_cgx = 0; 96 void *cgxd = NULL; 97 98 for (; first_enabled_cgx < rvu->cgx_cnt_max; first_enabled_cgx++) { 99 cgxd = rvu_cgx_pdata(first_enabled_cgx, rvu); 100 if (cgxd) 101 break; 102 } 103 104 return cgxd; 105 } 106 107 /* Based on P2X connectivity find mapped NIX block for a PF */ 108 static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf, 109 int cgx_id, int lmac_id) 110 { 111 struct rvu_pfvf *pfvf = &rvu->pf[pf]; 112 u8 p2x; 113 114 p2x = cgx_lmac_get_p2x(cgx_id, lmac_id); 115 /* Firmware sets P2X_SELECT as either NIX0 or NIX1 */ 116 pfvf->nix_blkaddr = BLKADDR_NIX0; 117 if (is_rvu_supports_nix1(rvu) && p2x == CMR_P2X_SEL_NIX1) 118 pfvf->nix_blkaddr = BLKADDR_NIX1; 119 } 120 121 static int rvu_map_cgx_lmac_pf(struct rvu *rvu) 122 { 123 struct npc_pkind *pkind = &rvu->hw->pkind; 124 int cgx_cnt_max = rvu->cgx_cnt_max; 125 int pf = PF_CGXMAP_BASE; 126 unsigned long lmac_bmap; 127 int size, free_pkind; 128 int cgx, lmac, iter; 129 int numvfs, hwvfs; 130 131 if (!cgx_cnt_max) 132 return 0; 133 134 if (cgx_cnt_max > 0xF || rvu->hw->lmac_per_cgx > 0xF) 135 return -EINVAL; 136 137 /* Alloc map table 138 * An additional entry is required since PF id starts from 1 and 139 * hence entry at offset 0 is invalid. 140 */ 141 size = (cgx_cnt_max * rvu->hw->lmac_per_cgx + 1) * sizeof(u8); 142 rvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL); 143 if (!rvu->pf2cgxlmac_map) 144 return -ENOMEM; 145 146 /* Initialize all entries with an invalid cgx and lmac id */ 147 memset(rvu->pf2cgxlmac_map, 0xFF, size); 148 149 /* Reverse map table */ 150 rvu->cgxlmac2pf_map = 151 devm_kzalloc(rvu->dev, 152 cgx_cnt_max * rvu->hw->lmac_per_cgx * sizeof(u64), 153 GFP_KERNEL); 154 if (!rvu->cgxlmac2pf_map) 155 return -ENOMEM; 156 157 rvu->cgx_mapped_pfs = 0; 158 for (cgx = 0; cgx < cgx_cnt_max; cgx++) { 159 if (!rvu_cgx_pdata(cgx, rvu)) 160 continue; 161 lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu)); 162 for_each_set_bit(iter, &lmac_bmap, rvu->hw->lmac_per_cgx) { 163 lmac = cgx_get_lmacid(rvu_cgx_pdata(cgx, rvu), 164 iter); 165 rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac); 166 rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf; 167 free_pkind = rvu_alloc_rsrc(&pkind->rsrc); 168 pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16; 169 rvu_map_cgx_nix_block(rvu, pf, cgx, lmac); 170 rvu->cgx_mapped_pfs++; 171 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvfs); 172 rvu->cgx_mapped_vfs += numvfs; 173 pf++; 174 } 175 } 176 return 0; 177 } 178 179 static int rvu_cgx_send_link_info(int cgx_id, int lmac_id, struct rvu *rvu) 180 { 181 struct cgx_evq_entry *qentry; 182 unsigned long flags; 183 int err; 184 185 qentry = kmalloc(sizeof(*qentry), GFP_KERNEL); 186 if (!qentry) 187 return -ENOMEM; 188 189 /* Lock the event queue before we read the local link status */ 190 spin_lock_irqsave(&rvu->cgx_evq_lock, flags); 191 err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id, 192 &qentry->link_event.link_uinfo); 193 qentry->link_event.cgx_id = cgx_id; 194 qentry->link_event.lmac_id = lmac_id; 195 if (err) { 196 kfree(qentry); 197 goto skip_add; 198 } 199 list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head); 200 skip_add: 201 spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags); 202 203 /* start worker to process the events */ 204 queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work); 205 206 return 0; 207 } 208 209 /* This is called from interrupt context and is expected to be atomic */ 210 static int cgx_lmac_postevent(struct cgx_link_event *event, void *data) 211 { 212 struct cgx_evq_entry *qentry; 213 struct rvu *rvu = data; 214 215 /* post event to the event queue */ 216 qentry = kmalloc(sizeof(*qentry), GFP_ATOMIC); 217 if (!qentry) 218 return -ENOMEM; 219 qentry->link_event = *event; 220 spin_lock(&rvu->cgx_evq_lock); 221 list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head); 222 spin_unlock(&rvu->cgx_evq_lock); 223 224 /* start worker to process the events */ 225 queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work); 226 227 return 0; 228 } 229 230 static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu) 231 { 232 struct cgx_link_user_info *linfo; 233 struct cgx_link_info_msg *msg; 234 unsigned long pfmap; 235 int err, pfid; 236 237 linfo = &event->link_uinfo; 238 pfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id); 239 if (!pfmap) { 240 dev_err(rvu->dev, "CGX port%d:%d not mapped with PF\n", 241 event->cgx_id, event->lmac_id); 242 return; 243 } 244 245 do { 246 pfid = find_first_bit(&pfmap, 247 rvu->cgx_cnt_max * rvu->hw->lmac_per_cgx); 248 clear_bit(pfid, &pfmap); 249 250 /* check if notification is enabled */ 251 if (!test_bit(pfid, &rvu->pf_notify_bmap)) { 252 dev_info(rvu->dev, "cgx %d: lmac %d Link status %s\n", 253 event->cgx_id, event->lmac_id, 254 linfo->link_up ? "UP" : "DOWN"); 255 continue; 256 } 257 258 /* Send mbox message to PF */ 259 msg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid); 260 if (!msg) 261 continue; 262 msg->link_info = *linfo; 263 otx2_mbox_msg_send(&rvu->afpf_wq_info.mbox_up, pfid); 264 err = otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, pfid); 265 if (err) 266 dev_warn(rvu->dev, "notification to pf %d failed\n", 267 pfid); 268 } while (pfmap); 269 } 270 271 static void cgx_evhandler_task(struct work_struct *work) 272 { 273 struct rvu *rvu = container_of(work, struct rvu, cgx_evh_work); 274 struct cgx_evq_entry *qentry; 275 struct cgx_link_event *event; 276 unsigned long flags; 277 278 do { 279 /* Dequeue an event */ 280 spin_lock_irqsave(&rvu->cgx_evq_lock, flags); 281 qentry = list_first_entry_or_null(&rvu->cgx_evq_head, 282 struct cgx_evq_entry, 283 evq_node); 284 if (qentry) 285 list_del(&qentry->evq_node); 286 spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags); 287 if (!qentry) 288 break; /* nothing more to process */ 289 290 event = &qentry->link_event; 291 292 /* process event */ 293 cgx_notify_pfs(event, rvu); 294 kfree(qentry); 295 } while (1); 296 } 297 298 static int cgx_lmac_event_handler_init(struct rvu *rvu) 299 { 300 unsigned long lmac_bmap; 301 struct cgx_event_cb cb; 302 int cgx, lmac, err; 303 void *cgxd; 304 305 spin_lock_init(&rvu->cgx_evq_lock); 306 INIT_LIST_HEAD(&rvu->cgx_evq_head); 307 INIT_WORK(&rvu->cgx_evh_work, cgx_evhandler_task); 308 rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0); 309 if (!rvu->cgx_evh_wq) { 310 dev_err(rvu->dev, "alloc workqueue failed"); 311 return -ENOMEM; 312 } 313 314 cb.notify_link_chg = cgx_lmac_postevent; /* link change call back */ 315 cb.data = rvu; 316 317 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) { 318 cgxd = rvu_cgx_pdata(cgx, rvu); 319 if (!cgxd) 320 continue; 321 lmac_bmap = cgx_get_lmac_bmap(cgxd); 322 for_each_set_bit(lmac, &lmac_bmap, rvu->hw->lmac_per_cgx) { 323 err = cgx_lmac_evh_register(&cb, cgxd, lmac); 324 if (err) 325 dev_err(rvu->dev, 326 "%d:%d handler register failed\n", 327 cgx, lmac); 328 } 329 } 330 331 return 0; 332 } 333 334 static void rvu_cgx_wq_destroy(struct rvu *rvu) 335 { 336 if (rvu->cgx_evh_wq) { 337 destroy_workqueue(rvu->cgx_evh_wq); 338 rvu->cgx_evh_wq = NULL; 339 } 340 } 341 342 int rvu_cgx_init(struct rvu *rvu) 343 { 344 int cgx, err; 345 void *cgxd; 346 347 /* CGX port id starts from 0 and are not necessarily contiguous 348 * Hence we allocate resources based on the maximum port id value. 349 */ 350 rvu->cgx_cnt_max = cgx_get_cgxcnt_max(); 351 if (!rvu->cgx_cnt_max) { 352 dev_info(rvu->dev, "No CGX devices found!\n"); 353 return 0; 354 } 355 356 rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt_max * 357 sizeof(void *), GFP_KERNEL); 358 if (!rvu->cgx_idmap) 359 return -ENOMEM; 360 361 /* Initialize the cgxdata table */ 362 for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++) 363 rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx); 364 365 /* Map CGX LMAC interfaces to RVU PFs */ 366 err = rvu_map_cgx_lmac_pf(rvu); 367 if (err) 368 return err; 369 370 /* Register for CGX events */ 371 err = cgx_lmac_event_handler_init(rvu); 372 if (err) 373 return err; 374 375 mutex_init(&rvu->cgx_cfg_lock); 376 377 /* Ensure event handler registration is completed, before 378 * we turn on the links 379 */ 380 mb(); 381 382 /* Do link up for all CGX ports */ 383 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) { 384 cgxd = rvu_cgx_pdata(cgx, rvu); 385 if (!cgxd) 386 continue; 387 err = cgx_lmac_linkup_start(cgxd); 388 if (err) 389 dev_err(rvu->dev, 390 "Link up process failed to start on cgx %d\n", 391 cgx); 392 } 393 394 return 0; 395 } 396 397 int rvu_cgx_exit(struct rvu *rvu) 398 { 399 unsigned long lmac_bmap; 400 int cgx, lmac; 401 void *cgxd; 402 403 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) { 404 cgxd = rvu_cgx_pdata(cgx, rvu); 405 if (!cgxd) 406 continue; 407 lmac_bmap = cgx_get_lmac_bmap(cgxd); 408 for_each_set_bit(lmac, &lmac_bmap, rvu->hw->lmac_per_cgx) 409 cgx_lmac_evh_unregister(cgxd, lmac); 410 } 411 412 /* Ensure event handler unregister is completed */ 413 mb(); 414 415 rvu_cgx_wq_destroy(rvu); 416 return 0; 417 } 418 419 /* Most of the CGX configuration is restricted to the mapped PF only, 420 * VF's of mapped PF and other PFs are not allowed. This fn() checks 421 * whether a PFFUNC is permitted to do the config or not. 422 */ 423 inline bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc) 424 { 425 if ((pcifunc & RVU_PFVF_FUNC_MASK) || 426 !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) 427 return false; 428 return true; 429 } 430 431 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable) 432 { 433 struct mac_ops *mac_ops; 434 u8 cgx_id, lmac_id; 435 void *cgxd; 436 437 if (!is_pf_cgxmapped(rvu, pf)) 438 return; 439 440 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 441 cgxd = rvu_cgx_pdata(cgx_id, rvu); 442 443 mac_ops = get_mac_ops(cgxd); 444 /* Set / clear CTL_BCK to control pause frame forwarding to NIX */ 445 if (enable) 446 mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, true); 447 else 448 mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, false); 449 } 450 451 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start) 452 { 453 int pf = rvu_get_pf(pcifunc); 454 struct mac_ops *mac_ops; 455 u8 cgx_id, lmac_id; 456 void *cgxd; 457 458 if (!is_cgx_config_permitted(rvu, pcifunc)) 459 return LMAC_AF_ERR_PERM_DENIED; 460 461 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 462 cgxd = rvu_cgx_pdata(cgx_id, rvu); 463 mac_ops = get_mac_ops(cgxd); 464 465 return mac_ops->mac_rx_tx_enable(cgxd, lmac_id, start); 466 } 467 468 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable) 469 { 470 int pf = rvu_get_pf(pcifunc); 471 struct mac_ops *mac_ops; 472 u8 cgx_id, lmac_id; 473 void *cgxd; 474 475 if (!is_cgx_config_permitted(rvu, pcifunc)) 476 return LMAC_AF_ERR_PERM_DENIED; 477 478 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 479 cgxd = rvu_cgx_pdata(cgx_id, rvu); 480 mac_ops = get_mac_ops(cgxd); 481 482 return mac_ops->mac_tx_enable(cgxd, lmac_id, enable); 483 } 484 485 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable) 486 { 487 struct mac_ops *mac_ops; 488 489 mac_ops = get_mac_ops(cgxd); 490 return mac_ops->mac_tx_enable(cgxd, lmac_id, enable); 491 } 492 493 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc) 494 { 495 int pf = rvu_get_pf(pcifunc); 496 int i = 0, lmac_count = 0; 497 struct mac_ops *mac_ops; 498 u8 max_dmac_filters; 499 u8 cgx_id, lmac_id; 500 void *cgx_dev; 501 502 if (!is_cgx_config_permitted(rvu, pcifunc)) 503 return; 504 505 if (rvu_npc_exact_has_match_table(rvu)) { 506 rvu_npc_exact_reset(rvu, pcifunc); 507 return; 508 } 509 510 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 511 cgx_dev = cgx_get_pdata(cgx_id); 512 lmac_count = cgx_get_lmac_cnt(cgx_dev); 513 514 mac_ops = get_mac_ops(cgx_dev); 515 if (!mac_ops) 516 return; 517 518 max_dmac_filters = mac_ops->dmac_filter_count / lmac_count; 519 520 for (i = 0; i < max_dmac_filters; i++) 521 cgx_lmac_addr_del(cgx_id, lmac_id, i); 522 523 /* As cgx_lmac_addr_del does not clear entry for index 0 524 * so it needs to be done explicitly 525 */ 526 cgx_lmac_addr_reset(cgx_id, lmac_id); 527 } 528 529 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req, 530 struct msg_rsp *rsp) 531 { 532 rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, true); 533 return 0; 534 } 535 536 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req, 537 struct msg_rsp *rsp) 538 { 539 rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false); 540 return 0; 541 } 542 543 static int rvu_lmac_get_stats(struct rvu *rvu, struct msg_req *req, 544 void *rsp) 545 { 546 int pf = rvu_get_pf(req->hdr.pcifunc); 547 struct mac_ops *mac_ops; 548 int stat = 0, err = 0; 549 u64 tx_stat, rx_stat; 550 u8 cgx_idx, lmac; 551 void *cgxd; 552 553 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 554 return LMAC_AF_ERR_PERM_DENIED; 555 556 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac); 557 cgxd = rvu_cgx_pdata(cgx_idx, rvu); 558 mac_ops = get_mac_ops(cgxd); 559 560 /* Rx stats */ 561 while (stat < mac_ops->rx_stats_cnt) { 562 err = mac_ops->mac_get_rx_stats(cgxd, lmac, stat, &rx_stat); 563 if (err) 564 return err; 565 if (mac_ops->rx_stats_cnt == RPM_RX_STATS_COUNT) 566 ((struct rpm_stats_rsp *)rsp)->rx_stats[stat] = rx_stat; 567 else 568 ((struct cgx_stats_rsp *)rsp)->rx_stats[stat] = rx_stat; 569 stat++; 570 } 571 572 /* Tx stats */ 573 stat = 0; 574 while (stat < mac_ops->tx_stats_cnt) { 575 err = mac_ops->mac_get_tx_stats(cgxd, lmac, stat, &tx_stat); 576 if (err) 577 return err; 578 if (mac_ops->tx_stats_cnt == RPM_TX_STATS_COUNT) 579 ((struct rpm_stats_rsp *)rsp)->tx_stats[stat] = tx_stat; 580 else 581 ((struct cgx_stats_rsp *)rsp)->tx_stats[stat] = tx_stat; 582 stat++; 583 } 584 return 0; 585 } 586 587 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req, 588 struct cgx_stats_rsp *rsp) 589 { 590 return rvu_lmac_get_stats(rvu, req, (void *)rsp); 591 } 592 593 int rvu_mbox_handler_rpm_stats(struct rvu *rvu, struct msg_req *req, 594 struct rpm_stats_rsp *rsp) 595 { 596 return rvu_lmac_get_stats(rvu, req, (void *)rsp); 597 } 598 599 int rvu_mbox_handler_cgx_fec_stats(struct rvu *rvu, 600 struct msg_req *req, 601 struct cgx_fec_stats_rsp *rsp) 602 { 603 int pf = rvu_get_pf(req->hdr.pcifunc); 604 struct mac_ops *mac_ops; 605 u8 cgx_idx, lmac; 606 void *cgxd; 607 608 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 609 return LMAC_AF_ERR_PERM_DENIED; 610 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac); 611 612 cgxd = rvu_cgx_pdata(cgx_idx, rvu); 613 mac_ops = get_mac_ops(cgxd); 614 return mac_ops->get_fec_stats(cgxd, lmac, rsp); 615 } 616 617 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu, 618 struct cgx_mac_addr_set_or_get *req, 619 struct cgx_mac_addr_set_or_get *rsp) 620 { 621 int pf = rvu_get_pf(req->hdr.pcifunc); 622 u8 cgx_id, lmac_id; 623 624 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 625 return -EPERM; 626 627 if (rvu_npc_exact_has_match_table(rvu)) 628 return rvu_npc_exact_mac_addr_set(rvu, req, rsp); 629 630 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 631 632 cgx_lmac_addr_set(cgx_id, lmac_id, req->mac_addr); 633 634 return 0; 635 } 636 637 int rvu_mbox_handler_cgx_mac_addr_add(struct rvu *rvu, 638 struct cgx_mac_addr_add_req *req, 639 struct cgx_mac_addr_add_rsp *rsp) 640 { 641 int pf = rvu_get_pf(req->hdr.pcifunc); 642 u8 cgx_id, lmac_id; 643 int rc = 0; 644 645 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 646 return -EPERM; 647 648 if (rvu_npc_exact_has_match_table(rvu)) 649 return rvu_npc_exact_mac_addr_add(rvu, req, rsp); 650 651 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 652 rc = cgx_lmac_addr_add(cgx_id, lmac_id, req->mac_addr); 653 if (rc >= 0) { 654 rsp->index = rc; 655 return 0; 656 } 657 658 return rc; 659 } 660 661 int rvu_mbox_handler_cgx_mac_addr_del(struct rvu *rvu, 662 struct cgx_mac_addr_del_req *req, 663 struct msg_rsp *rsp) 664 { 665 int pf = rvu_get_pf(req->hdr.pcifunc); 666 u8 cgx_id, lmac_id; 667 668 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 669 return -EPERM; 670 671 if (rvu_npc_exact_has_match_table(rvu)) 672 return rvu_npc_exact_mac_addr_del(rvu, req, rsp); 673 674 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 675 return cgx_lmac_addr_del(cgx_id, lmac_id, req->index); 676 } 677 678 int rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu *rvu, 679 struct msg_req *req, 680 struct cgx_max_dmac_entries_get_rsp 681 *rsp) 682 { 683 int pf = rvu_get_pf(req->hdr.pcifunc); 684 u8 cgx_id, lmac_id; 685 686 /* If msg is received from PFs(which are not mapped to CGX LMACs) 687 * or VF then no entries are allocated for DMAC filters at CGX level. 688 * So returning zero. 689 */ 690 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) { 691 rsp->max_dmac_filters = 0; 692 return 0; 693 } 694 695 if (rvu_npc_exact_has_match_table(rvu)) { 696 rsp->max_dmac_filters = rvu_npc_exact_get_max_entries(rvu); 697 return 0; 698 } 699 700 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 701 rsp->max_dmac_filters = cgx_lmac_addr_max_entries_get(cgx_id, lmac_id); 702 return 0; 703 } 704 705 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu, 706 struct cgx_mac_addr_set_or_get *req, 707 struct cgx_mac_addr_set_or_get *rsp) 708 { 709 int pf = rvu_get_pf(req->hdr.pcifunc); 710 u8 cgx_id, lmac_id; 711 int rc = 0; 712 u64 cfg; 713 714 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 715 return -EPERM; 716 717 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 718 719 rsp->hdr.rc = rc; 720 cfg = cgx_lmac_addr_get(cgx_id, lmac_id); 721 /* copy 48 bit mac address to req->mac_addr */ 722 u64_to_ether_addr(cfg, rsp->mac_addr); 723 return 0; 724 } 725 726 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req, 727 struct msg_rsp *rsp) 728 { 729 u16 pcifunc = req->hdr.pcifunc; 730 int pf = rvu_get_pf(pcifunc); 731 u8 cgx_id, lmac_id; 732 733 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 734 return -EPERM; 735 736 /* Disable drop on non hit rule */ 737 if (rvu_npc_exact_has_match_table(rvu)) 738 return rvu_npc_exact_promisc_enable(rvu, req->hdr.pcifunc); 739 740 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 741 742 cgx_lmac_promisc_config(cgx_id, lmac_id, true); 743 return 0; 744 } 745 746 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req, 747 struct msg_rsp *rsp) 748 { 749 int pf = rvu_get_pf(req->hdr.pcifunc); 750 u8 cgx_id, lmac_id; 751 752 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 753 return -EPERM; 754 755 /* Disable drop on non hit rule */ 756 if (rvu_npc_exact_has_match_table(rvu)) 757 return rvu_npc_exact_promisc_disable(rvu, req->hdr.pcifunc); 758 759 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 760 761 cgx_lmac_promisc_config(cgx_id, lmac_id, false); 762 return 0; 763 } 764 765 static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcifunc, bool enable) 766 { 767 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 768 int pf = rvu_get_pf(pcifunc); 769 struct mac_ops *mac_ops; 770 u8 cgx_id, lmac_id; 771 void *cgxd; 772 773 if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP)) 774 return 0; 775 776 /* This msg is expected only from PFs that are mapped to CGX LMACs, 777 * if received from other PF/VF simply ACK, nothing to do. 778 */ 779 if ((pcifunc & RVU_PFVF_FUNC_MASK) || 780 !is_pf_cgxmapped(rvu, pf)) 781 return -ENODEV; 782 783 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 784 cgxd = rvu_cgx_pdata(cgx_id, rvu); 785 786 mac_ops = get_mac_ops(cgxd); 787 mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, enable); 788 /* If PTP is enabled then inform NPC that packets to be 789 * parsed by this PF will have their data shifted by 8 bytes 790 * and if PTP is disabled then no shift is required 791 */ 792 if (npc_config_ts_kpuaction(rvu, pf, pcifunc, enable)) 793 return -EINVAL; 794 /* This flag is required to clean up CGX conf if app gets killed */ 795 pfvf->hw_rx_tstamp_en = enable; 796 797 /* Inform MCS about 8B RX header */ 798 rvu_mcs_ptp_cfg(rvu, cgx_id, lmac_id, enable); 799 return 0; 800 } 801 802 int rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu *rvu, struct msg_req *req, 803 struct msg_rsp *rsp) 804 { 805 if (!is_pf_cgxmapped(rvu, rvu_get_pf(req->hdr.pcifunc))) 806 return -EPERM; 807 808 return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, true); 809 } 810 811 int rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu *rvu, struct msg_req *req, 812 struct msg_rsp *rsp) 813 { 814 return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, false); 815 } 816 817 static int rvu_cgx_config_linkevents(struct rvu *rvu, u16 pcifunc, bool en) 818 { 819 int pf = rvu_get_pf(pcifunc); 820 u8 cgx_id, lmac_id; 821 822 if (!is_cgx_config_permitted(rvu, pcifunc)) 823 return -EPERM; 824 825 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 826 827 if (en) { 828 set_bit(pf, &rvu->pf_notify_bmap); 829 /* Send the current link status to PF */ 830 rvu_cgx_send_link_info(cgx_id, lmac_id, rvu); 831 } else { 832 clear_bit(pf, &rvu->pf_notify_bmap); 833 } 834 835 return 0; 836 } 837 838 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req, 839 struct msg_rsp *rsp) 840 { 841 rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, true); 842 return 0; 843 } 844 845 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req, 846 struct msg_rsp *rsp) 847 { 848 rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, false); 849 return 0; 850 } 851 852 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req, 853 struct cgx_link_info_msg *rsp) 854 { 855 u8 cgx_id, lmac_id; 856 int pf, err; 857 858 pf = rvu_get_pf(req->hdr.pcifunc); 859 860 if (!is_pf_cgxmapped(rvu, pf)) 861 return -ENODEV; 862 863 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 864 865 err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id, 866 &rsp->link_info); 867 return err; 868 } 869 870 int rvu_mbox_handler_cgx_features_get(struct rvu *rvu, 871 struct msg_req *req, 872 struct cgx_features_info_msg *rsp) 873 { 874 int pf = rvu_get_pf(req->hdr.pcifunc); 875 u8 cgx_idx, lmac; 876 void *cgxd; 877 878 if (!is_pf_cgxmapped(rvu, pf)) 879 return 0; 880 881 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac); 882 cgxd = rvu_cgx_pdata(cgx_idx, rvu); 883 rsp->lmac_features = cgx_features_get(cgxd); 884 885 return 0; 886 } 887 888 u32 rvu_cgx_get_fifolen(struct rvu *rvu) 889 { 890 struct mac_ops *mac_ops; 891 u32 fifo_len; 892 893 mac_ops = get_mac_ops(rvu_first_cgx_pdata(rvu)); 894 fifo_len = mac_ops ? mac_ops->fifo_len : 0; 895 896 return fifo_len; 897 } 898 899 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac) 900 { 901 struct mac_ops *mac_ops; 902 void *cgxd; 903 904 cgxd = rvu_cgx_pdata(cgx, rvu); 905 if (!cgxd) 906 return 0; 907 908 mac_ops = get_mac_ops(cgxd); 909 if (!mac_ops->lmac_fifo_len) 910 return 0; 911 912 return mac_ops->lmac_fifo_len(cgxd, lmac); 913 } 914 915 static int rvu_cgx_config_intlbk(struct rvu *rvu, u16 pcifunc, bool en) 916 { 917 int pf = rvu_get_pf(pcifunc); 918 struct mac_ops *mac_ops; 919 u8 cgx_id, lmac_id; 920 921 if (!is_cgx_config_permitted(rvu, pcifunc)) 922 return -EPERM; 923 924 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 925 mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu)); 926 927 return mac_ops->mac_lmac_intl_lbk(rvu_cgx_pdata(cgx_id, rvu), 928 lmac_id, en); 929 } 930 931 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req, 932 struct msg_rsp *rsp) 933 { 934 rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, true); 935 return 0; 936 } 937 938 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req, 939 struct msg_rsp *rsp) 940 { 941 rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, false); 942 return 0; 943 } 944 945 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause) 946 { 947 int pf = rvu_get_pf(pcifunc); 948 u8 rx_pfc = 0, tx_pfc = 0; 949 struct mac_ops *mac_ops; 950 u8 cgx_id, lmac_id; 951 void *cgxd; 952 953 if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_FC)) 954 return 0; 955 956 /* This msg is expected only from PF/VFs that are mapped to CGX LMACs, 957 * if received from other PF/VF simply ACK, nothing to do. 958 */ 959 if (!is_pf_cgxmapped(rvu, pf)) 960 return LMAC_AF_ERR_PF_NOT_MAPPED; 961 962 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 963 cgxd = rvu_cgx_pdata(cgx_id, rvu); 964 mac_ops = get_mac_ops(cgxd); 965 966 mac_ops->mac_get_pfc_frm_cfg(cgxd, lmac_id, &tx_pfc, &rx_pfc); 967 if (tx_pfc || rx_pfc) { 968 dev_warn(rvu->dev, 969 "Can not configure 802.3X flow control as PFC frames are enabled"); 970 return LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED; 971 } 972 973 mutex_lock(&rvu->rsrc_lock); 974 if (verify_lmac_fc_cfg(cgxd, lmac_id, tx_pause, rx_pause, 975 pcifunc & RVU_PFVF_FUNC_MASK)) { 976 mutex_unlock(&rvu->rsrc_lock); 977 return LMAC_AF_ERR_PERM_DENIED; 978 } 979 mutex_unlock(&rvu->rsrc_lock); 980 981 return mac_ops->mac_enadis_pause_frm(cgxd, lmac_id, tx_pause, rx_pause); 982 } 983 984 int rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu *rvu, 985 struct cgx_pause_frm_cfg *req, 986 struct cgx_pause_frm_cfg *rsp) 987 { 988 int pf = rvu_get_pf(req->hdr.pcifunc); 989 struct mac_ops *mac_ops; 990 u8 cgx_id, lmac_id; 991 int err = 0; 992 void *cgxd; 993 994 /* This msg is expected only from PF/VFs that are mapped to CGX LMACs, 995 * if received from other PF/VF simply ACK, nothing to do. 996 */ 997 if (!is_pf_cgxmapped(rvu, pf)) 998 return -ENODEV; 999 1000 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1001 cgxd = rvu_cgx_pdata(cgx_id, rvu); 1002 mac_ops = get_mac_ops(cgxd); 1003 1004 if (req->set) 1005 err = rvu_cgx_cfg_pause_frm(rvu, req->hdr.pcifunc, req->tx_pause, req->rx_pause); 1006 else 1007 mac_ops->mac_get_pause_frm_status(cgxd, lmac_id, &rsp->tx_pause, &rsp->rx_pause); 1008 1009 return err; 1010 } 1011 1012 int rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu *rvu, struct msg_req *req, 1013 struct msg_rsp *rsp) 1014 { 1015 int pf = rvu_get_pf(req->hdr.pcifunc); 1016 u8 cgx_id, lmac_id; 1017 1018 if (!is_pf_cgxmapped(rvu, pf)) 1019 return LMAC_AF_ERR_PF_NOT_MAPPED; 1020 1021 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1022 return cgx_get_phy_fec_stats(rvu_cgx_pdata(cgx_id, rvu), lmac_id); 1023 } 1024 1025 /* Finds cumulative status of NIX rx/tx counters from LF of a PF and those 1026 * from its VFs as well. ie. NIX rx/tx counters at the CGX port level 1027 */ 1028 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, 1029 int index, int rxtxflag, u64 *stat) 1030 { 1031 struct rvu_block *block; 1032 int blkaddr; 1033 u16 pcifunc; 1034 int pf, lf; 1035 1036 *stat = 0; 1037 1038 if (!cgxd || !rvu) 1039 return -EINVAL; 1040 1041 pf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id); 1042 if (pf < 0) 1043 return pf; 1044 1045 /* Assumes LF of a PF and all of its VF belongs to the same 1046 * NIX block 1047 */ 1048 pcifunc = pf << RVU_PFVF_PF_SHIFT; 1049 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1050 if (blkaddr < 0) 1051 return 0; 1052 block = &rvu->hw->block[blkaddr]; 1053 1054 for (lf = 0; lf < block->lf.max; lf++) { 1055 /* Check if a lf is attached to this PF or one of its VFs */ 1056 if (!((block->fn_map[lf] & ~RVU_PFVF_FUNC_MASK) == (pcifunc & 1057 ~RVU_PFVF_FUNC_MASK))) 1058 continue; 1059 if (rxtxflag == NIX_STATS_RX) 1060 *stat += rvu_read64(rvu, blkaddr, 1061 NIX_AF_LFX_RX_STATX(lf, index)); 1062 else 1063 *stat += rvu_read64(rvu, blkaddr, 1064 NIX_AF_LFX_TX_STATX(lf, index)); 1065 } 1066 1067 return 0; 1068 } 1069 1070 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start) 1071 { 1072 struct rvu_pfvf *parent_pf, *pfvf; 1073 int cgx_users, err = 0; 1074 1075 if (!is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) 1076 return 0; 1077 1078 parent_pf = &rvu->pf[rvu_get_pf(pcifunc)]; 1079 pfvf = rvu_get_pfvf(rvu, pcifunc); 1080 1081 mutex_lock(&rvu->cgx_cfg_lock); 1082 1083 if (start && pfvf->cgx_in_use) 1084 goto exit; /* CGX is already started hence nothing to do */ 1085 if (!start && !pfvf->cgx_in_use) 1086 goto exit; /* CGX is already stopped hence nothing to do */ 1087 1088 if (start) { 1089 cgx_users = parent_pf->cgx_users; 1090 parent_pf->cgx_users++; 1091 } else { 1092 parent_pf->cgx_users--; 1093 cgx_users = parent_pf->cgx_users; 1094 } 1095 1096 /* Start CGX when first of all NIXLFs is started. 1097 * Stop CGX when last of all NIXLFs is stopped. 1098 */ 1099 if (!cgx_users) { 1100 err = rvu_cgx_config_rxtx(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK, 1101 start); 1102 if (err) { 1103 dev_err(rvu->dev, "Unable to %s CGX\n", 1104 start ? "start" : "stop"); 1105 /* Revert the usage count in case of error */ 1106 parent_pf->cgx_users = start ? parent_pf->cgx_users - 1 1107 : parent_pf->cgx_users + 1; 1108 goto exit; 1109 } 1110 } 1111 pfvf->cgx_in_use = start; 1112 exit: 1113 mutex_unlock(&rvu->cgx_cfg_lock); 1114 return err; 1115 } 1116 1117 int rvu_mbox_handler_cgx_set_fec_param(struct rvu *rvu, 1118 struct fec_mode *req, 1119 struct fec_mode *rsp) 1120 { 1121 int pf = rvu_get_pf(req->hdr.pcifunc); 1122 u8 cgx_id, lmac_id; 1123 1124 if (!is_pf_cgxmapped(rvu, pf)) 1125 return -EPERM; 1126 1127 if (req->fec == OTX2_FEC_OFF) 1128 req->fec = OTX2_FEC_NONE; 1129 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1130 rsp->fec = cgx_set_fec(req->fec, cgx_id, lmac_id); 1131 return 0; 1132 } 1133 1134 int rvu_mbox_handler_cgx_get_aux_link_info(struct rvu *rvu, struct msg_req *req, 1135 struct cgx_fw_data *rsp) 1136 { 1137 int pf = rvu_get_pf(req->hdr.pcifunc); 1138 u8 cgx_id, lmac_id; 1139 1140 if (!rvu->fwdata) 1141 return LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED; 1142 1143 if (!is_pf_cgxmapped(rvu, pf)) 1144 return -EPERM; 1145 1146 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1147 1148 if (rvu->hw->lmac_per_cgx == CGX_LMACS_USX) 1149 memcpy(&rsp->fwdata, 1150 &rvu->fwdata->cgx_fw_data_usx[cgx_id][lmac_id], 1151 sizeof(struct cgx_lmac_fwdata_s)); 1152 else 1153 memcpy(&rsp->fwdata, 1154 &rvu->fwdata->cgx_fw_data[cgx_id][lmac_id], 1155 sizeof(struct cgx_lmac_fwdata_s)); 1156 1157 return 0; 1158 } 1159 1160 int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu, 1161 struct cgx_set_link_mode_req *req, 1162 struct cgx_set_link_mode_rsp *rsp) 1163 { 1164 int pf = rvu_get_pf(req->hdr.pcifunc); 1165 u8 cgx_idx, lmac; 1166 void *cgxd; 1167 1168 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 1169 return -EPERM; 1170 1171 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac); 1172 cgxd = rvu_cgx_pdata(cgx_idx, rvu); 1173 rsp->status = cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac); 1174 return 0; 1175 } 1176 1177 int rvu_mbox_handler_cgx_mac_addr_reset(struct rvu *rvu, struct cgx_mac_addr_reset_req *req, 1178 struct msg_rsp *rsp) 1179 { 1180 int pf = rvu_get_pf(req->hdr.pcifunc); 1181 u8 cgx_id, lmac_id; 1182 1183 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 1184 return LMAC_AF_ERR_PERM_DENIED; 1185 1186 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1187 1188 if (rvu_npc_exact_has_match_table(rvu)) 1189 return rvu_npc_exact_mac_addr_reset(rvu, req, rsp); 1190 1191 return cgx_lmac_addr_reset(cgx_id, lmac_id); 1192 } 1193 1194 int rvu_mbox_handler_cgx_mac_addr_update(struct rvu *rvu, 1195 struct cgx_mac_addr_update_req *req, 1196 struct cgx_mac_addr_update_rsp *rsp) 1197 { 1198 int pf = rvu_get_pf(req->hdr.pcifunc); 1199 u8 cgx_id, lmac_id; 1200 1201 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 1202 return LMAC_AF_ERR_PERM_DENIED; 1203 1204 if (rvu_npc_exact_has_match_table(rvu)) 1205 return rvu_npc_exact_mac_addr_update(rvu, req, rsp); 1206 1207 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1208 return cgx_lmac_addr_update(cgx_id, lmac_id, req->mac_addr, req->index); 1209 } 1210 1211 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, 1212 u8 rx_pause, u16 pfc_en) 1213 { 1214 int pf = rvu_get_pf(pcifunc); 1215 u8 rx_8023 = 0, tx_8023 = 0; 1216 struct mac_ops *mac_ops; 1217 u8 cgx_id, lmac_id; 1218 void *cgxd; 1219 1220 /* This msg is expected only from PF/VFs that are mapped to CGX LMACs, 1221 * if received from other PF/VF simply ACK, nothing to do. 1222 */ 1223 if (!is_pf_cgxmapped(rvu, pf)) 1224 return -ENODEV; 1225 1226 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1227 cgxd = rvu_cgx_pdata(cgx_id, rvu); 1228 mac_ops = get_mac_ops(cgxd); 1229 1230 mac_ops->mac_get_pause_frm_status(cgxd, lmac_id, &tx_8023, &rx_8023); 1231 if (tx_8023 || rx_8023) { 1232 dev_warn(rvu->dev, 1233 "Can not configure PFC as 802.3X pause frames are enabled"); 1234 return LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED; 1235 } 1236 1237 mutex_lock(&rvu->rsrc_lock); 1238 if (verify_lmac_fc_cfg(cgxd, lmac_id, tx_pause, rx_pause, 1239 pcifunc & RVU_PFVF_FUNC_MASK)) { 1240 mutex_unlock(&rvu->rsrc_lock); 1241 return LMAC_AF_ERR_PERM_DENIED; 1242 } 1243 mutex_unlock(&rvu->rsrc_lock); 1244 1245 return mac_ops->pfc_config(cgxd, lmac_id, tx_pause, rx_pause, pfc_en); 1246 } 1247 1248 int rvu_mbox_handler_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, 1249 struct cgx_pfc_cfg *req, 1250 struct cgx_pfc_rsp *rsp) 1251 { 1252 int pf = rvu_get_pf(req->hdr.pcifunc); 1253 struct mac_ops *mac_ops; 1254 u8 cgx_id, lmac_id; 1255 void *cgxd; 1256 int err; 1257 1258 /* This msg is expected only from PF/VFs that are mapped to CGX LMACs, 1259 * if received from other PF/VF simply ACK, nothing to do. 1260 */ 1261 if (!is_pf_cgxmapped(rvu, pf)) 1262 return -ENODEV; 1263 1264 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 1265 cgxd = rvu_cgx_pdata(cgx_id, rvu); 1266 mac_ops = get_mac_ops(cgxd); 1267 1268 err = rvu_cgx_prio_flow_ctrl_cfg(rvu, req->hdr.pcifunc, req->tx_pause, 1269 req->rx_pause, req->pfc_en); 1270 1271 mac_ops->mac_get_pfc_frm_cfg(cgxd, lmac_id, &rsp->tx_pause, &rsp->rx_pause); 1272 return err; 1273 } 1274 1275 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc) 1276 { 1277 int pf = rvu_get_pf(pcifunc); 1278 struct mac_ops *mac_ops; 1279 struct cgx *cgxd; 1280 u8 cgx, lmac; 1281 1282 if (!is_pf_cgxmapped(rvu, pf)) 1283 return; 1284 1285 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx, &lmac); 1286 cgxd = rvu_cgx_pdata(cgx, rvu); 1287 mac_ops = get_mac_ops(cgxd); 1288 1289 if (mac_ops->mac_reset(cgxd, lmac, !is_vf(pcifunc))) 1290 dev_err(rvu->dev, "Failed to reset MAC\n"); 1291 } 1292