1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell International Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 
15 #include "rvu.h"
16 #include "cgx.h"
17 #include "lmac_common.h"
18 #include "rvu_reg.h"
19 #include "rvu_trace.h"
20 
21 struct cgx_evq_entry {
22 	struct list_head evq_node;
23 	struct cgx_link_event link_event;
24 };
25 
26 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
27 static struct _req_type __maybe_unused					\
28 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid)		\
29 {									\
30 	struct _req_type *req;						\
31 									\
32 	req = (struct _req_type *)otx2_mbox_alloc_msg_rsp(		\
33 		&rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
34 		sizeof(struct _rsp_type));				\
35 	if (!req)							\
36 		return NULL;						\
37 	req->hdr.sig = OTX2_MBOX_REQ_SIG;				\
38 	req->hdr.id = _id;						\
39 	trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req));		\
40 	return req;							\
41 }
42 
43 MBOX_UP_CGX_MESSAGES
44 #undef M
45 
46 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature)
47 {
48 	u8 cgx_id, lmac_id;
49 	void *cgxd;
50 
51 	if (!is_pf_cgxmapped(rvu, pf))
52 		return 0;
53 
54 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
55 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
56 
57 	return  (cgx_features_get(cgxd) & feature);
58 }
59 
60 /* Returns bitmap of mapped PFs */
61 static u16 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id)
62 {
63 	return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id];
64 }
65 
66 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id)
67 {
68 	unsigned long pfmap;
69 
70 	pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id);
71 
72 	/* Assumes only one pf mapped to a cgx lmac port */
73 	if (!pfmap)
74 		return -ENODEV;
75 	else
76 		return find_first_bit(&pfmap, 16);
77 }
78 
79 static u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
80 {
81 	return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);
82 }
83 
84 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
85 {
86 	if (cgx_id >= rvu->cgx_cnt_max)
87 		return NULL;
88 
89 	return rvu->cgx_idmap[cgx_id];
90 }
91 
92 /* Return first enabled CGX instance if none are enabled then return NULL */
93 void *rvu_first_cgx_pdata(struct rvu *rvu)
94 {
95 	int first_enabled_cgx = 0;
96 	void *cgxd = NULL;
97 
98 	for (; first_enabled_cgx < rvu->cgx_cnt_max; first_enabled_cgx++) {
99 		cgxd = rvu_cgx_pdata(first_enabled_cgx, rvu);
100 		if (cgxd)
101 			break;
102 	}
103 
104 	return cgxd;
105 }
106 
107 /* Based on P2X connectivity find mapped NIX block for a PF */
108 static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf,
109 				  int cgx_id, int lmac_id)
110 {
111 	struct rvu_pfvf *pfvf = &rvu->pf[pf];
112 	u8 p2x;
113 
114 	p2x = cgx_lmac_get_p2x(cgx_id, lmac_id);
115 	/* Firmware sets P2X_SELECT as either NIX0 or NIX1 */
116 	pfvf->nix_blkaddr = BLKADDR_NIX0;
117 	if (p2x == CMR_P2X_SEL_NIX1)
118 		pfvf->nix_blkaddr = BLKADDR_NIX1;
119 }
120 
121 static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
122 {
123 	struct npc_pkind *pkind = &rvu->hw->pkind;
124 	int cgx_cnt_max = rvu->cgx_cnt_max;
125 	int pf = PF_CGXMAP_BASE;
126 	unsigned long lmac_bmap;
127 	int size, free_pkind;
128 	int cgx, lmac, iter;
129 	int numvfs, hwvfs;
130 
131 	if (!cgx_cnt_max)
132 		return 0;
133 
134 	if (cgx_cnt_max > 0xF || MAX_LMAC_PER_CGX > 0xF)
135 		return -EINVAL;
136 
137 	/* Alloc map table
138 	 * An additional entry is required since PF id starts from 1 and
139 	 * hence entry at offset 0 is invalid.
140 	 */
141 	size = (cgx_cnt_max * MAX_LMAC_PER_CGX + 1) * sizeof(u8);
142 	rvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL);
143 	if (!rvu->pf2cgxlmac_map)
144 		return -ENOMEM;
145 
146 	/* Initialize all entries with an invalid cgx and lmac id */
147 	memset(rvu->pf2cgxlmac_map, 0xFF, size);
148 
149 	/* Reverse map table */
150 	rvu->cgxlmac2pf_map = devm_kzalloc(rvu->dev,
151 				  cgx_cnt_max * MAX_LMAC_PER_CGX * sizeof(u16),
152 				  GFP_KERNEL);
153 	if (!rvu->cgxlmac2pf_map)
154 		return -ENOMEM;
155 
156 	rvu->cgx_mapped_pfs = 0;
157 	for (cgx = 0; cgx < cgx_cnt_max; cgx++) {
158 		if (!rvu_cgx_pdata(cgx, rvu))
159 			continue;
160 		lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu));
161 		for_each_set_bit(iter, &lmac_bmap, MAX_LMAC_PER_CGX) {
162 			lmac = cgx_get_lmacid(rvu_cgx_pdata(cgx, rvu),
163 					      iter);
164 			rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);
165 			rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;
166 			free_pkind = rvu_alloc_rsrc(&pkind->rsrc);
167 			pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16;
168 			rvu_map_cgx_nix_block(rvu, pf, cgx, lmac);
169 			rvu->cgx_mapped_pfs++;
170 			rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvfs);
171 			rvu->cgx_mapped_vfs += numvfs;
172 			pf++;
173 		}
174 	}
175 	return 0;
176 }
177 
178 static int rvu_cgx_send_link_info(int cgx_id, int lmac_id, struct rvu *rvu)
179 {
180 	struct cgx_evq_entry *qentry;
181 	unsigned long flags;
182 	int err;
183 
184 	qentry = kmalloc(sizeof(*qentry), GFP_KERNEL);
185 	if (!qentry)
186 		return -ENOMEM;
187 
188 	/* Lock the event queue before we read the local link status */
189 	spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
190 	err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
191 				&qentry->link_event.link_uinfo);
192 	qentry->link_event.cgx_id = cgx_id;
193 	qentry->link_event.lmac_id = lmac_id;
194 	if (err) {
195 		kfree(qentry);
196 		goto skip_add;
197 	}
198 	list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
199 skip_add:
200 	spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
201 
202 	/* start worker to process the events */
203 	queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
204 
205 	return 0;
206 }
207 
208 /* This is called from interrupt context and is expected to be atomic */
209 static int cgx_lmac_postevent(struct cgx_link_event *event, void *data)
210 {
211 	struct cgx_evq_entry *qentry;
212 	struct rvu *rvu = data;
213 
214 	/* post event to the event queue */
215 	qentry = kmalloc(sizeof(*qentry), GFP_ATOMIC);
216 	if (!qentry)
217 		return -ENOMEM;
218 	qentry->link_event = *event;
219 	spin_lock(&rvu->cgx_evq_lock);
220 	list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
221 	spin_unlock(&rvu->cgx_evq_lock);
222 
223 	/* start worker to process the events */
224 	queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
225 
226 	return 0;
227 }
228 
229 static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu)
230 {
231 	struct cgx_link_user_info *linfo;
232 	struct cgx_link_info_msg *msg;
233 	unsigned long pfmap;
234 	int err, pfid;
235 
236 	linfo = &event->link_uinfo;
237 	pfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id);
238 
239 	do {
240 		pfid = find_first_bit(&pfmap, 16);
241 		clear_bit(pfid, &pfmap);
242 
243 		/* check if notification is enabled */
244 		if (!test_bit(pfid, &rvu->pf_notify_bmap)) {
245 			dev_info(rvu->dev, "cgx %d: lmac %d Link status %s\n",
246 				 event->cgx_id, event->lmac_id,
247 				 linfo->link_up ? "UP" : "DOWN");
248 			continue;
249 		}
250 
251 		/* Send mbox message to PF */
252 		msg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid);
253 		if (!msg)
254 			continue;
255 		msg->link_info = *linfo;
256 		otx2_mbox_msg_send(&rvu->afpf_wq_info.mbox_up, pfid);
257 		err = otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, pfid);
258 		if (err)
259 			dev_warn(rvu->dev, "notification to pf %d failed\n",
260 				 pfid);
261 	} while (pfmap);
262 }
263 
264 static void cgx_evhandler_task(struct work_struct *work)
265 {
266 	struct rvu *rvu = container_of(work, struct rvu, cgx_evh_work);
267 	struct cgx_evq_entry *qentry;
268 	struct cgx_link_event *event;
269 	unsigned long flags;
270 
271 	do {
272 		/* Dequeue an event */
273 		spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
274 		qentry = list_first_entry_or_null(&rvu->cgx_evq_head,
275 						  struct cgx_evq_entry,
276 						  evq_node);
277 		if (qentry)
278 			list_del(&qentry->evq_node);
279 		spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
280 		if (!qentry)
281 			break; /* nothing more to process */
282 
283 		event = &qentry->link_event;
284 
285 		/* process event */
286 		cgx_notify_pfs(event, rvu);
287 		kfree(qentry);
288 	} while (1);
289 }
290 
291 static int cgx_lmac_event_handler_init(struct rvu *rvu)
292 {
293 	unsigned long lmac_bmap;
294 	struct cgx_event_cb cb;
295 	int cgx, lmac, err;
296 	void *cgxd;
297 
298 	spin_lock_init(&rvu->cgx_evq_lock);
299 	INIT_LIST_HEAD(&rvu->cgx_evq_head);
300 	INIT_WORK(&rvu->cgx_evh_work, cgx_evhandler_task);
301 	rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0);
302 	if (!rvu->cgx_evh_wq) {
303 		dev_err(rvu->dev, "alloc workqueue failed");
304 		return -ENOMEM;
305 	}
306 
307 	cb.notify_link_chg = cgx_lmac_postevent; /* link change call back */
308 	cb.data = rvu;
309 
310 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
311 		cgxd = rvu_cgx_pdata(cgx, rvu);
312 		if (!cgxd)
313 			continue;
314 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
315 		for_each_set_bit(lmac, &lmac_bmap, MAX_LMAC_PER_CGX) {
316 			err = cgx_lmac_evh_register(&cb, cgxd, lmac);
317 			if (err)
318 				dev_err(rvu->dev,
319 					"%d:%d handler register failed\n",
320 					cgx, lmac);
321 		}
322 	}
323 
324 	return 0;
325 }
326 
327 static void rvu_cgx_wq_destroy(struct rvu *rvu)
328 {
329 	if (rvu->cgx_evh_wq) {
330 		flush_workqueue(rvu->cgx_evh_wq);
331 		destroy_workqueue(rvu->cgx_evh_wq);
332 		rvu->cgx_evh_wq = NULL;
333 	}
334 }
335 
336 int rvu_cgx_init(struct rvu *rvu)
337 {
338 	int cgx, err;
339 	void *cgxd;
340 
341 	/* CGX port id starts from 0 and are not necessarily contiguous
342 	 * Hence we allocate resources based on the maximum port id value.
343 	 */
344 	rvu->cgx_cnt_max = cgx_get_cgxcnt_max();
345 	if (!rvu->cgx_cnt_max) {
346 		dev_info(rvu->dev, "No CGX devices found!\n");
347 		return -ENODEV;
348 	}
349 
350 	rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt_max *
351 				      sizeof(void *), GFP_KERNEL);
352 	if (!rvu->cgx_idmap)
353 		return -ENOMEM;
354 
355 	/* Initialize the cgxdata table */
356 	for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++)
357 		rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx);
358 
359 	/* Map CGX LMAC interfaces to RVU PFs */
360 	err = rvu_map_cgx_lmac_pf(rvu);
361 	if (err)
362 		return err;
363 
364 	/* Register for CGX events */
365 	err = cgx_lmac_event_handler_init(rvu);
366 	if (err)
367 		return err;
368 
369 	mutex_init(&rvu->cgx_cfg_lock);
370 
371 	/* Ensure event handler registration is completed, before
372 	 * we turn on the links
373 	 */
374 	mb();
375 
376 	/* Do link up for all CGX ports */
377 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
378 		cgxd = rvu_cgx_pdata(cgx, rvu);
379 		if (!cgxd)
380 			continue;
381 		err = cgx_lmac_linkup_start(cgxd);
382 		if (err)
383 			dev_err(rvu->dev,
384 				"Link up process failed to start on cgx %d\n",
385 				cgx);
386 	}
387 
388 	return 0;
389 }
390 
391 int rvu_cgx_exit(struct rvu *rvu)
392 {
393 	unsigned long lmac_bmap;
394 	int cgx, lmac;
395 	void *cgxd;
396 
397 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
398 		cgxd = rvu_cgx_pdata(cgx, rvu);
399 		if (!cgxd)
400 			continue;
401 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
402 		for_each_set_bit(lmac, &lmac_bmap, MAX_LMAC_PER_CGX)
403 			cgx_lmac_evh_unregister(cgxd, lmac);
404 	}
405 
406 	/* Ensure event handler unregister is completed */
407 	mb();
408 
409 	rvu_cgx_wq_destroy(rvu);
410 	return 0;
411 }
412 
413 /* Most of the CGX configuration is restricted to the mapped PF only,
414  * VF's of mapped PF and other PFs are not allowed. This fn() checks
415  * whether a PFFUNC is permitted to do the config or not.
416  */
417 static bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc)
418 {
419 	if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
420 	    !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
421 		return false;
422 	return true;
423 }
424 
425 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable)
426 {
427 	struct mac_ops *mac_ops;
428 	u8 cgx_id, lmac_id;
429 	void *cgxd;
430 
431 	if (!is_pf_cgxmapped(rvu, pf))
432 		return;
433 
434 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
435 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
436 
437 	mac_ops = get_mac_ops(cgxd);
438 	/* Set / clear CTL_BCK to control pause frame forwarding to NIX */
439 	if (enable)
440 		mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, true);
441 	else
442 		mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, false);
443 }
444 
445 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start)
446 {
447 	int pf = rvu_get_pf(pcifunc);
448 	u8 cgx_id, lmac_id;
449 
450 	if (!is_cgx_config_permitted(rvu, pcifunc))
451 		return -EPERM;
452 
453 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
454 
455 	cgx_lmac_rx_tx_enable(rvu_cgx_pdata(cgx_id, rvu), lmac_id, start);
456 
457 	return 0;
458 }
459 
460 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc)
461 {
462 	int pf = rvu_get_pf(pcifunc);
463 	int i = 0, lmac_count = 0;
464 	u8 max_dmac_filters;
465 	u8 cgx_id, lmac_id;
466 	void *cgx_dev;
467 
468 	if (!is_cgx_config_permitted(rvu, pcifunc))
469 		return;
470 
471 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
472 	cgx_dev = cgx_get_pdata(cgx_id);
473 	lmac_count = cgx_get_lmac_cnt(cgx_dev);
474 	max_dmac_filters = MAX_DMAC_ENTRIES_PER_CGX / lmac_count;
475 
476 	for (i = 0; i < max_dmac_filters; i++)
477 		cgx_lmac_addr_del(cgx_id, lmac_id, i);
478 
479 	/* As cgx_lmac_addr_del does not clear entry for index 0
480 	 * so it needs to be done explicitly
481 	 */
482 	cgx_lmac_addr_reset(cgx_id, lmac_id);
483 }
484 
485 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req,
486 				    struct msg_rsp *rsp)
487 {
488 	rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, true);
489 	return 0;
490 }
491 
492 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req,
493 				   struct msg_rsp *rsp)
494 {
495 	rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false);
496 	return 0;
497 }
498 
499 static int rvu_lmac_get_stats(struct rvu *rvu, struct msg_req *req,
500 			      void *rsp)
501 {
502 	int pf = rvu_get_pf(req->hdr.pcifunc);
503 	struct mac_ops *mac_ops;
504 	int stat = 0, err = 0;
505 	u64 tx_stat, rx_stat;
506 	u8 cgx_idx, lmac;
507 	void *cgxd;
508 
509 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
510 		return -ENODEV;
511 
512 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
513 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
514 	mac_ops = get_mac_ops(cgxd);
515 
516 	/* Rx stats */
517 	while (stat < mac_ops->rx_stats_cnt) {
518 		err = mac_ops->mac_get_rx_stats(cgxd, lmac, stat, &rx_stat);
519 		if (err)
520 			return err;
521 		if (mac_ops->rx_stats_cnt == RPM_RX_STATS_COUNT)
522 			((struct rpm_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
523 		else
524 			((struct cgx_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
525 		stat++;
526 	}
527 
528 	/* Tx stats */
529 	stat = 0;
530 	while (stat < mac_ops->tx_stats_cnt) {
531 		err = mac_ops->mac_get_tx_stats(cgxd, lmac, stat, &tx_stat);
532 		if (err)
533 			return err;
534 		if (mac_ops->tx_stats_cnt == RPM_TX_STATS_COUNT)
535 			((struct rpm_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
536 		else
537 			((struct cgx_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
538 		stat++;
539 	}
540 	return 0;
541 }
542 
543 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req,
544 			       struct cgx_stats_rsp *rsp)
545 {
546 	return rvu_lmac_get_stats(rvu, req, (void *)rsp);
547 }
548 
549 int rvu_mbox_handler_rpm_stats(struct rvu *rvu, struct msg_req *req,
550 			       struct rpm_stats_rsp *rsp)
551 {
552 	return rvu_lmac_get_stats(rvu, req, (void *)rsp);
553 }
554 
555 int rvu_mbox_handler_cgx_fec_stats(struct rvu *rvu,
556 				   struct msg_req *req,
557 				   struct cgx_fec_stats_rsp *rsp)
558 {
559 	int pf = rvu_get_pf(req->hdr.pcifunc);
560 	u8 cgx_idx, lmac;
561 	void *cgxd;
562 
563 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
564 		return -EPERM;
565 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
566 
567 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
568 	return cgx_get_fec_stats(cgxd, lmac, rsp);
569 }
570 
571 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu,
572 				      struct cgx_mac_addr_set_or_get *req,
573 				      struct cgx_mac_addr_set_or_get *rsp)
574 {
575 	int pf = rvu_get_pf(req->hdr.pcifunc);
576 	u8 cgx_id, lmac_id;
577 
578 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
579 		return -EPERM;
580 
581 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
582 
583 	cgx_lmac_addr_set(cgx_id, lmac_id, req->mac_addr);
584 
585 	return 0;
586 }
587 
588 int rvu_mbox_handler_cgx_mac_addr_add(struct rvu *rvu,
589 				      struct cgx_mac_addr_add_req *req,
590 				      struct cgx_mac_addr_add_rsp *rsp)
591 {
592 	int pf = rvu_get_pf(req->hdr.pcifunc);
593 	u8 cgx_id, lmac_id;
594 	int rc = 0;
595 
596 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
597 		return -EPERM;
598 
599 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
600 	rc = cgx_lmac_addr_add(cgx_id, lmac_id, req->mac_addr);
601 	if (rc >= 0) {
602 		rsp->index = rc;
603 		return 0;
604 	}
605 
606 	return rc;
607 }
608 
609 int rvu_mbox_handler_cgx_mac_addr_del(struct rvu *rvu,
610 				      struct cgx_mac_addr_del_req *req,
611 				      struct msg_rsp *rsp)
612 {
613 	int pf = rvu_get_pf(req->hdr.pcifunc);
614 	u8 cgx_id, lmac_id;
615 
616 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
617 		return -EPERM;
618 
619 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
620 	return cgx_lmac_addr_del(cgx_id, lmac_id, req->index);
621 }
622 
623 int rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu *rvu,
624 					     struct msg_req *req,
625 					     struct cgx_max_dmac_entries_get_rsp
626 					     *rsp)
627 {
628 	int pf = rvu_get_pf(req->hdr.pcifunc);
629 	u8 cgx_id, lmac_id;
630 
631 	/* If msg is received from PFs(which are not mapped to CGX LMACs)
632 	 * or VF then no entries are allocated for DMAC filters at CGX level.
633 	 * So returning zero.
634 	 */
635 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) {
636 		rsp->max_dmac_filters = 0;
637 		return 0;
638 	}
639 
640 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
641 	rsp->max_dmac_filters = cgx_lmac_addr_max_entries_get(cgx_id, lmac_id);
642 	return 0;
643 }
644 
645 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu,
646 				      struct cgx_mac_addr_set_or_get *req,
647 				      struct cgx_mac_addr_set_or_get *rsp)
648 {
649 	int pf = rvu_get_pf(req->hdr.pcifunc);
650 	u8 cgx_id, lmac_id;
651 	int rc = 0, i;
652 	u64 cfg;
653 
654 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
655 		return -EPERM;
656 
657 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
658 
659 	rsp->hdr.rc = rc;
660 	cfg = cgx_lmac_addr_get(cgx_id, lmac_id);
661 	/* copy 48 bit mac address to req->mac_addr */
662 	for (i = 0; i < ETH_ALEN; i++)
663 		rsp->mac_addr[i] = cfg >> (ETH_ALEN - 1 - i) * 8;
664 	return 0;
665 }
666 
667 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req,
668 					struct msg_rsp *rsp)
669 {
670 	u16 pcifunc = req->hdr.pcifunc;
671 	int pf = rvu_get_pf(pcifunc);
672 	u8 cgx_id, lmac_id;
673 
674 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
675 		return -EPERM;
676 
677 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
678 
679 	cgx_lmac_promisc_config(cgx_id, lmac_id, true);
680 	return 0;
681 }
682 
683 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req,
684 					 struct msg_rsp *rsp)
685 {
686 	int pf = rvu_get_pf(req->hdr.pcifunc);
687 	u8 cgx_id, lmac_id;
688 
689 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
690 		return -EPERM;
691 
692 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
693 
694 	cgx_lmac_promisc_config(cgx_id, lmac_id, false);
695 	return 0;
696 }
697 
698 static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcifunc, bool enable)
699 {
700 	int pf = rvu_get_pf(pcifunc);
701 	u8 cgx_id, lmac_id;
702 	void *cgxd;
703 
704 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP))
705 		return 0;
706 
707 	/* This msg is expected only from PFs that are mapped to CGX LMACs,
708 	 * if received from other PF/VF simply ACK, nothing to do.
709 	 */
710 	if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
711 	    !is_pf_cgxmapped(rvu, pf))
712 		return -ENODEV;
713 
714 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
715 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
716 
717 	cgx_lmac_ptp_config(cgxd, lmac_id, enable);
718 	/* If PTP is enabled then inform NPC that packets to be
719 	 * parsed by this PF will have their data shifted by 8 bytes
720 	 * and if PTP is disabled then no shift is required
721 	 */
722 	if (npc_config_ts_kpuaction(rvu, pf, pcifunc, enable))
723 		return -EINVAL;
724 
725 	return 0;
726 }
727 
728 int rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu *rvu, struct msg_req *req,
729 				       struct msg_rsp *rsp)
730 {
731 	return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, true);
732 }
733 
734 int rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu *rvu, struct msg_req *req,
735 					struct msg_rsp *rsp)
736 {
737 	return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, false);
738 }
739 
740 static int rvu_cgx_config_linkevents(struct rvu *rvu, u16 pcifunc, bool en)
741 {
742 	int pf = rvu_get_pf(pcifunc);
743 	u8 cgx_id, lmac_id;
744 
745 	if (!is_cgx_config_permitted(rvu, pcifunc))
746 		return -EPERM;
747 
748 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
749 
750 	if (en) {
751 		set_bit(pf, &rvu->pf_notify_bmap);
752 		/* Send the current link status to PF */
753 		rvu_cgx_send_link_info(cgx_id, lmac_id, rvu);
754 	} else {
755 		clear_bit(pf, &rvu->pf_notify_bmap);
756 	}
757 
758 	return 0;
759 }
760 
761 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req,
762 					  struct msg_rsp *rsp)
763 {
764 	rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, true);
765 	return 0;
766 }
767 
768 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req,
769 					 struct msg_rsp *rsp)
770 {
771 	rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, false);
772 	return 0;
773 }
774 
775 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req,
776 				      struct cgx_link_info_msg *rsp)
777 {
778 	u8 cgx_id, lmac_id;
779 	int pf, err;
780 
781 	pf = rvu_get_pf(req->hdr.pcifunc);
782 
783 	if (!is_pf_cgxmapped(rvu, pf))
784 		return -ENODEV;
785 
786 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
787 
788 	err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
789 				&rsp->link_info);
790 	return err;
791 }
792 
793 int rvu_mbox_handler_cgx_features_get(struct rvu *rvu,
794 				      struct msg_req *req,
795 				      struct cgx_features_info_msg *rsp)
796 {
797 	int pf = rvu_get_pf(req->hdr.pcifunc);
798 	u8 cgx_idx, lmac;
799 	void *cgxd;
800 
801 	if (!is_pf_cgxmapped(rvu, pf))
802 		return 0;
803 
804 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
805 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
806 	rsp->lmac_features = cgx_features_get(cgxd);
807 
808 	return 0;
809 }
810 
811 u32 rvu_cgx_get_fifolen(struct rvu *rvu)
812 {
813 	struct mac_ops *mac_ops;
814 	u32 fifo_len;
815 
816 	mac_ops = get_mac_ops(rvu_first_cgx_pdata(rvu));
817 	fifo_len = mac_ops ? mac_ops->fifo_len : 0;
818 
819 	return fifo_len;
820 }
821 
822 static int rvu_cgx_config_intlbk(struct rvu *rvu, u16 pcifunc, bool en)
823 {
824 	int pf = rvu_get_pf(pcifunc);
825 	struct mac_ops *mac_ops;
826 	u8 cgx_id, lmac_id;
827 
828 	if (!is_cgx_config_permitted(rvu, pcifunc))
829 		return -EPERM;
830 
831 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
832 	mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu));
833 
834 	return mac_ops->mac_lmac_intl_lbk(rvu_cgx_pdata(cgx_id, rvu),
835 					  lmac_id, en);
836 }
837 
838 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req,
839 				       struct msg_rsp *rsp)
840 {
841 	rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, true);
842 	return 0;
843 }
844 
845 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req,
846 					struct msg_rsp *rsp)
847 {
848 	rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, false);
849 	return 0;
850 }
851 
852 int rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu *rvu,
853 				       struct cgx_pause_frm_cfg *req,
854 				       struct cgx_pause_frm_cfg *rsp)
855 {
856 	int pf = rvu_get_pf(req->hdr.pcifunc);
857 	struct mac_ops *mac_ops;
858 	u8 cgx_id, lmac_id;
859 	void *cgxd;
860 
861 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_FC))
862 		return 0;
863 
864 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
865 	 * if received from other PF/VF simply ACK, nothing to do.
866 	 */
867 	if (!is_pf_cgxmapped(rvu, pf))
868 		return -ENODEV;
869 
870 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
871 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
872 	mac_ops = get_mac_ops(cgxd);
873 
874 	if (req->set)
875 		mac_ops->mac_enadis_pause_frm(cgxd, lmac_id,
876 					      req->tx_pause, req->rx_pause);
877 	else
878 		mac_ops->mac_get_pause_frm_status(cgxd, lmac_id,
879 						  &rsp->tx_pause,
880 						  &rsp->rx_pause);
881 	return 0;
882 }
883 
884 int rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu *rvu, struct msg_req *req,
885 					   struct msg_rsp *rsp)
886 {
887 	int pf = rvu_get_pf(req->hdr.pcifunc);
888 	u8 cgx_id, lmac_id;
889 
890 	if (!is_pf_cgxmapped(rvu, pf))
891 		return -EPERM;
892 
893 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
894 	return cgx_get_phy_fec_stats(rvu_cgx_pdata(cgx_id, rvu), lmac_id);
895 }
896 
897 /* Finds cumulative status of NIX rx/tx counters from LF of a PF and those
898  * from its VFs as well. ie. NIX rx/tx counters at the CGX port level
899  */
900 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id,
901 			   int index, int rxtxflag, u64 *stat)
902 {
903 	struct rvu_block *block;
904 	int blkaddr;
905 	u16 pcifunc;
906 	int pf, lf;
907 
908 	*stat = 0;
909 
910 	if (!cgxd || !rvu)
911 		return -EINVAL;
912 
913 	pf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id);
914 	if (pf < 0)
915 		return pf;
916 
917 	/* Assumes LF of a PF and all of its VF belongs to the same
918 	 * NIX block
919 	 */
920 	pcifunc = pf << RVU_PFVF_PF_SHIFT;
921 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
922 	if (blkaddr < 0)
923 		return 0;
924 	block = &rvu->hw->block[blkaddr];
925 
926 	for (lf = 0; lf < block->lf.max; lf++) {
927 		/* Check if a lf is attached to this PF or one of its VFs */
928 		if (!((block->fn_map[lf] & ~RVU_PFVF_FUNC_MASK) == (pcifunc &
929 			 ~RVU_PFVF_FUNC_MASK)))
930 			continue;
931 		if (rxtxflag == NIX_STATS_RX)
932 			*stat += rvu_read64(rvu, blkaddr,
933 					    NIX_AF_LFX_RX_STATX(lf, index));
934 		else
935 			*stat += rvu_read64(rvu, blkaddr,
936 					    NIX_AF_LFX_TX_STATX(lf, index));
937 	}
938 
939 	return 0;
940 }
941 
942 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start)
943 {
944 	struct rvu_pfvf *parent_pf, *pfvf;
945 	int cgx_users, err = 0;
946 
947 	if (!is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
948 		return 0;
949 
950 	parent_pf = &rvu->pf[rvu_get_pf(pcifunc)];
951 	pfvf = rvu_get_pfvf(rvu, pcifunc);
952 
953 	mutex_lock(&rvu->cgx_cfg_lock);
954 
955 	if (start && pfvf->cgx_in_use)
956 		goto exit;  /* CGX is already started hence nothing to do */
957 	if (!start && !pfvf->cgx_in_use)
958 		goto exit; /* CGX is already stopped hence nothing to do */
959 
960 	if (start) {
961 		cgx_users = parent_pf->cgx_users;
962 		parent_pf->cgx_users++;
963 	} else {
964 		parent_pf->cgx_users--;
965 		cgx_users = parent_pf->cgx_users;
966 	}
967 
968 	/* Start CGX when first of all NIXLFs is started.
969 	 * Stop CGX when last of all NIXLFs is stopped.
970 	 */
971 	if (!cgx_users) {
972 		err = rvu_cgx_config_rxtx(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK,
973 					  start);
974 		if (err) {
975 			dev_err(rvu->dev, "Unable to %s CGX\n",
976 				start ? "start" : "stop");
977 			/* Revert the usage count in case of error */
978 			parent_pf->cgx_users = start ? parent_pf->cgx_users  - 1
979 					       : parent_pf->cgx_users  + 1;
980 			goto exit;
981 		}
982 	}
983 	pfvf->cgx_in_use = start;
984 exit:
985 	mutex_unlock(&rvu->cgx_cfg_lock);
986 	return err;
987 }
988 
989 int rvu_mbox_handler_cgx_set_fec_param(struct rvu *rvu,
990 				       struct fec_mode *req,
991 				       struct fec_mode *rsp)
992 {
993 	int pf = rvu_get_pf(req->hdr.pcifunc);
994 	u8 cgx_id, lmac_id;
995 
996 	if (!is_pf_cgxmapped(rvu, pf))
997 		return -EPERM;
998 
999 	if (req->fec == OTX2_FEC_OFF)
1000 		req->fec = OTX2_FEC_NONE;
1001 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1002 	rsp->fec = cgx_set_fec(req->fec, cgx_id, lmac_id);
1003 	return 0;
1004 }
1005 
1006 int rvu_mbox_handler_cgx_get_aux_link_info(struct rvu *rvu, struct msg_req *req,
1007 					   struct cgx_fw_data *rsp)
1008 {
1009 	int pf = rvu_get_pf(req->hdr.pcifunc);
1010 	u8 cgx_id, lmac_id;
1011 
1012 	if (!rvu->fwdata)
1013 		return -ENXIO;
1014 
1015 	if (!is_pf_cgxmapped(rvu, pf))
1016 		return -EPERM;
1017 
1018 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1019 
1020 	memcpy(&rsp->fwdata, &rvu->fwdata->cgx_fw_data[cgx_id][lmac_id],
1021 	       sizeof(struct cgx_lmac_fwdata_s));
1022 	return 0;
1023 }
1024 
1025 int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu,
1026 				       struct cgx_set_link_mode_req *req,
1027 				       struct cgx_set_link_mode_rsp *rsp)
1028 {
1029 	int pf = rvu_get_pf(req->hdr.pcifunc);
1030 	u8 cgx_idx, lmac;
1031 	void *cgxd;
1032 
1033 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1034 		return -EPERM;
1035 
1036 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
1037 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
1038 	rsp->status = cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac);
1039 	return 0;
1040 }
1041 
1042 int rvu_mbox_handler_cgx_mac_addr_reset(struct rvu *rvu, struct msg_req *req,
1043 					struct msg_rsp *rsp)
1044 {
1045 	int pf = rvu_get_pf(req->hdr.pcifunc);
1046 	u8 cgx_id, lmac_id;
1047 
1048 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1049 		return -EPERM;
1050 
1051 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1052 	return cgx_lmac_addr_reset(cgx_id, lmac_id);
1053 }
1054 
1055 int rvu_mbox_handler_cgx_mac_addr_update(struct rvu *rvu,
1056 					 struct cgx_mac_addr_update_req *req,
1057 					 struct msg_rsp *rsp)
1058 {
1059 	int pf = rvu_get_pf(req->hdr.pcifunc);
1060 	u8 cgx_id, lmac_id;
1061 
1062 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1063 		return -EPERM;
1064 
1065 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1066 	return cgx_lmac_addr_update(cgx_id, lmac_id, req->mac_addr, req->index);
1067 }
1068