1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/types.h> 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 15 #include "rvu.h" 16 #include "cgx.h" 17 #include "rvu_reg.h" 18 #include "rvu_trace.h" 19 20 struct cgx_evq_entry { 21 struct list_head evq_node; 22 struct cgx_link_event link_event; 23 }; 24 25 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 26 static struct _req_type __maybe_unused \ 27 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \ 28 { \ 29 struct _req_type *req; \ 30 \ 31 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 32 &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \ 33 sizeof(struct _rsp_type)); \ 34 if (!req) \ 35 return NULL; \ 36 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 37 req->hdr.id = _id; \ 38 trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req)); \ 39 return req; \ 40 } 41 42 MBOX_UP_CGX_MESSAGES 43 #undef M 44 45 /* Returns bitmap of mapped PFs */ 46 static u16 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id) 47 { 48 return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id]; 49 } 50 51 static int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id) 52 { 53 unsigned long pfmap; 54 55 pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id); 56 57 /* Assumes only one pf mapped to a cgx lmac port */ 58 if (!pfmap) 59 return -ENODEV; 60 else 61 return find_first_bit(&pfmap, 16); 62 } 63 64 static u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id) 65 { 66 return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF); 67 } 68 69 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu) 70 { 71 if (cgx_id >= rvu->cgx_cnt_max) 72 return NULL; 73 74 return rvu->cgx_idmap[cgx_id]; 75 } 76 77 /* Based on P2X connectivity find mapped NIX block for a PF */ 78 static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf, 79 int cgx_id, int lmac_id) 80 { 81 struct rvu_pfvf *pfvf = &rvu->pf[pf]; 82 u8 p2x; 83 84 p2x = cgx_lmac_get_p2x(cgx_id, lmac_id); 85 /* Firmware sets P2X_SELECT as either NIX0 or NIX1 */ 86 pfvf->nix_blkaddr = BLKADDR_NIX0; 87 if (p2x == CMR_P2X_SEL_NIX1) 88 pfvf->nix_blkaddr = BLKADDR_NIX1; 89 } 90 91 static int rvu_map_cgx_lmac_pf(struct rvu *rvu) 92 { 93 struct npc_pkind *pkind = &rvu->hw->pkind; 94 int cgx_cnt_max = rvu->cgx_cnt_max; 95 int cgx, lmac_cnt, lmac; 96 int pf = PF_CGXMAP_BASE; 97 int size, free_pkind; 98 99 if (!cgx_cnt_max) 100 return 0; 101 102 if (cgx_cnt_max > 0xF || MAX_LMAC_PER_CGX > 0xF) 103 return -EINVAL; 104 105 /* Alloc map table 106 * An additional entry is required since PF id starts from 1 and 107 * hence entry at offset 0 is invalid. 108 */ 109 size = (cgx_cnt_max * MAX_LMAC_PER_CGX + 1) * sizeof(u8); 110 rvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL); 111 if (!rvu->pf2cgxlmac_map) 112 return -ENOMEM; 113 114 /* Initialize all entries with an invalid cgx and lmac id */ 115 memset(rvu->pf2cgxlmac_map, 0xFF, size); 116 117 /* Reverse map table */ 118 rvu->cgxlmac2pf_map = devm_kzalloc(rvu->dev, 119 cgx_cnt_max * MAX_LMAC_PER_CGX * sizeof(u16), 120 GFP_KERNEL); 121 if (!rvu->cgxlmac2pf_map) 122 return -ENOMEM; 123 124 rvu->cgx_mapped_pfs = 0; 125 for (cgx = 0; cgx < cgx_cnt_max; cgx++) { 126 if (!rvu_cgx_pdata(cgx, rvu)) 127 continue; 128 lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); 129 for (lmac = 0; lmac < lmac_cnt; lmac++, pf++) { 130 rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac); 131 rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf; 132 free_pkind = rvu_alloc_rsrc(&pkind->rsrc); 133 pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16; 134 rvu_map_cgx_nix_block(rvu, pf, cgx, lmac); 135 rvu->cgx_mapped_pfs++; 136 } 137 } 138 return 0; 139 } 140 141 static int rvu_cgx_send_link_info(int cgx_id, int lmac_id, struct rvu *rvu) 142 { 143 struct cgx_evq_entry *qentry; 144 unsigned long flags; 145 int err; 146 147 qentry = kmalloc(sizeof(*qentry), GFP_KERNEL); 148 if (!qentry) 149 return -ENOMEM; 150 151 /* Lock the event queue before we read the local link status */ 152 spin_lock_irqsave(&rvu->cgx_evq_lock, flags); 153 err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id, 154 &qentry->link_event.link_uinfo); 155 qentry->link_event.cgx_id = cgx_id; 156 qentry->link_event.lmac_id = lmac_id; 157 if (err) 158 goto skip_add; 159 list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head); 160 skip_add: 161 spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags); 162 163 /* start worker to process the events */ 164 queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work); 165 166 return 0; 167 } 168 169 /* This is called from interrupt context and is expected to be atomic */ 170 static int cgx_lmac_postevent(struct cgx_link_event *event, void *data) 171 { 172 struct cgx_evq_entry *qentry; 173 struct rvu *rvu = data; 174 175 /* post event to the event queue */ 176 qentry = kmalloc(sizeof(*qentry), GFP_ATOMIC); 177 if (!qentry) 178 return -ENOMEM; 179 qentry->link_event = *event; 180 spin_lock(&rvu->cgx_evq_lock); 181 list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head); 182 spin_unlock(&rvu->cgx_evq_lock); 183 184 /* start worker to process the events */ 185 queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work); 186 187 return 0; 188 } 189 190 static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu) 191 { 192 struct cgx_link_user_info *linfo; 193 struct cgx_link_info_msg *msg; 194 unsigned long pfmap; 195 int err, pfid; 196 197 linfo = &event->link_uinfo; 198 pfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id); 199 200 do { 201 pfid = find_first_bit(&pfmap, 16); 202 clear_bit(pfid, &pfmap); 203 204 /* check if notification is enabled */ 205 if (!test_bit(pfid, &rvu->pf_notify_bmap)) { 206 dev_info(rvu->dev, "cgx %d: lmac %d Link status %s\n", 207 event->cgx_id, event->lmac_id, 208 linfo->link_up ? "UP" : "DOWN"); 209 continue; 210 } 211 212 /* Send mbox message to PF */ 213 msg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid); 214 if (!msg) 215 continue; 216 msg->link_info = *linfo; 217 otx2_mbox_msg_send(&rvu->afpf_wq_info.mbox_up, pfid); 218 err = otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, pfid); 219 if (err) 220 dev_warn(rvu->dev, "notification to pf %d failed\n", 221 pfid); 222 } while (pfmap); 223 } 224 225 static void cgx_evhandler_task(struct work_struct *work) 226 { 227 struct rvu *rvu = container_of(work, struct rvu, cgx_evh_work); 228 struct cgx_evq_entry *qentry; 229 struct cgx_link_event *event; 230 unsigned long flags; 231 232 do { 233 /* Dequeue an event */ 234 spin_lock_irqsave(&rvu->cgx_evq_lock, flags); 235 qentry = list_first_entry_or_null(&rvu->cgx_evq_head, 236 struct cgx_evq_entry, 237 evq_node); 238 if (qentry) 239 list_del(&qentry->evq_node); 240 spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags); 241 if (!qentry) 242 break; /* nothing more to process */ 243 244 event = &qentry->link_event; 245 246 /* process event */ 247 cgx_notify_pfs(event, rvu); 248 kfree(qentry); 249 } while (1); 250 } 251 252 static int cgx_lmac_event_handler_init(struct rvu *rvu) 253 { 254 struct cgx_event_cb cb; 255 int cgx, lmac, err; 256 void *cgxd; 257 258 spin_lock_init(&rvu->cgx_evq_lock); 259 INIT_LIST_HEAD(&rvu->cgx_evq_head); 260 INIT_WORK(&rvu->cgx_evh_work, cgx_evhandler_task); 261 rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0); 262 if (!rvu->cgx_evh_wq) { 263 dev_err(rvu->dev, "alloc workqueue failed"); 264 return -ENOMEM; 265 } 266 267 cb.notify_link_chg = cgx_lmac_postevent; /* link change call back */ 268 cb.data = rvu; 269 270 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) { 271 cgxd = rvu_cgx_pdata(cgx, rvu); 272 if (!cgxd) 273 continue; 274 for (lmac = 0; lmac < cgx_get_lmac_cnt(cgxd); lmac++) { 275 err = cgx_lmac_evh_register(&cb, cgxd, lmac); 276 if (err) 277 dev_err(rvu->dev, 278 "%d:%d handler register failed\n", 279 cgx, lmac); 280 } 281 } 282 283 return 0; 284 } 285 286 static void rvu_cgx_wq_destroy(struct rvu *rvu) 287 { 288 if (rvu->cgx_evh_wq) { 289 flush_workqueue(rvu->cgx_evh_wq); 290 destroy_workqueue(rvu->cgx_evh_wq); 291 rvu->cgx_evh_wq = NULL; 292 } 293 } 294 295 int rvu_cgx_init(struct rvu *rvu) 296 { 297 int cgx, err; 298 void *cgxd; 299 300 /* CGX port id starts from 0 and are not necessarily contiguous 301 * Hence we allocate resources based on the maximum port id value. 302 */ 303 rvu->cgx_cnt_max = cgx_get_cgxcnt_max(); 304 if (!rvu->cgx_cnt_max) { 305 dev_info(rvu->dev, "No CGX devices found!\n"); 306 return -ENODEV; 307 } 308 309 rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt_max * 310 sizeof(void *), GFP_KERNEL); 311 if (!rvu->cgx_idmap) 312 return -ENOMEM; 313 314 /* Initialize the cgxdata table */ 315 for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++) 316 rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx); 317 318 /* Map CGX LMAC interfaces to RVU PFs */ 319 err = rvu_map_cgx_lmac_pf(rvu); 320 if (err) 321 return err; 322 323 /* Register for CGX events */ 324 err = cgx_lmac_event_handler_init(rvu); 325 if (err) 326 return err; 327 328 mutex_init(&rvu->cgx_cfg_lock); 329 330 /* Ensure event handler registration is completed, before 331 * we turn on the links 332 */ 333 mb(); 334 335 /* Do link up for all CGX ports */ 336 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) { 337 cgxd = rvu_cgx_pdata(cgx, rvu); 338 if (!cgxd) 339 continue; 340 err = cgx_lmac_linkup_start(cgxd); 341 if (err) 342 dev_err(rvu->dev, 343 "Link up process failed to start on cgx %d\n", 344 cgx); 345 } 346 347 return 0; 348 } 349 350 int rvu_cgx_exit(struct rvu *rvu) 351 { 352 int cgx, lmac; 353 void *cgxd; 354 355 for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) { 356 cgxd = rvu_cgx_pdata(cgx, rvu); 357 if (!cgxd) 358 continue; 359 for (lmac = 0; lmac < cgx_get_lmac_cnt(cgxd); lmac++) 360 cgx_lmac_evh_unregister(cgxd, lmac); 361 } 362 363 /* Ensure event handler unregister is completed */ 364 mb(); 365 366 rvu_cgx_wq_destroy(rvu); 367 return 0; 368 } 369 370 /* Most of the CGX configuration is restricted to the mapped PF only, 371 * VF's of mapped PF and other PFs are not allowed. This fn() checks 372 * whether a PFFUNC is permitted to do the config or not. 373 */ 374 static bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc) 375 { 376 if ((pcifunc & RVU_PFVF_FUNC_MASK) || 377 !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) 378 return false; 379 return true; 380 } 381 382 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable) 383 { 384 u8 cgx_id, lmac_id; 385 void *cgxd; 386 387 if (!is_pf_cgxmapped(rvu, pf)) 388 return; 389 390 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 391 cgxd = rvu_cgx_pdata(cgx_id, rvu); 392 393 /* Set / clear CTL_BCK to control pause frame forwarding to NIX */ 394 if (enable) 395 cgx_lmac_enadis_rx_pause_fwding(cgxd, lmac_id, true); 396 else 397 cgx_lmac_enadis_rx_pause_fwding(cgxd, lmac_id, false); 398 } 399 400 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start) 401 { 402 int pf = rvu_get_pf(pcifunc); 403 u8 cgx_id, lmac_id; 404 405 if (!is_cgx_config_permitted(rvu, pcifunc)) 406 return -EPERM; 407 408 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 409 410 cgx_lmac_rx_tx_enable(rvu_cgx_pdata(cgx_id, rvu), lmac_id, start); 411 412 return 0; 413 } 414 415 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req, 416 struct msg_rsp *rsp) 417 { 418 rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, true); 419 return 0; 420 } 421 422 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req, 423 struct msg_rsp *rsp) 424 { 425 rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false); 426 return 0; 427 } 428 429 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req, 430 struct cgx_stats_rsp *rsp) 431 { 432 int pf = rvu_get_pf(req->hdr.pcifunc); 433 int stat = 0, err = 0; 434 u64 tx_stat, rx_stat; 435 u8 cgx_idx, lmac; 436 void *cgxd; 437 438 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 439 return -ENODEV; 440 441 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac); 442 cgxd = rvu_cgx_pdata(cgx_idx, rvu); 443 444 /* Rx stats */ 445 while (stat < CGX_RX_STATS_COUNT) { 446 err = cgx_get_rx_stats(cgxd, lmac, stat, &rx_stat); 447 if (err) 448 return err; 449 rsp->rx_stats[stat] = rx_stat; 450 stat++; 451 } 452 453 /* Tx stats */ 454 stat = 0; 455 while (stat < CGX_TX_STATS_COUNT) { 456 err = cgx_get_tx_stats(cgxd, lmac, stat, &tx_stat); 457 if (err) 458 return err; 459 rsp->tx_stats[stat] = tx_stat; 460 stat++; 461 } 462 return 0; 463 } 464 465 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu, 466 struct cgx_mac_addr_set_or_get *req, 467 struct cgx_mac_addr_set_or_get *rsp) 468 { 469 int pf = rvu_get_pf(req->hdr.pcifunc); 470 u8 cgx_id, lmac_id; 471 472 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 473 474 cgx_lmac_addr_set(cgx_id, lmac_id, req->mac_addr); 475 476 return 0; 477 } 478 479 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu, 480 struct cgx_mac_addr_set_or_get *req, 481 struct cgx_mac_addr_set_or_get *rsp) 482 { 483 int pf = rvu_get_pf(req->hdr.pcifunc); 484 u8 cgx_id, lmac_id; 485 int rc = 0, i; 486 u64 cfg; 487 488 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 489 490 rsp->hdr.rc = rc; 491 cfg = cgx_lmac_addr_get(cgx_id, lmac_id); 492 /* copy 48 bit mac address to req->mac_addr */ 493 for (i = 0; i < ETH_ALEN; i++) 494 rsp->mac_addr[i] = cfg >> (ETH_ALEN - 1 - i) * 8; 495 return 0; 496 } 497 498 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req, 499 struct msg_rsp *rsp) 500 { 501 u16 pcifunc = req->hdr.pcifunc; 502 int pf = rvu_get_pf(pcifunc); 503 u8 cgx_id, lmac_id; 504 505 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 506 return -EPERM; 507 508 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 509 510 cgx_lmac_promisc_config(cgx_id, lmac_id, true); 511 return 0; 512 } 513 514 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req, 515 struct msg_rsp *rsp) 516 { 517 int pf = rvu_get_pf(req->hdr.pcifunc); 518 u8 cgx_id, lmac_id; 519 520 if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) 521 return -EPERM; 522 523 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 524 525 cgx_lmac_promisc_config(cgx_id, lmac_id, false); 526 return 0; 527 } 528 529 static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcifunc, bool enable) 530 { 531 int pf = rvu_get_pf(pcifunc); 532 u8 cgx_id, lmac_id; 533 void *cgxd; 534 535 /* This msg is expected only from PFs that are mapped to CGX LMACs, 536 * if received from other PF/VF simply ACK, nothing to do. 537 */ 538 if ((pcifunc & RVU_PFVF_FUNC_MASK) || 539 !is_pf_cgxmapped(rvu, pf)) 540 return -ENODEV; 541 542 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 543 cgxd = rvu_cgx_pdata(cgx_id, rvu); 544 545 cgx_lmac_ptp_config(cgxd, lmac_id, enable); 546 /* If PTP is enabled then inform NPC that packets to be 547 * parsed by this PF will have their data shifted by 8 bytes 548 * and if PTP is disabled then no shift is required 549 */ 550 if (npc_config_ts_kpuaction(rvu, pf, pcifunc, enable)) 551 return -EINVAL; 552 553 return 0; 554 } 555 556 int rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu *rvu, struct msg_req *req, 557 struct msg_rsp *rsp) 558 { 559 return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, true); 560 } 561 562 int rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu *rvu, struct msg_req *req, 563 struct msg_rsp *rsp) 564 { 565 return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, false); 566 } 567 568 static int rvu_cgx_config_linkevents(struct rvu *rvu, u16 pcifunc, bool en) 569 { 570 int pf = rvu_get_pf(pcifunc); 571 u8 cgx_id, lmac_id; 572 573 if (!is_cgx_config_permitted(rvu, pcifunc)) 574 return -EPERM; 575 576 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 577 578 if (en) { 579 set_bit(pf, &rvu->pf_notify_bmap); 580 /* Send the current link status to PF */ 581 rvu_cgx_send_link_info(cgx_id, lmac_id, rvu); 582 } else { 583 clear_bit(pf, &rvu->pf_notify_bmap); 584 } 585 586 return 0; 587 } 588 589 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req, 590 struct msg_rsp *rsp) 591 { 592 rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, true); 593 return 0; 594 } 595 596 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req, 597 struct msg_rsp *rsp) 598 { 599 rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, false); 600 return 0; 601 } 602 603 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req, 604 struct cgx_link_info_msg *rsp) 605 { 606 u8 cgx_id, lmac_id; 607 int pf, err; 608 609 pf = rvu_get_pf(req->hdr.pcifunc); 610 611 if (!is_pf_cgxmapped(rvu, pf)) 612 return -ENODEV; 613 614 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 615 616 err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id, 617 &rsp->link_info); 618 return err; 619 } 620 621 static int rvu_cgx_config_intlbk(struct rvu *rvu, u16 pcifunc, bool en) 622 { 623 int pf = rvu_get_pf(pcifunc); 624 u8 cgx_id, lmac_id; 625 626 if (!is_cgx_config_permitted(rvu, pcifunc)) 627 return -EPERM; 628 629 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 630 631 return cgx_lmac_internal_loopback(rvu_cgx_pdata(cgx_id, rvu), 632 lmac_id, en); 633 } 634 635 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req, 636 struct msg_rsp *rsp) 637 { 638 rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, true); 639 return 0; 640 } 641 642 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req, 643 struct msg_rsp *rsp) 644 { 645 rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, false); 646 return 0; 647 } 648 649 int rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu *rvu, 650 struct cgx_pause_frm_cfg *req, 651 struct cgx_pause_frm_cfg *rsp) 652 { 653 int pf = rvu_get_pf(req->hdr.pcifunc); 654 u8 cgx_id, lmac_id; 655 656 /* This msg is expected only from PF/VFs that are mapped to CGX LMACs, 657 * if received from other PF/VF simply ACK, nothing to do. 658 */ 659 if (!is_pf_cgxmapped(rvu, pf)) 660 return -ENODEV; 661 662 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); 663 664 if (req->set) 665 cgx_lmac_set_pause_frm(rvu_cgx_pdata(cgx_id, rvu), lmac_id, 666 req->tx_pause, req->rx_pause); 667 else 668 cgx_lmac_get_pause_frm(rvu_cgx_pdata(cgx_id, rvu), lmac_id, 669 &rsp->tx_pause, &rsp->rx_pause); 670 return 0; 671 } 672 673 /* Finds cumulative status of NIX rx/tx counters from LF of a PF and those 674 * from its VFs as well. ie. NIX rx/tx counters at the CGX port level 675 */ 676 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, 677 int index, int rxtxflag, u64 *stat) 678 { 679 struct rvu_block *block; 680 int blkaddr; 681 u16 pcifunc; 682 int pf, lf; 683 684 *stat = 0; 685 686 if (!cgxd || !rvu) 687 return -EINVAL; 688 689 pf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id); 690 if (pf < 0) 691 return pf; 692 693 /* Assumes LF of a PF and all of its VF belongs to the same 694 * NIX block 695 */ 696 pcifunc = pf << RVU_PFVF_PF_SHIFT; 697 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 698 if (blkaddr < 0) 699 return 0; 700 block = &rvu->hw->block[blkaddr]; 701 702 for (lf = 0; lf < block->lf.max; lf++) { 703 /* Check if a lf is attached to this PF or one of its VFs */ 704 if (!((block->fn_map[lf] & ~RVU_PFVF_FUNC_MASK) == (pcifunc & 705 ~RVU_PFVF_FUNC_MASK))) 706 continue; 707 if (rxtxflag == NIX_STATS_RX) 708 *stat += rvu_read64(rvu, blkaddr, 709 NIX_AF_LFX_RX_STATX(lf, index)); 710 else 711 *stat += rvu_read64(rvu, blkaddr, 712 NIX_AF_LFX_TX_STATX(lf, index)); 713 } 714 715 return 0; 716 } 717 718 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start) 719 { 720 struct rvu_pfvf *parent_pf, *pfvf; 721 int cgx_users, err = 0; 722 723 if (!is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) 724 return 0; 725 726 parent_pf = &rvu->pf[rvu_get_pf(pcifunc)]; 727 pfvf = rvu_get_pfvf(rvu, pcifunc); 728 729 mutex_lock(&rvu->cgx_cfg_lock); 730 731 if (start && pfvf->cgx_in_use) 732 goto exit; /* CGX is already started hence nothing to do */ 733 if (!start && !pfvf->cgx_in_use) 734 goto exit; /* CGX is already stopped hence nothing to do */ 735 736 if (start) { 737 cgx_users = parent_pf->cgx_users; 738 parent_pf->cgx_users++; 739 } else { 740 parent_pf->cgx_users--; 741 cgx_users = parent_pf->cgx_users; 742 } 743 744 /* Start CGX when first of all NIXLFs is started. 745 * Stop CGX when last of all NIXLFs is stopped. 746 */ 747 if (!cgx_users) { 748 err = rvu_cgx_config_rxtx(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK, 749 start); 750 if (err) { 751 dev_err(rvu->dev, "Unable to %s CGX\n", 752 start ? "start" : "stop"); 753 /* Revert the usage count in case of error */ 754 parent_pf->cgx_users = start ? parent_pf->cgx_users - 1 755 : parent_pf->cgx_users + 1; 756 goto exit; 757 } 758 } 759 pfvf->cgx_in_use = start; 760 exit: 761 mutex_unlock(&rvu->cgx_cfg_lock); 762 return err; 763 } 764