1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef RVU_H 12 #define RVU_H 13 14 #include <linux/pci.h> 15 #include <net/devlink.h> 16 17 #include "rvu_struct.h" 18 #include "rvu_devlink.h" 19 #include "common.h" 20 #include "mbox.h" 21 #include "npc.h" 22 #include "rvu_reg.h" 23 24 /* PCI device IDs */ 25 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 26 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 27 28 /* Subsystem Device ID */ 29 #define PCI_SUBSYS_DEVID_96XX 0xB200 30 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 31 32 /* PCI BAR nos */ 33 #define PCI_AF_REG_BAR_NUM 0 34 #define PCI_PF_REG_BAR_NUM 2 35 #define PCI_MBOX_BAR_NUM 4 36 37 #define NAME_SIZE 32 38 #define MAX_NIX_BLKS 2 39 #define MAX_CPT_BLKS 2 40 41 /* PF_FUNC */ 42 #define RVU_PFVF_PF_SHIFT 10 43 #define RVU_PFVF_PF_MASK 0x3F 44 #define RVU_PFVF_FUNC_SHIFT 0 45 #define RVU_PFVF_FUNC_MASK 0x3FF 46 47 #ifdef CONFIG_DEBUG_FS 48 struct dump_ctx { 49 int lf; 50 int id; 51 bool all; 52 }; 53 54 struct cpt_ctx { 55 int blkaddr; 56 struct rvu *rvu; 57 }; 58 59 struct rvu_debugfs { 60 struct dentry *root; 61 struct dentry *cgx_root; 62 struct dentry *cgx; 63 struct dentry *lmac; 64 struct dentry *npa; 65 struct dentry *nix; 66 struct dentry *npc; 67 struct dentry *cpt; 68 struct dump_ctx npa_aura_ctx; 69 struct dump_ctx npa_pool_ctx; 70 struct dump_ctx nix_cq_ctx; 71 struct dump_ctx nix_rq_ctx; 72 struct dump_ctx nix_sq_ctx; 73 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 74 int npa_qsize_id; 75 int nix_qsize_id; 76 }; 77 #endif 78 79 struct rvu_work { 80 struct work_struct work; 81 struct rvu *rvu; 82 int num_msgs; 83 int up_num_msgs; 84 }; 85 86 struct rsrc_bmap { 87 unsigned long *bmap; /* Pointer to resource bitmap */ 88 u16 max; /* Max resource id or count */ 89 }; 90 91 struct rvu_block { 92 struct rsrc_bmap lf; 93 struct admin_queue *aq; /* NIX/NPA AQ */ 94 u16 *fn_map; /* LF to pcifunc mapping */ 95 bool multislot; 96 bool implemented; 97 u8 addr; /* RVU_BLOCK_ADDR_E */ 98 u8 type; /* RVU_BLOCK_TYPE_E */ 99 u8 lfshift; 100 u64 lookup_reg; 101 u64 pf_lfcnt_reg; 102 u64 vf_lfcnt_reg; 103 u64 lfcfg_reg; 104 u64 msixcfg_reg; 105 u64 lfreset_reg; 106 unsigned char name[NAME_SIZE]; 107 }; 108 109 struct nix_mcast { 110 struct qmem *mce_ctx; 111 struct qmem *mcast_buf; 112 int replay_pkind; 113 int next_free_mce; 114 struct mutex mce_lock; /* Serialize MCE updates */ 115 }; 116 117 struct nix_mce_list { 118 struct hlist_head head; 119 int count; 120 int max; 121 }; 122 123 /* layer metadata to uniquely identify a packet header field */ 124 struct npc_layer_mdata { 125 u8 lid; 126 u8 ltype; 127 u8 hdr; 128 u8 key; 129 u8 len; 130 }; 131 132 /* Structure to represent a field present in the 133 * generated key. A key field may present anywhere and can 134 * be of any size in the generated key. Once this structure 135 * is populated for fields of interest then field's presence 136 * and location (if present) can be known. 137 */ 138 struct npc_key_field { 139 /* Masks where all set bits indicate position 140 * of a field in the key 141 */ 142 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 143 /* Number of words in the key a field spans. If a field is 144 * of 16 bytes and key offset is 4 then the field will use 145 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 146 * nr_kws will be 3(KW0, KW1 and KW2). 147 */ 148 int nr_kws; 149 /* used by packet header fields */ 150 struct npc_layer_mdata layer_mdata; 151 }; 152 153 struct npc_mcam { 154 struct rsrc_bmap counters; 155 struct mutex lock; /* MCAM entries and counters update lock */ 156 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 157 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 158 u16 bmap_entries; /* Number of unreserved MCAM entries */ 159 u16 bmap_fcnt; /* MCAM entries free count */ 160 u16 *entry2pfvf_map; 161 u16 *entry2cntr_map; 162 u16 *cntr2pfvf_map; 163 u16 *cntr_refcnt; 164 u16 *entry2target_pffunc; 165 u8 keysize; /* MCAM keysize 112/224/448 bits */ 166 u8 banks; /* Number of MCAM banks */ 167 u8 banks_per_entry;/* Number of keywords in key */ 168 u16 banksize; /* Number of MCAM entries in each bank */ 169 u16 total_entries; /* Total number of MCAM entries */ 170 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 171 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 172 u16 lprio_count; 173 u16 lprio_start; 174 u16 hprio_count; 175 u16 hprio_end; 176 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 177 /* fields present in the generated key */ 178 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 179 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 180 u64 tx_features; 181 u64 rx_features; 182 struct list_head mcam_rules; 183 }; 184 185 /* Structure for per RVU func info ie PF/VF */ 186 struct rvu_pfvf { 187 bool npalf; /* Only one NPALF per RVU_FUNC */ 188 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 189 u16 sso; 190 u16 ssow; 191 u16 cptlfs; 192 u16 timlfs; 193 u16 cpt1_lfs; 194 u8 cgx_lmac; 195 196 /* Block LF's MSIX vector info */ 197 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 198 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 199 u16 *msix_lfmap; /* Vector to block LF mapping */ 200 201 /* NPA contexts */ 202 struct qmem *aura_ctx; 203 struct qmem *pool_ctx; 204 struct qmem *npa_qints_ctx; 205 unsigned long *aura_bmap; 206 unsigned long *pool_bmap; 207 208 /* NIX contexts */ 209 struct qmem *rq_ctx; 210 struct qmem *sq_ctx; 211 struct qmem *cq_ctx; 212 struct qmem *rss_ctx; 213 struct qmem *cq_ints_ctx; 214 struct qmem *nix_qints_ctx; 215 unsigned long *sq_bmap; 216 unsigned long *rq_bmap; 217 unsigned long *cq_bmap; 218 219 u16 rx_chan_base; 220 u16 tx_chan_base; 221 u8 rx_chan_cnt; /* total number of RX channels */ 222 u8 tx_chan_cnt; /* total number of TX channels */ 223 u16 maxlen; 224 u16 minlen; 225 226 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 227 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 228 229 /* Broadcast/Multicast/Promisc pkt replication info */ 230 u16 bcast_mce_idx; 231 u16 mcast_mce_idx; 232 u16 promisc_mce_idx; 233 struct nix_mce_list bcast_mce_list; 234 struct nix_mce_list mcast_mce_list; 235 struct nix_mce_list promisc_mce_list; 236 bool use_mce_list; 237 238 struct rvu_npc_mcam_rule *def_ucast_rule; 239 240 bool cgx_in_use; /* this PF/VF using CGX? */ 241 int cgx_users; /* number of cgx users - used only by PFs */ 242 243 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 244 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 245 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 246 u8 lbkid; /* NIX0/1 lbk link ID */ 247 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 248 unsigned long flags; 249 struct sdp_node_info *sdp_info; 250 }; 251 252 enum rvu_pfvf_flags { 253 NIXLF_INITIALIZED = 0, 254 PF_SET_VF_MAC, 255 PF_SET_VF_CFG, 256 PF_SET_VF_TRUSTED, 257 }; 258 259 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 260 261 struct nix_txsch { 262 struct rsrc_bmap schq; 263 u8 lvl; 264 #define NIX_TXSCHQ_FREE BIT_ULL(1) 265 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 266 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 267 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 268 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 269 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 270 u32 *pfvf_map; 271 }; 272 273 struct nix_mark_format { 274 u8 total; 275 u8 in_use; 276 u32 *cfg; 277 }; 278 279 struct npc_pkind { 280 struct rsrc_bmap rsrc; 281 u32 *pfchan_map; 282 }; 283 284 struct nix_flowkey { 285 #define NIX_FLOW_KEY_ALG_MAX 32 286 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 287 int in_use; 288 }; 289 290 struct nix_lso { 291 u8 total; 292 u8 in_use; 293 }; 294 295 struct nix_txvlan { 296 #define NIX_TX_VTAG_DEF_MAX 0x400 297 struct rsrc_bmap rsrc; 298 u16 *entry2pfvf_map; 299 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 300 }; 301 302 struct nix_ipolicer { 303 struct rsrc_bmap band_prof; 304 u16 *pfvf_map; 305 u16 *match_id; 306 u16 *ref_count; 307 }; 308 309 struct nix_hw { 310 int blkaddr; 311 struct rvu *rvu; 312 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 313 struct nix_mcast mcast; 314 struct nix_flowkey flowkey; 315 struct nix_mark_format mark_format; 316 struct nix_lso lso; 317 struct nix_txvlan txvlan; 318 struct nix_ipolicer *ipolicer; 319 u64 *tx_credits; 320 }; 321 322 /* RVU block's capabilities or functionality, 323 * which vary by silicon version/skew. 324 */ 325 struct hw_cap { 326 /* Transmit side supported functionality */ 327 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 328 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 329 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 330 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 331 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 332 bool nix_shaping; /* Is shaping and coloring supported */ 333 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 334 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 335 bool nix_rx_multicast; /* Rx packet replication support */ 336 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 337 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 338 bool programmable_chans; /* Channels programmable ? */ 339 bool ipolicer; 340 }; 341 342 struct rvu_hwinfo { 343 u8 total_pfs; /* MAX RVU PFs HW supports */ 344 u16 total_vfs; /* Max RVU VFs HW supports */ 345 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 346 u8 cgx; 347 u8 lmac_per_cgx; 348 u16 cgx_chan_base; /* CGX base channel number */ 349 u16 lbk_chan_base; /* LBK base channel number */ 350 u16 sdp_chan_base; /* SDP base channel number */ 351 u16 cpt_chan_base; /* CPT base channel number */ 352 u8 cgx_links; 353 u8 lbk_links; 354 u8 sdp_links; 355 u8 cpt_links; /* Number of CPT links */ 356 u8 npc_kpus; /* No of parser units */ 357 u8 npc_pkinds; /* No of port kinds */ 358 u8 npc_intfs; /* No of interfaces */ 359 u8 npc_kpu_entries; /* No of KPU entries */ 360 u16 npc_counters; /* No of match stats counters */ 361 u32 lbk_bufsize; /* FIFO size supported by LBK */ 362 bool npc_ext_set; /* Extended register set */ 363 u64 npc_stat_ena; /* Match stats enable bit */ 364 365 struct hw_cap cap; 366 struct rvu_block block[BLK_COUNT]; /* Block info */ 367 struct nix_hw *nix; 368 struct rvu *rvu; 369 struct npc_pkind pkind; 370 struct npc_mcam mcam; 371 }; 372 373 struct mbox_wq_info { 374 struct otx2_mbox mbox; 375 struct rvu_work *mbox_wrk; 376 377 struct otx2_mbox mbox_up; 378 struct rvu_work *mbox_wrk_up; 379 380 struct workqueue_struct *mbox_wq; 381 }; 382 383 struct rvu_fwdata { 384 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 385 #define RVU_FWDATA_VERSION 0x0001 386 u32 header_magic; 387 u32 version; /* version id */ 388 389 /* MAC address */ 390 #define PF_MACNUM_MAX 32 391 #define VF_MACNUM_MAX 256 392 u64 pf_macs[PF_MACNUM_MAX]; 393 u64 vf_macs[VF_MACNUM_MAX]; 394 u64 sclk; 395 u64 rclk; 396 u64 mcam_addr; 397 u64 mcam_sz; 398 u64 msixtr_base; 399 #define FWDATA_RESERVED_MEM 1023 400 u64 reserved[FWDATA_RESERVED_MEM]; 401 #define CGX_MAX 5 402 #define CGX_LMACS_MAX 4 403 struct cgx_lmac_fwdata_s cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 404 /* Do not add new fields below this line */ 405 }; 406 407 struct ptp; 408 409 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 410 * source where it came from. 411 */ 412 struct npc_kpu_profile_adapter { 413 const char *name; 414 u64 version; 415 const struct npc_lt_def_cfg *lt_def; 416 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 417 const struct npc_kpu_profile *kpu; /* array[kpus] */ 418 struct npc_mcam_kex *mkex; 419 bool custom; 420 size_t pkinds; 421 size_t kpus; 422 }; 423 424 #define RVU_SWITCH_LBK_CHAN 63 425 426 struct rvu_switch { 427 struct mutex switch_lock; /* Serialize flow installation */ 428 u32 used_entries; 429 u16 *entry2pcifunc; 430 u16 mode; 431 u16 start_entry; 432 }; 433 434 struct rvu { 435 void __iomem *afreg_base; 436 void __iomem *pfreg_base; 437 struct pci_dev *pdev; 438 struct device *dev; 439 struct rvu_hwinfo *hw; 440 struct rvu_pfvf *pf; 441 struct rvu_pfvf *hwvf; 442 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 443 int vfs; /* Number of VFs attached to RVU */ 444 int nix_blkaddr[MAX_NIX_BLKS]; 445 446 /* Mbox */ 447 struct mbox_wq_info afpf_wq_info; 448 struct mbox_wq_info afvf_wq_info; 449 450 /* PF FLR */ 451 struct rvu_work *flr_wrk; 452 struct workqueue_struct *flr_wq; 453 struct mutex flr_lock; /* Serialize FLRs */ 454 455 /* MSI-X */ 456 u16 num_vec; 457 char *irq_name; 458 bool *irq_allocated; 459 dma_addr_t msix_base_iova; 460 u64 msixtr_base_phy; /* Register reset value */ 461 462 /* CGX */ 463 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 464 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 465 u8 cgx_mapped_pfs; 466 u8 cgx_cnt_max; /* CGX port count max */ 467 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 468 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 469 * every cgx lmac port 470 */ 471 unsigned long pf_notify_bmap; /* Flags for PF notification */ 472 void **cgx_idmap; /* cgx id to cgx data map table */ 473 struct work_struct cgx_evh_work; 474 struct workqueue_struct *cgx_evh_wq; 475 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 476 struct list_head cgx_evq_head; /* cgx event queue head */ 477 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 478 479 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 480 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 481 482 /* Firmware data */ 483 struct rvu_fwdata *fwdata; 484 void *kpu_fwdata; 485 size_t kpu_fwdata_sz; 486 void __iomem *kpu_prfl_addr; 487 488 /* NPC KPU data */ 489 struct npc_kpu_profile_adapter kpu; 490 491 struct ptp *ptp; 492 493 #ifdef CONFIG_DEBUG_FS 494 struct rvu_debugfs rvu_dbg; 495 #endif 496 struct rvu_devlink *rvu_dl; 497 498 /* RVU switch implementation over NPC with DMAC rules */ 499 struct rvu_switch rswitch; 500 }; 501 502 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 503 { 504 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 505 } 506 507 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 508 { 509 return readq(rvu->afreg_base + ((block << 28) | offset)); 510 } 511 512 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 513 { 514 writeq(val, rvu->pfreg_base + offset); 515 } 516 517 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 518 { 519 return readq(rvu->pfreg_base + offset); 520 } 521 522 /* Silicon revisions */ 523 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 524 { 525 struct pci_dev *pdev = rvu->pdev; 526 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 527 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 528 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 529 (pdev->revision == 0x14)); 530 } 531 532 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 533 { 534 struct pci_dev *pdev = rvu->pdev; 535 536 return (pdev->revision == 0x00); 537 } 538 539 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 540 { 541 struct pci_dev *pdev = rvu->pdev; 542 543 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 544 } 545 546 static inline bool is_rvu_95xx_A0(struct rvu *rvu) 547 { 548 struct pci_dev *pdev = rvu->pdev; 549 550 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 551 } 552 553 /* REVID for PCIe devices. 554 * Bits 0..1: minor pass, bit 3..2: major pass 555 * bits 7..4: midr id 556 */ 557 #define PCI_REVISION_ID_96XX 0x00 558 #define PCI_REVISION_ID_95XX 0x10 559 #define PCI_REVISION_ID_LOKI 0x20 560 #define PCI_REVISION_ID_98XX 0x30 561 #define PCI_REVISION_ID_95XXMM 0x40 562 563 static inline bool is_rvu_otx2(struct rvu *rvu) 564 { 565 struct pci_dev *pdev = rvu->pdev; 566 567 u8 midr = pdev->revision & 0xF0; 568 569 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 570 midr == PCI_REVISION_ID_LOKI || midr == PCI_REVISION_ID_98XX || 571 midr == PCI_REVISION_ID_95XXMM); 572 } 573 574 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 575 u8 lmacid, u8 chan) 576 { 577 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 578 u16 cgx_chans = nix_const & 0xFFULL; 579 struct rvu_hwinfo *hw = rvu->hw; 580 581 if (!hw->cap.programmable_chans) 582 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 583 584 return rvu->hw->cgx_chan_base + 585 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 586 } 587 588 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 589 u8 chan) 590 { 591 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 592 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 593 struct rvu_hwinfo *hw = rvu->hw; 594 595 if (!hw->cap.programmable_chans) 596 return NIX_CHAN_LBK_CHX(lbkid, chan); 597 598 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 599 } 600 601 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 602 { 603 struct rvu_hwinfo *hw = rvu->hw; 604 605 if (!hw->cap.programmable_chans) 606 return NIX_CHAN_SDP_CHX(chan); 607 608 return hw->sdp_chan_base + chan; 609 } 610 611 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 612 { 613 return rvu->hw->cpt_chan_base + chan; 614 } 615 616 /* Function Prototypes 617 * RVU 618 */ 619 static inline bool is_afvf(u16 pcifunc) 620 { 621 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 622 } 623 624 static inline bool is_vf(u16 pcifunc) 625 { 626 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 627 } 628 629 /* check if PF_FUNC is AF */ 630 static inline bool is_pffunc_af(u16 pcifunc) 631 { 632 return !pcifunc; 633 } 634 635 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 636 { 637 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 638 (rvu->fwdata->version == RVU_FWDATA_VERSION); 639 } 640 641 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 642 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 643 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 644 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 645 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 646 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 647 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 648 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 649 int rvu_get_pf(u16 pcifunc); 650 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 651 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 652 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 653 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 654 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 655 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 656 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 657 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 658 int rvu_get_num_lbk_chans(void); 659 660 /* RVU HW reg validation */ 661 enum regmap_block { 662 TXSCHQ_HWREGMAP = 0, 663 MAX_HWREGMAP, 664 }; 665 666 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 667 668 /* NPA/NIX AQ APIs */ 669 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 670 int qsize, int inst_size, int res_size); 671 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 672 673 /* SDP APIs */ 674 int rvu_sdp_init(struct rvu *rvu); 675 bool is_sdp_pfvf(u16 pcifunc); 676 bool is_sdp_pf(u16 pcifunc); 677 bool is_sdp_vf(u16 pcifunc); 678 679 /* CGX APIs */ 680 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 681 { 682 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 683 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT); 684 } 685 686 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 687 { 688 *cgx_id = (map >> 4) & 0xF; 689 *lmac_id = (map & 0xF); 690 } 691 692 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 693 { 694 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 695 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))); 696 } 697 698 #define M(_name, _id, fn_name, req, rsp) \ 699 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 700 MBOX_MESSAGES 701 #undef M 702 703 int rvu_cgx_init(struct rvu *rvu); 704 int rvu_cgx_exit(struct rvu *rvu); 705 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 706 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 707 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 708 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 709 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 710 int rxtxflag, u64 *stat); 711 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 712 713 /* NPA APIs */ 714 int rvu_npa_init(struct rvu *rvu); 715 void rvu_npa_freemem(struct rvu *rvu); 716 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 717 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 718 struct npa_aq_enq_rsp *rsp); 719 720 /* NIX APIs */ 721 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 722 int rvu_nix_init(struct rvu *rvu); 723 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 724 int blkaddr, u32 cfg); 725 void rvu_nix_freemem(struct rvu *rvu); 726 int rvu_get_nixlf_count(struct rvu *rvu); 727 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 728 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 729 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 730 struct nix_mce_list *mce_list, 731 int mce_idx, int mcam_index, bool add); 732 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 733 struct nix_mce_list **mce_list, int *mce_idx); 734 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 735 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 736 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 737 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 738 struct nix_hw **nix_hw, int *blkaddr); 739 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 740 u16 rq_idx, u16 match_id); 741 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 742 struct nix_cn10k_aq_enq_req *aq_req, 743 struct nix_cn10k_aq_enq_rsp *aq_rsp, 744 u16 pcifunc, u8 ctype, u32 qidx); 745 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 746 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 747 u32 convert_bytes_to_dwrr_mtu(u32 bytes); 748 749 /* NPC APIs */ 750 int rvu_npc_init(struct rvu *rvu); 751 void rvu_npc_freemem(struct rvu *rvu); 752 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 753 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 754 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 755 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 756 int nixlf, u64 chan, u8 *mac_addr); 757 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 758 int nixlf, u64 chan, u8 chan_cnt); 759 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 760 bool enable); 761 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 762 int nixlf, u64 chan); 763 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 764 bool enable); 765 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 766 u64 chan); 767 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 768 bool enable); 769 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 770 int nixlf, int type, bool enable); 771 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 772 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 773 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 774 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 775 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 776 int group, int alg_idx, int mcam_index); 777 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 778 int blkaddr, int *alloc_cnt, 779 int *enable_cnt); 780 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 781 int blkaddr, int *alloc_cnt, 782 int *enable_cnt); 783 bool is_npc_intf_tx(u8 intf); 784 bool is_npc_intf_rx(u8 intf); 785 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 786 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 787 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 788 const char *npc_get_field_name(u8 hdr); 789 int npc_get_bank(struct npc_mcam *mcam, int index); 790 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 791 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 792 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 793 int blkaddr, int index, bool enable); 794 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 795 int blkaddr, u16 src, struct mcam_entry *entry, 796 u8 *intf, u8 *ena); 797 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 798 u32 rvu_cgx_get_fifolen(struct rvu *rvu); 799 void *rvu_first_cgx_pdata(struct rvu *rvu); 800 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 801 802 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 803 int type); 804 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 805 int index); 806 807 /* CPT APIs */ 808 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot); 809 810 /* CN10K RVU */ 811 int rvu_set_channels_base(struct rvu *rvu); 812 void rvu_program_channels(struct rvu *rvu); 813 814 /* CN10K RVU - LMT*/ 815 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 816 817 #ifdef CONFIG_DEBUG_FS 818 void rvu_dbg_init(struct rvu *rvu); 819 void rvu_dbg_exit(struct rvu *rvu); 820 #else 821 static inline void rvu_dbg_init(struct rvu *rvu) {} 822 static inline void rvu_dbg_exit(struct rvu *rvu) {} 823 #endif 824 825 /* RVU Switch */ 826 void rvu_switch_enable(struct rvu *rvu); 827 void rvu_switch_disable(struct rvu *rvu); 828 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc); 829 830 #endif /* RVU_H */ 831