1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef RVU_H 9 #define RVU_H 10 11 #include <linux/pci.h> 12 #include <net/devlink.h> 13 14 #include "rvu_struct.h" 15 #include "rvu_devlink.h" 16 #include "common.h" 17 #include "mbox.h" 18 #include "npc.h" 19 #include "rvu_reg.h" 20 21 /* PCI device IDs */ 22 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 23 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 24 25 /* Subsystem Device ID */ 26 #define PCI_SUBSYS_DEVID_96XX 0xB200 27 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 28 29 /* PCI BAR nos */ 30 #define PCI_AF_REG_BAR_NUM 0 31 #define PCI_PF_REG_BAR_NUM 2 32 #define PCI_MBOX_BAR_NUM 4 33 34 #define NAME_SIZE 32 35 #define MAX_NIX_BLKS 2 36 #define MAX_CPT_BLKS 2 37 38 /* PF_FUNC */ 39 #define RVU_PFVF_PF_SHIFT 10 40 #define RVU_PFVF_PF_MASK 0x3F 41 #define RVU_PFVF_FUNC_SHIFT 0 42 #define RVU_PFVF_FUNC_MASK 0x3FF 43 44 #ifdef CONFIG_DEBUG_FS 45 struct dump_ctx { 46 int lf; 47 int id; 48 bool all; 49 }; 50 51 struct cpt_ctx { 52 int blkaddr; 53 struct rvu *rvu; 54 }; 55 56 struct rvu_debugfs { 57 struct dentry *root; 58 struct dentry *cgx_root; 59 struct dentry *cgx; 60 struct dentry *lmac; 61 struct dentry *npa; 62 struct dentry *nix; 63 struct dentry *npc; 64 struct dentry *cpt; 65 struct dump_ctx npa_aura_ctx; 66 struct dump_ctx npa_pool_ctx; 67 struct dump_ctx nix_cq_ctx; 68 struct dump_ctx nix_rq_ctx; 69 struct dump_ctx nix_sq_ctx; 70 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 71 int npa_qsize_id; 72 int nix_qsize_id; 73 }; 74 #endif 75 76 struct rvu_work { 77 struct work_struct work; 78 struct rvu *rvu; 79 int num_msgs; 80 int up_num_msgs; 81 }; 82 83 struct rsrc_bmap { 84 unsigned long *bmap; /* Pointer to resource bitmap */ 85 u16 max; /* Max resource id or count */ 86 }; 87 88 struct rvu_block { 89 struct rsrc_bmap lf; 90 struct admin_queue *aq; /* NIX/NPA AQ */ 91 u16 *fn_map; /* LF to pcifunc mapping */ 92 bool multislot; 93 bool implemented; 94 u8 addr; /* RVU_BLOCK_ADDR_E */ 95 u8 type; /* RVU_BLOCK_TYPE_E */ 96 u8 lfshift; 97 u64 lookup_reg; 98 u64 pf_lfcnt_reg; 99 u64 vf_lfcnt_reg; 100 u64 lfcfg_reg; 101 u64 msixcfg_reg; 102 u64 lfreset_reg; 103 unsigned char name[NAME_SIZE]; 104 }; 105 106 struct nix_mcast { 107 struct qmem *mce_ctx; 108 struct qmem *mcast_buf; 109 int replay_pkind; 110 int next_free_mce; 111 struct mutex mce_lock; /* Serialize MCE updates */ 112 }; 113 114 struct nix_mce_list { 115 struct hlist_head head; 116 int count; 117 int max; 118 }; 119 120 /* layer metadata to uniquely identify a packet header field */ 121 struct npc_layer_mdata { 122 u8 lid; 123 u8 ltype; 124 u8 hdr; 125 u8 key; 126 u8 len; 127 }; 128 129 /* Structure to represent a field present in the 130 * generated key. A key field may present anywhere and can 131 * be of any size in the generated key. Once this structure 132 * is populated for fields of interest then field's presence 133 * and location (if present) can be known. 134 */ 135 struct npc_key_field { 136 /* Masks where all set bits indicate position 137 * of a field in the key 138 */ 139 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 140 /* Number of words in the key a field spans. If a field is 141 * of 16 bytes and key offset is 4 then the field will use 142 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 143 * nr_kws will be 3(KW0, KW1 and KW2). 144 */ 145 int nr_kws; 146 /* used by packet header fields */ 147 struct npc_layer_mdata layer_mdata; 148 }; 149 150 struct npc_mcam { 151 struct rsrc_bmap counters; 152 struct mutex lock; /* MCAM entries and counters update lock */ 153 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 154 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 155 u16 bmap_entries; /* Number of unreserved MCAM entries */ 156 u16 bmap_fcnt; /* MCAM entries free count */ 157 u16 *entry2pfvf_map; 158 u16 *entry2cntr_map; 159 u16 *cntr2pfvf_map; 160 u16 *cntr_refcnt; 161 u16 *entry2target_pffunc; 162 u8 keysize; /* MCAM keysize 112/224/448 bits */ 163 u8 banks; /* Number of MCAM banks */ 164 u8 banks_per_entry;/* Number of keywords in key */ 165 u16 banksize; /* Number of MCAM entries in each bank */ 166 u16 total_entries; /* Total number of MCAM entries */ 167 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 168 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 169 u16 lprio_count; 170 u16 lprio_start; 171 u16 hprio_count; 172 u16 hprio_end; 173 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 174 /* fields present in the generated key */ 175 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 176 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 177 u64 tx_features; 178 u64 rx_features; 179 struct list_head mcam_rules; 180 }; 181 182 /* Structure for per RVU func info ie PF/VF */ 183 struct rvu_pfvf { 184 bool npalf; /* Only one NPALF per RVU_FUNC */ 185 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 186 u16 sso; 187 u16 ssow; 188 u16 cptlfs; 189 u16 timlfs; 190 u16 cpt1_lfs; 191 u8 cgx_lmac; 192 193 /* Block LF's MSIX vector info */ 194 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 195 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 196 u16 *msix_lfmap; /* Vector to block LF mapping */ 197 198 /* NPA contexts */ 199 struct qmem *aura_ctx; 200 struct qmem *pool_ctx; 201 struct qmem *npa_qints_ctx; 202 unsigned long *aura_bmap; 203 unsigned long *pool_bmap; 204 205 /* NIX contexts */ 206 struct qmem *rq_ctx; 207 struct qmem *sq_ctx; 208 struct qmem *cq_ctx; 209 struct qmem *rss_ctx; 210 struct qmem *cq_ints_ctx; 211 struct qmem *nix_qints_ctx; 212 unsigned long *sq_bmap; 213 unsigned long *rq_bmap; 214 unsigned long *cq_bmap; 215 216 u16 rx_chan_base; 217 u16 tx_chan_base; 218 u8 rx_chan_cnt; /* total number of RX channels */ 219 u8 tx_chan_cnt; /* total number of TX channels */ 220 u16 maxlen; 221 u16 minlen; 222 223 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 224 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 225 226 /* Broadcast/Multicast/Promisc pkt replication info */ 227 u16 bcast_mce_idx; 228 u16 mcast_mce_idx; 229 u16 promisc_mce_idx; 230 struct nix_mce_list bcast_mce_list; 231 struct nix_mce_list mcast_mce_list; 232 struct nix_mce_list promisc_mce_list; 233 bool use_mce_list; 234 235 struct rvu_npc_mcam_rule *def_ucast_rule; 236 237 bool cgx_in_use; /* this PF/VF using CGX? */ 238 int cgx_users; /* number of cgx users - used only by PFs */ 239 240 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 241 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 242 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 243 u8 lbkid; /* NIX0/1 lbk link ID */ 244 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 245 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ 246 unsigned long flags; 247 struct sdp_node_info *sdp_info; 248 }; 249 250 enum rvu_pfvf_flags { 251 NIXLF_INITIALIZED = 0, 252 PF_SET_VF_MAC, 253 PF_SET_VF_CFG, 254 PF_SET_VF_TRUSTED, 255 }; 256 257 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 258 259 struct nix_txsch { 260 struct rsrc_bmap schq; 261 u8 lvl; 262 #define NIX_TXSCHQ_FREE BIT_ULL(1) 263 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 264 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 265 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 266 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 267 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 268 u32 *pfvf_map; 269 }; 270 271 struct nix_mark_format { 272 u8 total; 273 u8 in_use; 274 u32 *cfg; 275 }; 276 277 struct npc_pkind { 278 struct rsrc_bmap rsrc; 279 u32 *pfchan_map; 280 }; 281 282 struct nix_flowkey { 283 #define NIX_FLOW_KEY_ALG_MAX 32 284 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 285 int in_use; 286 }; 287 288 struct nix_lso { 289 u8 total; 290 u8 in_use; 291 }; 292 293 struct nix_txvlan { 294 #define NIX_TX_VTAG_DEF_MAX 0x400 295 struct rsrc_bmap rsrc; 296 u16 *entry2pfvf_map; 297 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 298 }; 299 300 struct nix_ipolicer { 301 struct rsrc_bmap band_prof; 302 u16 *pfvf_map; 303 u16 *match_id; 304 u16 *ref_count; 305 }; 306 307 struct nix_hw { 308 int blkaddr; 309 struct rvu *rvu; 310 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 311 struct nix_mcast mcast; 312 struct nix_flowkey flowkey; 313 struct nix_mark_format mark_format; 314 struct nix_lso lso; 315 struct nix_txvlan txvlan; 316 struct nix_ipolicer *ipolicer; 317 u64 *tx_credits; 318 }; 319 320 /* RVU block's capabilities or functionality, 321 * which vary by silicon version/skew. 322 */ 323 struct hw_cap { 324 /* Transmit side supported functionality */ 325 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 326 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 327 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 328 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 329 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 330 bool nix_shaping; /* Is shaping and coloring supported */ 331 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 332 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 333 bool nix_rx_multicast; /* Rx packet replication support */ 334 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 335 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 336 bool programmable_chans; /* Channels programmable ? */ 337 bool ipolicer; 338 }; 339 340 struct rvu_hwinfo { 341 u8 total_pfs; /* MAX RVU PFs HW supports */ 342 u16 total_vfs; /* Max RVU VFs HW supports */ 343 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 344 u8 cgx; 345 u8 lmac_per_cgx; 346 u16 cgx_chan_base; /* CGX base channel number */ 347 u16 lbk_chan_base; /* LBK base channel number */ 348 u16 sdp_chan_base; /* SDP base channel number */ 349 u16 cpt_chan_base; /* CPT base channel number */ 350 u8 cgx_links; 351 u8 lbk_links; 352 u8 sdp_links; 353 u8 cpt_links; /* Number of CPT links */ 354 u8 npc_kpus; /* No of parser units */ 355 u8 npc_pkinds; /* No of port kinds */ 356 u8 npc_intfs; /* No of interfaces */ 357 u8 npc_kpu_entries; /* No of KPU entries */ 358 u16 npc_counters; /* No of match stats counters */ 359 u32 lbk_bufsize; /* FIFO size supported by LBK */ 360 bool npc_ext_set; /* Extended register set */ 361 u64 npc_stat_ena; /* Match stats enable bit */ 362 363 struct hw_cap cap; 364 struct rvu_block block[BLK_COUNT]; /* Block info */ 365 struct nix_hw *nix; 366 struct rvu *rvu; 367 struct npc_pkind pkind; 368 struct npc_mcam mcam; 369 }; 370 371 struct mbox_wq_info { 372 struct otx2_mbox mbox; 373 struct rvu_work *mbox_wrk; 374 375 struct otx2_mbox mbox_up; 376 struct rvu_work *mbox_wrk_up; 377 378 struct workqueue_struct *mbox_wq; 379 }; 380 381 struct rvu_fwdata { 382 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 383 #define RVU_FWDATA_VERSION 0x0001 384 u32 header_magic; 385 u32 version; /* version id */ 386 387 /* MAC address */ 388 #define PF_MACNUM_MAX 32 389 #define VF_MACNUM_MAX 256 390 u64 pf_macs[PF_MACNUM_MAX]; 391 u64 vf_macs[VF_MACNUM_MAX]; 392 u64 sclk; 393 u64 rclk; 394 u64 mcam_addr; 395 u64 mcam_sz; 396 u64 msixtr_base; 397 #define FWDATA_RESERVED_MEM 1023 398 u64 reserved[FWDATA_RESERVED_MEM]; 399 #define CGX_MAX 5 400 #define CGX_LMACS_MAX 4 401 struct cgx_lmac_fwdata_s cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 402 /* Do not add new fields below this line */ 403 }; 404 405 struct ptp; 406 407 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 408 * source where it came from. 409 */ 410 struct npc_kpu_profile_adapter { 411 const char *name; 412 u64 version; 413 const struct npc_lt_def_cfg *lt_def; 414 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 415 const struct npc_kpu_profile *kpu; /* array[kpus] */ 416 struct npc_mcam_kex *mkex; 417 bool custom; 418 size_t pkinds; 419 size_t kpus; 420 }; 421 422 #define RVU_SWITCH_LBK_CHAN 63 423 424 struct rvu_switch { 425 struct mutex switch_lock; /* Serialize flow installation */ 426 u32 used_entries; 427 u16 *entry2pcifunc; 428 u16 mode; 429 u16 start_entry; 430 }; 431 432 struct rvu { 433 void __iomem *afreg_base; 434 void __iomem *pfreg_base; 435 struct pci_dev *pdev; 436 struct device *dev; 437 struct rvu_hwinfo *hw; 438 struct rvu_pfvf *pf; 439 struct rvu_pfvf *hwvf; 440 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 441 int vfs; /* Number of VFs attached to RVU */ 442 int nix_blkaddr[MAX_NIX_BLKS]; 443 444 /* Mbox */ 445 struct mbox_wq_info afpf_wq_info; 446 struct mbox_wq_info afvf_wq_info; 447 448 /* PF FLR */ 449 struct rvu_work *flr_wrk; 450 struct workqueue_struct *flr_wq; 451 struct mutex flr_lock; /* Serialize FLRs */ 452 453 /* MSI-X */ 454 u16 num_vec; 455 char *irq_name; 456 bool *irq_allocated; 457 dma_addr_t msix_base_iova; 458 u64 msixtr_base_phy; /* Register reset value */ 459 460 /* CGX */ 461 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 462 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 463 u8 cgx_mapped_pfs; 464 u8 cgx_cnt_max; /* CGX port count max */ 465 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 466 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 467 * every cgx lmac port 468 */ 469 unsigned long pf_notify_bmap; /* Flags for PF notification */ 470 void **cgx_idmap; /* cgx id to cgx data map table */ 471 struct work_struct cgx_evh_work; 472 struct workqueue_struct *cgx_evh_wq; 473 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 474 struct list_head cgx_evq_head; /* cgx event queue head */ 475 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 476 477 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 478 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 479 480 /* Firmware data */ 481 struct rvu_fwdata *fwdata; 482 void *kpu_fwdata; 483 size_t kpu_fwdata_sz; 484 void __iomem *kpu_prfl_addr; 485 486 /* NPC KPU data */ 487 struct npc_kpu_profile_adapter kpu; 488 489 struct ptp *ptp; 490 491 #ifdef CONFIG_DEBUG_FS 492 struct rvu_debugfs rvu_dbg; 493 #endif 494 struct rvu_devlink *rvu_dl; 495 496 /* RVU switch implementation over NPC with DMAC rules */ 497 struct rvu_switch rswitch; 498 }; 499 500 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 501 { 502 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 503 } 504 505 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 506 { 507 return readq(rvu->afreg_base + ((block << 28) | offset)); 508 } 509 510 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 511 { 512 writeq(val, rvu->pfreg_base + offset); 513 } 514 515 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 516 { 517 return readq(rvu->pfreg_base + offset); 518 } 519 520 /* Silicon revisions */ 521 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 522 { 523 struct pci_dev *pdev = rvu->pdev; 524 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 525 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 526 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 527 (pdev->revision == 0x14)); 528 } 529 530 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 531 { 532 struct pci_dev *pdev = rvu->pdev; 533 534 return (pdev->revision == 0x00); 535 } 536 537 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 538 { 539 struct pci_dev *pdev = rvu->pdev; 540 541 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 542 } 543 544 static inline bool is_rvu_95xx_A0(struct rvu *rvu) 545 { 546 struct pci_dev *pdev = rvu->pdev; 547 548 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 549 } 550 551 /* REVID for PCIe devices. 552 * Bits 0..1: minor pass, bit 3..2: major pass 553 * bits 7..4: midr id 554 */ 555 #define PCI_REVISION_ID_96XX 0x00 556 #define PCI_REVISION_ID_95XX 0x10 557 #define PCI_REVISION_ID_95XXN 0x20 558 #define PCI_REVISION_ID_98XX 0x30 559 #define PCI_REVISION_ID_95XXMM 0x40 560 #define PCI_REVISION_ID_95XXO 0xE0 561 562 static inline bool is_rvu_otx2(struct rvu *rvu) 563 { 564 struct pci_dev *pdev = rvu->pdev; 565 566 u8 midr = pdev->revision & 0xF0; 567 568 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 569 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 570 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 571 } 572 573 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 574 u8 lmacid, u8 chan) 575 { 576 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 577 u16 cgx_chans = nix_const & 0xFFULL; 578 struct rvu_hwinfo *hw = rvu->hw; 579 580 if (!hw->cap.programmable_chans) 581 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 582 583 return rvu->hw->cgx_chan_base + 584 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 585 } 586 587 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 588 u8 chan) 589 { 590 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 591 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 592 struct rvu_hwinfo *hw = rvu->hw; 593 594 if (!hw->cap.programmable_chans) 595 return NIX_CHAN_LBK_CHX(lbkid, chan); 596 597 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 598 } 599 600 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 601 { 602 struct rvu_hwinfo *hw = rvu->hw; 603 604 if (!hw->cap.programmable_chans) 605 return NIX_CHAN_SDP_CHX(chan); 606 607 return hw->sdp_chan_base + chan; 608 } 609 610 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 611 { 612 return rvu->hw->cpt_chan_base + chan; 613 } 614 615 /* Function Prototypes 616 * RVU 617 */ 618 static inline bool is_afvf(u16 pcifunc) 619 { 620 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 621 } 622 623 static inline bool is_vf(u16 pcifunc) 624 { 625 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 626 } 627 628 /* check if PF_FUNC is AF */ 629 static inline bool is_pffunc_af(u16 pcifunc) 630 { 631 return !pcifunc; 632 } 633 634 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 635 { 636 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 637 (rvu->fwdata->version == RVU_FWDATA_VERSION); 638 } 639 640 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 641 void rvu_free_bitmap(struct rsrc_bmap *rsrc); 642 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 643 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 644 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 645 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 646 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 647 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 648 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 649 int rvu_get_pf(u16 pcifunc); 650 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 651 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 652 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 653 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 654 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 655 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 656 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 657 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 658 int rvu_get_num_lbk_chans(void); 659 660 /* RVU HW reg validation */ 661 enum regmap_block { 662 TXSCHQ_HWREGMAP = 0, 663 MAX_HWREGMAP, 664 }; 665 666 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 667 668 /* NPA/NIX AQ APIs */ 669 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 670 int qsize, int inst_size, int res_size); 671 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 672 673 /* SDP APIs */ 674 int rvu_sdp_init(struct rvu *rvu); 675 bool is_sdp_pfvf(u16 pcifunc); 676 bool is_sdp_pf(u16 pcifunc); 677 bool is_sdp_vf(u16 pcifunc); 678 679 /* CGX APIs */ 680 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 681 { 682 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 683 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT); 684 } 685 686 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 687 { 688 *cgx_id = (map >> 4) & 0xF; 689 *lmac_id = (map & 0xF); 690 } 691 692 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 693 { 694 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 695 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))); 696 } 697 698 #define M(_name, _id, fn_name, req, rsp) \ 699 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 700 MBOX_MESSAGES 701 #undef M 702 703 int rvu_cgx_init(struct rvu *rvu); 704 int rvu_cgx_exit(struct rvu *rvu); 705 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 706 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 707 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 708 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 709 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 710 int rxtxflag, u64 *stat); 711 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 712 713 /* NPA APIs */ 714 int rvu_npa_init(struct rvu *rvu); 715 void rvu_npa_freemem(struct rvu *rvu); 716 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 717 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 718 struct npa_aq_enq_rsp *rsp); 719 720 /* NIX APIs */ 721 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 722 int rvu_nix_init(struct rvu *rvu); 723 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 724 int blkaddr, u32 cfg); 725 void rvu_nix_freemem(struct rvu *rvu); 726 int rvu_get_nixlf_count(struct rvu *rvu); 727 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 728 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 729 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 730 struct nix_mce_list *mce_list, 731 int mce_idx, int mcam_index, bool add); 732 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 733 struct nix_mce_list **mce_list, int *mce_idx); 734 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 735 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 736 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 737 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 738 struct nix_hw **nix_hw, int *blkaddr); 739 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 740 u16 rq_idx, u16 match_id); 741 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 742 struct nix_cn10k_aq_enq_req *aq_req, 743 struct nix_cn10k_aq_enq_rsp *aq_rsp, 744 u16 pcifunc, u8 ctype, u32 qidx); 745 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 746 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 747 u32 convert_bytes_to_dwrr_mtu(u32 bytes); 748 749 /* NPC APIs */ 750 int rvu_npc_init(struct rvu *rvu); 751 void rvu_npc_freemem(struct rvu *rvu); 752 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 753 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 754 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 755 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 756 int nixlf, u64 chan, u8 *mac_addr); 757 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 758 int nixlf, u64 chan, u8 chan_cnt); 759 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 760 bool enable); 761 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 762 int nixlf, u64 chan); 763 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 764 bool enable); 765 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 766 u64 chan); 767 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 768 bool enable); 769 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 770 int nixlf, int type, bool enable); 771 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 772 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 773 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 774 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 775 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 776 int group, int alg_idx, int mcam_index); 777 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 778 int blkaddr, int *alloc_cnt, 779 int *enable_cnt); 780 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 781 int blkaddr, int *alloc_cnt, 782 int *enable_cnt); 783 bool is_npc_intf_tx(u8 intf); 784 bool is_npc_intf_rx(u8 intf); 785 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 786 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 787 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 788 const char *npc_get_field_name(u8 hdr); 789 int npc_get_bank(struct npc_mcam *mcam, int index); 790 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 791 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 792 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 793 int blkaddr, int index, bool enable); 794 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 795 int blkaddr, u16 src, struct mcam_entry *entry, 796 u8 *intf, u8 *ena); 797 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 798 u32 rvu_cgx_get_fifolen(struct rvu *rvu); 799 void *rvu_first_cgx_pdata(struct rvu *rvu); 800 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 801 802 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 803 int type); 804 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 805 int index); 806 807 /* CPT APIs */ 808 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot); 809 810 /* CN10K RVU */ 811 int rvu_set_channels_base(struct rvu *rvu); 812 void rvu_program_channels(struct rvu *rvu); 813 814 /* CN10K RVU - LMT*/ 815 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 816 817 #ifdef CONFIG_DEBUG_FS 818 void rvu_dbg_init(struct rvu *rvu); 819 void rvu_dbg_exit(struct rvu *rvu); 820 #else 821 static inline void rvu_dbg_init(struct rvu *rvu) {} 822 static inline void rvu_dbg_exit(struct rvu *rvu) {} 823 #endif 824 825 /* RVU Switch */ 826 void rvu_switch_enable(struct rvu *rvu); 827 void rvu_switch_disable(struct rvu *rvu); 828 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc); 829 830 #endif /* RVU_H */ 831