1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef RVU_H 12 #define RVU_H 13 14 #include <linux/pci.h> 15 #include <net/devlink.h> 16 17 #include "rvu_struct.h" 18 #include "rvu_devlink.h" 19 #include "common.h" 20 #include "mbox.h" 21 #include "npc.h" 22 #include "rvu_reg.h" 23 24 /* PCI device IDs */ 25 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 26 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 27 28 /* Subsystem Device ID */ 29 #define PCI_SUBSYS_DEVID_96XX 0xB200 30 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 31 32 /* PCI BAR nos */ 33 #define PCI_AF_REG_BAR_NUM 0 34 #define PCI_PF_REG_BAR_NUM 2 35 #define PCI_MBOX_BAR_NUM 4 36 37 #define NAME_SIZE 32 38 #define MAX_NIX_BLKS 2 39 #define MAX_CPT_BLKS 2 40 41 /* PF_FUNC */ 42 #define RVU_PFVF_PF_SHIFT 10 43 #define RVU_PFVF_PF_MASK 0x3F 44 #define RVU_PFVF_FUNC_SHIFT 0 45 #define RVU_PFVF_FUNC_MASK 0x3FF 46 47 #ifdef CONFIG_DEBUG_FS 48 struct dump_ctx { 49 int lf; 50 int id; 51 bool all; 52 }; 53 54 struct cpt_ctx { 55 int blkaddr; 56 struct rvu *rvu; 57 }; 58 59 struct rvu_debugfs { 60 struct dentry *root; 61 struct dentry *cgx_root; 62 struct dentry *cgx; 63 struct dentry *lmac; 64 struct dentry *npa; 65 struct dentry *nix; 66 struct dentry *npc; 67 struct dentry *cpt; 68 struct dump_ctx npa_aura_ctx; 69 struct dump_ctx npa_pool_ctx; 70 struct dump_ctx nix_cq_ctx; 71 struct dump_ctx nix_rq_ctx; 72 struct dump_ctx nix_sq_ctx; 73 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 74 int npa_qsize_id; 75 int nix_qsize_id; 76 }; 77 #endif 78 79 struct rvu_work { 80 struct work_struct work; 81 struct rvu *rvu; 82 int num_msgs; 83 int up_num_msgs; 84 }; 85 86 struct rsrc_bmap { 87 unsigned long *bmap; /* Pointer to resource bitmap */ 88 u16 max; /* Max resource id or count */ 89 }; 90 91 struct rvu_block { 92 struct rsrc_bmap lf; 93 struct admin_queue *aq; /* NIX/NPA AQ */ 94 u16 *fn_map; /* LF to pcifunc mapping */ 95 bool multislot; 96 bool implemented; 97 u8 addr; /* RVU_BLOCK_ADDR_E */ 98 u8 type; /* RVU_BLOCK_TYPE_E */ 99 u8 lfshift; 100 u64 lookup_reg; 101 u64 pf_lfcnt_reg; 102 u64 vf_lfcnt_reg; 103 u64 lfcfg_reg; 104 u64 msixcfg_reg; 105 u64 lfreset_reg; 106 unsigned char name[NAME_SIZE]; 107 }; 108 109 struct nix_mcast { 110 struct qmem *mce_ctx; 111 struct qmem *mcast_buf; 112 int replay_pkind; 113 int next_free_mce; 114 struct mutex mce_lock; /* Serialize MCE updates */ 115 }; 116 117 struct nix_mce_list { 118 struct hlist_head head; 119 int count; 120 int max; 121 }; 122 123 /* layer metadata to uniquely identify a packet header field */ 124 struct npc_layer_mdata { 125 u8 lid; 126 u8 ltype; 127 u8 hdr; 128 u8 key; 129 u8 len; 130 }; 131 132 /* Structure to represent a field present in the 133 * generated key. A key field may present anywhere and can 134 * be of any size in the generated key. Once this structure 135 * is populated for fields of interest then field's presence 136 * and location (if present) can be known. 137 */ 138 struct npc_key_field { 139 /* Masks where all set bits indicate position 140 * of a field in the key 141 */ 142 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 143 /* Number of words in the key a field spans. If a field is 144 * of 16 bytes and key offset is 4 then the field will use 145 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 146 * nr_kws will be 3(KW0, KW1 and KW2). 147 */ 148 int nr_kws; 149 /* used by packet header fields */ 150 struct npc_layer_mdata layer_mdata; 151 }; 152 153 struct npc_mcam { 154 struct rsrc_bmap counters; 155 struct mutex lock; /* MCAM entries and counters update lock */ 156 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 157 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 158 u16 bmap_entries; /* Number of unreserved MCAM entries */ 159 u16 bmap_fcnt; /* MCAM entries free count */ 160 u16 *entry2pfvf_map; 161 u16 *entry2cntr_map; 162 u16 *cntr2pfvf_map; 163 u16 *cntr_refcnt; 164 u16 *entry2target_pffunc; 165 u8 keysize; /* MCAM keysize 112/224/448 bits */ 166 u8 banks; /* Number of MCAM banks */ 167 u8 banks_per_entry;/* Number of keywords in key */ 168 u16 banksize; /* Number of MCAM entries in each bank */ 169 u16 total_entries; /* Total number of MCAM entries */ 170 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 171 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 172 u16 lprio_count; 173 u16 lprio_start; 174 u16 hprio_count; 175 u16 hprio_end; 176 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 177 /* fields present in the generated key */ 178 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 179 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 180 u64 tx_features; 181 u64 rx_features; 182 struct list_head mcam_rules; 183 }; 184 185 /* Structure for per RVU func info ie PF/VF */ 186 struct rvu_pfvf { 187 bool npalf; /* Only one NPALF per RVU_FUNC */ 188 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 189 u16 sso; 190 u16 ssow; 191 u16 cptlfs; 192 u16 timlfs; 193 u16 cpt1_lfs; 194 u8 cgx_lmac; 195 196 /* Block LF's MSIX vector info */ 197 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 198 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 199 u16 *msix_lfmap; /* Vector to block LF mapping */ 200 201 /* NPA contexts */ 202 struct qmem *aura_ctx; 203 struct qmem *pool_ctx; 204 struct qmem *npa_qints_ctx; 205 unsigned long *aura_bmap; 206 unsigned long *pool_bmap; 207 208 /* NIX contexts */ 209 struct qmem *rq_ctx; 210 struct qmem *sq_ctx; 211 struct qmem *cq_ctx; 212 struct qmem *rss_ctx; 213 struct qmem *cq_ints_ctx; 214 struct qmem *nix_qints_ctx; 215 unsigned long *sq_bmap; 216 unsigned long *rq_bmap; 217 unsigned long *cq_bmap; 218 219 u16 rx_chan_base; 220 u16 tx_chan_base; 221 u8 rx_chan_cnt; /* total number of RX channels */ 222 u8 tx_chan_cnt; /* total number of TX channels */ 223 u16 maxlen; 224 u16 minlen; 225 226 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 227 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 228 229 /* Broadcast/Multicast/Promisc pkt replication info */ 230 u16 bcast_mce_idx; 231 u16 mcast_mce_idx; 232 u16 promisc_mce_idx; 233 struct nix_mce_list bcast_mce_list; 234 struct nix_mce_list mcast_mce_list; 235 struct nix_mce_list promisc_mce_list; 236 bool use_mce_list; 237 238 struct rvu_npc_mcam_rule *def_ucast_rule; 239 240 bool cgx_in_use; /* this PF/VF using CGX? */ 241 int cgx_users; /* number of cgx users - used only by PFs */ 242 243 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 244 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 245 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 246 unsigned long flags; 247 }; 248 249 enum rvu_pfvf_flags { 250 NIXLF_INITIALIZED = 0, 251 PF_SET_VF_MAC, 252 PF_SET_VF_CFG, 253 PF_SET_VF_TRUSTED, 254 }; 255 256 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 257 258 struct nix_txsch { 259 struct rsrc_bmap schq; 260 u8 lvl; 261 #define NIX_TXSCHQ_FREE BIT_ULL(1) 262 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 263 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 264 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 265 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 266 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 267 u32 *pfvf_map; 268 }; 269 270 struct nix_mark_format { 271 u8 total; 272 u8 in_use; 273 u32 *cfg; 274 }; 275 276 struct npc_pkind { 277 struct rsrc_bmap rsrc; 278 u32 *pfchan_map; 279 }; 280 281 struct nix_flowkey { 282 #define NIX_FLOW_KEY_ALG_MAX 32 283 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 284 int in_use; 285 }; 286 287 struct nix_lso { 288 u8 total; 289 u8 in_use; 290 }; 291 292 struct nix_txvlan { 293 #define NIX_TX_VTAG_DEF_MAX 0x400 294 struct rsrc_bmap rsrc; 295 u16 *entry2pfvf_map; 296 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 297 }; 298 299 struct nix_ipolicer { 300 struct rsrc_bmap band_prof; 301 u16 *pfvf_map; 302 u16 *match_id; 303 u16 *ref_count; 304 }; 305 306 struct nix_hw { 307 int blkaddr; 308 struct rvu *rvu; 309 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 310 struct nix_mcast mcast; 311 struct nix_flowkey flowkey; 312 struct nix_mark_format mark_format; 313 struct nix_lso lso; 314 struct nix_txvlan txvlan; 315 struct nix_ipolicer *ipolicer; 316 }; 317 318 /* RVU block's capabilities or functionality, 319 * which vary by silicon version/skew. 320 */ 321 struct hw_cap { 322 /* Transmit side supported functionality */ 323 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 324 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 325 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 326 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 327 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 328 bool nix_shaping; /* Is shaping and coloring supported */ 329 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 330 bool nix_rx_multicast; /* Rx packet replication support */ 331 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 332 bool programmable_chans; /* Channels programmable ? */ 333 bool ipolicer; 334 }; 335 336 struct rvu_hwinfo { 337 u8 total_pfs; /* MAX RVU PFs HW supports */ 338 u16 total_vfs; /* Max RVU VFs HW supports */ 339 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 340 u8 cgx; 341 u8 lmac_per_cgx; 342 u16 cgx_chan_base; /* CGX base channel number */ 343 u16 lbk_chan_base; /* LBK base channel number */ 344 u16 sdp_chan_base; /* SDP base channel number */ 345 u16 cpt_chan_base; /* CPT base channel number */ 346 u8 cgx_links; 347 u8 lbk_links; 348 u8 sdp_links; 349 u8 cpt_links; /* Number of CPT links */ 350 u8 npc_kpus; /* No of parser units */ 351 u8 npc_pkinds; /* No of port kinds */ 352 u8 npc_intfs; /* No of interfaces */ 353 u8 npc_kpu_entries; /* No of KPU entries */ 354 u16 npc_counters; /* No of match stats counters */ 355 u32 lbk_bufsize; /* FIFO size supported by LBK */ 356 bool npc_ext_set; /* Extended register set */ 357 358 struct hw_cap cap; 359 struct rvu_block block[BLK_COUNT]; /* Block info */ 360 struct nix_hw *nix; 361 struct rvu *rvu; 362 struct npc_pkind pkind; 363 struct npc_mcam mcam; 364 }; 365 366 struct mbox_wq_info { 367 struct otx2_mbox mbox; 368 struct rvu_work *mbox_wrk; 369 370 struct otx2_mbox mbox_up; 371 struct rvu_work *mbox_wrk_up; 372 373 struct workqueue_struct *mbox_wq; 374 }; 375 376 struct rvu_fwdata { 377 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 378 #define RVU_FWDATA_VERSION 0x0001 379 u32 header_magic; 380 u32 version; /* version id */ 381 382 /* MAC address */ 383 #define PF_MACNUM_MAX 32 384 #define VF_MACNUM_MAX 256 385 u64 pf_macs[PF_MACNUM_MAX]; 386 u64 vf_macs[VF_MACNUM_MAX]; 387 u64 sclk; 388 u64 rclk; 389 u64 mcam_addr; 390 u64 mcam_sz; 391 u64 msixtr_base; 392 #define FWDATA_RESERVED_MEM 1023 393 u64 reserved[FWDATA_RESERVED_MEM]; 394 #define CGX_MAX 5 395 #define CGX_LMACS_MAX 4 396 struct cgx_lmac_fwdata_s cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 397 /* Do not add new fields below this line */ 398 }; 399 400 struct ptp; 401 402 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 403 * source where it came from. 404 */ 405 struct npc_kpu_profile_adapter { 406 const char *name; 407 u64 version; 408 const struct npc_lt_def_cfg *lt_def; 409 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 410 const struct npc_kpu_profile *kpu; /* array[kpus] */ 411 struct npc_mcam_kex *mkex; 412 bool custom; 413 size_t pkinds; 414 size_t kpus; 415 }; 416 417 struct rvu { 418 void __iomem *afreg_base; 419 void __iomem *pfreg_base; 420 struct pci_dev *pdev; 421 struct device *dev; 422 struct rvu_hwinfo *hw; 423 struct rvu_pfvf *pf; 424 struct rvu_pfvf *hwvf; 425 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 426 int vfs; /* Number of VFs attached to RVU */ 427 int nix_blkaddr[MAX_NIX_BLKS]; 428 429 /* Mbox */ 430 struct mbox_wq_info afpf_wq_info; 431 struct mbox_wq_info afvf_wq_info; 432 433 /* PF FLR */ 434 struct rvu_work *flr_wrk; 435 struct workqueue_struct *flr_wq; 436 struct mutex flr_lock; /* Serialize FLRs */ 437 438 /* MSI-X */ 439 u16 num_vec; 440 char *irq_name; 441 bool *irq_allocated; 442 dma_addr_t msix_base_iova; 443 u64 msixtr_base_phy; /* Register reset value */ 444 445 /* CGX */ 446 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 447 u8 cgx_mapped_pfs; 448 u8 cgx_cnt_max; /* CGX port count max */ 449 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 450 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 451 * every cgx lmac port 452 */ 453 unsigned long pf_notify_bmap; /* Flags for PF notification */ 454 void **cgx_idmap; /* cgx id to cgx data map table */ 455 struct work_struct cgx_evh_work; 456 struct workqueue_struct *cgx_evh_wq; 457 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 458 struct list_head cgx_evq_head; /* cgx event queue head */ 459 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 460 461 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 462 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 463 464 /* Firmware data */ 465 struct rvu_fwdata *fwdata; 466 void *kpu_fwdata; 467 size_t kpu_fwdata_sz; 468 void __iomem *kpu_prfl_addr; 469 470 /* NPC KPU data */ 471 struct npc_kpu_profile_adapter kpu; 472 473 struct ptp *ptp; 474 475 #ifdef CONFIG_DEBUG_FS 476 struct rvu_debugfs rvu_dbg; 477 #endif 478 struct rvu_devlink *rvu_dl; 479 }; 480 481 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 482 { 483 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 484 } 485 486 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 487 { 488 return readq(rvu->afreg_base + ((block << 28) | offset)); 489 } 490 491 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 492 { 493 writeq(val, rvu->pfreg_base + offset); 494 } 495 496 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 497 { 498 return readq(rvu->pfreg_base + offset); 499 } 500 501 /* Silicon revisions */ 502 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 503 { 504 struct pci_dev *pdev = rvu->pdev; 505 506 return (pdev->revision == 0x00) && 507 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 508 } 509 510 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 511 { 512 struct pci_dev *pdev = rvu->pdev; 513 514 return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) && 515 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 516 } 517 518 /* REVID for PCIe devices. 519 * Bits 0..1: minor pass, bit 3..2: major pass 520 * bits 7..4: midr id 521 */ 522 #define PCI_REVISION_ID_96XX 0x00 523 #define PCI_REVISION_ID_95XX 0x10 524 #define PCI_REVISION_ID_LOKI 0x20 525 #define PCI_REVISION_ID_98XX 0x30 526 #define PCI_REVISION_ID_95XXMM 0x40 527 528 static inline bool is_rvu_otx2(struct rvu *rvu) 529 { 530 struct pci_dev *pdev = rvu->pdev; 531 532 u8 midr = pdev->revision & 0xF0; 533 534 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 535 midr == PCI_REVISION_ID_LOKI || midr == PCI_REVISION_ID_98XX || 536 midr == PCI_REVISION_ID_95XXMM); 537 } 538 539 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 540 u8 lmacid, u8 chan) 541 { 542 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 543 u16 cgx_chans = nix_const & 0xFFULL; 544 struct rvu_hwinfo *hw = rvu->hw; 545 546 if (!hw->cap.programmable_chans) 547 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 548 549 return rvu->hw->cgx_chan_base + 550 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 551 } 552 553 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 554 u8 chan) 555 { 556 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 557 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 558 struct rvu_hwinfo *hw = rvu->hw; 559 560 if (!hw->cap.programmable_chans) 561 return NIX_CHAN_LBK_CHX(lbkid, chan); 562 563 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 564 } 565 566 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 567 { 568 return rvu->hw->cpt_chan_base + chan; 569 } 570 571 /* Function Prototypes 572 * RVU 573 */ 574 static inline bool is_afvf(u16 pcifunc) 575 { 576 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 577 } 578 579 static inline bool is_vf(u16 pcifunc) 580 { 581 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 582 } 583 584 /* check if PF_FUNC is AF */ 585 static inline bool is_pffunc_af(u16 pcifunc) 586 { 587 return !pcifunc; 588 } 589 590 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 591 { 592 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 593 (rvu->fwdata->version == RVU_FWDATA_VERSION); 594 } 595 596 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 597 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 598 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 599 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 600 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 601 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 602 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 603 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 604 int rvu_get_pf(u16 pcifunc); 605 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 606 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 607 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 608 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 609 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 610 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 611 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 612 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 613 int rvu_get_num_lbk_chans(void); 614 615 /* RVU HW reg validation */ 616 enum regmap_block { 617 TXSCHQ_HWREGMAP = 0, 618 MAX_HWREGMAP, 619 }; 620 621 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 622 623 /* NPA/NIX AQ APIs */ 624 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 625 int qsize, int inst_size, int res_size); 626 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 627 628 /* CGX APIs */ 629 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 630 { 631 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs); 632 } 633 634 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 635 { 636 *cgx_id = (map >> 4) & 0xF; 637 *lmac_id = (map & 0xF); 638 } 639 640 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 641 { 642 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 643 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))); 644 } 645 646 #define M(_name, _id, fn_name, req, rsp) \ 647 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 648 MBOX_MESSAGES 649 #undef M 650 651 int rvu_cgx_init(struct rvu *rvu); 652 int rvu_cgx_exit(struct rvu *rvu); 653 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 654 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 655 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 656 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 657 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 658 int rxtxflag, u64 *stat); 659 /* NPA APIs */ 660 int rvu_npa_init(struct rvu *rvu); 661 void rvu_npa_freemem(struct rvu *rvu); 662 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 663 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 664 struct npa_aq_enq_rsp *rsp); 665 666 /* NIX APIs */ 667 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 668 int rvu_nix_init(struct rvu *rvu); 669 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 670 int blkaddr, u32 cfg); 671 void rvu_nix_freemem(struct rvu *rvu); 672 int rvu_get_nixlf_count(struct rvu *rvu); 673 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 674 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 675 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 676 struct nix_mce_list *mce_list, 677 int mce_idx, int mcam_index, bool add); 678 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 679 struct nix_mce_list **mce_list, int *mce_idx); 680 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 681 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 682 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 683 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 684 struct nix_hw **nix_hw, int *blkaddr); 685 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 686 u16 rq_idx, u16 match_id); 687 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 688 struct nix_cn10k_aq_enq_req *aq_req, 689 struct nix_cn10k_aq_enq_rsp *aq_rsp, 690 u16 pcifunc, u8 ctype, u32 qidx); 691 692 /* NPC APIs */ 693 int rvu_npc_init(struct rvu *rvu); 694 void rvu_npc_freemem(struct rvu *rvu); 695 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 696 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 697 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 698 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 699 int nixlf, u64 chan, u8 *mac_addr); 700 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 701 int nixlf, u64 chan, u8 chan_cnt); 702 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 703 bool enable); 704 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 705 int nixlf, u64 chan); 706 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 707 bool enable); 708 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 709 u64 chan); 710 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 711 bool enable); 712 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 713 int nixlf, int type, bool enable); 714 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 715 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 716 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 717 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 718 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 719 int group, int alg_idx, int mcam_index); 720 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 721 int blkaddr, int *alloc_cnt, 722 int *enable_cnt); 723 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 724 int blkaddr, int *alloc_cnt, 725 int *enable_cnt); 726 bool is_npc_intf_tx(u8 intf); 727 bool is_npc_intf_rx(u8 intf); 728 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 729 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 730 int npc_mcam_verify_channel(struct rvu *rvu, u16 pcifunc, u8 intf, u16 channel); 731 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 732 const char *npc_get_field_name(u8 hdr); 733 int npc_get_bank(struct npc_mcam *mcam, int index); 734 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 735 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 736 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 737 int blkaddr, int index, bool enable); 738 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 739 int blkaddr, u16 src, struct mcam_entry *entry, 740 u8 *intf, u8 *ena); 741 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 742 u32 rvu_cgx_get_fifolen(struct rvu *rvu); 743 void *rvu_first_cgx_pdata(struct rvu *rvu); 744 745 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 746 int type); 747 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 748 int index); 749 750 /* CPT APIs */ 751 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot); 752 753 /* CN10K RVU */ 754 int rvu_set_channels_base(struct rvu *rvu); 755 void rvu_program_channels(struct rvu *rvu); 756 757 #ifdef CONFIG_DEBUG_FS 758 void rvu_dbg_init(struct rvu *rvu); 759 void rvu_dbg_exit(struct rvu *rvu); 760 #else 761 static inline void rvu_dbg_init(struct rvu *rvu) {} 762 static inline void rvu_dbg_exit(struct rvu *rvu) {} 763 #endif 764 #endif /* RVU_H */ 765