1 /* SPDX-License-Identifier: GPL-2.0 2 * Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef RVU_H 12 #define RVU_H 13 14 #include <linux/pci.h> 15 #include "rvu_struct.h" 16 #include "common.h" 17 #include "mbox.h" 18 19 /* PCI device IDs */ 20 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 21 22 /* Subsystem Device ID */ 23 #define PCI_SUBSYS_DEVID_96XX 0xB200 24 25 /* PCI BAR nos */ 26 #define PCI_AF_REG_BAR_NUM 0 27 #define PCI_PF_REG_BAR_NUM 2 28 #define PCI_MBOX_BAR_NUM 4 29 30 #define NAME_SIZE 32 31 32 /* PF_FUNC */ 33 #define RVU_PFVF_PF_SHIFT 10 34 #define RVU_PFVF_PF_MASK 0x3F 35 #define RVU_PFVF_FUNC_SHIFT 0 36 #define RVU_PFVF_FUNC_MASK 0x3FF 37 38 struct rvu_work { 39 struct work_struct work; 40 struct rvu *rvu; 41 }; 42 43 struct rsrc_bmap { 44 unsigned long *bmap; /* Pointer to resource bitmap */ 45 u16 max; /* Max resource id or count */ 46 }; 47 48 struct rvu_block { 49 struct rsrc_bmap lf; 50 struct admin_queue *aq; /* NIX/NPA AQ */ 51 u16 *fn_map; /* LF to pcifunc mapping */ 52 bool multislot; 53 bool implemented; 54 u8 addr; /* RVU_BLOCK_ADDR_E */ 55 u8 type; /* RVU_BLOCK_TYPE_E */ 56 u8 lfshift; 57 u64 lookup_reg; 58 u64 pf_lfcnt_reg; 59 u64 vf_lfcnt_reg; 60 u64 lfcfg_reg; 61 u64 msixcfg_reg; 62 u64 lfreset_reg; 63 unsigned char name[NAME_SIZE]; 64 }; 65 66 struct nix_mcast { 67 struct qmem *mce_ctx; 68 struct qmem *mcast_buf; 69 int replay_pkind; 70 int next_free_mce; 71 struct mutex mce_lock; /* Serialize MCE updates */ 72 }; 73 74 struct nix_mce_list { 75 struct hlist_head head; 76 int count; 77 int max; 78 }; 79 80 struct npc_mcam { 81 struct rsrc_bmap counters; 82 struct mutex lock; /* MCAM entries and counters update lock */ 83 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 84 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 85 u16 bmap_entries; /* Number of unreserved MCAM entries */ 86 u16 bmap_fcnt; /* MCAM entries free count */ 87 u16 *entry2pfvf_map; 88 u16 *entry2cntr_map; 89 u16 *cntr2pfvf_map; 90 u16 *cntr_refcnt; 91 u8 keysize; /* MCAM keysize 112/224/448 bits */ 92 u8 banks; /* Number of MCAM banks */ 93 u8 banks_per_entry;/* Number of keywords in key */ 94 u16 banksize; /* Number of MCAM entries in each bank */ 95 u16 total_entries; /* Total number of MCAM entries */ 96 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 97 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 98 u16 lprio_count; 99 u16 lprio_start; 100 u16 hprio_count; 101 u16 hprio_end; 102 }; 103 104 /* Structure for per RVU func info ie PF/VF */ 105 struct rvu_pfvf { 106 bool npalf; /* Only one NPALF per RVU_FUNC */ 107 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 108 u16 sso; 109 u16 ssow; 110 u16 cptlfs; 111 u16 timlfs; 112 u8 cgx_lmac; 113 114 /* Block LF's MSIX vector info */ 115 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 116 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 117 u16 *msix_lfmap; /* Vector to block LF mapping */ 118 119 /* NPA contexts */ 120 struct qmem *aura_ctx; 121 struct qmem *pool_ctx; 122 struct qmem *npa_qints_ctx; 123 unsigned long *aura_bmap; 124 unsigned long *pool_bmap; 125 126 /* NIX contexts */ 127 struct qmem *rq_ctx; 128 struct qmem *sq_ctx; 129 struct qmem *cq_ctx; 130 struct qmem *rss_ctx; 131 struct qmem *cq_ints_ctx; 132 struct qmem *nix_qints_ctx; 133 unsigned long *sq_bmap; 134 unsigned long *rq_bmap; 135 unsigned long *cq_bmap; 136 137 u16 rx_chan_base; 138 u16 tx_chan_base; 139 u8 rx_chan_cnt; /* total number of RX channels */ 140 u8 tx_chan_cnt; /* total number of TX channels */ 141 u16 maxlen; 142 u16 minlen; 143 144 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 145 146 /* Broadcast pkt replication info */ 147 u16 bcast_mce_idx; 148 struct nix_mce_list bcast_mce_list; 149 150 /* VLAN offload */ 151 struct mcam_entry entry; 152 int rxvlan_index; 153 bool rxvlan; 154 }; 155 156 struct nix_txsch { 157 struct rsrc_bmap schq; 158 u8 lvl; 159 u16 *pfvf_map; 160 }; 161 162 struct npc_pkind { 163 struct rsrc_bmap rsrc; 164 u32 *pfchan_map; 165 }; 166 167 struct nix_hw { 168 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 169 struct nix_mcast mcast; 170 }; 171 172 struct rvu_hwinfo { 173 u8 total_pfs; /* MAX RVU PFs HW supports */ 174 u16 total_vfs; /* Max RVU VFs HW supports */ 175 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 176 u8 cgx; 177 u8 lmac_per_cgx; 178 u8 cgx_links; 179 u8 lbk_links; 180 u8 sdp_links; 181 u8 npc_kpus; /* No of parser units */ 182 183 184 struct rvu_block block[BLK_COUNT]; /* Block info */ 185 struct nix_hw *nix0; 186 struct npc_pkind pkind; 187 struct npc_mcam mcam; 188 }; 189 190 struct mbox_wq_info { 191 struct otx2_mbox mbox; 192 struct rvu_work *mbox_wrk; 193 194 struct otx2_mbox mbox_up; 195 struct rvu_work *mbox_wrk_up; 196 197 struct workqueue_struct *mbox_wq; 198 }; 199 200 struct rvu { 201 void __iomem *afreg_base; 202 void __iomem *pfreg_base; 203 struct pci_dev *pdev; 204 struct device *dev; 205 struct rvu_hwinfo *hw; 206 struct rvu_pfvf *pf; 207 struct rvu_pfvf *hwvf; 208 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 209 int vfs; /* Number of VFs attached to RVU */ 210 211 /* Mbox */ 212 struct mbox_wq_info afpf_wq_info; 213 struct mbox_wq_info afvf_wq_info; 214 215 /* PF FLR */ 216 struct rvu_work *flr_wrk; 217 struct workqueue_struct *flr_wq; 218 struct mutex flr_lock; /* Serialize FLRs */ 219 220 /* MSI-X */ 221 u16 num_vec; 222 char *irq_name; 223 bool *irq_allocated; 224 dma_addr_t msix_base_iova; 225 226 /* CGX */ 227 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 228 u8 cgx_mapped_pfs; 229 u8 cgx_cnt_max; /* CGX port count max */ 230 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 231 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 232 * every cgx lmac port 233 */ 234 unsigned long pf_notify_bmap; /* Flags for PF notification */ 235 void **cgx_idmap; /* cgx id to cgx data map table */ 236 struct work_struct cgx_evh_work; 237 struct workqueue_struct *cgx_evh_wq; 238 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 239 struct list_head cgx_evq_head; /* cgx event queue head */ 240 }; 241 242 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 243 { 244 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 245 } 246 247 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 248 { 249 return readq(rvu->afreg_base + ((block << 28) | offset)); 250 } 251 252 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 253 { 254 writeq(val, rvu->pfreg_base + offset); 255 } 256 257 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 258 { 259 return readq(rvu->pfreg_base + offset); 260 } 261 262 static inline bool is_rvu_9xxx_A0(struct rvu *rvu) 263 { 264 struct pci_dev *pdev = rvu->pdev; 265 266 return (pdev->revision == 0x00) && 267 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 268 } 269 270 /* Function Prototypes 271 * RVU 272 */ 273 static inline int is_afvf(u16 pcifunc) 274 { 275 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 276 } 277 278 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 279 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 280 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 281 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 282 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 283 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 284 int rvu_get_pf(u16 pcifunc); 285 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 286 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 287 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 288 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 289 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 290 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 291 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 292 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 293 294 /* RVU HW reg validation */ 295 enum regmap_block { 296 TXSCHQ_HWREGMAP = 0, 297 MAX_HWREGMAP, 298 }; 299 300 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 301 302 /* NPA/NIX AQ APIs */ 303 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 304 int qsize, int inst_size, int res_size); 305 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 306 307 /* CGX APIs */ 308 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 309 { 310 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs); 311 } 312 313 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 314 { 315 *cgx_id = (map >> 4) & 0xF; 316 *lmac_id = (map & 0xF); 317 } 318 319 int rvu_cgx_init(struct rvu *rvu); 320 int rvu_cgx_exit(struct rvu *rvu); 321 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 322 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 323 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req, 324 struct msg_rsp *rsp); 325 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req, 326 struct msg_rsp *rsp); 327 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req, 328 struct cgx_stats_rsp *rsp); 329 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu, 330 struct cgx_mac_addr_set_or_get *req, 331 struct cgx_mac_addr_set_or_get *rsp); 332 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu, 333 struct cgx_mac_addr_set_or_get *req, 334 struct cgx_mac_addr_set_or_get *rsp); 335 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req, 336 struct msg_rsp *rsp); 337 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req, 338 struct msg_rsp *rsp); 339 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req, 340 struct msg_rsp *rsp); 341 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req, 342 struct msg_rsp *rsp); 343 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req, 344 struct cgx_link_info_msg *rsp); 345 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req, 346 struct msg_rsp *rsp); 347 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req, 348 struct msg_rsp *rsp); 349 350 /* NPA APIs */ 351 int rvu_npa_init(struct rvu *rvu); 352 void rvu_npa_freemem(struct rvu *rvu); 353 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 354 int rvu_mbox_handler_npa_aq_enq(struct rvu *rvu, 355 struct npa_aq_enq_req *req, 356 struct npa_aq_enq_rsp *rsp); 357 int rvu_mbox_handler_npa_hwctx_disable(struct rvu *rvu, 358 struct hwctx_disable_req *req, 359 struct msg_rsp *rsp); 360 int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu, 361 struct npa_lf_alloc_req *req, 362 struct npa_lf_alloc_rsp *rsp); 363 int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struct msg_req *req, 364 struct msg_rsp *rsp); 365 366 /* NIX APIs */ 367 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 368 int rvu_nix_init(struct rvu *rvu); 369 void rvu_nix_freemem(struct rvu *rvu); 370 int rvu_get_nixlf_count(struct rvu *rvu); 371 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 372 int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, 373 struct nix_lf_alloc_req *req, 374 struct nix_lf_alloc_rsp *rsp); 375 int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct msg_req *req, 376 struct msg_rsp *rsp); 377 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu, 378 struct nix_aq_enq_req *req, 379 struct nix_aq_enq_rsp *rsp); 380 int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu, 381 struct hwctx_disable_req *req, 382 struct msg_rsp *rsp); 383 int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu, 384 struct nix_txsch_alloc_req *req, 385 struct nix_txsch_alloc_rsp *rsp); 386 int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu, 387 struct nix_txsch_free_req *req, 388 struct msg_rsp *rsp); 389 int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu, 390 struct nix_txschq_config *req, 391 struct msg_rsp *rsp); 392 int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req, 393 struct msg_rsp *rsp); 394 int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu, 395 struct nix_vtag_config *req, 396 struct msg_rsp *rsp); 397 int rvu_mbox_handler_nix_rxvlan_alloc(struct rvu *rvu, struct msg_req *req, 398 struct msg_rsp *rsp); 399 int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu, 400 struct nix_rss_flowkey_cfg *req, 401 struct msg_rsp *rsp); 402 int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu, 403 struct nix_set_mac_addr *req, 404 struct msg_rsp *rsp); 405 int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req, 406 struct msg_rsp *rsp); 407 int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req, 408 struct msg_rsp *rsp); 409 int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req, 410 struct msg_rsp *rsp); 411 int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req, 412 struct msg_rsp *rsp); 413 414 /* NPC APIs */ 415 int rvu_npc_init(struct rvu *rvu); 416 void rvu_npc_freemem(struct rvu *rvu); 417 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 418 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 419 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 420 int nixlf, u64 chan, u8 *mac_addr); 421 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 422 int nixlf, u64 chan, bool allmulti); 423 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 424 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 425 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 426 int nixlf, u64 chan); 427 int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf); 428 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 429 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 430 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 431 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 432 int group, int alg_idx, int mcam_index); 433 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu, 434 struct npc_mcam_alloc_entry_req *req, 435 struct npc_mcam_alloc_entry_rsp *rsp); 436 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu, 437 struct npc_mcam_free_entry_req *req, 438 struct msg_rsp *rsp); 439 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu, 440 struct npc_mcam_write_entry_req *req, 441 struct msg_rsp *rsp); 442 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu, 443 struct npc_mcam_ena_dis_entry_req *req, 444 struct msg_rsp *rsp); 445 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu, 446 struct npc_mcam_ena_dis_entry_req *req, 447 struct msg_rsp *rsp); 448 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu, 449 struct npc_mcam_shift_entry_req *req, 450 struct npc_mcam_shift_entry_rsp *rsp); 451 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, 452 struct npc_mcam_alloc_counter_req *req, 453 struct npc_mcam_alloc_counter_rsp *rsp); 454 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, 455 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp); 456 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu, 457 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp); 458 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, 459 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp); 460 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu, 461 struct npc_mcam_oper_counter_req *req, 462 struct npc_mcam_oper_counter_rsp *rsp); 463 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu, 464 struct npc_mcam_alloc_and_write_entry_req *req, 465 struct npc_mcam_alloc_and_write_entry_rsp *rsp); 466 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req, 467 struct npc_get_kex_cfg_rsp *rsp); 468 #endif /* RVU_H */ 469