1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef RVU_H 12 #define RVU_H 13 14 #include <linux/pci.h> 15 #include <net/devlink.h> 16 17 #include "rvu_struct.h" 18 #include "rvu_devlink.h" 19 #include "common.h" 20 #include "mbox.h" 21 #include "npc.h" 22 23 /* PCI device IDs */ 24 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 25 26 /* Subsystem Device ID */ 27 #define PCI_SUBSYS_DEVID_96XX 0xB200 28 29 /* PCI BAR nos */ 30 #define PCI_AF_REG_BAR_NUM 0 31 #define PCI_PF_REG_BAR_NUM 2 32 #define PCI_MBOX_BAR_NUM 4 33 34 #define NAME_SIZE 32 35 #define MAX_NIX_BLKS 2 36 37 /* PF_FUNC */ 38 #define RVU_PFVF_PF_SHIFT 10 39 #define RVU_PFVF_PF_MASK 0x3F 40 #define RVU_PFVF_FUNC_SHIFT 0 41 #define RVU_PFVF_FUNC_MASK 0x3FF 42 43 #ifdef CONFIG_DEBUG_FS 44 struct dump_ctx { 45 int lf; 46 int id; 47 bool all; 48 }; 49 50 struct rvu_debugfs { 51 struct dentry *root; 52 struct dentry *cgx_root; 53 struct dentry *cgx; 54 struct dentry *lmac; 55 struct dentry *npa; 56 struct dentry *nix; 57 struct dentry *npc; 58 struct dentry *cpt; 59 struct dump_ctx npa_aura_ctx; 60 struct dump_ctx npa_pool_ctx; 61 struct dump_ctx nix_cq_ctx; 62 struct dump_ctx nix_rq_ctx; 63 struct dump_ctx nix_sq_ctx; 64 int npa_qsize_id; 65 int nix_qsize_id; 66 }; 67 #endif 68 69 struct rvu_work { 70 struct work_struct work; 71 struct rvu *rvu; 72 int num_msgs; 73 int up_num_msgs; 74 }; 75 76 struct rsrc_bmap { 77 unsigned long *bmap; /* Pointer to resource bitmap */ 78 u16 max; /* Max resource id or count */ 79 }; 80 81 struct rvu_block { 82 struct rsrc_bmap lf; 83 struct admin_queue *aq; /* NIX/NPA AQ */ 84 u16 *fn_map; /* LF to pcifunc mapping */ 85 bool multislot; 86 bool implemented; 87 u8 addr; /* RVU_BLOCK_ADDR_E */ 88 u8 type; /* RVU_BLOCK_TYPE_E */ 89 u8 lfshift; 90 u64 lookup_reg; 91 u64 pf_lfcnt_reg; 92 u64 vf_lfcnt_reg; 93 u64 lfcfg_reg; 94 u64 msixcfg_reg; 95 u64 lfreset_reg; 96 unsigned char name[NAME_SIZE]; 97 }; 98 99 struct nix_mcast { 100 struct qmem *mce_ctx; 101 struct qmem *mcast_buf; 102 int replay_pkind; 103 int next_free_mce; 104 struct mutex mce_lock; /* Serialize MCE updates */ 105 }; 106 107 struct nix_mce_list { 108 struct hlist_head head; 109 int count; 110 int max; 111 }; 112 113 /* layer metadata to uniquely identify a packet header field */ 114 struct npc_layer_mdata { 115 u8 lid; 116 u8 ltype; 117 u8 hdr; 118 u8 key; 119 u8 len; 120 }; 121 122 /* Structure to represent a field present in the 123 * generated key. A key field may present anywhere and can 124 * be of any size in the generated key. Once this structure 125 * is populated for fields of interest then field's presence 126 * and location (if present) can be known. 127 */ 128 struct npc_key_field { 129 /* Masks where all set bits indicate position 130 * of a field in the key 131 */ 132 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 133 /* Number of words in the key a field spans. If a field is 134 * of 16 bytes and key offset is 4 then the field will use 135 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 136 * nr_kws will be 3(KW0, KW1 and KW2). 137 */ 138 int nr_kws; 139 /* used by packet header fields */ 140 struct npc_layer_mdata layer_mdata; 141 }; 142 143 struct npc_mcam { 144 struct rsrc_bmap counters; 145 struct mutex lock; /* MCAM entries and counters update lock */ 146 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 147 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 148 u16 bmap_entries; /* Number of unreserved MCAM entries */ 149 u16 bmap_fcnt; /* MCAM entries free count */ 150 u16 *entry2pfvf_map; 151 u16 *entry2cntr_map; 152 u16 *cntr2pfvf_map; 153 u16 *cntr_refcnt; 154 u16 *entry2target_pffunc; 155 u8 keysize; /* MCAM keysize 112/224/448 bits */ 156 u8 banks; /* Number of MCAM banks */ 157 u8 banks_per_entry;/* Number of keywords in key */ 158 u16 banksize; /* Number of MCAM entries in each bank */ 159 u16 total_entries; /* Total number of MCAM entries */ 160 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 161 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 162 u16 lprio_count; 163 u16 lprio_start; 164 u16 hprio_count; 165 u16 hprio_end; 166 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 167 /* fields present in the generated key */ 168 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 169 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 170 u64 tx_features; 171 u64 rx_features; 172 struct list_head mcam_rules; 173 }; 174 175 /* Structure for per RVU func info ie PF/VF */ 176 struct rvu_pfvf { 177 bool npalf; /* Only one NPALF per RVU_FUNC */ 178 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 179 u16 sso; 180 u16 ssow; 181 u16 cptlfs; 182 u16 timlfs; 183 u16 cpt1_lfs; 184 u8 cgx_lmac; 185 186 /* Block LF's MSIX vector info */ 187 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 188 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 189 u16 *msix_lfmap; /* Vector to block LF mapping */ 190 191 /* NPA contexts */ 192 struct qmem *aura_ctx; 193 struct qmem *pool_ctx; 194 struct qmem *npa_qints_ctx; 195 unsigned long *aura_bmap; 196 unsigned long *pool_bmap; 197 198 /* NIX contexts */ 199 struct qmem *rq_ctx; 200 struct qmem *sq_ctx; 201 struct qmem *cq_ctx; 202 struct qmem *rss_ctx; 203 struct qmem *cq_ints_ctx; 204 struct qmem *nix_qints_ctx; 205 unsigned long *sq_bmap; 206 unsigned long *rq_bmap; 207 unsigned long *cq_bmap; 208 209 u16 rx_chan_base; 210 u16 tx_chan_base; 211 u8 rx_chan_cnt; /* total number of RX channels */ 212 u8 tx_chan_cnt; /* total number of TX channels */ 213 u16 maxlen; 214 u16 minlen; 215 216 u8 pf_set_vf_cfg; 217 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 218 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 219 220 /* Broadcast pkt replication info */ 221 u16 bcast_mce_idx; 222 struct nix_mce_list bcast_mce_list; 223 224 struct rvu_npc_mcam_rule *def_ucast_rule; 225 226 bool cgx_in_use; /* this PF/VF using CGX? */ 227 int cgx_users; /* number of cgx users - used only by PFs */ 228 229 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 230 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 231 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 232 }; 233 234 struct nix_txsch { 235 struct rsrc_bmap schq; 236 u8 lvl; 237 #define NIX_TXSCHQ_FREE BIT_ULL(1) 238 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 239 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 240 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 241 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 242 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 243 u32 *pfvf_map; 244 }; 245 246 struct nix_mark_format { 247 u8 total; 248 u8 in_use; 249 u32 *cfg; 250 }; 251 252 struct npc_pkind { 253 struct rsrc_bmap rsrc; 254 u32 *pfchan_map; 255 }; 256 257 struct nix_flowkey { 258 #define NIX_FLOW_KEY_ALG_MAX 32 259 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 260 int in_use; 261 }; 262 263 struct nix_lso { 264 u8 total; 265 u8 in_use; 266 }; 267 268 struct nix_txvlan { 269 #define NIX_TX_VTAG_DEF_MAX 0x400 270 struct rsrc_bmap rsrc; 271 u16 *entry2pfvf_map; 272 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 273 }; 274 275 struct nix_hw { 276 int blkaddr; 277 struct rvu *rvu; 278 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 279 struct nix_mcast mcast; 280 struct nix_flowkey flowkey; 281 struct nix_mark_format mark_format; 282 struct nix_lso lso; 283 struct nix_txvlan txvlan; 284 }; 285 286 /* RVU block's capabilities or functionality, 287 * which vary by silicon version/skew. 288 */ 289 struct hw_cap { 290 /* Transmit side supported functionality */ 291 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 292 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 293 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 294 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 295 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 296 bool nix_shaping; /* Is shaping and coloring supported */ 297 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 298 bool nix_rx_multicast; /* Rx packet replication support */ 299 }; 300 301 struct rvu_hwinfo { 302 u8 total_pfs; /* MAX RVU PFs HW supports */ 303 u16 total_vfs; /* Max RVU VFs HW supports */ 304 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 305 u8 cgx; 306 u8 lmac_per_cgx; 307 u8 cgx_links; 308 u8 lbk_links; 309 u8 sdp_links; 310 u8 npc_kpus; /* No of parser units */ 311 u8 npc_pkinds; /* No of port kinds */ 312 u8 npc_intfs; /* No of interfaces */ 313 u8 npc_kpu_entries; /* No of KPU entries */ 314 u16 npc_counters; /* No of match stats counters */ 315 bool npc_ext_set; /* Extended register set */ 316 317 struct hw_cap cap; 318 struct rvu_block block[BLK_COUNT]; /* Block info */ 319 struct nix_hw *nix; 320 struct rvu *rvu; 321 struct npc_pkind pkind; 322 struct npc_mcam mcam; 323 }; 324 325 struct mbox_wq_info { 326 struct otx2_mbox mbox; 327 struct rvu_work *mbox_wrk; 328 329 struct otx2_mbox mbox_up; 330 struct rvu_work *mbox_wrk_up; 331 332 struct workqueue_struct *mbox_wq; 333 }; 334 335 struct rvu_fwdata { 336 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 337 #define RVU_FWDATA_VERSION 0x0001 338 u32 header_magic; 339 u32 version; /* version id */ 340 341 /* MAC address */ 342 #define PF_MACNUM_MAX 32 343 #define VF_MACNUM_MAX 256 344 u64 pf_macs[PF_MACNUM_MAX]; 345 u64 vf_macs[VF_MACNUM_MAX]; 346 u64 sclk; 347 u64 rclk; 348 u64 mcam_addr; 349 u64 mcam_sz; 350 u64 msixtr_base; 351 #define FWDATA_RESERVED_MEM 1023 352 u64 reserved[FWDATA_RESERVED_MEM]; 353 }; 354 355 struct ptp; 356 357 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 358 * source where it came from. 359 */ 360 struct npc_kpu_profile_adapter { 361 const char *name; 362 u64 version; 363 const struct npc_lt_def_cfg *lt_def; 364 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 365 const struct npc_kpu_profile *kpu; /* array[kpus] */ 366 struct npc_mcam_kex *mkex; 367 size_t pkinds; 368 size_t kpus; 369 }; 370 371 struct rvu { 372 void __iomem *afreg_base; 373 void __iomem *pfreg_base; 374 struct pci_dev *pdev; 375 struct device *dev; 376 struct rvu_hwinfo *hw; 377 struct rvu_pfvf *pf; 378 struct rvu_pfvf *hwvf; 379 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 380 int vfs; /* Number of VFs attached to RVU */ 381 int nix_blkaddr[MAX_NIX_BLKS]; 382 383 /* Mbox */ 384 struct mbox_wq_info afpf_wq_info; 385 struct mbox_wq_info afvf_wq_info; 386 387 /* PF FLR */ 388 struct rvu_work *flr_wrk; 389 struct workqueue_struct *flr_wq; 390 struct mutex flr_lock; /* Serialize FLRs */ 391 392 /* MSI-X */ 393 u16 num_vec; 394 char *irq_name; 395 bool *irq_allocated; 396 dma_addr_t msix_base_iova; 397 u64 msixtr_base_phy; /* Register reset value */ 398 399 /* CGX */ 400 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 401 u8 cgx_mapped_pfs; 402 u8 cgx_cnt_max; /* CGX port count max */ 403 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 404 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 405 * every cgx lmac port 406 */ 407 unsigned long pf_notify_bmap; /* Flags for PF notification */ 408 void **cgx_idmap; /* cgx id to cgx data map table */ 409 struct work_struct cgx_evh_work; 410 struct workqueue_struct *cgx_evh_wq; 411 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 412 struct list_head cgx_evq_head; /* cgx event queue head */ 413 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 414 415 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 416 417 /* Firmware data */ 418 struct rvu_fwdata *fwdata; 419 420 /* NPC KPU data */ 421 struct npc_kpu_profile_adapter kpu; 422 423 struct ptp *ptp; 424 425 #ifdef CONFIG_DEBUG_FS 426 struct rvu_debugfs rvu_dbg; 427 #endif 428 struct rvu_devlink *rvu_dl; 429 }; 430 431 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 432 { 433 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 434 } 435 436 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 437 { 438 return readq(rvu->afreg_base + ((block << 28) | offset)); 439 } 440 441 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 442 { 443 writeq(val, rvu->pfreg_base + offset); 444 } 445 446 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 447 { 448 return readq(rvu->pfreg_base + offset); 449 } 450 451 /* Silicon revisions */ 452 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 453 { 454 struct pci_dev *pdev = rvu->pdev; 455 456 return (pdev->revision == 0x00) && 457 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 458 } 459 460 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 461 { 462 struct pci_dev *pdev = rvu->pdev; 463 464 return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) && 465 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 466 } 467 468 /* Function Prototypes 469 * RVU 470 */ 471 static inline int is_afvf(u16 pcifunc) 472 { 473 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 474 } 475 476 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 477 { 478 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 479 (rvu->fwdata->version == RVU_FWDATA_VERSION); 480 } 481 482 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 483 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 484 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 485 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 486 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 487 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 488 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 489 int rvu_get_pf(u16 pcifunc); 490 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 491 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 492 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 493 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 494 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 495 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 496 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 497 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 498 int rvu_get_num_lbk_chans(void); 499 500 /* RVU HW reg validation */ 501 enum regmap_block { 502 TXSCHQ_HWREGMAP = 0, 503 MAX_HWREGMAP, 504 }; 505 506 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 507 508 /* NPA/NIX AQ APIs */ 509 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 510 int qsize, int inst_size, int res_size); 511 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 512 513 /* CGX APIs */ 514 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 515 { 516 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs); 517 } 518 519 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 520 { 521 *cgx_id = (map >> 4) & 0xF; 522 *lmac_id = (map & 0xF); 523 } 524 525 #define M(_name, _id, fn_name, req, rsp) \ 526 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 527 MBOX_MESSAGES 528 #undef M 529 530 int rvu_cgx_init(struct rvu *rvu); 531 int rvu_cgx_exit(struct rvu *rvu); 532 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 533 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 534 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 535 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 536 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 537 int rxtxflag, u64 *stat); 538 /* NPA APIs */ 539 int rvu_npa_init(struct rvu *rvu); 540 void rvu_npa_freemem(struct rvu *rvu); 541 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 542 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 543 struct npa_aq_enq_rsp *rsp); 544 545 /* NIX APIs */ 546 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 547 int rvu_nix_init(struct rvu *rvu); 548 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 549 int blkaddr, u32 cfg); 550 void rvu_nix_freemem(struct rvu *rvu); 551 int rvu_get_nixlf_count(struct rvu *rvu); 552 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 553 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 554 int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add); 555 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 556 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 557 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 558 559 /* NPC APIs */ 560 int rvu_npc_init(struct rvu *rvu); 561 void rvu_npc_freemem(struct rvu *rvu); 562 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 563 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 564 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 565 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 566 int nixlf, u64 chan, u8 *mac_addr); 567 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 568 int nixlf, u64 chan, bool allmulti); 569 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 570 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 571 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 572 int nixlf, u64 chan); 573 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable); 574 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 575 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 576 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 577 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 578 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 579 int group, int alg_idx, int mcam_index); 580 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 581 int blkaddr, int *alloc_cnt, 582 int *enable_cnt); 583 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 584 int blkaddr, int *alloc_cnt, 585 int *enable_cnt); 586 bool is_npc_intf_tx(u8 intf); 587 bool is_npc_intf_rx(u8 intf); 588 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 589 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 590 int npc_mcam_verify_channel(struct rvu *rvu, u16 pcifunc, u8 intf, u16 channel); 591 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 592 const char *npc_get_field_name(u8 hdr); 593 bool rvu_npc_write_default_rule(struct rvu *rvu, int blkaddr, int nixlf, 594 u16 pcifunc, u8 intf, struct mcam_entry *entry, 595 int *entry_index); 596 int npc_get_bank(struct npc_mcam *mcam, int index); 597 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 598 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 599 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 600 int blkaddr, int index, bool enable); 601 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 602 int blkaddr, u16 src, struct mcam_entry *entry, 603 u8 *intf, u8 *ena); 604 605 #ifdef CONFIG_DEBUG_FS 606 void rvu_dbg_init(struct rvu *rvu); 607 void rvu_dbg_exit(struct rvu *rvu); 608 #else 609 static inline void rvu_dbg_init(struct rvu *rvu) {} 610 static inline void rvu_dbg_exit(struct rvu *rvu) {} 611 #endif 612 #endif /* RVU_H */ 613