1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef RVU_H 9 #define RVU_H 10 11 #include <linux/pci.h> 12 #include <net/devlink.h> 13 14 #include "rvu_struct.h" 15 #include "rvu_devlink.h" 16 #include "common.h" 17 #include "mbox.h" 18 #include "npc.h" 19 #include "rvu_reg.h" 20 21 /* PCI device IDs */ 22 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 23 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 24 25 /* Subsystem Device ID */ 26 #define PCI_SUBSYS_DEVID_96XX 0xB200 27 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 28 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00 29 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00 30 31 /* PCI BAR nos */ 32 #define PCI_AF_REG_BAR_NUM 0 33 #define PCI_PF_REG_BAR_NUM 2 34 #define PCI_MBOX_BAR_NUM 4 35 36 #define NAME_SIZE 32 37 #define MAX_NIX_BLKS 2 38 #define MAX_CPT_BLKS 2 39 40 /* PF_FUNC */ 41 #define RVU_PFVF_PF_SHIFT 10 42 #define RVU_PFVF_PF_MASK 0x3F 43 #define RVU_PFVF_FUNC_SHIFT 0 44 #define RVU_PFVF_FUNC_MASK 0x3FF 45 46 #ifdef CONFIG_DEBUG_FS 47 struct dump_ctx { 48 int lf; 49 int id; 50 bool all; 51 }; 52 53 struct cpt_ctx { 54 int blkaddr; 55 struct rvu *rvu; 56 }; 57 58 struct rvu_debugfs { 59 struct dentry *root; 60 struct dentry *cgx_root; 61 struct dentry *cgx; 62 struct dentry *lmac; 63 struct dentry *npa; 64 struct dentry *nix; 65 struct dentry *npc; 66 struct dentry *cpt; 67 struct dentry *mcs_root; 68 struct dentry *mcs; 69 struct dentry *mcs_rx; 70 struct dentry *mcs_tx; 71 struct dump_ctx npa_aura_ctx; 72 struct dump_ctx npa_pool_ctx; 73 struct dump_ctx nix_cq_ctx; 74 struct dump_ctx nix_rq_ctx; 75 struct dump_ctx nix_sq_ctx; 76 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 77 int npa_qsize_id; 78 int nix_qsize_id; 79 }; 80 #endif 81 82 struct rvu_work { 83 struct work_struct work; 84 struct rvu *rvu; 85 int num_msgs; 86 int up_num_msgs; 87 }; 88 89 struct rsrc_bmap { 90 unsigned long *bmap; /* Pointer to resource bitmap */ 91 u16 max; /* Max resource id or count */ 92 }; 93 94 struct rvu_block { 95 struct rsrc_bmap lf; 96 struct admin_queue *aq; /* NIX/NPA AQ */ 97 u16 *fn_map; /* LF to pcifunc mapping */ 98 bool multislot; 99 bool implemented; 100 u8 addr; /* RVU_BLOCK_ADDR_E */ 101 u8 type; /* RVU_BLOCK_TYPE_E */ 102 u8 lfshift; 103 u64 lookup_reg; 104 u64 pf_lfcnt_reg; 105 u64 vf_lfcnt_reg; 106 u64 lfcfg_reg; 107 u64 msixcfg_reg; 108 u64 lfreset_reg; 109 unsigned char name[NAME_SIZE]; 110 struct rvu *rvu; 111 u64 cpt_flt_eng_map[3]; 112 u64 cpt_rcvrd_eng_map[3]; 113 }; 114 115 struct nix_mcast { 116 struct qmem *mce_ctx; 117 struct qmem *mcast_buf; 118 int replay_pkind; 119 int next_free_mce; 120 struct mutex mce_lock; /* Serialize MCE updates */ 121 }; 122 123 struct nix_mce_list { 124 struct hlist_head head; 125 int count; 126 int max; 127 }; 128 129 /* layer metadata to uniquely identify a packet header field */ 130 struct npc_layer_mdata { 131 u8 lid; 132 u8 ltype; 133 u8 hdr; 134 u8 key; 135 u8 len; 136 }; 137 138 /* Structure to represent a field present in the 139 * generated key. A key field may present anywhere and can 140 * be of any size in the generated key. Once this structure 141 * is populated for fields of interest then field's presence 142 * and location (if present) can be known. 143 */ 144 struct npc_key_field { 145 /* Masks where all set bits indicate position 146 * of a field in the key 147 */ 148 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 149 /* Number of words in the key a field spans. If a field is 150 * of 16 bytes and key offset is 4 then the field will use 151 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 152 * nr_kws will be 3(KW0, KW1 and KW2). 153 */ 154 int nr_kws; 155 /* used by packet header fields */ 156 struct npc_layer_mdata layer_mdata; 157 }; 158 159 struct npc_mcam { 160 struct rsrc_bmap counters; 161 struct mutex lock; /* MCAM entries and counters update lock */ 162 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 163 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 164 u16 bmap_entries; /* Number of unreserved MCAM entries */ 165 u16 bmap_fcnt; /* MCAM entries free count */ 166 u16 *entry2pfvf_map; 167 u16 *entry2cntr_map; 168 u16 *cntr2pfvf_map; 169 u16 *cntr_refcnt; 170 u16 *entry2target_pffunc; 171 u8 keysize; /* MCAM keysize 112/224/448 bits */ 172 u8 banks; /* Number of MCAM banks */ 173 u8 banks_per_entry;/* Number of keywords in key */ 174 u16 banksize; /* Number of MCAM entries in each bank */ 175 u16 total_entries; /* Total number of MCAM entries */ 176 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 177 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 178 u16 lprio_count; 179 u16 lprio_start; 180 u16 hprio_count; 181 u16 hprio_end; 182 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 183 /* fields present in the generated key */ 184 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 185 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 186 u64 tx_features; 187 u64 rx_features; 188 struct list_head mcam_rules; 189 }; 190 191 /* Structure for per RVU func info ie PF/VF */ 192 struct rvu_pfvf { 193 bool npalf; /* Only one NPALF per RVU_FUNC */ 194 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 195 u16 sso; 196 u16 ssow; 197 u16 cptlfs; 198 u16 timlfs; 199 u16 cpt1_lfs; 200 u8 cgx_lmac; 201 202 /* Block LF's MSIX vector info */ 203 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 204 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 205 u16 *msix_lfmap; /* Vector to block LF mapping */ 206 207 /* NPA contexts */ 208 struct qmem *aura_ctx; 209 struct qmem *pool_ctx; 210 struct qmem *npa_qints_ctx; 211 unsigned long *aura_bmap; 212 unsigned long *pool_bmap; 213 214 /* NIX contexts */ 215 struct qmem *rq_ctx; 216 struct qmem *sq_ctx; 217 struct qmem *cq_ctx; 218 struct qmem *rss_ctx; 219 struct qmem *cq_ints_ctx; 220 struct qmem *nix_qints_ctx; 221 unsigned long *sq_bmap; 222 unsigned long *rq_bmap; 223 unsigned long *cq_bmap; 224 225 u16 rx_chan_base; 226 u16 tx_chan_base; 227 u8 rx_chan_cnt; /* total number of RX channels */ 228 u8 tx_chan_cnt; /* total number of TX channels */ 229 u16 maxlen; 230 u16 minlen; 231 232 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */ 233 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 234 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 235 236 /* Broadcast/Multicast/Promisc pkt replication info */ 237 u16 bcast_mce_idx; 238 u16 mcast_mce_idx; 239 u16 promisc_mce_idx; 240 struct nix_mce_list bcast_mce_list; 241 struct nix_mce_list mcast_mce_list; 242 struct nix_mce_list promisc_mce_list; 243 bool use_mce_list; 244 245 struct rvu_npc_mcam_rule *def_ucast_rule; 246 247 bool cgx_in_use; /* this PF/VF using CGX? */ 248 int cgx_users; /* number of cgx users - used only by PFs */ 249 250 int intf_mode; 251 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 252 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 253 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 254 u8 lbkid; /* NIX0/1 lbk link ID */ 255 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 256 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ 257 unsigned long flags; 258 struct sdp_node_info *sdp_info; 259 }; 260 261 enum rvu_pfvf_flags { 262 NIXLF_INITIALIZED = 0, 263 PF_SET_VF_MAC, 264 PF_SET_VF_CFG, 265 PF_SET_VF_TRUSTED, 266 }; 267 268 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 269 270 struct nix_txsch { 271 struct rsrc_bmap schq; 272 u8 lvl; 273 #define NIX_TXSCHQ_FREE BIT_ULL(1) 274 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 275 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 276 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 277 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 278 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 279 u32 *pfvf_map; 280 }; 281 282 struct nix_mark_format { 283 u8 total; 284 u8 in_use; 285 u32 *cfg; 286 }; 287 288 /* smq(flush) to tl1 cir/pir info */ 289 struct nix_smq_tree_ctx { 290 u64 cir_off; 291 u64 cir_val; 292 u64 pir_off; 293 u64 pir_val; 294 }; 295 296 /* smq flush context */ 297 struct nix_smq_flush_ctx { 298 int smq; 299 u16 tl1_schq; 300 u16 tl2_schq; 301 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT]; 302 }; 303 304 struct npc_pkind { 305 struct rsrc_bmap rsrc; 306 u32 *pfchan_map; 307 }; 308 309 struct nix_flowkey { 310 #define NIX_FLOW_KEY_ALG_MAX 32 311 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 312 int in_use; 313 }; 314 315 struct nix_lso { 316 u8 total; 317 u8 in_use; 318 }; 319 320 struct nix_txvlan { 321 #define NIX_TX_VTAG_DEF_MAX 0x400 322 struct rsrc_bmap rsrc; 323 u16 *entry2pfvf_map; 324 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 325 }; 326 327 struct nix_ipolicer { 328 struct rsrc_bmap band_prof; 329 u16 *pfvf_map; 330 u16 *match_id; 331 u16 *ref_count; 332 }; 333 334 struct nix_hw { 335 int blkaddr; 336 struct rvu *rvu; 337 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 338 struct nix_mcast mcast; 339 struct nix_flowkey flowkey; 340 struct nix_mark_format mark_format; 341 struct nix_lso lso; 342 struct nix_txvlan txvlan; 343 struct nix_ipolicer *ipolicer; 344 u64 *tx_credits; 345 }; 346 347 /* RVU block's capabilities or functionality, 348 * which vary by silicon version/skew. 349 */ 350 struct hw_cap { 351 /* Transmit side supported functionality */ 352 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 353 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 354 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 355 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 356 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 357 bool nix_shaping; /* Is shaping and coloring supported */ 358 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 359 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 360 bool nix_rx_multicast; /* Rx packet replication support */ 361 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 362 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 363 bool programmable_chans; /* Channels programmable ? */ 364 bool ipolicer; 365 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */ 366 bool npc_hash_extract; /* Hash extract enabled ? */ 367 bool npc_exact_match_enabled; /* Exact match supported ? */ 368 }; 369 370 struct rvu_hwinfo { 371 u8 total_pfs; /* MAX RVU PFs HW supports */ 372 u16 total_vfs; /* Max RVU VFs HW supports */ 373 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 374 u8 cgx; 375 u8 lmac_per_cgx; 376 u16 cgx_chan_base; /* CGX base channel number */ 377 u16 lbk_chan_base; /* LBK base channel number */ 378 u16 sdp_chan_base; /* SDP base channel number */ 379 u16 cpt_chan_base; /* CPT base channel number */ 380 u8 cgx_links; 381 u8 lbk_links; 382 u8 sdp_links; 383 u8 cpt_links; /* Number of CPT links */ 384 u8 npc_kpus; /* No of parser units */ 385 u8 npc_pkinds; /* No of port kinds */ 386 u8 npc_intfs; /* No of interfaces */ 387 u8 npc_kpu_entries; /* No of KPU entries */ 388 u16 npc_counters; /* No of match stats counters */ 389 u32 lbk_bufsize; /* FIFO size supported by LBK */ 390 bool npc_ext_set; /* Extended register set */ 391 u64 npc_stat_ena; /* Match stats enable bit */ 392 393 struct hw_cap cap; 394 struct rvu_block block[BLK_COUNT]; /* Block info */ 395 struct nix_hw *nix; 396 struct rvu *rvu; 397 struct npc_pkind pkind; 398 struct npc_mcam mcam; 399 struct npc_exact_table *table; 400 }; 401 402 struct mbox_wq_info { 403 struct otx2_mbox mbox; 404 struct rvu_work *mbox_wrk; 405 406 struct otx2_mbox mbox_up; 407 struct rvu_work *mbox_wrk_up; 408 409 struct workqueue_struct *mbox_wq; 410 }; 411 412 struct rvu_fwdata { 413 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 414 #define RVU_FWDATA_VERSION 0x0001 415 u32 header_magic; 416 u32 version; /* version id */ 417 418 /* MAC address */ 419 #define PF_MACNUM_MAX 32 420 #define VF_MACNUM_MAX 256 421 u64 pf_macs[PF_MACNUM_MAX]; 422 u64 vf_macs[VF_MACNUM_MAX]; 423 u64 sclk; 424 u64 rclk; 425 u64 mcam_addr; 426 u64 mcam_sz; 427 u64 msixtr_base; 428 u32 ptp_ext_clk_rate; 429 u32 ptp_ext_tstamp; 430 #define FWDATA_RESERVED_MEM 1022 431 u64 reserved[FWDATA_RESERVED_MEM]; 432 #define CGX_MAX 9 433 #define CGX_LMACS_MAX 4 434 #define CGX_LMACS_USX 8 435 union { 436 struct cgx_lmac_fwdata_s 437 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 438 struct cgx_lmac_fwdata_s 439 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX]; 440 }; 441 /* Do not add new fields below this line */ 442 }; 443 444 struct ptp; 445 446 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 447 * source where it came from. 448 */ 449 struct npc_kpu_profile_adapter { 450 const char *name; 451 u64 version; 452 const struct npc_lt_def_cfg *lt_def; 453 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 454 const struct npc_kpu_profile *kpu; /* array[kpus] */ 455 struct npc_mcam_kex *mkex; 456 struct npc_mcam_kex_hash *mkex_hash; 457 bool custom; 458 size_t pkinds; 459 size_t kpus; 460 }; 461 462 #define RVU_SWITCH_LBK_CHAN 63 463 464 struct rvu_switch { 465 struct mutex switch_lock; /* Serialize flow installation */ 466 u32 used_entries; 467 u16 *entry2pcifunc; 468 u16 mode; 469 u16 start_entry; 470 }; 471 472 struct rvu { 473 void __iomem *afreg_base; 474 void __iomem *pfreg_base; 475 struct pci_dev *pdev; 476 struct device *dev; 477 struct rvu_hwinfo *hw; 478 struct rvu_pfvf *pf; 479 struct rvu_pfvf *hwvf; 480 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 481 struct mutex alias_lock; /* Serialize bar2 alias access */ 482 int vfs; /* Number of VFs attached to RVU */ 483 int nix_blkaddr[MAX_NIX_BLKS]; 484 485 /* Mbox */ 486 struct mbox_wq_info afpf_wq_info; 487 struct mbox_wq_info afvf_wq_info; 488 489 /* PF FLR */ 490 struct rvu_work *flr_wrk; 491 struct workqueue_struct *flr_wq; 492 struct mutex flr_lock; /* Serialize FLRs */ 493 494 /* MSI-X */ 495 u16 num_vec; 496 char *irq_name; 497 bool *irq_allocated; 498 dma_addr_t msix_base_iova; 499 u64 msixtr_base_phy; /* Register reset value */ 500 501 /* CGX */ 502 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 503 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 504 u8 cgx_mapped_pfs; 505 u8 cgx_cnt_max; /* CGX port count max */ 506 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 507 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for 508 * every cgx lmac port 509 */ 510 unsigned long pf_notify_bmap; /* Flags for PF notification */ 511 void **cgx_idmap; /* cgx id to cgx data map table */ 512 struct work_struct cgx_evh_work; 513 struct workqueue_struct *cgx_evh_wq; 514 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 515 struct list_head cgx_evq_head; /* cgx event queue head */ 516 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 517 518 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 519 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 520 521 /* Firmware data */ 522 struct rvu_fwdata *fwdata; 523 void *kpu_fwdata; 524 size_t kpu_fwdata_sz; 525 void __iomem *kpu_prfl_addr; 526 527 /* NPC KPU data */ 528 struct npc_kpu_profile_adapter kpu; 529 530 struct ptp *ptp; 531 532 int mcs_blk_cnt; 533 int cpt_pf_num; 534 535 #ifdef CONFIG_DEBUG_FS 536 struct rvu_debugfs rvu_dbg; 537 #endif 538 struct rvu_devlink *rvu_dl; 539 540 /* RVU switch implementation over NPC with DMAC rules */ 541 struct rvu_switch rswitch; 542 543 struct work_struct mcs_intr_work; 544 struct workqueue_struct *mcs_intr_wq; 545 struct list_head mcs_intrq_head; 546 /* mcs interrupt queue lock */ 547 spinlock_t mcs_intrq_lock; 548 /* CPT interrupt lock */ 549 spinlock_t cpt_intr_lock; 550 }; 551 552 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 553 { 554 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 555 } 556 557 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 558 { 559 return readq(rvu->afreg_base + ((block << 28) | offset)); 560 } 561 562 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 563 { 564 writeq(val, rvu->pfreg_base + offset); 565 } 566 567 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 568 { 569 return readq(rvu->pfreg_base + offset); 570 } 571 572 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 573 { 574 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of 575 * write operation. 576 */ 577 rvu_write64(rvu, block, offset, val); 578 rvu_read64(rvu, block, offset); 579 /* Barrier to ensure read completes before accessing LF registers */ 580 mb(); 581 } 582 583 /* Silicon revisions */ 584 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 585 { 586 struct pci_dev *pdev = rvu->pdev; 587 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 588 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 589 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 590 (pdev->revision == 0x14)); 591 } 592 593 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 594 { 595 struct pci_dev *pdev = rvu->pdev; 596 597 return (pdev->revision == 0x00); 598 } 599 600 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 601 { 602 struct pci_dev *pdev = rvu->pdev; 603 604 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 605 } 606 607 static inline bool is_rvu_95xx_A0(struct rvu *rvu) 608 { 609 struct pci_dev *pdev = rvu->pdev; 610 611 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 612 } 613 614 /* REVID for PCIe devices. 615 * Bits 0..1: minor pass, bit 3..2: major pass 616 * bits 7..4: midr id 617 */ 618 #define PCI_REVISION_ID_96XX 0x00 619 #define PCI_REVISION_ID_95XX 0x10 620 #define PCI_REVISION_ID_95XXN 0x20 621 #define PCI_REVISION_ID_98XX 0x30 622 #define PCI_REVISION_ID_95XXMM 0x40 623 #define PCI_REVISION_ID_95XXO 0xE0 624 625 static inline bool is_rvu_otx2(struct rvu *rvu) 626 { 627 struct pci_dev *pdev = rvu->pdev; 628 629 u8 midr = pdev->revision & 0xF0; 630 631 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 632 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 633 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 634 } 635 636 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu) 637 { 638 u64 npc_const3; 639 640 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3); 641 if (!(npc_const3 & BIT_ULL(62))) 642 return false; 643 644 return true; 645 } 646 647 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 648 u8 lmacid, u8 chan) 649 { 650 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 651 u16 cgx_chans = nix_const & 0xFFULL; 652 struct rvu_hwinfo *hw = rvu->hw; 653 654 if (!hw->cap.programmable_chans) 655 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 656 657 return rvu->hw->cgx_chan_base + 658 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 659 } 660 661 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 662 u8 chan) 663 { 664 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 665 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 666 struct rvu_hwinfo *hw = rvu->hw; 667 668 if (!hw->cap.programmable_chans) 669 return NIX_CHAN_LBK_CHX(lbkid, chan); 670 671 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 672 } 673 674 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 675 { 676 struct rvu_hwinfo *hw = rvu->hw; 677 678 if (!hw->cap.programmable_chans) 679 return NIX_CHAN_SDP_CHX(chan); 680 681 return hw->sdp_chan_base + chan; 682 } 683 684 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 685 { 686 return rvu->hw->cpt_chan_base + chan; 687 } 688 689 /* Function Prototypes 690 * RVU 691 */ 692 static inline bool is_afvf(u16 pcifunc) 693 { 694 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 695 } 696 697 static inline bool is_vf(u16 pcifunc) 698 { 699 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 700 } 701 702 /* check if PF_FUNC is AF */ 703 static inline bool is_pffunc_af(u16 pcifunc) 704 { 705 return !pcifunc; 706 } 707 708 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 709 { 710 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 711 (rvu->fwdata->version == RVU_FWDATA_VERSION); 712 } 713 714 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 715 void rvu_free_bitmap(struct rsrc_bmap *rsrc); 716 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 717 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 718 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 719 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 720 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 721 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 722 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 723 int rvu_get_pf(u16 pcifunc); 724 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 725 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 726 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 727 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 728 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 729 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 730 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 731 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 732 int rvu_get_num_lbk_chans(void); 733 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 734 u16 global_slot, u16 *slot_in_block); 735 736 /* RVU HW reg validation */ 737 enum regmap_block { 738 TXSCHQ_HWREGMAP = 0, 739 MAX_HWREGMAP, 740 }; 741 742 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 743 744 /* NPA/NIX AQ APIs */ 745 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 746 int qsize, int inst_size, int res_size); 747 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 748 749 /* SDP APIs */ 750 int rvu_sdp_init(struct rvu *rvu); 751 bool is_sdp_pfvf(u16 pcifunc); 752 bool is_sdp_pf(u16 pcifunc); 753 bool is_sdp_vf(u16 pcifunc); 754 755 /* CGX APIs */ 756 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 757 { 758 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 759 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT); 760 } 761 762 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 763 { 764 *cgx_id = (map >> 4) & 0xF; 765 *lmac_id = (map & 0xF); 766 } 767 768 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 769 { 770 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 771 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))); 772 } 773 774 #define M(_name, _id, fn_name, req, rsp) \ 775 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 776 MBOX_MESSAGES 777 #undef M 778 779 int rvu_cgx_init(struct rvu *rvu); 780 int rvu_cgx_exit(struct rvu *rvu); 781 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 782 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 783 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 784 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 785 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 786 int rxtxflag, u64 *stat); 787 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 788 789 /* NPA APIs */ 790 int rvu_npa_init(struct rvu *rvu); 791 void rvu_npa_freemem(struct rvu *rvu); 792 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 793 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 794 struct npa_aq_enq_rsp *rsp); 795 796 /* NIX APIs */ 797 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 798 int rvu_nix_init(struct rvu *rvu); 799 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 800 int blkaddr, u32 cfg); 801 void rvu_nix_freemem(struct rvu *rvu); 802 int rvu_get_nixlf_count(struct rvu *rvu); 803 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 804 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 805 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 806 struct nix_mce_list *mce_list, 807 int mce_idx, int mcam_index, bool add); 808 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 809 struct nix_mce_list **mce_list, int *mce_idx); 810 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 811 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 812 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 813 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 814 struct nix_hw **nix_hw, int *blkaddr); 815 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 816 u16 rq_idx, u16 match_id); 817 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 818 struct nix_cn10k_aq_enq_req *aq_req, 819 struct nix_cn10k_aq_enq_rsp *aq_rsp, 820 u16 pcifunc, u8 ctype, u32 qidx); 821 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 822 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type); 823 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 824 u32 convert_bytes_to_dwrr_mtu(u32 bytes); 825 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc, 826 struct nix_txsch *txsch, bool enable); 827 828 /* NPC APIs */ 829 void rvu_npc_freemem(struct rvu *rvu); 830 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 831 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 832 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 833 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 834 int nixlf, u64 chan, u8 *mac_addr); 835 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 836 int nixlf, u64 chan, u8 chan_cnt); 837 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 838 bool enable); 839 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 840 int nixlf, u64 chan); 841 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 842 bool enable); 843 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 844 u64 chan); 845 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 846 bool enable); 847 848 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 849 int nixlf, int type, bool enable); 850 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 851 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable); 852 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 853 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 854 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 855 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 856 int group, int alg_idx, int mcam_index); 857 858 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 859 int blkaddr, int *alloc_cnt, 860 int *enable_cnt); 861 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 862 int blkaddr, int *alloc_cnt, 863 int *enable_cnt); 864 bool is_npc_intf_tx(u8 intf); 865 bool is_npc_intf_rx(u8 intf); 866 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 867 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 868 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 869 const char *npc_get_field_name(u8 hdr); 870 int npc_get_bank(struct npc_mcam *mcam, int index); 871 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 872 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 873 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 874 int blkaddr, int index, bool enable); 875 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 876 int blkaddr, u16 src, struct mcam_entry *entry, 877 u8 *intf, u8 *ena); 878 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); 879 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 880 u32 rvu_cgx_get_fifolen(struct rvu *rvu); 881 void *rvu_first_cgx_pdata(struct rvu *rvu); 882 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 883 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); 884 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, 885 u16 pfc_en); 886 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); 887 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); 888 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf, 889 int type); 890 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 891 int index); 892 int rvu_npc_init(struct rvu *rvu); 893 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 894 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 895 u64 bcast_mcast_val, u64 bcast_mcast_mask); 896 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx); 897 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf); 898 899 /* CPT APIs */ 900 int rvu_cpt_register_interrupts(struct rvu *rvu); 901 void rvu_cpt_unregister_interrupts(struct rvu *rvu); 902 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, 903 int slot); 904 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc); 905 int rvu_cpt_init(struct rvu *rvu); 906 907 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0) 908 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16) 909 910 /* CN10K RVU */ 911 int rvu_set_channels_base(struct rvu *rvu); 912 void rvu_program_channels(struct rvu *rvu); 913 914 /* CN10K NIX */ 915 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); 916 917 /* CN10K RVU - LMT*/ 918 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 919 920 #ifdef CONFIG_DEBUG_FS 921 void rvu_dbg_init(struct rvu *rvu); 922 void rvu_dbg_exit(struct rvu *rvu); 923 #else 924 static inline void rvu_dbg_init(struct rvu *rvu) {} 925 static inline void rvu_dbg_exit(struct rvu *rvu) {} 926 #endif 927 928 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); 929 930 /* RVU Switch */ 931 void rvu_switch_enable(struct rvu *rvu); 932 void rvu_switch_disable(struct rvu *rvu); 933 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc); 934 935 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 936 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 937 u8 shift_dir); 938 int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 939 940 /* CN10K MCS */ 941 int rvu_mcs_init(struct rvu *rvu); 942 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); 943 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); 944 void rvu_mcs_exit(struct rvu *rvu); 945 946 #endif /* RVU_H */ 947