1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef RVU_H 12 #define RVU_H 13 14 #include <linux/pci.h> 15 #include "rvu_struct.h" 16 #include "common.h" 17 #include "mbox.h" 18 19 /* PCI device IDs */ 20 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 21 22 /* Subsystem Device ID */ 23 #define PCI_SUBSYS_DEVID_96XX 0xB200 24 25 /* PCI BAR nos */ 26 #define PCI_AF_REG_BAR_NUM 0 27 #define PCI_PF_REG_BAR_NUM 2 28 #define PCI_MBOX_BAR_NUM 4 29 30 #define NAME_SIZE 32 31 32 /* PF_FUNC */ 33 #define RVU_PFVF_PF_SHIFT 10 34 #define RVU_PFVF_PF_MASK 0x3F 35 #define RVU_PFVF_FUNC_SHIFT 0 36 #define RVU_PFVF_FUNC_MASK 0x3FF 37 38 #ifdef CONFIG_DEBUG_FS 39 struct dump_ctx { 40 int lf; 41 int id; 42 bool all; 43 }; 44 45 struct rvu_debugfs { 46 struct dentry *root; 47 struct dentry *cgx_root; 48 struct dentry *cgx; 49 struct dentry *lmac; 50 struct dentry *npa; 51 struct dentry *nix; 52 struct dentry *npc; 53 struct dump_ctx npa_aura_ctx; 54 struct dump_ctx npa_pool_ctx; 55 struct dump_ctx nix_cq_ctx; 56 struct dump_ctx nix_rq_ctx; 57 struct dump_ctx nix_sq_ctx; 58 int npa_qsize_id; 59 int nix_qsize_id; 60 }; 61 #endif 62 63 struct rvu_work { 64 struct work_struct work; 65 struct rvu *rvu; 66 int num_msgs; 67 int up_num_msgs; 68 }; 69 70 struct rsrc_bmap { 71 unsigned long *bmap; /* Pointer to resource bitmap */ 72 u16 max; /* Max resource id or count */ 73 }; 74 75 struct rvu_block { 76 struct rsrc_bmap lf; 77 struct admin_queue *aq; /* NIX/NPA AQ */ 78 u16 *fn_map; /* LF to pcifunc mapping */ 79 bool multislot; 80 bool implemented; 81 u8 addr; /* RVU_BLOCK_ADDR_E */ 82 u8 type; /* RVU_BLOCK_TYPE_E */ 83 u8 lfshift; 84 u64 lookup_reg; 85 u64 pf_lfcnt_reg; 86 u64 vf_lfcnt_reg; 87 u64 lfcfg_reg; 88 u64 msixcfg_reg; 89 u64 lfreset_reg; 90 unsigned char name[NAME_SIZE]; 91 }; 92 93 struct nix_mcast { 94 struct qmem *mce_ctx; 95 struct qmem *mcast_buf; 96 int replay_pkind; 97 int next_free_mce; 98 struct mutex mce_lock; /* Serialize MCE updates */ 99 }; 100 101 struct nix_mce_list { 102 struct hlist_head head; 103 int count; 104 int max; 105 }; 106 107 struct npc_mcam { 108 struct rsrc_bmap counters; 109 struct mutex lock; /* MCAM entries and counters update lock */ 110 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 111 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 112 u16 bmap_entries; /* Number of unreserved MCAM entries */ 113 u16 bmap_fcnt; /* MCAM entries free count */ 114 u16 *entry2pfvf_map; 115 u16 *entry2cntr_map; 116 u16 *cntr2pfvf_map; 117 u16 *cntr_refcnt; 118 u8 keysize; /* MCAM keysize 112/224/448 bits */ 119 u8 banks; /* Number of MCAM banks */ 120 u8 banks_per_entry;/* Number of keywords in key */ 121 u16 banksize; /* Number of MCAM entries in each bank */ 122 u16 total_entries; /* Total number of MCAM entries */ 123 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 124 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 125 u16 lprio_count; 126 u16 lprio_start; 127 u16 hprio_count; 128 u16 hprio_end; 129 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 130 }; 131 132 /* Structure for per RVU func info ie PF/VF */ 133 struct rvu_pfvf { 134 bool npalf; /* Only one NPALF per RVU_FUNC */ 135 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 136 u16 sso; 137 u16 ssow; 138 u16 cptlfs; 139 u16 timlfs; 140 u8 cgx_lmac; 141 142 /* Block LF's MSIX vector info */ 143 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 144 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 145 u16 *msix_lfmap; /* Vector to block LF mapping */ 146 147 /* NPA contexts */ 148 struct qmem *aura_ctx; 149 struct qmem *pool_ctx; 150 struct qmem *npa_qints_ctx; 151 unsigned long *aura_bmap; 152 unsigned long *pool_bmap; 153 154 /* NIX contexts */ 155 struct qmem *rq_ctx; 156 struct qmem *sq_ctx; 157 struct qmem *cq_ctx; 158 struct qmem *rss_ctx; 159 struct qmem *cq_ints_ctx; 160 struct qmem *nix_qints_ctx; 161 unsigned long *sq_bmap; 162 unsigned long *rq_bmap; 163 unsigned long *cq_bmap; 164 165 u16 rx_chan_base; 166 u16 tx_chan_base; 167 u8 rx_chan_cnt; /* total number of RX channels */ 168 u8 tx_chan_cnt; /* total number of TX channels */ 169 u16 maxlen; 170 u16 minlen; 171 172 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 173 174 /* Broadcast pkt replication info */ 175 u16 bcast_mce_idx; 176 struct nix_mce_list bcast_mce_list; 177 178 /* VLAN offload */ 179 struct mcam_entry entry; 180 int rxvlan_index; 181 bool rxvlan; 182 183 bool cgx_in_use; /* this PF/VF using CGX? */ 184 int cgx_users; /* number of cgx users - used only by PFs */ 185 }; 186 187 struct nix_txsch { 188 struct rsrc_bmap schq; 189 u8 lvl; 190 #define NIX_TXSCHQ_FREE BIT_ULL(1) 191 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 192 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 193 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 194 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 195 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 196 u32 *pfvf_map; 197 }; 198 199 struct nix_mark_format { 200 u8 total; 201 u8 in_use; 202 u32 *cfg; 203 }; 204 205 struct npc_pkind { 206 struct rsrc_bmap rsrc; 207 u32 *pfchan_map; 208 }; 209 210 struct nix_flowkey { 211 #define NIX_FLOW_KEY_ALG_MAX 32 212 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 213 int in_use; 214 }; 215 216 struct nix_lso { 217 u8 total; 218 u8 in_use; 219 }; 220 221 struct nix_hw { 222 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 223 struct nix_mcast mcast; 224 struct nix_flowkey flowkey; 225 struct nix_mark_format mark_format; 226 struct nix_lso lso; 227 }; 228 229 /* RVU block's capabilities or functionality, 230 * which vary by silicon version/skew. 231 */ 232 struct hw_cap { 233 /* Transmit side supported functionality */ 234 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 235 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 236 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 237 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 238 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 239 bool nix_shaping; /* Is shaping and coloring supported */ 240 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 241 bool nix_rx_multicast; /* Rx packet replication support */ 242 }; 243 244 struct rvu_hwinfo { 245 u8 total_pfs; /* MAX RVU PFs HW supports */ 246 u16 total_vfs; /* Max RVU VFs HW supports */ 247 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 248 u8 cgx; 249 u8 lmac_per_cgx; 250 u8 cgx_links; 251 u8 lbk_links; 252 u8 sdp_links; 253 u8 npc_kpus; /* No of parser units */ 254 255 struct hw_cap cap; 256 struct rvu_block block[BLK_COUNT]; /* Block info */ 257 struct nix_hw *nix0; 258 struct npc_pkind pkind; 259 struct npc_mcam mcam; 260 }; 261 262 struct mbox_wq_info { 263 struct otx2_mbox mbox; 264 struct rvu_work *mbox_wrk; 265 266 struct otx2_mbox mbox_up; 267 struct rvu_work *mbox_wrk_up; 268 269 struct workqueue_struct *mbox_wq; 270 }; 271 272 struct rvu_fwdata { 273 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 274 #define RVU_FWDATA_VERSION 0x0001 275 u32 header_magic; 276 u32 version; /* version id */ 277 278 /* MAC address */ 279 #define PF_MACNUM_MAX 32 280 #define VF_MACNUM_MAX 256 281 u64 pf_macs[PF_MACNUM_MAX]; 282 u64 vf_macs[VF_MACNUM_MAX]; 283 u64 sclk; 284 u64 rclk; 285 u64 mcam_addr; 286 u64 mcam_sz; 287 u64 msixtr_base; 288 #define FWDATA_RESERVED_MEM 1023 289 u64 reserved[FWDATA_RESERVED_MEM]; 290 }; 291 292 struct ptp; 293 294 struct rvu { 295 void __iomem *afreg_base; 296 void __iomem *pfreg_base; 297 struct pci_dev *pdev; 298 struct device *dev; 299 struct rvu_hwinfo *hw; 300 struct rvu_pfvf *pf; 301 struct rvu_pfvf *hwvf; 302 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 303 int vfs; /* Number of VFs attached to RVU */ 304 305 /* Mbox */ 306 struct mbox_wq_info afpf_wq_info; 307 struct mbox_wq_info afvf_wq_info; 308 309 /* PF FLR */ 310 struct rvu_work *flr_wrk; 311 struct workqueue_struct *flr_wq; 312 struct mutex flr_lock; /* Serialize FLRs */ 313 314 /* MSI-X */ 315 u16 num_vec; 316 char *irq_name; 317 bool *irq_allocated; 318 dma_addr_t msix_base_iova; 319 u64 msixtr_base_phy; /* Register reset value */ 320 321 /* CGX */ 322 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 323 u8 cgx_mapped_pfs; 324 u8 cgx_cnt_max; /* CGX port count max */ 325 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 326 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for 327 * every cgx lmac port 328 */ 329 unsigned long pf_notify_bmap; /* Flags for PF notification */ 330 void **cgx_idmap; /* cgx id to cgx data map table */ 331 struct work_struct cgx_evh_work; 332 struct workqueue_struct *cgx_evh_wq; 333 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 334 struct list_head cgx_evq_head; /* cgx event queue head */ 335 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 336 337 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 338 339 /* Firmware data */ 340 struct rvu_fwdata *fwdata; 341 342 struct ptp *ptp; 343 344 #ifdef CONFIG_DEBUG_FS 345 struct rvu_debugfs rvu_dbg; 346 #endif 347 }; 348 349 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 350 { 351 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 352 } 353 354 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 355 { 356 return readq(rvu->afreg_base + ((block << 28) | offset)); 357 } 358 359 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 360 { 361 writeq(val, rvu->pfreg_base + offset); 362 } 363 364 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 365 { 366 return readq(rvu->pfreg_base + offset); 367 } 368 369 /* Silicon revisions */ 370 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 371 { 372 struct pci_dev *pdev = rvu->pdev; 373 374 return (pdev->revision == 0x00) && 375 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 376 } 377 378 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 379 { 380 struct pci_dev *pdev = rvu->pdev; 381 382 return ((pdev->revision == 0x00) || (pdev->revision == 0x01)) && 383 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX); 384 } 385 386 /* Function Prototypes 387 * RVU 388 */ 389 static inline int is_afvf(u16 pcifunc) 390 { 391 return !(pcifunc & ~RVU_PFVF_FUNC_MASK); 392 } 393 394 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 395 { 396 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 397 (rvu->fwdata->version == RVU_FWDATA_VERSION); 398 } 399 400 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 401 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 402 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 403 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 404 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 405 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 406 int rvu_get_pf(u16 pcifunc); 407 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 408 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 409 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 410 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 411 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 412 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 413 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 414 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 415 416 /* RVU HW reg validation */ 417 enum regmap_block { 418 TXSCHQ_HWREGMAP = 0, 419 MAX_HWREGMAP, 420 }; 421 422 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 423 424 /* NPA/NIX AQ APIs */ 425 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 426 int qsize, int inst_size, int res_size); 427 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 428 429 /* CGX APIs */ 430 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 431 { 432 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs); 433 } 434 435 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 436 { 437 *cgx_id = (map >> 4) & 0xF; 438 *lmac_id = (map & 0xF); 439 } 440 441 #define M(_name, _id, fn_name, req, rsp) \ 442 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 443 MBOX_MESSAGES 444 #undef M 445 446 int rvu_cgx_init(struct rvu *rvu); 447 int rvu_cgx_exit(struct rvu *rvu); 448 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 449 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 450 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 451 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 452 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 453 int rxtxflag, u64 *stat); 454 /* NPA APIs */ 455 int rvu_npa_init(struct rvu *rvu); 456 void rvu_npa_freemem(struct rvu *rvu); 457 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 458 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 459 struct npa_aq_enq_rsp *rsp); 460 461 /* NIX APIs */ 462 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 463 int rvu_nix_init(struct rvu *rvu); 464 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 465 int blkaddr, u32 cfg); 466 void rvu_nix_freemem(struct rvu *rvu); 467 int rvu_get_nixlf_count(struct rvu *rvu); 468 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 469 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 470 471 /* NPC APIs */ 472 int rvu_npc_init(struct rvu *rvu); 473 void rvu_npc_freemem(struct rvu *rvu); 474 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 475 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 476 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 477 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 478 int nixlf, u64 chan, u8 *mac_addr); 479 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 480 int nixlf, u64 chan, bool allmulti); 481 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 482 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf); 483 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 484 int nixlf, u64 chan); 485 void rvu_npc_disable_bcast_entry(struct rvu *rvu, u16 pcifunc); 486 int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf); 487 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 488 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 489 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 490 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 491 int group, int alg_idx, int mcam_index); 492 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 493 int blkaddr, int *alloc_cnt, 494 int *enable_cnt); 495 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 496 int blkaddr, int *alloc_cnt, 497 int *enable_cnt); 498 499 #ifdef CONFIG_DEBUG_FS 500 void rvu_dbg_init(struct rvu *rvu); 501 void rvu_dbg_exit(struct rvu *rvu); 502 #else 503 static inline void rvu_dbg_init(struct rvu *rvu) {} 504 static inline void rvu_dbg_exit(struct rvu *rvu) {} 505 #endif 506 #endif /* RVU_H */ 507