1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/delay.h> 11 #include <linux/irq.h> 12 #include <linux/pci.h> 13 #include <linux/sysfs.h> 14 15 #include "cgx.h" 16 #include "rvu.h" 17 #include "rvu_reg.h" 18 #include "ptp.h" 19 20 #include "rvu_trace.h" 21 22 #define DRV_NAME "rvu_af" 23 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 24 25 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 26 27 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 28 struct rvu_block *block, int lf); 29 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 30 struct rvu_block *block, int lf); 31 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 32 33 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 34 int type, int num, 35 void (mbox_handler)(struct work_struct *), 36 void (mbox_up_handler)(struct work_struct *)); 37 enum { 38 TYPE_AFVF, 39 TYPE_AFPF, 40 }; 41 42 /* Supported devices */ 43 static const struct pci_device_id rvu_id_table[] = { 44 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 45 { 0, } /* end of table */ 46 }; 47 48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 49 MODULE_DESCRIPTION(DRV_STRING); 50 MODULE_LICENSE("GPL v2"); 51 MODULE_DEVICE_TABLE(pci, rvu_id_table); 52 53 static char *mkex_profile; /* MKEX profile name */ 54 module_param(mkex_profile, charp, 0000); 55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 56 57 static char *kpu_profile; /* KPU profile name */ 58 module_param(kpu_profile, charp, 0000); 59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string"); 60 61 static void rvu_setup_hw_capabilities(struct rvu *rvu) 62 { 63 struct rvu_hwinfo *hw = rvu->hw; 64 65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 66 hw->cap.nix_fixed_txschq_mapping = false; 67 hw->cap.nix_shaping = true; 68 hw->cap.nix_tx_link_bp = true; 69 hw->cap.nix_rx_multicast = true; 70 hw->cap.nix_shaper_toggle_wait = false; 71 hw->rvu = rvu; 72 73 if (is_rvu_pre_96xx_C0(rvu)) { 74 hw->cap.nix_fixed_txschq_mapping = true; 75 hw->cap.nix_txsch_per_cgx_lmac = 4; 76 hw->cap.nix_txsch_per_lbk_lmac = 132; 77 hw->cap.nix_txsch_per_sdp_lmac = 76; 78 hw->cap.nix_shaping = false; 79 hw->cap.nix_tx_link_bp = false; 80 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu)) 81 hw->cap.nix_rx_multicast = false; 82 } 83 if (!is_rvu_pre_96xx_C0(rvu)) 84 hw->cap.nix_shaper_toggle_wait = true; 85 86 if (!is_rvu_otx2(rvu)) 87 hw->cap.per_pf_mbox_regs = true; 88 } 89 90 /* Poll a RVU block's register 'offset', for a 'zero' 91 * or 'nonzero' at bits specified by 'mask' 92 */ 93 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 94 { 95 unsigned long timeout = jiffies + usecs_to_jiffies(20000); 96 bool twice = false; 97 void __iomem *reg; 98 u64 reg_val; 99 100 reg = rvu->afreg_base + ((block << 28) | offset); 101 again: 102 reg_val = readq(reg); 103 if (zero && !(reg_val & mask)) 104 return 0; 105 if (!zero && (reg_val & mask)) 106 return 0; 107 if (time_before(jiffies, timeout)) { 108 usleep_range(1, 5); 109 goto again; 110 } 111 /* In scenarios where CPU is scheduled out before checking 112 * 'time_before' (above) and gets scheduled in such that 113 * jiffies are beyond timeout value, then check again if HW is 114 * done with the operation in the meantime. 115 */ 116 if (!twice) { 117 twice = true; 118 goto again; 119 } 120 return -EBUSY; 121 } 122 123 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 124 { 125 int id; 126 127 if (!rsrc->bmap) 128 return -EINVAL; 129 130 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 131 if (id >= rsrc->max) 132 return -ENOSPC; 133 134 __set_bit(id, rsrc->bmap); 135 136 return id; 137 } 138 139 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 140 { 141 int start; 142 143 if (!rsrc->bmap) 144 return -EINVAL; 145 146 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 147 if (start >= rsrc->max) 148 return -ENOSPC; 149 150 bitmap_set(rsrc->bmap, start, nrsrc); 151 return start; 152 } 153 154 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 155 { 156 if (!rsrc->bmap) 157 return; 158 if (start >= rsrc->max) 159 return; 160 161 bitmap_clear(rsrc->bmap, start, nrsrc); 162 } 163 164 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 165 { 166 int start; 167 168 if (!rsrc->bmap) 169 return false; 170 171 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 172 if (start >= rsrc->max) 173 return false; 174 175 return true; 176 } 177 178 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 179 { 180 if (!rsrc->bmap) 181 return; 182 183 __clear_bit(id, rsrc->bmap); 184 } 185 186 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 187 { 188 int used; 189 190 if (!rsrc->bmap) 191 return 0; 192 193 used = bitmap_weight(rsrc->bmap, rsrc->max); 194 return (rsrc->max - used); 195 } 196 197 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id) 198 { 199 if (!rsrc->bmap) 200 return false; 201 202 return !test_bit(id, rsrc->bmap); 203 } 204 205 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 206 { 207 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 208 sizeof(long), GFP_KERNEL); 209 if (!rsrc->bmap) 210 return -ENOMEM; 211 return 0; 212 } 213 214 void rvu_free_bitmap(struct rsrc_bmap *rsrc) 215 { 216 kfree(rsrc->bmap); 217 } 218 219 /* Get block LF's HW index from a PF_FUNC's block slot number */ 220 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 221 { 222 u16 match = 0; 223 int lf; 224 225 mutex_lock(&rvu->rsrc_lock); 226 for (lf = 0; lf < block->lf.max; lf++) { 227 if (block->fn_map[lf] == pcifunc) { 228 if (slot == match) { 229 mutex_unlock(&rvu->rsrc_lock); 230 return lf; 231 } 232 match++; 233 } 234 } 235 mutex_unlock(&rvu->rsrc_lock); 236 return -ENODEV; 237 } 238 239 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 240 * Some silicon variants of OcteonTX2 supports 241 * multiple blocks of same type. 242 * 243 * @pcifunc has to be zero when no LF is yet attached. 244 * 245 * For a pcifunc if LFs are attached from multiple blocks of same type, then 246 * return blkaddr of first encountered block. 247 */ 248 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 249 { 250 int devnum, blkaddr = -ENODEV; 251 u64 cfg, reg; 252 bool is_pf; 253 254 switch (blktype) { 255 case BLKTYPE_NPC: 256 blkaddr = BLKADDR_NPC; 257 goto exit; 258 case BLKTYPE_NPA: 259 blkaddr = BLKADDR_NPA; 260 goto exit; 261 case BLKTYPE_NIX: 262 /* For now assume NIX0 */ 263 if (!pcifunc) { 264 blkaddr = BLKADDR_NIX0; 265 goto exit; 266 } 267 break; 268 case BLKTYPE_SSO: 269 blkaddr = BLKADDR_SSO; 270 goto exit; 271 case BLKTYPE_SSOW: 272 blkaddr = BLKADDR_SSOW; 273 goto exit; 274 case BLKTYPE_TIM: 275 blkaddr = BLKADDR_TIM; 276 goto exit; 277 case BLKTYPE_CPT: 278 /* For now assume CPT0 */ 279 if (!pcifunc) { 280 blkaddr = BLKADDR_CPT0; 281 goto exit; 282 } 283 break; 284 } 285 286 /* Check if this is a RVU PF or VF */ 287 if (pcifunc & RVU_PFVF_FUNC_MASK) { 288 is_pf = false; 289 devnum = rvu_get_hwvf(rvu, pcifunc); 290 } else { 291 is_pf = true; 292 devnum = rvu_get_pf(pcifunc); 293 } 294 295 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or 296 * 'BLKADDR_NIX1'. 297 */ 298 if (blktype == BLKTYPE_NIX) { 299 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) : 300 RVU_PRIV_HWVFX_NIXX_CFG(0); 301 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 302 if (cfg) { 303 blkaddr = BLKADDR_NIX0; 304 goto exit; 305 } 306 307 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) : 308 RVU_PRIV_HWVFX_NIXX_CFG(1); 309 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 310 if (cfg) 311 blkaddr = BLKADDR_NIX1; 312 } 313 314 if (blktype == BLKTYPE_CPT) { 315 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) : 316 RVU_PRIV_HWVFX_CPTX_CFG(0); 317 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 318 if (cfg) { 319 blkaddr = BLKADDR_CPT0; 320 goto exit; 321 } 322 323 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) : 324 RVU_PRIV_HWVFX_CPTX_CFG(1); 325 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 326 if (cfg) 327 blkaddr = BLKADDR_CPT1; 328 } 329 330 exit: 331 if (is_block_implemented(rvu->hw, blkaddr)) 332 return blkaddr; 333 return -ENODEV; 334 } 335 336 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 337 struct rvu_block *block, u16 pcifunc, 338 u16 lf, bool attach) 339 { 340 int devnum, num_lfs = 0; 341 bool is_pf; 342 u64 reg; 343 344 if (lf >= block->lf.max) { 345 dev_err(&rvu->pdev->dev, 346 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 347 __func__, lf, block->name, block->lf.max); 348 return; 349 } 350 351 /* Check if this is for a RVU PF or VF */ 352 if (pcifunc & RVU_PFVF_FUNC_MASK) { 353 is_pf = false; 354 devnum = rvu_get_hwvf(rvu, pcifunc); 355 } else { 356 is_pf = true; 357 devnum = rvu_get_pf(pcifunc); 358 } 359 360 block->fn_map[lf] = attach ? pcifunc : 0; 361 362 switch (block->addr) { 363 case BLKADDR_NPA: 364 pfvf->npalf = attach ? true : false; 365 num_lfs = pfvf->npalf; 366 break; 367 case BLKADDR_NIX0: 368 case BLKADDR_NIX1: 369 pfvf->nixlf = attach ? true : false; 370 num_lfs = pfvf->nixlf; 371 break; 372 case BLKADDR_SSO: 373 attach ? pfvf->sso++ : pfvf->sso--; 374 num_lfs = pfvf->sso; 375 break; 376 case BLKADDR_SSOW: 377 attach ? pfvf->ssow++ : pfvf->ssow--; 378 num_lfs = pfvf->ssow; 379 break; 380 case BLKADDR_TIM: 381 attach ? pfvf->timlfs++ : pfvf->timlfs--; 382 num_lfs = pfvf->timlfs; 383 break; 384 case BLKADDR_CPT0: 385 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 386 num_lfs = pfvf->cptlfs; 387 break; 388 case BLKADDR_CPT1: 389 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; 390 num_lfs = pfvf->cpt1_lfs; 391 break; 392 } 393 394 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 395 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 396 } 397 398 inline int rvu_get_pf(u16 pcifunc) 399 { 400 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 401 } 402 403 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 404 { 405 u64 cfg; 406 407 /* Get numVFs attached to this PF and first HWVF */ 408 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 409 if (numvfs) 410 *numvfs = (cfg >> 12) & 0xFF; 411 if (hwvf) 412 *hwvf = cfg & 0xFFF; 413 } 414 415 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 416 { 417 int pf, func; 418 u64 cfg; 419 420 pf = rvu_get_pf(pcifunc); 421 func = pcifunc & RVU_PFVF_FUNC_MASK; 422 423 /* Get first HWVF attached to this PF */ 424 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 425 426 return ((cfg & 0xFFF) + func - 1); 427 } 428 429 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 430 { 431 /* Check if it is a PF or VF */ 432 if (pcifunc & RVU_PFVF_FUNC_MASK) 433 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 434 else 435 return &rvu->pf[rvu_get_pf(pcifunc)]; 436 } 437 438 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 439 { 440 int pf, vf, nvfs; 441 u64 cfg; 442 443 pf = rvu_get_pf(pcifunc); 444 if (pf >= rvu->hw->total_pfs) 445 return false; 446 447 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 448 return true; 449 450 /* Check if VF is within number of VFs attached to this PF */ 451 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 452 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 453 nvfs = (cfg >> 12) & 0xFF; 454 if (vf >= nvfs) 455 return false; 456 457 return true; 458 } 459 460 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 461 { 462 struct rvu_block *block; 463 464 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 465 return false; 466 467 block = &hw->block[blkaddr]; 468 return block->implemented; 469 } 470 471 static void rvu_check_block_implemented(struct rvu *rvu) 472 { 473 struct rvu_hwinfo *hw = rvu->hw; 474 struct rvu_block *block; 475 int blkid; 476 u64 cfg; 477 478 /* For each block check if 'implemented' bit is set */ 479 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 480 block = &hw->block[blkid]; 481 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 482 if (cfg & BIT_ULL(11)) 483 block->implemented = true; 484 } 485 } 486 487 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 488 { 489 rvu_write64(rvu, BLKADDR_RVUM, 490 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 491 RVU_BLK_RVUM_REVID); 492 } 493 494 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 495 { 496 rvu_write64(rvu, BLKADDR_RVUM, 497 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 498 } 499 500 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 501 { 502 int err; 503 504 if (!block->implemented) 505 return 0; 506 507 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 508 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 509 true); 510 return err; 511 } 512 513 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 514 { 515 struct rvu_block *block = &rvu->hw->block[blkaddr]; 516 int err; 517 518 if (!block->implemented) 519 return; 520 521 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 522 err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 523 if (err) 524 dev_err(rvu->dev, "HW block:%d reset failed\n", blkaddr); 525 } 526 527 static void rvu_reset_all_blocks(struct rvu *rvu) 528 { 529 /* Do a HW reset of all RVU blocks */ 530 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 531 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 532 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST); 533 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 534 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 535 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 536 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 537 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST); 538 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 539 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 540 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST); 541 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST); 542 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 543 } 544 545 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 546 { 547 struct rvu_pfvf *pfvf; 548 u64 cfg; 549 int lf; 550 551 for (lf = 0; lf < block->lf.max; lf++) { 552 cfg = rvu_read64(rvu, block->addr, 553 block->lfcfg_reg | (lf << block->lfshift)); 554 if (!(cfg & BIT_ULL(63))) 555 continue; 556 557 /* Set this resource as being used */ 558 __set_bit(lf, block->lf.bmap); 559 560 /* Get, to whom this LF is attached */ 561 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 562 rvu_update_rsrc_map(rvu, pfvf, block, 563 (cfg >> 8) & 0xFFFF, lf, true); 564 565 /* Set start MSIX vector for this LF within this PF/VF */ 566 rvu_set_msix_offset(rvu, pfvf, block, lf); 567 } 568 } 569 570 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 571 { 572 int min_vecs; 573 574 if (!vf) 575 goto check_pf; 576 577 if (!nvecs) { 578 dev_warn(rvu->dev, 579 "PF%d:VF%d is configured with zero msix vectors, %d\n", 580 pf, vf - 1, nvecs); 581 } 582 return; 583 584 check_pf: 585 if (pf == 0) 586 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 587 else 588 min_vecs = RVU_PF_INT_VEC_CNT; 589 590 if (!(nvecs < min_vecs)) 591 return; 592 dev_warn(rvu->dev, 593 "PF%d is configured with too few vectors, %d, min is %d\n", 594 pf, nvecs, min_vecs); 595 } 596 597 static int rvu_setup_msix_resources(struct rvu *rvu) 598 { 599 struct rvu_hwinfo *hw = rvu->hw; 600 int pf, vf, numvfs, hwvf, err; 601 int nvecs, offset, max_msix; 602 struct rvu_pfvf *pfvf; 603 u64 cfg, phy_addr; 604 dma_addr_t iova; 605 606 for (pf = 0; pf < hw->total_pfs; pf++) { 607 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 608 /* If PF is not enabled, nothing to do */ 609 if (!((cfg >> 20) & 0x01)) 610 continue; 611 612 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 613 614 pfvf = &rvu->pf[pf]; 615 /* Get num of MSIX vectors attached to this PF */ 616 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 617 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 618 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 619 620 /* Alloc msix bitmap for this PF */ 621 err = rvu_alloc_bitmap(&pfvf->msix); 622 if (err) 623 return err; 624 625 /* Allocate memory for MSIX vector to RVU block LF mapping */ 626 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 627 sizeof(u16), GFP_KERNEL); 628 if (!pfvf->msix_lfmap) 629 return -ENOMEM; 630 631 /* For PF0 (AF) firmware will set msix vector offsets for 632 * AF, block AF and PF0_INT vectors, so jump to VFs. 633 */ 634 if (!pf) 635 goto setup_vfmsix; 636 637 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 638 * These are allocated on driver init and never freed, 639 * so no need to set 'msix_lfmap' for these. 640 */ 641 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 642 nvecs = (cfg >> 12) & 0xFF; 643 cfg &= ~0x7FFULL; 644 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 645 rvu_write64(rvu, BLKADDR_RVUM, 646 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 647 setup_vfmsix: 648 /* Alloc msix bitmap for VFs */ 649 for (vf = 0; vf < numvfs; vf++) { 650 pfvf = &rvu->hwvf[hwvf + vf]; 651 /* Get num of MSIX vectors attached to this VF */ 652 cfg = rvu_read64(rvu, BLKADDR_RVUM, 653 RVU_PRIV_PFX_MSIX_CFG(pf)); 654 pfvf->msix.max = (cfg & 0xFFF) + 1; 655 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 656 657 /* Alloc msix bitmap for this VF */ 658 err = rvu_alloc_bitmap(&pfvf->msix); 659 if (err) 660 return err; 661 662 pfvf->msix_lfmap = 663 devm_kcalloc(rvu->dev, pfvf->msix.max, 664 sizeof(u16), GFP_KERNEL); 665 if (!pfvf->msix_lfmap) 666 return -ENOMEM; 667 668 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 669 * These are allocated on driver init and never freed, 670 * so no need to set 'msix_lfmap' for these. 671 */ 672 cfg = rvu_read64(rvu, BLKADDR_RVUM, 673 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 674 nvecs = (cfg >> 12) & 0xFF; 675 cfg &= ~0x7FFULL; 676 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 677 rvu_write64(rvu, BLKADDR_RVUM, 678 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 679 cfg | offset); 680 } 681 } 682 683 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 684 * create an IOMMU mapping for the physical address configured by 685 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 686 */ 687 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 688 max_msix = cfg & 0xFFFFF; 689 if (rvu->fwdata && rvu->fwdata->msixtr_base) 690 phy_addr = rvu->fwdata->msixtr_base; 691 else 692 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 693 694 iova = dma_map_resource(rvu->dev, phy_addr, 695 max_msix * PCI_MSIX_ENTRY_SIZE, 696 DMA_BIDIRECTIONAL, 0); 697 698 if (dma_mapping_error(rvu->dev, iova)) 699 return -ENOMEM; 700 701 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 702 rvu->msix_base_iova = iova; 703 rvu->msixtr_base_phy = phy_addr; 704 705 return 0; 706 } 707 708 static void rvu_reset_msix(struct rvu *rvu) 709 { 710 /* Restore msixtr base register */ 711 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 712 rvu->msixtr_base_phy); 713 } 714 715 static void rvu_free_hw_resources(struct rvu *rvu) 716 { 717 struct rvu_hwinfo *hw = rvu->hw; 718 struct rvu_block *block; 719 struct rvu_pfvf *pfvf; 720 int id, max_msix; 721 u64 cfg; 722 723 rvu_npa_freemem(rvu); 724 rvu_npc_freemem(rvu); 725 rvu_nix_freemem(rvu); 726 727 /* Free block LF bitmaps */ 728 for (id = 0; id < BLK_COUNT; id++) { 729 block = &hw->block[id]; 730 kfree(block->lf.bmap); 731 } 732 733 /* Free MSIX bitmaps */ 734 for (id = 0; id < hw->total_pfs; id++) { 735 pfvf = &rvu->pf[id]; 736 kfree(pfvf->msix.bmap); 737 } 738 739 for (id = 0; id < hw->total_vfs; id++) { 740 pfvf = &rvu->hwvf[id]; 741 kfree(pfvf->msix.bmap); 742 } 743 744 /* Unmap MSIX vector base IOVA mapping */ 745 if (!rvu->msix_base_iova) 746 return; 747 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 748 max_msix = cfg & 0xFFFFF; 749 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 750 max_msix * PCI_MSIX_ENTRY_SIZE, 751 DMA_BIDIRECTIONAL, 0); 752 753 rvu_reset_msix(rvu); 754 mutex_destroy(&rvu->rsrc_lock); 755 } 756 757 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 758 { 759 struct rvu_hwinfo *hw = rvu->hw; 760 int pf, vf, numvfs, hwvf; 761 struct rvu_pfvf *pfvf; 762 u64 *mac; 763 764 for (pf = 0; pf < hw->total_pfs; pf++) { 765 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */ 766 if (!pf) 767 goto lbkvf; 768 769 if (!is_pf_cgxmapped(rvu, pf)) 770 continue; 771 /* Assign MAC address to PF */ 772 pfvf = &rvu->pf[pf]; 773 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 774 mac = &rvu->fwdata->pf_macs[pf]; 775 if (*mac) 776 u64_to_ether_addr(*mac, pfvf->mac_addr); 777 else 778 eth_random_addr(pfvf->mac_addr); 779 } else { 780 eth_random_addr(pfvf->mac_addr); 781 } 782 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 783 784 lbkvf: 785 /* Assign MAC address to VFs*/ 786 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 787 for (vf = 0; vf < numvfs; vf++, hwvf++) { 788 pfvf = &rvu->hwvf[hwvf]; 789 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 790 mac = &rvu->fwdata->vf_macs[hwvf]; 791 if (*mac) 792 u64_to_ether_addr(*mac, pfvf->mac_addr); 793 else 794 eth_random_addr(pfvf->mac_addr); 795 } else { 796 eth_random_addr(pfvf->mac_addr); 797 } 798 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 799 } 800 } 801 } 802 803 static int rvu_fwdata_init(struct rvu *rvu) 804 { 805 u64 fwdbase; 806 int err; 807 808 /* Get firmware data base address */ 809 err = cgx_get_fwdata_base(&fwdbase); 810 if (err) 811 goto fail; 812 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 813 if (!rvu->fwdata) 814 goto fail; 815 if (!is_rvu_fwdata_valid(rvu)) { 816 dev_err(rvu->dev, 817 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 818 iounmap(rvu->fwdata); 819 rvu->fwdata = NULL; 820 return -EINVAL; 821 } 822 return 0; 823 fail: 824 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 825 return -EIO; 826 } 827 828 static void rvu_fwdata_exit(struct rvu *rvu) 829 { 830 if (rvu->fwdata) 831 iounmap(rvu->fwdata); 832 } 833 834 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr) 835 { 836 struct rvu_hwinfo *hw = rvu->hw; 837 struct rvu_block *block; 838 int blkid; 839 u64 cfg; 840 841 /* Init NIX LF's bitmap */ 842 block = &hw->block[blkaddr]; 843 if (!block->implemented) 844 return 0; 845 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 846 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 847 block->lf.max = cfg & 0xFFF; 848 block->addr = blkaddr; 849 block->type = BLKTYPE_NIX; 850 block->lfshift = 8; 851 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 852 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); 853 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); 854 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 855 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 856 block->lfreset_reg = NIX_AF_LF_RST; 857 sprintf(block->name, "NIX%d", blkid); 858 rvu->nix_blkaddr[blkid] = blkaddr; 859 return rvu_alloc_bitmap(&block->lf); 860 } 861 862 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr) 863 { 864 struct rvu_hwinfo *hw = rvu->hw; 865 struct rvu_block *block; 866 int blkid; 867 u64 cfg; 868 869 /* Init CPT LF's bitmap */ 870 block = &hw->block[blkaddr]; 871 if (!block->implemented) 872 return 0; 873 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; 874 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0); 875 block->lf.max = cfg & 0xFF; 876 block->addr = blkaddr; 877 block->type = BLKTYPE_CPT; 878 block->multislot = true; 879 block->lfshift = 3; 880 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 881 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); 882 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); 883 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 884 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 885 block->lfreset_reg = CPT_AF_LF_RST; 886 sprintf(block->name, "CPT%d", blkid); 887 return rvu_alloc_bitmap(&block->lf); 888 } 889 890 static void rvu_get_lbk_bufsize(struct rvu *rvu) 891 { 892 struct pci_dev *pdev = NULL; 893 void __iomem *base; 894 u64 lbk_const; 895 896 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 897 PCI_DEVID_OCTEONTX2_LBK, pdev); 898 if (!pdev) 899 return; 900 901 base = pci_ioremap_bar(pdev, 0); 902 if (!base) 903 goto err_put; 904 905 lbk_const = readq(base + LBK_CONST); 906 907 /* cache fifo size */ 908 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const); 909 910 iounmap(base); 911 err_put: 912 pci_dev_put(pdev); 913 } 914 915 static int rvu_setup_hw_resources(struct rvu *rvu) 916 { 917 struct rvu_hwinfo *hw = rvu->hw; 918 struct rvu_block *block; 919 int blkid, err; 920 u64 cfg; 921 922 /* Get HW supported max RVU PF & VF count */ 923 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 924 hw->total_pfs = (cfg >> 32) & 0xFF; 925 hw->total_vfs = (cfg >> 20) & 0xFFF; 926 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 927 928 /* Init NPA LF's bitmap */ 929 block = &hw->block[BLKADDR_NPA]; 930 if (!block->implemented) 931 goto nix; 932 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 933 block->lf.max = (cfg >> 16) & 0xFFF; 934 block->addr = BLKADDR_NPA; 935 block->type = BLKTYPE_NPA; 936 block->lfshift = 8; 937 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 938 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 939 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 940 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 941 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 942 block->lfreset_reg = NPA_AF_LF_RST; 943 sprintf(block->name, "NPA"); 944 err = rvu_alloc_bitmap(&block->lf); 945 if (err) { 946 dev_err(rvu->dev, 947 "%s: Failed to allocate NPA LF bitmap\n", __func__); 948 return err; 949 } 950 951 nix: 952 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0); 953 if (err) { 954 dev_err(rvu->dev, 955 "%s: Failed to allocate NIX0 LFs bitmap\n", __func__); 956 return err; 957 } 958 959 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1); 960 if (err) { 961 dev_err(rvu->dev, 962 "%s: Failed to allocate NIX1 LFs bitmap\n", __func__); 963 return err; 964 } 965 966 /* Init SSO group's bitmap */ 967 block = &hw->block[BLKADDR_SSO]; 968 if (!block->implemented) 969 goto ssow; 970 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 971 block->lf.max = cfg & 0xFFFF; 972 block->addr = BLKADDR_SSO; 973 block->type = BLKTYPE_SSO; 974 block->multislot = true; 975 block->lfshift = 3; 976 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 977 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 978 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 979 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 980 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 981 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 982 sprintf(block->name, "SSO GROUP"); 983 err = rvu_alloc_bitmap(&block->lf); 984 if (err) { 985 dev_err(rvu->dev, 986 "%s: Failed to allocate SSO LF bitmap\n", __func__); 987 return err; 988 } 989 990 ssow: 991 /* Init SSO workslot's bitmap */ 992 block = &hw->block[BLKADDR_SSOW]; 993 if (!block->implemented) 994 goto tim; 995 block->lf.max = (cfg >> 56) & 0xFF; 996 block->addr = BLKADDR_SSOW; 997 block->type = BLKTYPE_SSOW; 998 block->multislot = true; 999 block->lfshift = 3; 1000 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 1001 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 1002 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 1003 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 1004 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 1005 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 1006 sprintf(block->name, "SSOWS"); 1007 err = rvu_alloc_bitmap(&block->lf); 1008 if (err) { 1009 dev_err(rvu->dev, 1010 "%s: Failed to allocate SSOW LF bitmap\n", __func__); 1011 return err; 1012 } 1013 1014 tim: 1015 /* Init TIM LF's bitmap */ 1016 block = &hw->block[BLKADDR_TIM]; 1017 if (!block->implemented) 1018 goto cpt; 1019 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 1020 block->lf.max = cfg & 0xFFFF; 1021 block->addr = BLKADDR_TIM; 1022 block->type = BLKTYPE_TIM; 1023 block->multislot = true; 1024 block->lfshift = 3; 1025 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 1026 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 1027 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 1028 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 1029 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 1030 block->lfreset_reg = TIM_AF_LF_RST; 1031 sprintf(block->name, "TIM"); 1032 err = rvu_alloc_bitmap(&block->lf); 1033 if (err) { 1034 dev_err(rvu->dev, 1035 "%s: Failed to allocate TIM LF bitmap\n", __func__); 1036 return err; 1037 } 1038 1039 cpt: 1040 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); 1041 if (err) { 1042 dev_err(rvu->dev, 1043 "%s: Failed to allocate CPT0 LF bitmap\n", __func__); 1044 return err; 1045 } 1046 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1); 1047 if (err) { 1048 dev_err(rvu->dev, 1049 "%s: Failed to allocate CPT1 LF bitmap\n", __func__); 1050 return err; 1051 } 1052 1053 /* Allocate memory for PFVF data */ 1054 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 1055 sizeof(struct rvu_pfvf), GFP_KERNEL); 1056 if (!rvu->pf) { 1057 dev_err(rvu->dev, 1058 "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__); 1059 return -ENOMEM; 1060 } 1061 1062 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 1063 sizeof(struct rvu_pfvf), GFP_KERNEL); 1064 if (!rvu->hwvf) { 1065 dev_err(rvu->dev, 1066 "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__); 1067 return -ENOMEM; 1068 } 1069 1070 mutex_init(&rvu->rsrc_lock); 1071 1072 rvu_fwdata_init(rvu); 1073 1074 err = rvu_setup_msix_resources(rvu); 1075 if (err) { 1076 dev_err(rvu->dev, 1077 "%s: Failed to setup MSIX resources\n", __func__); 1078 return err; 1079 } 1080 1081 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1082 block = &hw->block[blkid]; 1083 if (!block->lf.bmap) 1084 continue; 1085 1086 /* Allocate memory for block LF/slot to pcifunc mapping info */ 1087 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 1088 sizeof(u16), GFP_KERNEL); 1089 if (!block->fn_map) { 1090 err = -ENOMEM; 1091 goto msix_err; 1092 } 1093 1094 /* Scan all blocks to check if low level firmware has 1095 * already provisioned any of the resources to a PF/VF. 1096 */ 1097 rvu_scan_block(rvu, block); 1098 } 1099 1100 err = rvu_set_channels_base(rvu); 1101 if (err) 1102 goto msix_err; 1103 1104 err = rvu_npc_init(rvu); 1105 if (err) { 1106 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__); 1107 goto npc_err; 1108 } 1109 1110 err = rvu_cgx_init(rvu); 1111 if (err) { 1112 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__); 1113 goto cgx_err; 1114 } 1115 1116 /* Assign MACs for CGX mapped functions */ 1117 rvu_setup_pfvf_macaddress(rvu); 1118 1119 err = rvu_npa_init(rvu); 1120 if (err) { 1121 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__); 1122 goto npa_err; 1123 } 1124 1125 rvu_get_lbk_bufsize(rvu); 1126 1127 err = rvu_nix_init(rvu); 1128 if (err) { 1129 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__); 1130 goto nix_err; 1131 } 1132 1133 err = rvu_sdp_init(rvu); 1134 if (err) { 1135 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__); 1136 goto nix_err; 1137 } 1138 1139 rvu_program_channels(rvu); 1140 1141 return 0; 1142 1143 nix_err: 1144 rvu_nix_freemem(rvu); 1145 npa_err: 1146 rvu_npa_freemem(rvu); 1147 cgx_err: 1148 rvu_cgx_exit(rvu); 1149 npc_err: 1150 rvu_npc_freemem(rvu); 1151 rvu_fwdata_exit(rvu); 1152 msix_err: 1153 rvu_reset_msix(rvu); 1154 return err; 1155 } 1156 1157 /* NPA and NIX admin queue APIs */ 1158 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 1159 { 1160 if (!aq) 1161 return; 1162 1163 qmem_free(rvu->dev, aq->inst); 1164 qmem_free(rvu->dev, aq->res); 1165 devm_kfree(rvu->dev, aq); 1166 } 1167 1168 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 1169 int qsize, int inst_size, int res_size) 1170 { 1171 struct admin_queue *aq; 1172 int err; 1173 1174 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 1175 if (!*ad_queue) 1176 return -ENOMEM; 1177 aq = *ad_queue; 1178 1179 /* Alloc memory for instructions i.e AQ */ 1180 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 1181 if (err) { 1182 devm_kfree(rvu->dev, aq); 1183 return err; 1184 } 1185 1186 /* Alloc memory for results */ 1187 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1188 if (err) { 1189 rvu_aq_free(rvu, aq); 1190 return err; 1191 } 1192 1193 spin_lock_init(&aq->lock); 1194 return 0; 1195 } 1196 1197 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1198 struct ready_msg_rsp *rsp) 1199 { 1200 if (rvu->fwdata) { 1201 rsp->rclk_freq = rvu->fwdata->rclk; 1202 rsp->sclk_freq = rvu->fwdata->sclk; 1203 } 1204 return 0; 1205 } 1206 1207 /* Get current count of a RVU block's LF/slots 1208 * provisioned to a given RVU func. 1209 */ 1210 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr) 1211 { 1212 switch (blkaddr) { 1213 case BLKADDR_NPA: 1214 return pfvf->npalf ? 1 : 0; 1215 case BLKADDR_NIX0: 1216 case BLKADDR_NIX1: 1217 return pfvf->nixlf ? 1 : 0; 1218 case BLKADDR_SSO: 1219 return pfvf->sso; 1220 case BLKADDR_SSOW: 1221 return pfvf->ssow; 1222 case BLKADDR_TIM: 1223 return pfvf->timlfs; 1224 case BLKADDR_CPT0: 1225 return pfvf->cptlfs; 1226 case BLKADDR_CPT1: 1227 return pfvf->cpt1_lfs; 1228 } 1229 return 0; 1230 } 1231 1232 /* Return true if LFs of block type are attached to pcifunc */ 1233 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype) 1234 { 1235 switch (blktype) { 1236 case BLKTYPE_NPA: 1237 return pfvf->npalf ? 1 : 0; 1238 case BLKTYPE_NIX: 1239 return pfvf->nixlf ? 1 : 0; 1240 case BLKTYPE_SSO: 1241 return !!pfvf->sso; 1242 case BLKTYPE_SSOW: 1243 return !!pfvf->ssow; 1244 case BLKTYPE_TIM: 1245 return !!pfvf->timlfs; 1246 case BLKTYPE_CPT: 1247 return pfvf->cptlfs || pfvf->cpt1_lfs; 1248 } 1249 1250 return false; 1251 } 1252 1253 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1254 { 1255 struct rvu_pfvf *pfvf; 1256 1257 if (!is_pf_func_valid(rvu, pcifunc)) 1258 return false; 1259 1260 pfvf = rvu_get_pfvf(rvu, pcifunc); 1261 1262 /* Check if this PFFUNC has a LF of type blktype attached */ 1263 if (!is_blktype_attached(pfvf, blktype)) 1264 return false; 1265 1266 return true; 1267 } 1268 1269 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1270 int pcifunc, int slot) 1271 { 1272 u64 val; 1273 1274 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1275 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1276 /* Wait for the lookup to finish */ 1277 /* TODO: put some timeout here */ 1278 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1279 ; 1280 1281 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1282 1283 /* Check LF valid bit */ 1284 if (!(val & (1ULL << 12))) 1285 return -1; 1286 1287 return (val & 0xFFF); 1288 } 1289 1290 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 1291 u16 global_slot, u16 *slot_in_block) 1292 { 1293 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1294 int numlfs, total_lfs = 0, nr_blocks = 0; 1295 int i, num_blkaddr[BLK_COUNT] = { 0 }; 1296 struct rvu_block *block; 1297 int blkaddr; 1298 u16 start_slot; 1299 1300 if (!is_blktype_attached(pfvf, blktype)) 1301 return -ENODEV; 1302 1303 /* Get all the block addresses from which LFs are attached to 1304 * the given pcifunc in num_blkaddr[]. 1305 */ 1306 for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) { 1307 block = &rvu->hw->block[blkaddr]; 1308 if (block->type != blktype) 1309 continue; 1310 if (!is_block_implemented(rvu->hw, blkaddr)) 1311 continue; 1312 1313 numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr); 1314 if (numlfs) { 1315 total_lfs += numlfs; 1316 num_blkaddr[nr_blocks] = blkaddr; 1317 nr_blocks++; 1318 } 1319 } 1320 1321 if (global_slot >= total_lfs) 1322 return -ENODEV; 1323 1324 /* Based on the given global slot number retrieve the 1325 * correct block address out of all attached block 1326 * addresses and slot number in that block. 1327 */ 1328 total_lfs = 0; 1329 blkaddr = -ENODEV; 1330 for (i = 0; i < nr_blocks; i++) { 1331 numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]); 1332 total_lfs += numlfs; 1333 if (global_slot < total_lfs) { 1334 blkaddr = num_blkaddr[i]; 1335 start_slot = total_lfs - numlfs; 1336 *slot_in_block = global_slot - start_slot; 1337 break; 1338 } 1339 } 1340 1341 return blkaddr; 1342 } 1343 1344 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1345 { 1346 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1347 struct rvu_hwinfo *hw = rvu->hw; 1348 struct rvu_block *block; 1349 int slot, lf, num_lfs; 1350 int blkaddr; 1351 1352 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1353 if (blkaddr < 0) 1354 return; 1355 1356 if (blktype == BLKTYPE_NIX) 1357 rvu_nix_reset_mac(pfvf, pcifunc); 1358 1359 block = &hw->block[blkaddr]; 1360 1361 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1362 if (!num_lfs) 1363 return; 1364 1365 for (slot = 0; slot < num_lfs; slot++) { 1366 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1367 if (lf < 0) /* This should never happen */ 1368 continue; 1369 1370 /* Disable the LF */ 1371 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1372 (lf << block->lfshift), 0x00ULL); 1373 1374 /* Update SW maintained mapping info as well */ 1375 rvu_update_rsrc_map(rvu, pfvf, block, 1376 pcifunc, lf, false); 1377 1378 /* Free the resource */ 1379 rvu_free_rsrc(&block->lf, lf); 1380 1381 /* Clear MSIX vector offset for this LF */ 1382 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1383 } 1384 } 1385 1386 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1387 u16 pcifunc) 1388 { 1389 struct rvu_hwinfo *hw = rvu->hw; 1390 bool detach_all = true; 1391 struct rvu_block *block; 1392 int blkid; 1393 1394 mutex_lock(&rvu->rsrc_lock); 1395 1396 /* Check for partial resource detach */ 1397 if (detach && detach->partial) 1398 detach_all = false; 1399 1400 /* Check for RVU block's LFs attached to this func, 1401 * if so, detach them. 1402 */ 1403 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1404 block = &hw->block[blkid]; 1405 if (!block->lf.bmap) 1406 continue; 1407 if (!detach_all && detach) { 1408 if (blkid == BLKADDR_NPA && !detach->npalf) 1409 continue; 1410 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1411 continue; 1412 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) 1413 continue; 1414 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1415 continue; 1416 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1417 continue; 1418 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1419 continue; 1420 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1421 continue; 1422 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) 1423 continue; 1424 } 1425 rvu_detach_block(rvu, pcifunc, block->type); 1426 } 1427 1428 mutex_unlock(&rvu->rsrc_lock); 1429 return 0; 1430 } 1431 1432 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1433 struct rsrc_detach *detach, 1434 struct msg_rsp *rsp) 1435 { 1436 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1437 } 1438 1439 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 1440 { 1441 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1442 int blkaddr = BLKADDR_NIX0, vf; 1443 struct rvu_pfvf *pf; 1444 1445 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1446 1447 /* All CGX mapped PFs are set with assigned NIX block during init */ 1448 if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 1449 blkaddr = pf->nix_blkaddr; 1450 } else if (is_afvf(pcifunc)) { 1451 vf = pcifunc - 1; 1452 /* Assign NIX based on VF number. All even numbered VFs get 1453 * NIX0 and odd numbered gets NIX1 1454 */ 1455 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0; 1456 /* NIX1 is not present on all silicons */ 1457 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1458 blkaddr = BLKADDR_NIX0; 1459 } 1460 1461 /* if SDP1 then the blkaddr is NIX1 */ 1462 if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1) 1463 blkaddr = BLKADDR_NIX1; 1464 1465 switch (blkaddr) { 1466 case BLKADDR_NIX1: 1467 pfvf->nix_blkaddr = BLKADDR_NIX1; 1468 pfvf->nix_rx_intf = NIX_INTFX_RX(1); 1469 pfvf->nix_tx_intf = NIX_INTFX_TX(1); 1470 break; 1471 case BLKADDR_NIX0: 1472 default: 1473 pfvf->nix_blkaddr = BLKADDR_NIX0; 1474 pfvf->nix_rx_intf = NIX_INTFX_RX(0); 1475 pfvf->nix_tx_intf = NIX_INTFX_TX(0); 1476 break; 1477 } 1478 1479 return pfvf->nix_blkaddr; 1480 } 1481 1482 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype, 1483 u16 pcifunc, struct rsrc_attach *attach) 1484 { 1485 int blkaddr; 1486 1487 switch (blktype) { 1488 case BLKTYPE_NIX: 1489 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc); 1490 break; 1491 case BLKTYPE_CPT: 1492 if (attach->hdr.ver < RVU_MULTI_BLK_VER) 1493 return rvu_get_blkaddr(rvu, blktype, 0); 1494 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : 1495 BLKADDR_CPT0; 1496 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 1497 return -ENODEV; 1498 break; 1499 default: 1500 return rvu_get_blkaddr(rvu, blktype, 0); 1501 } 1502 1503 if (is_block_implemented(rvu->hw, blkaddr)) 1504 return blkaddr; 1505 1506 return -ENODEV; 1507 } 1508 1509 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype, 1510 int num_lfs, struct rsrc_attach *attach) 1511 { 1512 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1513 struct rvu_hwinfo *hw = rvu->hw; 1514 struct rvu_block *block; 1515 int slot, lf; 1516 int blkaddr; 1517 u64 cfg; 1518 1519 if (!num_lfs) 1520 return; 1521 1522 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach); 1523 if (blkaddr < 0) 1524 return; 1525 1526 block = &hw->block[blkaddr]; 1527 if (!block->lf.bmap) 1528 return; 1529 1530 for (slot = 0; slot < num_lfs; slot++) { 1531 /* Allocate the resource */ 1532 lf = rvu_alloc_rsrc(&block->lf); 1533 if (lf < 0) 1534 return; 1535 1536 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1537 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1538 (lf << block->lfshift), cfg); 1539 rvu_update_rsrc_map(rvu, pfvf, block, 1540 pcifunc, lf, true); 1541 1542 /* Set start MSIX vector for this LF within this PF/VF */ 1543 rvu_set_msix_offset(rvu, pfvf, block, lf); 1544 } 1545 } 1546 1547 static int rvu_check_rsrc_availability(struct rvu *rvu, 1548 struct rsrc_attach *req, u16 pcifunc) 1549 { 1550 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1551 int free_lfs, mappedlfs, blkaddr; 1552 struct rvu_hwinfo *hw = rvu->hw; 1553 struct rvu_block *block; 1554 1555 /* Only one NPA LF can be attached */ 1556 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { 1557 block = &hw->block[BLKADDR_NPA]; 1558 free_lfs = rvu_rsrc_free_count(&block->lf); 1559 if (!free_lfs) 1560 goto fail; 1561 } else if (req->npalf) { 1562 dev_err(&rvu->pdev->dev, 1563 "Func 0x%x: Invalid req, already has NPA\n", 1564 pcifunc); 1565 return -EINVAL; 1566 } 1567 1568 /* Only one NIX LF can be attached */ 1569 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { 1570 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX, 1571 pcifunc, req); 1572 if (blkaddr < 0) 1573 return blkaddr; 1574 block = &hw->block[blkaddr]; 1575 free_lfs = rvu_rsrc_free_count(&block->lf); 1576 if (!free_lfs) 1577 goto fail; 1578 } else if (req->nixlf) { 1579 dev_err(&rvu->pdev->dev, 1580 "Func 0x%x: Invalid req, already has NIX\n", 1581 pcifunc); 1582 return -EINVAL; 1583 } 1584 1585 if (req->sso) { 1586 block = &hw->block[BLKADDR_SSO]; 1587 /* Is request within limits ? */ 1588 if (req->sso > block->lf.max) { 1589 dev_err(&rvu->pdev->dev, 1590 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1591 pcifunc, req->sso, block->lf.max); 1592 return -EINVAL; 1593 } 1594 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1595 free_lfs = rvu_rsrc_free_count(&block->lf); 1596 /* Check if additional resources are available */ 1597 if (req->sso > mappedlfs && 1598 ((req->sso - mappedlfs) > free_lfs)) 1599 goto fail; 1600 } 1601 1602 if (req->ssow) { 1603 block = &hw->block[BLKADDR_SSOW]; 1604 if (req->ssow > block->lf.max) { 1605 dev_err(&rvu->pdev->dev, 1606 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1607 pcifunc, req->sso, block->lf.max); 1608 return -EINVAL; 1609 } 1610 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1611 free_lfs = rvu_rsrc_free_count(&block->lf); 1612 if (req->ssow > mappedlfs && 1613 ((req->ssow - mappedlfs) > free_lfs)) 1614 goto fail; 1615 } 1616 1617 if (req->timlfs) { 1618 block = &hw->block[BLKADDR_TIM]; 1619 if (req->timlfs > block->lf.max) { 1620 dev_err(&rvu->pdev->dev, 1621 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1622 pcifunc, req->timlfs, block->lf.max); 1623 return -EINVAL; 1624 } 1625 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1626 free_lfs = rvu_rsrc_free_count(&block->lf); 1627 if (req->timlfs > mappedlfs && 1628 ((req->timlfs - mappedlfs) > free_lfs)) 1629 goto fail; 1630 } 1631 1632 if (req->cptlfs) { 1633 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT, 1634 pcifunc, req); 1635 if (blkaddr < 0) 1636 return blkaddr; 1637 block = &hw->block[blkaddr]; 1638 if (req->cptlfs > block->lf.max) { 1639 dev_err(&rvu->pdev->dev, 1640 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1641 pcifunc, req->cptlfs, block->lf.max); 1642 return -EINVAL; 1643 } 1644 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1645 free_lfs = rvu_rsrc_free_count(&block->lf); 1646 if (req->cptlfs > mappedlfs && 1647 ((req->cptlfs - mappedlfs) > free_lfs)) 1648 goto fail; 1649 } 1650 1651 return 0; 1652 1653 fail: 1654 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1655 return -ENOSPC; 1656 } 1657 1658 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype, 1659 struct rsrc_attach *attach) 1660 { 1661 int blkaddr, num_lfs; 1662 1663 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, 1664 attach->hdr.pcifunc, attach); 1665 if (blkaddr < 0) 1666 return false; 1667 1668 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), 1669 blkaddr); 1670 /* Requester already has LFs from given block ? */ 1671 return !!num_lfs; 1672 } 1673 1674 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1675 struct rsrc_attach *attach, 1676 struct msg_rsp *rsp) 1677 { 1678 u16 pcifunc = attach->hdr.pcifunc; 1679 int err; 1680 1681 /* If first request, detach all existing attached resources */ 1682 if (!attach->modify) 1683 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1684 1685 mutex_lock(&rvu->rsrc_lock); 1686 1687 /* Check if the request can be accommodated */ 1688 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1689 if (err) 1690 goto exit; 1691 1692 /* Now attach the requested resources */ 1693 if (attach->npalf) 1694 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach); 1695 1696 if (attach->nixlf) 1697 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach); 1698 1699 if (attach->sso) { 1700 /* RVU func doesn't know which exact LF or slot is attached 1701 * to it, it always sees as slot 0,1,2. So for a 'modify' 1702 * request, simply detach all existing attached LFs/slots 1703 * and attach a fresh. 1704 */ 1705 if (attach->modify) 1706 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1707 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, 1708 attach->sso, attach); 1709 } 1710 1711 if (attach->ssow) { 1712 if (attach->modify) 1713 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1714 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, 1715 attach->ssow, attach); 1716 } 1717 1718 if (attach->timlfs) { 1719 if (attach->modify) 1720 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1721 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, 1722 attach->timlfs, attach); 1723 } 1724 1725 if (attach->cptlfs) { 1726 if (attach->modify && 1727 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach)) 1728 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1729 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, 1730 attach->cptlfs, attach); 1731 } 1732 1733 exit: 1734 mutex_unlock(&rvu->rsrc_lock); 1735 return err; 1736 } 1737 1738 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1739 int blkaddr, int lf) 1740 { 1741 u16 vec; 1742 1743 if (lf < 0) 1744 return MSIX_VECTOR_INVALID; 1745 1746 for (vec = 0; vec < pfvf->msix.max; vec++) { 1747 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1748 return vec; 1749 } 1750 return MSIX_VECTOR_INVALID; 1751 } 1752 1753 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1754 struct rvu_block *block, int lf) 1755 { 1756 u16 nvecs, vec, offset; 1757 u64 cfg; 1758 1759 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1760 (lf << block->lfshift)); 1761 nvecs = (cfg >> 12) & 0xFF; 1762 1763 /* Check and alloc MSIX vectors, must be contiguous */ 1764 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1765 return; 1766 1767 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1768 1769 /* Config MSIX offset in LF */ 1770 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1771 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1772 1773 /* Update the bitmap as well */ 1774 for (vec = 0; vec < nvecs; vec++) 1775 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1776 } 1777 1778 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1779 struct rvu_block *block, int lf) 1780 { 1781 u16 nvecs, vec, offset; 1782 u64 cfg; 1783 1784 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1785 (lf << block->lfshift)); 1786 nvecs = (cfg >> 12) & 0xFF; 1787 1788 /* Clear MSIX offset in LF */ 1789 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1790 (lf << block->lfshift), cfg & ~0x7FFULL); 1791 1792 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1793 1794 /* Update the mapping */ 1795 for (vec = 0; vec < nvecs; vec++) 1796 pfvf->msix_lfmap[offset + vec] = 0; 1797 1798 /* Free the same in MSIX bitmap */ 1799 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1800 } 1801 1802 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1803 struct msix_offset_rsp *rsp) 1804 { 1805 struct rvu_hwinfo *hw = rvu->hw; 1806 u16 pcifunc = req->hdr.pcifunc; 1807 struct rvu_pfvf *pfvf; 1808 int lf, slot, blkaddr; 1809 1810 pfvf = rvu_get_pfvf(rvu, pcifunc); 1811 if (!pfvf->msix.bmap) 1812 return 0; 1813 1814 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1815 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1816 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1817 1818 /* Get BLKADDR from which LFs are attached to pcifunc */ 1819 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1820 if (blkaddr < 0) { 1821 rsp->nix_msixoff = MSIX_VECTOR_INVALID; 1822 } else { 1823 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 1824 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); 1825 } 1826 1827 rsp->sso = pfvf->sso; 1828 for (slot = 0; slot < rsp->sso; slot++) { 1829 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1830 rsp->sso_msixoff[slot] = 1831 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1832 } 1833 1834 rsp->ssow = pfvf->ssow; 1835 for (slot = 0; slot < rsp->ssow; slot++) { 1836 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1837 rsp->ssow_msixoff[slot] = 1838 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1839 } 1840 1841 rsp->timlfs = pfvf->timlfs; 1842 for (slot = 0; slot < rsp->timlfs; slot++) { 1843 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1844 rsp->timlf_msixoff[slot] = 1845 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1846 } 1847 1848 rsp->cptlfs = pfvf->cptlfs; 1849 for (slot = 0; slot < rsp->cptlfs; slot++) { 1850 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1851 rsp->cptlf_msixoff[slot] = 1852 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1853 } 1854 1855 rsp->cpt1_lfs = pfvf->cpt1_lfs; 1856 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { 1857 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); 1858 rsp->cpt1_lf_msixoff[slot] = 1859 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf); 1860 } 1861 1862 return 0; 1863 } 1864 1865 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req, 1866 struct free_rsrcs_rsp *rsp) 1867 { 1868 struct rvu_hwinfo *hw = rvu->hw; 1869 struct rvu_block *block; 1870 struct nix_txsch *txsch; 1871 struct nix_hw *nix_hw; 1872 1873 mutex_lock(&rvu->rsrc_lock); 1874 1875 block = &hw->block[BLKADDR_NPA]; 1876 rsp->npa = rvu_rsrc_free_count(&block->lf); 1877 1878 block = &hw->block[BLKADDR_NIX0]; 1879 rsp->nix = rvu_rsrc_free_count(&block->lf); 1880 1881 block = &hw->block[BLKADDR_NIX1]; 1882 rsp->nix1 = rvu_rsrc_free_count(&block->lf); 1883 1884 block = &hw->block[BLKADDR_SSO]; 1885 rsp->sso = rvu_rsrc_free_count(&block->lf); 1886 1887 block = &hw->block[BLKADDR_SSOW]; 1888 rsp->ssow = rvu_rsrc_free_count(&block->lf); 1889 1890 block = &hw->block[BLKADDR_TIM]; 1891 rsp->tim = rvu_rsrc_free_count(&block->lf); 1892 1893 block = &hw->block[BLKADDR_CPT0]; 1894 rsp->cpt = rvu_rsrc_free_count(&block->lf); 1895 1896 block = &hw->block[BLKADDR_CPT1]; 1897 rsp->cpt1 = rvu_rsrc_free_count(&block->lf); 1898 1899 if (rvu->hw->cap.nix_fixed_txschq_mapping) { 1900 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1; 1901 rsp->schq[NIX_TXSCH_LVL_TL4] = 1; 1902 rsp->schq[NIX_TXSCH_LVL_TL3] = 1; 1903 rsp->schq[NIX_TXSCH_LVL_TL2] = 1; 1904 /* NIX1 */ 1905 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1906 goto out; 1907 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1; 1908 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1; 1909 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1; 1910 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1; 1911 } else { 1912 nix_hw = get_nix_hw(hw, BLKADDR_NIX0); 1913 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1914 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1915 rvu_rsrc_free_count(&txsch->schq); 1916 1917 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1918 rsp->schq[NIX_TXSCH_LVL_TL4] = 1919 rvu_rsrc_free_count(&txsch->schq); 1920 1921 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1922 rsp->schq[NIX_TXSCH_LVL_TL3] = 1923 rvu_rsrc_free_count(&txsch->schq); 1924 1925 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1926 rsp->schq[NIX_TXSCH_LVL_TL2] = 1927 rvu_rsrc_free_count(&txsch->schq); 1928 1929 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1930 goto out; 1931 1932 nix_hw = get_nix_hw(hw, BLKADDR_NIX1); 1933 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1934 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1935 rvu_rsrc_free_count(&txsch->schq); 1936 1937 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1938 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1939 rvu_rsrc_free_count(&txsch->schq); 1940 1941 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1942 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1943 rvu_rsrc_free_count(&txsch->schq); 1944 1945 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1946 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1947 rvu_rsrc_free_count(&txsch->schq); 1948 } 1949 1950 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1; 1951 out: 1952 rsp->schq[NIX_TXSCH_LVL_TL1] = 1; 1953 mutex_unlock(&rvu->rsrc_lock); 1954 1955 return 0; 1956 } 1957 1958 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1959 struct msg_rsp *rsp) 1960 { 1961 u16 pcifunc = req->hdr.pcifunc; 1962 u16 vf, numvfs; 1963 u64 cfg; 1964 1965 vf = pcifunc & RVU_PFVF_FUNC_MASK; 1966 cfg = rvu_read64(rvu, BLKADDR_RVUM, 1967 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 1968 numvfs = (cfg >> 12) & 0xFF; 1969 1970 if (vf && vf <= numvfs) 1971 __rvu_flr_handler(rvu, pcifunc); 1972 else 1973 return RVU_INVALID_VF_ID; 1974 1975 return 0; 1976 } 1977 1978 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 1979 struct get_hw_cap_rsp *rsp) 1980 { 1981 struct rvu_hwinfo *hw = rvu->hw; 1982 1983 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 1984 rsp->nix_shaping = hw->cap.nix_shaping; 1985 1986 return 0; 1987 } 1988 1989 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req, 1990 struct msg_rsp *rsp) 1991 { 1992 struct rvu_hwinfo *hw = rvu->hw; 1993 u16 pcifunc = req->hdr.pcifunc; 1994 struct rvu_pfvf *pfvf; 1995 int blkaddr, nixlf; 1996 u16 target; 1997 1998 /* Only PF can add VF permissions */ 1999 if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc)) 2000 return -EOPNOTSUPP; 2001 2002 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1); 2003 pfvf = rvu_get_pfvf(rvu, target); 2004 2005 if (req->flags & RESET_VF_PERM) { 2006 pfvf->flags &= RVU_CLEAR_VF_PERM; 2007 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^ 2008 (req->flags & VF_TRUSTED)) { 2009 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags); 2010 /* disable multicast and promisc entries */ 2011 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) { 2012 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target); 2013 if (blkaddr < 0) 2014 return 0; 2015 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 2016 target, 0); 2017 if (nixlf < 0) 2018 return 0; 2019 npc_enadis_default_mce_entry(rvu, target, nixlf, 2020 NIXLF_ALLMULTI_ENTRY, 2021 false); 2022 npc_enadis_default_mce_entry(rvu, target, nixlf, 2023 NIXLF_PROMISC_ENTRY, 2024 false); 2025 } 2026 } 2027 2028 return 0; 2029 } 2030 2031 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 2032 struct mbox_msghdr *req) 2033 { 2034 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 2035 2036 /* Check if valid, if not reply with a invalid msg */ 2037 if (req->sig != OTX2_MBOX_REQ_SIG) 2038 goto bad_message; 2039 2040 switch (req->id) { 2041 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 2042 case _id: { \ 2043 struct _rsp_type *rsp; \ 2044 int err; \ 2045 \ 2046 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 2047 mbox, devid, \ 2048 sizeof(struct _rsp_type)); \ 2049 /* some handlers should complete even if reply */ \ 2050 /* could not be allocated */ \ 2051 if (!rsp && \ 2052 _id != MBOX_MSG_DETACH_RESOURCES && \ 2053 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 2054 _id != MBOX_MSG_VF_FLR) \ 2055 return -ENOMEM; \ 2056 if (rsp) { \ 2057 rsp->hdr.id = _id; \ 2058 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 2059 rsp->hdr.pcifunc = req->pcifunc; \ 2060 rsp->hdr.rc = 0; \ 2061 } \ 2062 \ 2063 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 2064 (struct _req_type *)req, \ 2065 rsp); \ 2066 if (rsp && err) \ 2067 rsp->hdr.rc = err; \ 2068 \ 2069 trace_otx2_msg_process(mbox->pdev, _id, err); \ 2070 return rsp ? err : -ENOMEM; \ 2071 } 2072 MBOX_MESSAGES 2073 #undef M 2074 2075 bad_message: 2076 default: 2077 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 2078 return -ENODEV; 2079 } 2080 } 2081 2082 static void __rvu_mbox_handler(struct rvu_work *mwork, int type) 2083 { 2084 struct rvu *rvu = mwork->rvu; 2085 int offset, err, id, devid; 2086 struct otx2_mbox_dev *mdev; 2087 struct mbox_hdr *req_hdr; 2088 struct mbox_msghdr *msg; 2089 struct mbox_wq_info *mw; 2090 struct otx2_mbox *mbox; 2091 2092 switch (type) { 2093 case TYPE_AFPF: 2094 mw = &rvu->afpf_wq_info; 2095 break; 2096 case TYPE_AFVF: 2097 mw = &rvu->afvf_wq_info; 2098 break; 2099 default: 2100 return; 2101 } 2102 2103 devid = mwork - mw->mbox_wrk; 2104 mbox = &mw->mbox; 2105 mdev = &mbox->dev[devid]; 2106 2107 /* Process received mbox messages */ 2108 req_hdr = mdev->mbase + mbox->rx_start; 2109 if (mw->mbox_wrk[devid].num_msgs == 0) 2110 return; 2111 2112 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 2113 2114 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 2115 msg = mdev->mbase + offset; 2116 2117 /* Set which PF/VF sent this message based on mbox IRQ */ 2118 switch (type) { 2119 case TYPE_AFPF: 2120 msg->pcifunc &= 2121 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 2122 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 2123 break; 2124 case TYPE_AFVF: 2125 msg->pcifunc &= 2126 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 2127 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 2128 break; 2129 } 2130 2131 err = rvu_process_mbox_msg(mbox, devid, msg); 2132 if (!err) { 2133 offset = mbox->rx_start + msg->next_msgoff; 2134 continue; 2135 } 2136 2137 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 2138 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 2139 err, otx2_mbox_id2name(msg->id), 2140 msg->id, rvu_get_pf(msg->pcifunc), 2141 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 2142 else 2143 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 2144 err, otx2_mbox_id2name(msg->id), 2145 msg->id, devid); 2146 } 2147 mw->mbox_wrk[devid].num_msgs = 0; 2148 2149 /* Send mbox responses to VF/PF */ 2150 otx2_mbox_msg_send(mbox, devid); 2151 } 2152 2153 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 2154 { 2155 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2156 2157 __rvu_mbox_handler(mwork, TYPE_AFPF); 2158 } 2159 2160 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 2161 { 2162 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2163 2164 __rvu_mbox_handler(mwork, TYPE_AFVF); 2165 } 2166 2167 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 2168 { 2169 struct rvu *rvu = mwork->rvu; 2170 struct otx2_mbox_dev *mdev; 2171 struct mbox_hdr *rsp_hdr; 2172 struct mbox_msghdr *msg; 2173 struct mbox_wq_info *mw; 2174 struct otx2_mbox *mbox; 2175 int offset, id, devid; 2176 2177 switch (type) { 2178 case TYPE_AFPF: 2179 mw = &rvu->afpf_wq_info; 2180 break; 2181 case TYPE_AFVF: 2182 mw = &rvu->afvf_wq_info; 2183 break; 2184 default: 2185 return; 2186 } 2187 2188 devid = mwork - mw->mbox_wrk_up; 2189 mbox = &mw->mbox_up; 2190 mdev = &mbox->dev[devid]; 2191 2192 rsp_hdr = mdev->mbase + mbox->rx_start; 2193 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 2194 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 2195 return; 2196 } 2197 2198 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 2199 2200 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 2201 msg = mdev->mbase + offset; 2202 2203 if (msg->id >= MBOX_MSG_MAX) { 2204 dev_err(rvu->dev, 2205 "Mbox msg with unknown ID 0x%x\n", msg->id); 2206 goto end; 2207 } 2208 2209 if (msg->sig != OTX2_MBOX_RSP_SIG) { 2210 dev_err(rvu->dev, 2211 "Mbox msg with wrong signature %x, ID 0x%x\n", 2212 msg->sig, msg->id); 2213 goto end; 2214 } 2215 2216 switch (msg->id) { 2217 case MBOX_MSG_CGX_LINK_EVENT: 2218 break; 2219 default: 2220 if (msg->rc) 2221 dev_err(rvu->dev, 2222 "Mbox msg response has err %d, ID 0x%x\n", 2223 msg->rc, msg->id); 2224 break; 2225 } 2226 end: 2227 offset = mbox->rx_start + msg->next_msgoff; 2228 mdev->msgs_acked++; 2229 } 2230 mw->mbox_wrk_up[devid].up_num_msgs = 0; 2231 2232 otx2_mbox_reset(mbox, devid); 2233 } 2234 2235 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 2236 { 2237 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2238 2239 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 2240 } 2241 2242 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 2243 { 2244 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2245 2246 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 2247 } 2248 2249 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr, 2250 int num, int type) 2251 { 2252 struct rvu_hwinfo *hw = rvu->hw; 2253 int region; 2254 u64 bar4; 2255 2256 /* For cn10k platform VF mailbox regions of a PF follows after the 2257 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from 2258 * RVU_PF_VF_BAR4_ADDR register. 2259 */ 2260 if (type == TYPE_AFVF) { 2261 for (region = 0; region < num; region++) { 2262 if (hw->cap.per_pf_mbox_regs) { 2263 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2264 RVU_AF_PFX_BAR4_ADDR(0)) + 2265 MBOX_SIZE; 2266 bar4 += region * MBOX_SIZE; 2267 } else { 2268 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 2269 bar4 += region * MBOX_SIZE; 2270 } 2271 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2272 if (!mbox_addr[region]) 2273 goto error; 2274 } 2275 return 0; 2276 } 2277 2278 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per 2279 * PF registers. Whereas for Octeontx2 it is read from 2280 * RVU_AF_PF_BAR4_ADDR register. 2281 */ 2282 for (region = 0; region < num; region++) { 2283 if (hw->cap.per_pf_mbox_regs) { 2284 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2285 RVU_AF_PFX_BAR4_ADDR(region)); 2286 } else { 2287 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2288 RVU_AF_PF_BAR4_ADDR); 2289 bar4 += region * MBOX_SIZE; 2290 } 2291 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2292 if (!mbox_addr[region]) 2293 goto error; 2294 } 2295 return 0; 2296 2297 error: 2298 while (region--) 2299 iounmap((void __iomem *)mbox_addr[region]); 2300 return -ENOMEM; 2301 } 2302 2303 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 2304 int type, int num, 2305 void (mbox_handler)(struct work_struct *), 2306 void (mbox_up_handler)(struct work_struct *)) 2307 { 2308 int err = -EINVAL, i, dir, dir_up; 2309 void __iomem *reg_base; 2310 struct rvu_work *mwork; 2311 void **mbox_regions; 2312 const char *name; 2313 2314 mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL); 2315 if (!mbox_regions) 2316 return -ENOMEM; 2317 2318 switch (type) { 2319 case TYPE_AFPF: 2320 name = "rvu_afpf_mailbox"; 2321 dir = MBOX_DIR_AFPF; 2322 dir_up = MBOX_DIR_AFPF_UP; 2323 reg_base = rvu->afreg_base; 2324 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF); 2325 if (err) 2326 goto free_regions; 2327 break; 2328 case TYPE_AFVF: 2329 name = "rvu_afvf_mailbox"; 2330 dir = MBOX_DIR_PFVF; 2331 dir_up = MBOX_DIR_PFVF_UP; 2332 reg_base = rvu->pfreg_base; 2333 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF); 2334 if (err) 2335 goto free_regions; 2336 break; 2337 default: 2338 return err; 2339 } 2340 2341 mw->mbox_wq = alloc_workqueue(name, 2342 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2343 num); 2344 if (!mw->mbox_wq) { 2345 err = -ENOMEM; 2346 goto unmap_regions; 2347 } 2348 2349 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 2350 sizeof(struct rvu_work), GFP_KERNEL); 2351 if (!mw->mbox_wrk) { 2352 err = -ENOMEM; 2353 goto exit; 2354 } 2355 2356 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 2357 sizeof(struct rvu_work), GFP_KERNEL); 2358 if (!mw->mbox_wrk_up) { 2359 err = -ENOMEM; 2360 goto exit; 2361 } 2362 2363 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, 2364 reg_base, dir, num); 2365 if (err) 2366 goto exit; 2367 2368 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, 2369 reg_base, dir_up, num); 2370 if (err) 2371 goto exit; 2372 2373 for (i = 0; i < num; i++) { 2374 mwork = &mw->mbox_wrk[i]; 2375 mwork->rvu = rvu; 2376 INIT_WORK(&mwork->work, mbox_handler); 2377 2378 mwork = &mw->mbox_wrk_up[i]; 2379 mwork->rvu = rvu; 2380 INIT_WORK(&mwork->work, mbox_up_handler); 2381 } 2382 kfree(mbox_regions); 2383 return 0; 2384 2385 exit: 2386 destroy_workqueue(mw->mbox_wq); 2387 unmap_regions: 2388 while (num--) 2389 iounmap((void __iomem *)mbox_regions[num]); 2390 free_regions: 2391 kfree(mbox_regions); 2392 return err; 2393 } 2394 2395 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 2396 { 2397 struct otx2_mbox *mbox = &mw->mbox; 2398 struct otx2_mbox_dev *mdev; 2399 int devid; 2400 2401 if (mw->mbox_wq) { 2402 flush_workqueue(mw->mbox_wq); 2403 destroy_workqueue(mw->mbox_wq); 2404 mw->mbox_wq = NULL; 2405 } 2406 2407 for (devid = 0; devid < mbox->ndevs; devid++) { 2408 mdev = &mbox->dev[devid]; 2409 if (mdev->hwbase) 2410 iounmap((void __iomem *)mdev->hwbase); 2411 } 2412 2413 otx2_mbox_destroy(&mw->mbox); 2414 otx2_mbox_destroy(&mw->mbox_up); 2415 } 2416 2417 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 2418 int mdevs, u64 intr) 2419 { 2420 struct otx2_mbox_dev *mdev; 2421 struct otx2_mbox *mbox; 2422 struct mbox_hdr *hdr; 2423 int i; 2424 2425 for (i = first; i < mdevs; i++) { 2426 /* start from 0 */ 2427 if (!(intr & BIT_ULL(i - first))) 2428 continue; 2429 2430 mbox = &mw->mbox; 2431 mdev = &mbox->dev[i]; 2432 hdr = mdev->mbase + mbox->rx_start; 2433 2434 /*The hdr->num_msgs is set to zero immediately in the interrupt 2435 * handler to ensure that it holds a correct value next time 2436 * when the interrupt handler is called. 2437 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 2438 * pf>mbox.up_num_msgs holds the data for use in 2439 * pfaf_mbox_up_handler. 2440 */ 2441 2442 if (hdr->num_msgs) { 2443 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 2444 hdr->num_msgs = 0; 2445 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 2446 } 2447 mbox = &mw->mbox_up; 2448 mdev = &mbox->dev[i]; 2449 hdr = mdev->mbase + mbox->rx_start; 2450 if (hdr->num_msgs) { 2451 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 2452 hdr->num_msgs = 0; 2453 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 2454 } 2455 } 2456 } 2457 2458 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 2459 { 2460 struct rvu *rvu = (struct rvu *)rvu_irq; 2461 int vfs = rvu->vfs; 2462 u64 intr; 2463 2464 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 2465 /* Clear interrupts */ 2466 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 2467 if (intr) 2468 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); 2469 2470 /* Sync with mbox memory region */ 2471 rmb(); 2472 2473 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 2474 2475 /* Handle VF interrupts */ 2476 if (vfs > 64) { 2477 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 2478 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 2479 2480 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 2481 vfs -= 64; 2482 } 2483 2484 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 2485 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 2486 if (intr) 2487 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); 2488 2489 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 2490 2491 return IRQ_HANDLED; 2492 } 2493 2494 static void rvu_enable_mbox_intr(struct rvu *rvu) 2495 { 2496 struct rvu_hwinfo *hw = rvu->hw; 2497 2498 /* Clear spurious irqs, if any */ 2499 rvu_write64(rvu, BLKADDR_RVUM, 2500 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 2501 2502 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 2503 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 2504 INTR_MASK(hw->total_pfs) & ~1ULL); 2505 } 2506 2507 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 2508 { 2509 struct rvu_block *block; 2510 int slot, lf, num_lfs; 2511 int err; 2512 2513 block = &rvu->hw->block[blkaddr]; 2514 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 2515 block->addr); 2516 if (!num_lfs) 2517 return; 2518 for (slot = 0; slot < num_lfs; slot++) { 2519 lf = rvu_get_lf(rvu, block, pcifunc, slot); 2520 if (lf < 0) 2521 continue; 2522 2523 /* Cleanup LF and reset it */ 2524 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) 2525 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 2526 else if (block->addr == BLKADDR_NPA) 2527 rvu_npa_lf_teardown(rvu, pcifunc, lf); 2528 else if ((block->addr == BLKADDR_CPT0) || 2529 (block->addr == BLKADDR_CPT1)) 2530 rvu_cpt_lf_teardown(rvu, pcifunc, lf, slot); 2531 2532 err = rvu_lf_reset(rvu, block, lf); 2533 if (err) { 2534 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 2535 block->addr, lf); 2536 } 2537 } 2538 } 2539 2540 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 2541 { 2542 mutex_lock(&rvu->flr_lock); 2543 /* Reset order should reflect inter-block dependencies: 2544 * 1. Reset any packet/work sources (NIX, CPT, TIM) 2545 * 2. Flush and reset SSO/SSOW 2546 * 3. Cleanup pools (NPA) 2547 */ 2548 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 2549 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1); 2550 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 2551 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1); 2552 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 2553 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 2554 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 2555 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 2556 rvu_reset_lmt_map_tbl(rvu, pcifunc); 2557 rvu_detach_rsrcs(rvu, NULL, pcifunc); 2558 mutex_unlock(&rvu->flr_lock); 2559 } 2560 2561 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 2562 { 2563 int reg = 0; 2564 2565 /* pcifunc = 0(PF0) | (vf + 1) */ 2566 __rvu_flr_handler(rvu, vf + 1); 2567 2568 if (vf >= 64) { 2569 reg = 1; 2570 vf = vf - 64; 2571 } 2572 2573 /* Signal FLR finish and enable IRQ */ 2574 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 2575 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 2576 } 2577 2578 static void rvu_flr_handler(struct work_struct *work) 2579 { 2580 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 2581 struct rvu *rvu = flrwork->rvu; 2582 u16 pcifunc, numvfs, vf; 2583 u64 cfg; 2584 int pf; 2585 2586 pf = flrwork - rvu->flr_wrk; 2587 if (pf >= rvu->hw->total_pfs) { 2588 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 2589 return; 2590 } 2591 2592 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2593 numvfs = (cfg >> 12) & 0xFF; 2594 pcifunc = pf << RVU_PFVF_PF_SHIFT; 2595 2596 for (vf = 0; vf < numvfs; vf++) 2597 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2598 2599 __rvu_flr_handler(rvu, pcifunc); 2600 2601 /* Signal FLR finish */ 2602 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2603 2604 /* Enable interrupt */ 2605 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2606 } 2607 2608 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2609 { 2610 int dev, vf, reg = 0; 2611 u64 intr; 2612 2613 if (start_vf >= 64) 2614 reg = 1; 2615 2616 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2617 if (!intr) 2618 return; 2619 2620 for (vf = 0; vf < numvfs; vf++) { 2621 if (!(intr & BIT_ULL(vf))) 2622 continue; 2623 /* Clear and disable the interrupt */ 2624 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2625 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2626 2627 dev = vf + start_vf + rvu->hw->total_pfs; 2628 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2629 } 2630 } 2631 2632 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2633 { 2634 struct rvu *rvu = (struct rvu *)rvu_irq; 2635 u64 intr; 2636 u8 pf; 2637 2638 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2639 if (!intr) 2640 goto afvf_flr; 2641 2642 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2643 if (intr & (1ULL << pf)) { 2644 /* clear interrupt */ 2645 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2646 BIT_ULL(pf)); 2647 /* Disable the interrupt */ 2648 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2649 BIT_ULL(pf)); 2650 /* PF is already dead do only AF related operations */ 2651 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2652 } 2653 } 2654 2655 afvf_flr: 2656 rvu_afvf_queue_flr_work(rvu, 0, 64); 2657 if (rvu->vfs > 64) 2658 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2659 2660 return IRQ_HANDLED; 2661 } 2662 2663 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2664 { 2665 int vf; 2666 2667 /* Nothing to be done here other than clearing the 2668 * TRPEND bit. 2669 */ 2670 for (vf = 0; vf < 64; vf++) { 2671 if (intr & (1ULL << vf)) { 2672 /* clear the trpend due to ME(master enable) */ 2673 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2674 /* clear interrupt */ 2675 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2676 } 2677 } 2678 } 2679 2680 /* Handles ME interrupts from VFs of AF */ 2681 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2682 { 2683 struct rvu *rvu = (struct rvu *)rvu_irq; 2684 int vfset; 2685 u64 intr; 2686 2687 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2688 2689 for (vfset = 0; vfset <= 1; vfset++) { 2690 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2691 if (intr) 2692 rvu_me_handle_vfset(rvu, vfset, intr); 2693 } 2694 2695 return IRQ_HANDLED; 2696 } 2697 2698 /* Handles ME interrupts from PFs */ 2699 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2700 { 2701 struct rvu *rvu = (struct rvu *)rvu_irq; 2702 u64 intr; 2703 u8 pf; 2704 2705 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2706 2707 /* Nothing to be done here other than clearing the 2708 * TRPEND bit. 2709 */ 2710 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2711 if (intr & (1ULL << pf)) { 2712 /* clear the trpend due to ME(master enable) */ 2713 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2714 BIT_ULL(pf)); 2715 /* clear interrupt */ 2716 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2717 BIT_ULL(pf)); 2718 } 2719 } 2720 2721 return IRQ_HANDLED; 2722 } 2723 2724 static void rvu_unregister_interrupts(struct rvu *rvu) 2725 { 2726 int irq; 2727 2728 /* Disable the Mbox interrupt */ 2729 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2730 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2731 2732 /* Disable the PF FLR interrupt */ 2733 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2734 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2735 2736 /* Disable the PF ME interrupt */ 2737 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2738 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2739 2740 for (irq = 0; irq < rvu->num_vec; irq++) { 2741 if (rvu->irq_allocated[irq]) { 2742 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2743 rvu->irq_allocated[irq] = false; 2744 } 2745 } 2746 2747 pci_free_irq_vectors(rvu->pdev); 2748 rvu->num_vec = 0; 2749 } 2750 2751 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 2752 { 2753 struct rvu_pfvf *pfvf = &rvu->pf[0]; 2754 int offset; 2755 2756 pfvf = &rvu->pf[0]; 2757 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2758 2759 /* Make sure there are enough MSIX vectors configured so that 2760 * VF interrupts can be handled. Offset equal to zero means 2761 * that PF vectors are not configured and overlapping AF vectors. 2762 */ 2763 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2764 offset; 2765 } 2766 2767 static int rvu_register_interrupts(struct rvu *rvu) 2768 { 2769 int ret, offset, pf_vec_start; 2770 2771 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2772 2773 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2774 NAME_SIZE, GFP_KERNEL); 2775 if (!rvu->irq_name) 2776 return -ENOMEM; 2777 2778 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2779 sizeof(bool), GFP_KERNEL); 2780 if (!rvu->irq_allocated) 2781 return -ENOMEM; 2782 2783 /* Enable MSI-X */ 2784 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2785 rvu->num_vec, PCI_IRQ_MSIX); 2786 if (ret < 0) { 2787 dev_err(rvu->dev, 2788 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2789 rvu->num_vec, ret); 2790 return ret; 2791 } 2792 2793 /* Register mailbox interrupt handler */ 2794 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2795 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2796 rvu_mbox_intr_handler, 0, 2797 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2798 if (ret) { 2799 dev_err(rvu->dev, 2800 "RVUAF: IRQ registration failed for mbox irq\n"); 2801 goto fail; 2802 } 2803 2804 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2805 2806 /* Enable mailbox interrupts from all PFs */ 2807 rvu_enable_mbox_intr(rvu); 2808 2809 /* Register FLR interrupt handler */ 2810 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2811 "RVUAF FLR"); 2812 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2813 rvu_flr_intr_handler, 0, 2814 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2815 rvu); 2816 if (ret) { 2817 dev_err(rvu->dev, 2818 "RVUAF: IRQ registration failed for FLR\n"); 2819 goto fail; 2820 } 2821 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 2822 2823 /* Enable FLR interrupt for all PFs*/ 2824 rvu_write64(rvu, BLKADDR_RVUM, 2825 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 2826 2827 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 2828 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2829 2830 /* Register ME interrupt handler */ 2831 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2832 "RVUAF ME"); 2833 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 2834 rvu_me_pf_intr_handler, 0, 2835 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2836 rvu); 2837 if (ret) { 2838 dev_err(rvu->dev, 2839 "RVUAF: IRQ registration failed for ME\n"); 2840 } 2841 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 2842 2843 /* Clear TRPEND bit for all PF */ 2844 rvu_write64(rvu, BLKADDR_RVUM, 2845 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 2846 /* Enable ME interrupt for all PFs*/ 2847 rvu_write64(rvu, BLKADDR_RVUM, 2848 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 2849 2850 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 2851 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2852 2853 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 2854 return 0; 2855 2856 /* Get PF MSIX vectors offset. */ 2857 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 2858 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2859 2860 /* Register MBOX0 interrupt. */ 2861 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 2862 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 2863 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2864 rvu_mbox_intr_handler, 0, 2865 &rvu->irq_name[offset * NAME_SIZE], 2866 rvu); 2867 if (ret) 2868 dev_err(rvu->dev, 2869 "RVUAF: IRQ registration failed for Mbox0\n"); 2870 2871 rvu->irq_allocated[offset] = true; 2872 2873 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 2874 * simply increment current offset by 1. 2875 */ 2876 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 2877 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 2878 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2879 rvu_mbox_intr_handler, 0, 2880 &rvu->irq_name[offset * NAME_SIZE], 2881 rvu); 2882 if (ret) 2883 dev_err(rvu->dev, 2884 "RVUAF: IRQ registration failed for Mbox1\n"); 2885 2886 rvu->irq_allocated[offset] = true; 2887 2888 /* Register FLR interrupt handler for AF's VFs */ 2889 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 2890 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 2891 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2892 rvu_flr_intr_handler, 0, 2893 &rvu->irq_name[offset * NAME_SIZE], rvu); 2894 if (ret) { 2895 dev_err(rvu->dev, 2896 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 2897 goto fail; 2898 } 2899 rvu->irq_allocated[offset] = true; 2900 2901 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 2902 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 2903 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2904 rvu_flr_intr_handler, 0, 2905 &rvu->irq_name[offset * NAME_SIZE], rvu); 2906 if (ret) { 2907 dev_err(rvu->dev, 2908 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 2909 goto fail; 2910 } 2911 rvu->irq_allocated[offset] = true; 2912 2913 /* Register ME interrupt handler for AF's VFs */ 2914 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 2915 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 2916 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2917 rvu_me_vf_intr_handler, 0, 2918 &rvu->irq_name[offset * NAME_SIZE], rvu); 2919 if (ret) { 2920 dev_err(rvu->dev, 2921 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 2922 goto fail; 2923 } 2924 rvu->irq_allocated[offset] = true; 2925 2926 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 2927 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 2928 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2929 rvu_me_vf_intr_handler, 0, 2930 &rvu->irq_name[offset * NAME_SIZE], rvu); 2931 if (ret) { 2932 dev_err(rvu->dev, 2933 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 2934 goto fail; 2935 } 2936 rvu->irq_allocated[offset] = true; 2937 return 0; 2938 2939 fail: 2940 rvu_unregister_interrupts(rvu); 2941 return ret; 2942 } 2943 2944 static void rvu_flr_wq_destroy(struct rvu *rvu) 2945 { 2946 if (rvu->flr_wq) { 2947 flush_workqueue(rvu->flr_wq); 2948 destroy_workqueue(rvu->flr_wq); 2949 rvu->flr_wq = NULL; 2950 } 2951 } 2952 2953 static int rvu_flr_init(struct rvu *rvu) 2954 { 2955 int dev, num_devs; 2956 u64 cfg; 2957 int pf; 2958 2959 /* Enable FLR for all PFs*/ 2960 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2961 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2962 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 2963 cfg | BIT_ULL(22)); 2964 } 2965 2966 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", 2967 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2968 1); 2969 if (!rvu->flr_wq) 2970 return -ENOMEM; 2971 2972 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 2973 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 2974 sizeof(struct rvu_work), GFP_KERNEL); 2975 if (!rvu->flr_wrk) { 2976 destroy_workqueue(rvu->flr_wq); 2977 return -ENOMEM; 2978 } 2979 2980 for (dev = 0; dev < num_devs; dev++) { 2981 rvu->flr_wrk[dev].rvu = rvu; 2982 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 2983 } 2984 2985 mutex_init(&rvu->flr_lock); 2986 2987 return 0; 2988 } 2989 2990 static void rvu_disable_afvf_intr(struct rvu *rvu) 2991 { 2992 int vfs = rvu->vfs; 2993 2994 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2995 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2996 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2997 if (vfs <= 64) 2998 return; 2999 3000 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 3001 INTR_MASK(vfs - 64)); 3002 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3003 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3004 } 3005 3006 static void rvu_enable_afvf_intr(struct rvu *rvu) 3007 { 3008 int vfs = rvu->vfs; 3009 3010 /* Clear any pending interrupts and enable AF VF interrupts for 3011 * the first 64 VFs. 3012 */ 3013 /* Mbox */ 3014 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 3015 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3016 3017 /* FLR */ 3018 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 3019 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3020 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3021 3022 /* Same for remaining VFs, if any. */ 3023 if (vfs <= 64) 3024 return; 3025 3026 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 3027 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 3028 INTR_MASK(vfs - 64)); 3029 3030 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 3031 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3032 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3033 } 3034 3035 int rvu_get_num_lbk_chans(void) 3036 { 3037 struct pci_dev *pdev; 3038 void __iomem *base; 3039 int ret = -EIO; 3040 3041 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 3042 NULL); 3043 if (!pdev) 3044 goto err; 3045 3046 base = pci_ioremap_bar(pdev, 0); 3047 if (!base) 3048 goto err_put; 3049 3050 /* Read number of available LBK channels from LBK(0)_CONST register. */ 3051 ret = (readq(base + 0x10) >> 32) & 0xffff; 3052 iounmap(base); 3053 err_put: 3054 pci_dev_put(pdev); 3055 err: 3056 return ret; 3057 } 3058 3059 static int rvu_enable_sriov(struct rvu *rvu) 3060 { 3061 struct pci_dev *pdev = rvu->pdev; 3062 int err, chans, vfs; 3063 3064 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 3065 dev_warn(&pdev->dev, 3066 "Skipping SRIOV enablement since not enough IRQs are available\n"); 3067 return 0; 3068 } 3069 3070 chans = rvu_get_num_lbk_chans(); 3071 if (chans < 0) 3072 return chans; 3073 3074 vfs = pci_sriov_get_totalvfs(pdev); 3075 3076 /* Limit VFs in case we have more VFs than LBK channels available. */ 3077 if (vfs > chans) 3078 vfs = chans; 3079 3080 if (!vfs) 3081 return 0; 3082 3083 /* LBK channel number 63 is used for switching packets between 3084 * CGX mapped VFs. Hence limit LBK pairs till 62 only. 3085 */ 3086 if (vfs > 62) 3087 vfs = 62; 3088 3089 /* Save VFs number for reference in VF interrupts handlers. 3090 * Since interrupts might start arriving during SRIOV enablement 3091 * ordinary API cannot be used to get number of enabled VFs. 3092 */ 3093 rvu->vfs = vfs; 3094 3095 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 3096 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 3097 if (err) 3098 return err; 3099 3100 rvu_enable_afvf_intr(rvu); 3101 /* Make sure IRQs are enabled before SRIOV. */ 3102 mb(); 3103 3104 err = pci_enable_sriov(pdev, vfs); 3105 if (err) { 3106 rvu_disable_afvf_intr(rvu); 3107 rvu_mbox_destroy(&rvu->afvf_wq_info); 3108 return err; 3109 } 3110 3111 return 0; 3112 } 3113 3114 static void rvu_disable_sriov(struct rvu *rvu) 3115 { 3116 rvu_disable_afvf_intr(rvu); 3117 rvu_mbox_destroy(&rvu->afvf_wq_info); 3118 pci_disable_sriov(rvu->pdev); 3119 } 3120 3121 static void rvu_update_module_params(struct rvu *rvu) 3122 { 3123 const char *default_pfl_name = "default"; 3124 3125 strscpy(rvu->mkex_pfl_name, 3126 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 3127 strscpy(rvu->kpu_pfl_name, 3128 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN); 3129 } 3130 3131 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3132 { 3133 struct device *dev = &pdev->dev; 3134 struct rvu *rvu; 3135 int err; 3136 3137 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 3138 if (!rvu) 3139 return -ENOMEM; 3140 3141 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 3142 if (!rvu->hw) { 3143 devm_kfree(dev, rvu); 3144 return -ENOMEM; 3145 } 3146 3147 pci_set_drvdata(pdev, rvu); 3148 rvu->pdev = pdev; 3149 rvu->dev = &pdev->dev; 3150 3151 err = pci_enable_device(pdev); 3152 if (err) { 3153 dev_err(dev, "Failed to enable PCI device\n"); 3154 goto err_freemem; 3155 } 3156 3157 err = pci_request_regions(pdev, DRV_NAME); 3158 if (err) { 3159 dev_err(dev, "PCI request regions failed 0x%x\n", err); 3160 goto err_disable_device; 3161 } 3162 3163 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3164 if (err) { 3165 dev_err(dev, "DMA mask config failed, abort\n"); 3166 goto err_release_regions; 3167 } 3168 3169 pci_set_master(pdev); 3170 3171 rvu->ptp = ptp_get(); 3172 if (IS_ERR(rvu->ptp)) { 3173 err = PTR_ERR(rvu->ptp); 3174 if (err == -EPROBE_DEFER) 3175 goto err_release_regions; 3176 rvu->ptp = NULL; 3177 } 3178 3179 /* Map Admin function CSRs */ 3180 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 3181 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 3182 if (!rvu->afreg_base || !rvu->pfreg_base) { 3183 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 3184 err = -ENOMEM; 3185 goto err_put_ptp; 3186 } 3187 3188 /* Store module params in rvu structure */ 3189 rvu_update_module_params(rvu); 3190 3191 /* Check which blocks the HW supports */ 3192 rvu_check_block_implemented(rvu); 3193 3194 rvu_reset_all_blocks(rvu); 3195 3196 rvu_setup_hw_capabilities(rvu); 3197 3198 err = rvu_setup_hw_resources(rvu); 3199 if (err) 3200 goto err_put_ptp; 3201 3202 /* Init mailbox btw AF and PFs */ 3203 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 3204 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 3205 rvu_afpf_mbox_up_handler); 3206 if (err) { 3207 dev_err(dev, "%s: Failed to initialize mbox\n", __func__); 3208 goto err_hwsetup; 3209 } 3210 3211 err = rvu_flr_init(rvu); 3212 if (err) { 3213 dev_err(dev, "%s: Failed to initialize flr\n", __func__); 3214 goto err_mbox; 3215 } 3216 3217 err = rvu_register_interrupts(rvu); 3218 if (err) { 3219 dev_err(dev, "%s: Failed to register interrupts\n", __func__); 3220 goto err_flr; 3221 } 3222 3223 err = rvu_register_dl(rvu); 3224 if (err) { 3225 dev_err(dev, "%s: Failed to register devlink\n", __func__); 3226 goto err_irq; 3227 } 3228 3229 rvu_setup_rvum_blk_revid(rvu); 3230 3231 /* Enable AF's VFs (if any) */ 3232 err = rvu_enable_sriov(rvu); 3233 if (err) { 3234 dev_err(dev, "%s: Failed to enable sriov\n", __func__); 3235 goto err_dl; 3236 } 3237 3238 /* Initialize debugfs */ 3239 rvu_dbg_init(rvu); 3240 3241 mutex_init(&rvu->rswitch.switch_lock); 3242 3243 if (rvu->fwdata) 3244 ptp_start(rvu->ptp, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate, 3245 rvu->fwdata->ptp_ext_tstamp); 3246 3247 return 0; 3248 err_dl: 3249 rvu_unregister_dl(rvu); 3250 err_irq: 3251 rvu_unregister_interrupts(rvu); 3252 err_flr: 3253 rvu_flr_wq_destroy(rvu); 3254 err_mbox: 3255 rvu_mbox_destroy(&rvu->afpf_wq_info); 3256 err_hwsetup: 3257 rvu_cgx_exit(rvu); 3258 rvu_fwdata_exit(rvu); 3259 rvu_reset_all_blocks(rvu); 3260 rvu_free_hw_resources(rvu); 3261 rvu_clear_rvum_blk_revid(rvu); 3262 err_put_ptp: 3263 ptp_put(rvu->ptp); 3264 err_release_regions: 3265 pci_release_regions(pdev); 3266 err_disable_device: 3267 pci_disable_device(pdev); 3268 err_freemem: 3269 pci_set_drvdata(pdev, NULL); 3270 devm_kfree(&pdev->dev, rvu->hw); 3271 devm_kfree(dev, rvu); 3272 return err; 3273 } 3274 3275 static void rvu_remove(struct pci_dev *pdev) 3276 { 3277 struct rvu *rvu = pci_get_drvdata(pdev); 3278 3279 rvu_dbg_exit(rvu); 3280 rvu_unregister_dl(rvu); 3281 rvu_unregister_interrupts(rvu); 3282 rvu_flr_wq_destroy(rvu); 3283 rvu_cgx_exit(rvu); 3284 rvu_fwdata_exit(rvu); 3285 rvu_mbox_destroy(&rvu->afpf_wq_info); 3286 rvu_disable_sriov(rvu); 3287 rvu_reset_all_blocks(rvu); 3288 rvu_free_hw_resources(rvu); 3289 rvu_clear_rvum_blk_revid(rvu); 3290 ptp_put(rvu->ptp); 3291 pci_release_regions(pdev); 3292 pci_disable_device(pdev); 3293 pci_set_drvdata(pdev, NULL); 3294 3295 devm_kfree(&pdev->dev, rvu->hw); 3296 devm_kfree(&pdev->dev, rvu); 3297 } 3298 3299 static struct pci_driver rvu_driver = { 3300 .name = DRV_NAME, 3301 .id_table = rvu_id_table, 3302 .probe = rvu_probe, 3303 .remove = rvu_remove, 3304 }; 3305 3306 static int __init rvu_init_module(void) 3307 { 3308 int err; 3309 3310 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3311 3312 err = pci_register_driver(&cgx_driver); 3313 if (err < 0) 3314 return err; 3315 3316 err = pci_register_driver(&ptp_driver); 3317 if (err < 0) 3318 goto ptp_err; 3319 3320 err = pci_register_driver(&rvu_driver); 3321 if (err < 0) 3322 goto rvu_err; 3323 3324 return 0; 3325 rvu_err: 3326 pci_unregister_driver(&ptp_driver); 3327 ptp_err: 3328 pci_unregister_driver(&cgx_driver); 3329 3330 return err; 3331 } 3332 3333 static void __exit rvu_cleanup_module(void) 3334 { 3335 pci_unregister_driver(&rvu_driver); 3336 pci_unregister_driver(&ptp_driver); 3337 pci_unregister_driver(&cgx_driver); 3338 } 3339 3340 module_init(rvu_init_module); 3341 module_exit(rvu_cleanup_module); 3342