1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/delay.h> 11 #include <linux/irq.h> 12 #include <linux/pci.h> 13 #include <linux/sysfs.h> 14 15 #include "cgx.h" 16 #include "rvu.h" 17 #include "rvu_reg.h" 18 #include "ptp.h" 19 #include "mcs.h" 20 21 #include "rvu_trace.h" 22 #include "rvu_npc_hash.h" 23 24 #define DRV_NAME "rvu_af" 25 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 26 27 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 28 struct rvu_block *block, int lf); 29 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 30 struct rvu_block *block, int lf); 31 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 32 33 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 34 int type, int num, 35 void (mbox_handler)(struct work_struct *), 36 void (mbox_up_handler)(struct work_struct *)); 37 enum { 38 TYPE_AFVF, 39 TYPE_AFPF, 40 }; 41 42 /* Supported devices */ 43 static const struct pci_device_id rvu_id_table[] = { 44 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 45 { 0, } /* end of table */ 46 }; 47 48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 49 MODULE_DESCRIPTION(DRV_STRING); 50 MODULE_LICENSE("GPL v2"); 51 MODULE_DEVICE_TABLE(pci, rvu_id_table); 52 53 static char *mkex_profile; /* MKEX profile name */ 54 module_param(mkex_profile, charp, 0000); 55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 56 57 static char *kpu_profile; /* KPU profile name */ 58 module_param(kpu_profile, charp, 0000); 59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string"); 60 61 static void rvu_setup_hw_capabilities(struct rvu *rvu) 62 { 63 struct rvu_hwinfo *hw = rvu->hw; 64 65 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 66 hw->cap.nix_fixed_txschq_mapping = false; 67 hw->cap.nix_shaping = true; 68 hw->cap.nix_tx_link_bp = true; 69 hw->cap.nix_rx_multicast = true; 70 hw->cap.nix_shaper_toggle_wait = false; 71 hw->cap.npc_hash_extract = false; 72 hw->cap.npc_exact_match_enabled = false; 73 hw->rvu = rvu; 74 75 if (is_rvu_pre_96xx_C0(rvu)) { 76 hw->cap.nix_fixed_txschq_mapping = true; 77 hw->cap.nix_txsch_per_cgx_lmac = 4; 78 hw->cap.nix_txsch_per_lbk_lmac = 132; 79 hw->cap.nix_txsch_per_sdp_lmac = 76; 80 hw->cap.nix_shaping = false; 81 hw->cap.nix_tx_link_bp = false; 82 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu)) 83 hw->cap.nix_rx_multicast = false; 84 } 85 if (!is_rvu_pre_96xx_C0(rvu)) 86 hw->cap.nix_shaper_toggle_wait = true; 87 88 if (!is_rvu_otx2(rvu)) 89 hw->cap.per_pf_mbox_regs = true; 90 91 if (is_rvu_npc_hash_extract_en(rvu)) 92 hw->cap.npc_hash_extract = true; 93 } 94 95 /* Poll a RVU block's register 'offset', for a 'zero' 96 * or 'nonzero' at bits specified by 'mask' 97 */ 98 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 99 { 100 unsigned long timeout = jiffies + usecs_to_jiffies(20000); 101 bool twice = false; 102 void __iomem *reg; 103 u64 reg_val; 104 105 reg = rvu->afreg_base + ((block << 28) | offset); 106 again: 107 reg_val = readq(reg); 108 if (zero && !(reg_val & mask)) 109 return 0; 110 if (!zero && (reg_val & mask)) 111 return 0; 112 if (time_before(jiffies, timeout)) { 113 usleep_range(1, 5); 114 goto again; 115 } 116 /* In scenarios where CPU is scheduled out before checking 117 * 'time_before' (above) and gets scheduled in such that 118 * jiffies are beyond timeout value, then check again if HW is 119 * done with the operation in the meantime. 120 */ 121 if (!twice) { 122 twice = true; 123 goto again; 124 } 125 return -EBUSY; 126 } 127 128 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 129 { 130 int id; 131 132 if (!rsrc->bmap) 133 return -EINVAL; 134 135 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 136 if (id >= rsrc->max) 137 return -ENOSPC; 138 139 __set_bit(id, rsrc->bmap); 140 141 return id; 142 } 143 144 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 145 { 146 int start; 147 148 if (!rsrc->bmap) 149 return -EINVAL; 150 151 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 152 if (start >= rsrc->max) 153 return -ENOSPC; 154 155 bitmap_set(rsrc->bmap, start, nrsrc); 156 return start; 157 } 158 159 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 160 { 161 if (!rsrc->bmap) 162 return; 163 if (start >= rsrc->max) 164 return; 165 166 bitmap_clear(rsrc->bmap, start, nrsrc); 167 } 168 169 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 170 { 171 int start; 172 173 if (!rsrc->bmap) 174 return false; 175 176 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 177 if (start >= rsrc->max) 178 return false; 179 180 return true; 181 } 182 183 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 184 { 185 if (!rsrc->bmap) 186 return; 187 188 __clear_bit(id, rsrc->bmap); 189 } 190 191 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 192 { 193 int used; 194 195 if (!rsrc->bmap) 196 return 0; 197 198 used = bitmap_weight(rsrc->bmap, rsrc->max); 199 return (rsrc->max - used); 200 } 201 202 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id) 203 { 204 if (!rsrc->bmap) 205 return false; 206 207 return !test_bit(id, rsrc->bmap); 208 } 209 210 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 211 { 212 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 213 sizeof(long), GFP_KERNEL); 214 if (!rsrc->bmap) 215 return -ENOMEM; 216 return 0; 217 } 218 219 void rvu_free_bitmap(struct rsrc_bmap *rsrc) 220 { 221 kfree(rsrc->bmap); 222 } 223 224 /* Get block LF's HW index from a PF_FUNC's block slot number */ 225 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 226 { 227 u16 match = 0; 228 int lf; 229 230 mutex_lock(&rvu->rsrc_lock); 231 for (lf = 0; lf < block->lf.max; lf++) { 232 if (block->fn_map[lf] == pcifunc) { 233 if (slot == match) { 234 mutex_unlock(&rvu->rsrc_lock); 235 return lf; 236 } 237 match++; 238 } 239 } 240 mutex_unlock(&rvu->rsrc_lock); 241 return -ENODEV; 242 } 243 244 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 245 * Some silicon variants of OcteonTX2 supports 246 * multiple blocks of same type. 247 * 248 * @pcifunc has to be zero when no LF is yet attached. 249 * 250 * For a pcifunc if LFs are attached from multiple blocks of same type, then 251 * return blkaddr of first encountered block. 252 */ 253 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 254 { 255 int devnum, blkaddr = -ENODEV; 256 u64 cfg, reg; 257 bool is_pf; 258 259 switch (blktype) { 260 case BLKTYPE_NPC: 261 blkaddr = BLKADDR_NPC; 262 goto exit; 263 case BLKTYPE_NPA: 264 blkaddr = BLKADDR_NPA; 265 goto exit; 266 case BLKTYPE_NIX: 267 /* For now assume NIX0 */ 268 if (!pcifunc) { 269 blkaddr = BLKADDR_NIX0; 270 goto exit; 271 } 272 break; 273 case BLKTYPE_SSO: 274 blkaddr = BLKADDR_SSO; 275 goto exit; 276 case BLKTYPE_SSOW: 277 blkaddr = BLKADDR_SSOW; 278 goto exit; 279 case BLKTYPE_TIM: 280 blkaddr = BLKADDR_TIM; 281 goto exit; 282 case BLKTYPE_CPT: 283 /* For now assume CPT0 */ 284 if (!pcifunc) { 285 blkaddr = BLKADDR_CPT0; 286 goto exit; 287 } 288 break; 289 } 290 291 /* Check if this is a RVU PF or VF */ 292 if (pcifunc & RVU_PFVF_FUNC_MASK) { 293 is_pf = false; 294 devnum = rvu_get_hwvf(rvu, pcifunc); 295 } else { 296 is_pf = true; 297 devnum = rvu_get_pf(pcifunc); 298 } 299 300 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or 301 * 'BLKADDR_NIX1'. 302 */ 303 if (blktype == BLKTYPE_NIX) { 304 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) : 305 RVU_PRIV_HWVFX_NIXX_CFG(0); 306 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 307 if (cfg) { 308 blkaddr = BLKADDR_NIX0; 309 goto exit; 310 } 311 312 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) : 313 RVU_PRIV_HWVFX_NIXX_CFG(1); 314 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 315 if (cfg) 316 blkaddr = BLKADDR_NIX1; 317 } 318 319 if (blktype == BLKTYPE_CPT) { 320 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) : 321 RVU_PRIV_HWVFX_CPTX_CFG(0); 322 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 323 if (cfg) { 324 blkaddr = BLKADDR_CPT0; 325 goto exit; 326 } 327 328 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) : 329 RVU_PRIV_HWVFX_CPTX_CFG(1); 330 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 331 if (cfg) 332 blkaddr = BLKADDR_CPT1; 333 } 334 335 exit: 336 if (is_block_implemented(rvu->hw, blkaddr)) 337 return blkaddr; 338 return -ENODEV; 339 } 340 341 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 342 struct rvu_block *block, u16 pcifunc, 343 u16 lf, bool attach) 344 { 345 int devnum, num_lfs = 0; 346 bool is_pf; 347 u64 reg; 348 349 if (lf >= block->lf.max) { 350 dev_err(&rvu->pdev->dev, 351 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 352 __func__, lf, block->name, block->lf.max); 353 return; 354 } 355 356 /* Check if this is for a RVU PF or VF */ 357 if (pcifunc & RVU_PFVF_FUNC_MASK) { 358 is_pf = false; 359 devnum = rvu_get_hwvf(rvu, pcifunc); 360 } else { 361 is_pf = true; 362 devnum = rvu_get_pf(pcifunc); 363 } 364 365 block->fn_map[lf] = attach ? pcifunc : 0; 366 367 switch (block->addr) { 368 case BLKADDR_NPA: 369 pfvf->npalf = attach ? true : false; 370 num_lfs = pfvf->npalf; 371 break; 372 case BLKADDR_NIX0: 373 case BLKADDR_NIX1: 374 pfvf->nixlf = attach ? true : false; 375 num_lfs = pfvf->nixlf; 376 break; 377 case BLKADDR_SSO: 378 attach ? pfvf->sso++ : pfvf->sso--; 379 num_lfs = pfvf->sso; 380 break; 381 case BLKADDR_SSOW: 382 attach ? pfvf->ssow++ : pfvf->ssow--; 383 num_lfs = pfvf->ssow; 384 break; 385 case BLKADDR_TIM: 386 attach ? pfvf->timlfs++ : pfvf->timlfs--; 387 num_lfs = pfvf->timlfs; 388 break; 389 case BLKADDR_CPT0: 390 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 391 num_lfs = pfvf->cptlfs; 392 break; 393 case BLKADDR_CPT1: 394 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; 395 num_lfs = pfvf->cpt1_lfs; 396 break; 397 } 398 399 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 400 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 401 } 402 403 inline int rvu_get_pf(u16 pcifunc) 404 { 405 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 406 } 407 408 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 409 { 410 u64 cfg; 411 412 /* Get numVFs attached to this PF and first HWVF */ 413 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 414 if (numvfs) 415 *numvfs = (cfg >> 12) & 0xFF; 416 if (hwvf) 417 *hwvf = cfg & 0xFFF; 418 } 419 420 int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 421 { 422 int pf, func; 423 u64 cfg; 424 425 pf = rvu_get_pf(pcifunc); 426 func = pcifunc & RVU_PFVF_FUNC_MASK; 427 428 /* Get first HWVF attached to this PF */ 429 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 430 431 return ((cfg & 0xFFF) + func - 1); 432 } 433 434 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 435 { 436 /* Check if it is a PF or VF */ 437 if (pcifunc & RVU_PFVF_FUNC_MASK) 438 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 439 else 440 return &rvu->pf[rvu_get_pf(pcifunc)]; 441 } 442 443 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 444 { 445 int pf, vf, nvfs; 446 u64 cfg; 447 448 pf = rvu_get_pf(pcifunc); 449 if (pf >= rvu->hw->total_pfs) 450 return false; 451 452 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 453 return true; 454 455 /* Check if VF is within number of VFs attached to this PF */ 456 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 457 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 458 nvfs = (cfg >> 12) & 0xFF; 459 if (vf >= nvfs) 460 return false; 461 462 return true; 463 } 464 465 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 466 { 467 struct rvu_block *block; 468 469 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 470 return false; 471 472 block = &hw->block[blkaddr]; 473 return block->implemented; 474 } 475 476 static void rvu_check_block_implemented(struct rvu *rvu) 477 { 478 struct rvu_hwinfo *hw = rvu->hw; 479 struct rvu_block *block; 480 int blkid; 481 u64 cfg; 482 483 /* For each block check if 'implemented' bit is set */ 484 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 485 block = &hw->block[blkid]; 486 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 487 if (cfg & BIT_ULL(11)) 488 block->implemented = true; 489 } 490 } 491 492 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 493 { 494 rvu_write64(rvu, BLKADDR_RVUM, 495 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 496 RVU_BLK_RVUM_REVID); 497 } 498 499 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 500 { 501 rvu_write64(rvu, BLKADDR_RVUM, 502 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 503 } 504 505 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 506 { 507 int err; 508 509 if (!block->implemented) 510 return 0; 511 512 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 513 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 514 true); 515 return err; 516 } 517 518 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 519 { 520 struct rvu_block *block = &rvu->hw->block[blkaddr]; 521 int err; 522 523 if (!block->implemented) 524 return; 525 526 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 527 err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 528 if (err) { 529 dev_err(rvu->dev, "HW block:%d reset timeout retrying again\n", blkaddr); 530 while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY) 531 ; 532 } 533 } 534 535 static void rvu_reset_all_blocks(struct rvu *rvu) 536 { 537 /* Do a HW reset of all RVU blocks */ 538 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 539 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 540 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST); 541 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 542 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 543 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 544 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 545 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST); 546 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 547 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 548 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST); 549 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST); 550 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 551 } 552 553 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 554 { 555 struct rvu_pfvf *pfvf; 556 u64 cfg; 557 int lf; 558 559 for (lf = 0; lf < block->lf.max; lf++) { 560 cfg = rvu_read64(rvu, block->addr, 561 block->lfcfg_reg | (lf << block->lfshift)); 562 if (!(cfg & BIT_ULL(63))) 563 continue; 564 565 /* Set this resource as being used */ 566 __set_bit(lf, block->lf.bmap); 567 568 /* Get, to whom this LF is attached */ 569 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 570 rvu_update_rsrc_map(rvu, pfvf, block, 571 (cfg >> 8) & 0xFFFF, lf, true); 572 573 /* Set start MSIX vector for this LF within this PF/VF */ 574 rvu_set_msix_offset(rvu, pfvf, block, lf); 575 } 576 } 577 578 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 579 { 580 int min_vecs; 581 582 if (!vf) 583 goto check_pf; 584 585 if (!nvecs) { 586 dev_warn(rvu->dev, 587 "PF%d:VF%d is configured with zero msix vectors, %d\n", 588 pf, vf - 1, nvecs); 589 } 590 return; 591 592 check_pf: 593 if (pf == 0) 594 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 595 else 596 min_vecs = RVU_PF_INT_VEC_CNT; 597 598 if (!(nvecs < min_vecs)) 599 return; 600 dev_warn(rvu->dev, 601 "PF%d is configured with too few vectors, %d, min is %d\n", 602 pf, nvecs, min_vecs); 603 } 604 605 static int rvu_setup_msix_resources(struct rvu *rvu) 606 { 607 struct rvu_hwinfo *hw = rvu->hw; 608 int pf, vf, numvfs, hwvf, err; 609 int nvecs, offset, max_msix; 610 struct rvu_pfvf *pfvf; 611 u64 cfg, phy_addr; 612 dma_addr_t iova; 613 614 for (pf = 0; pf < hw->total_pfs; pf++) { 615 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 616 /* If PF is not enabled, nothing to do */ 617 if (!((cfg >> 20) & 0x01)) 618 continue; 619 620 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 621 622 pfvf = &rvu->pf[pf]; 623 /* Get num of MSIX vectors attached to this PF */ 624 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 625 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 626 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 627 628 /* Alloc msix bitmap for this PF */ 629 err = rvu_alloc_bitmap(&pfvf->msix); 630 if (err) 631 return err; 632 633 /* Allocate memory for MSIX vector to RVU block LF mapping */ 634 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 635 sizeof(u16), GFP_KERNEL); 636 if (!pfvf->msix_lfmap) 637 return -ENOMEM; 638 639 /* For PF0 (AF) firmware will set msix vector offsets for 640 * AF, block AF and PF0_INT vectors, so jump to VFs. 641 */ 642 if (!pf) 643 goto setup_vfmsix; 644 645 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 646 * These are allocated on driver init and never freed, 647 * so no need to set 'msix_lfmap' for these. 648 */ 649 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 650 nvecs = (cfg >> 12) & 0xFF; 651 cfg &= ~0x7FFULL; 652 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 653 rvu_write64(rvu, BLKADDR_RVUM, 654 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 655 setup_vfmsix: 656 /* Alloc msix bitmap for VFs */ 657 for (vf = 0; vf < numvfs; vf++) { 658 pfvf = &rvu->hwvf[hwvf + vf]; 659 /* Get num of MSIX vectors attached to this VF */ 660 cfg = rvu_read64(rvu, BLKADDR_RVUM, 661 RVU_PRIV_PFX_MSIX_CFG(pf)); 662 pfvf->msix.max = (cfg & 0xFFF) + 1; 663 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 664 665 /* Alloc msix bitmap for this VF */ 666 err = rvu_alloc_bitmap(&pfvf->msix); 667 if (err) 668 return err; 669 670 pfvf->msix_lfmap = 671 devm_kcalloc(rvu->dev, pfvf->msix.max, 672 sizeof(u16), GFP_KERNEL); 673 if (!pfvf->msix_lfmap) 674 return -ENOMEM; 675 676 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 677 * These are allocated on driver init and never freed, 678 * so no need to set 'msix_lfmap' for these. 679 */ 680 cfg = rvu_read64(rvu, BLKADDR_RVUM, 681 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 682 nvecs = (cfg >> 12) & 0xFF; 683 cfg &= ~0x7FFULL; 684 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 685 rvu_write64(rvu, BLKADDR_RVUM, 686 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 687 cfg | offset); 688 } 689 } 690 691 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 692 * create an IOMMU mapping for the physical address configured by 693 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 694 */ 695 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 696 max_msix = cfg & 0xFFFFF; 697 if (rvu->fwdata && rvu->fwdata->msixtr_base) 698 phy_addr = rvu->fwdata->msixtr_base; 699 else 700 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 701 702 iova = dma_map_resource(rvu->dev, phy_addr, 703 max_msix * PCI_MSIX_ENTRY_SIZE, 704 DMA_BIDIRECTIONAL, 0); 705 706 if (dma_mapping_error(rvu->dev, iova)) 707 return -ENOMEM; 708 709 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 710 rvu->msix_base_iova = iova; 711 rvu->msixtr_base_phy = phy_addr; 712 713 return 0; 714 } 715 716 static void rvu_reset_msix(struct rvu *rvu) 717 { 718 /* Restore msixtr base register */ 719 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 720 rvu->msixtr_base_phy); 721 } 722 723 static void rvu_free_hw_resources(struct rvu *rvu) 724 { 725 struct rvu_hwinfo *hw = rvu->hw; 726 struct rvu_block *block; 727 struct rvu_pfvf *pfvf; 728 int id, max_msix; 729 u64 cfg; 730 731 rvu_npa_freemem(rvu); 732 rvu_npc_freemem(rvu); 733 rvu_nix_freemem(rvu); 734 735 /* Free block LF bitmaps */ 736 for (id = 0; id < BLK_COUNT; id++) { 737 block = &hw->block[id]; 738 kfree(block->lf.bmap); 739 } 740 741 /* Free MSIX bitmaps */ 742 for (id = 0; id < hw->total_pfs; id++) { 743 pfvf = &rvu->pf[id]; 744 kfree(pfvf->msix.bmap); 745 } 746 747 for (id = 0; id < hw->total_vfs; id++) { 748 pfvf = &rvu->hwvf[id]; 749 kfree(pfvf->msix.bmap); 750 } 751 752 /* Unmap MSIX vector base IOVA mapping */ 753 if (!rvu->msix_base_iova) 754 return; 755 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 756 max_msix = cfg & 0xFFFFF; 757 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 758 max_msix * PCI_MSIX_ENTRY_SIZE, 759 DMA_BIDIRECTIONAL, 0); 760 761 rvu_reset_msix(rvu); 762 mutex_destroy(&rvu->rsrc_lock); 763 } 764 765 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 766 { 767 struct rvu_hwinfo *hw = rvu->hw; 768 int pf, vf, numvfs, hwvf; 769 struct rvu_pfvf *pfvf; 770 u64 *mac; 771 772 for (pf = 0; pf < hw->total_pfs; pf++) { 773 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */ 774 if (!pf) 775 goto lbkvf; 776 777 if (!is_pf_cgxmapped(rvu, pf)) 778 continue; 779 /* Assign MAC address to PF */ 780 pfvf = &rvu->pf[pf]; 781 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 782 mac = &rvu->fwdata->pf_macs[pf]; 783 if (*mac) 784 u64_to_ether_addr(*mac, pfvf->mac_addr); 785 else 786 eth_random_addr(pfvf->mac_addr); 787 } else { 788 eth_random_addr(pfvf->mac_addr); 789 } 790 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 791 792 lbkvf: 793 /* Assign MAC address to VFs*/ 794 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 795 for (vf = 0; vf < numvfs; vf++, hwvf++) { 796 pfvf = &rvu->hwvf[hwvf]; 797 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 798 mac = &rvu->fwdata->vf_macs[hwvf]; 799 if (*mac) 800 u64_to_ether_addr(*mac, pfvf->mac_addr); 801 else 802 eth_random_addr(pfvf->mac_addr); 803 } else { 804 eth_random_addr(pfvf->mac_addr); 805 } 806 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 807 } 808 } 809 } 810 811 static int rvu_fwdata_init(struct rvu *rvu) 812 { 813 u64 fwdbase; 814 int err; 815 816 /* Get firmware data base address */ 817 err = cgx_get_fwdata_base(&fwdbase); 818 if (err) 819 goto fail; 820 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 821 if (!rvu->fwdata) 822 goto fail; 823 if (!is_rvu_fwdata_valid(rvu)) { 824 dev_err(rvu->dev, 825 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 826 iounmap(rvu->fwdata); 827 rvu->fwdata = NULL; 828 return -EINVAL; 829 } 830 return 0; 831 fail: 832 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 833 return -EIO; 834 } 835 836 static void rvu_fwdata_exit(struct rvu *rvu) 837 { 838 if (rvu->fwdata) 839 iounmap(rvu->fwdata); 840 } 841 842 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr) 843 { 844 struct rvu_hwinfo *hw = rvu->hw; 845 struct rvu_block *block; 846 int blkid; 847 u64 cfg; 848 849 /* Init NIX LF's bitmap */ 850 block = &hw->block[blkaddr]; 851 if (!block->implemented) 852 return 0; 853 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 854 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 855 block->lf.max = cfg & 0xFFF; 856 block->addr = blkaddr; 857 block->type = BLKTYPE_NIX; 858 block->lfshift = 8; 859 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 860 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); 861 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); 862 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 863 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 864 block->lfreset_reg = NIX_AF_LF_RST; 865 block->rvu = rvu; 866 sprintf(block->name, "NIX%d", blkid); 867 rvu->nix_blkaddr[blkid] = blkaddr; 868 return rvu_alloc_bitmap(&block->lf); 869 } 870 871 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr) 872 { 873 struct rvu_hwinfo *hw = rvu->hw; 874 struct rvu_block *block; 875 int blkid; 876 u64 cfg; 877 878 /* Init CPT LF's bitmap */ 879 block = &hw->block[blkaddr]; 880 if (!block->implemented) 881 return 0; 882 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; 883 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0); 884 block->lf.max = cfg & 0xFF; 885 block->addr = blkaddr; 886 block->type = BLKTYPE_CPT; 887 block->multislot = true; 888 block->lfshift = 3; 889 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 890 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); 891 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); 892 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 893 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 894 block->lfreset_reg = CPT_AF_LF_RST; 895 block->rvu = rvu; 896 sprintf(block->name, "CPT%d", blkid); 897 return rvu_alloc_bitmap(&block->lf); 898 } 899 900 static void rvu_get_lbk_bufsize(struct rvu *rvu) 901 { 902 struct pci_dev *pdev = NULL; 903 void __iomem *base; 904 u64 lbk_const; 905 906 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 907 PCI_DEVID_OCTEONTX2_LBK, pdev); 908 if (!pdev) 909 return; 910 911 base = pci_ioremap_bar(pdev, 0); 912 if (!base) 913 goto err_put; 914 915 lbk_const = readq(base + LBK_CONST); 916 917 /* cache fifo size */ 918 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const); 919 920 iounmap(base); 921 err_put: 922 pci_dev_put(pdev); 923 } 924 925 static int rvu_setup_hw_resources(struct rvu *rvu) 926 { 927 struct rvu_hwinfo *hw = rvu->hw; 928 struct rvu_block *block; 929 int blkid, err; 930 u64 cfg; 931 932 /* Get HW supported max RVU PF & VF count */ 933 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 934 hw->total_pfs = (cfg >> 32) & 0xFF; 935 hw->total_vfs = (cfg >> 20) & 0xFFF; 936 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 937 938 /* Init NPA LF's bitmap */ 939 block = &hw->block[BLKADDR_NPA]; 940 if (!block->implemented) 941 goto nix; 942 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 943 block->lf.max = (cfg >> 16) & 0xFFF; 944 block->addr = BLKADDR_NPA; 945 block->type = BLKTYPE_NPA; 946 block->lfshift = 8; 947 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 948 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 949 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 950 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 951 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 952 block->lfreset_reg = NPA_AF_LF_RST; 953 block->rvu = rvu; 954 sprintf(block->name, "NPA"); 955 err = rvu_alloc_bitmap(&block->lf); 956 if (err) { 957 dev_err(rvu->dev, 958 "%s: Failed to allocate NPA LF bitmap\n", __func__); 959 return err; 960 } 961 962 nix: 963 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0); 964 if (err) { 965 dev_err(rvu->dev, 966 "%s: Failed to allocate NIX0 LFs bitmap\n", __func__); 967 return err; 968 } 969 970 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1); 971 if (err) { 972 dev_err(rvu->dev, 973 "%s: Failed to allocate NIX1 LFs bitmap\n", __func__); 974 return err; 975 } 976 977 /* Init SSO group's bitmap */ 978 block = &hw->block[BLKADDR_SSO]; 979 if (!block->implemented) 980 goto ssow; 981 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 982 block->lf.max = cfg & 0xFFFF; 983 block->addr = BLKADDR_SSO; 984 block->type = BLKTYPE_SSO; 985 block->multislot = true; 986 block->lfshift = 3; 987 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 988 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 989 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 990 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 991 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 992 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 993 block->rvu = rvu; 994 sprintf(block->name, "SSO GROUP"); 995 err = rvu_alloc_bitmap(&block->lf); 996 if (err) { 997 dev_err(rvu->dev, 998 "%s: Failed to allocate SSO LF bitmap\n", __func__); 999 return err; 1000 } 1001 1002 ssow: 1003 /* Init SSO workslot's bitmap */ 1004 block = &hw->block[BLKADDR_SSOW]; 1005 if (!block->implemented) 1006 goto tim; 1007 block->lf.max = (cfg >> 56) & 0xFF; 1008 block->addr = BLKADDR_SSOW; 1009 block->type = BLKTYPE_SSOW; 1010 block->multislot = true; 1011 block->lfshift = 3; 1012 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 1013 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 1014 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 1015 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 1016 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 1017 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 1018 block->rvu = rvu; 1019 sprintf(block->name, "SSOWS"); 1020 err = rvu_alloc_bitmap(&block->lf); 1021 if (err) { 1022 dev_err(rvu->dev, 1023 "%s: Failed to allocate SSOW LF bitmap\n", __func__); 1024 return err; 1025 } 1026 1027 tim: 1028 /* Init TIM LF's bitmap */ 1029 block = &hw->block[BLKADDR_TIM]; 1030 if (!block->implemented) 1031 goto cpt; 1032 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 1033 block->lf.max = cfg & 0xFFFF; 1034 block->addr = BLKADDR_TIM; 1035 block->type = BLKTYPE_TIM; 1036 block->multislot = true; 1037 block->lfshift = 3; 1038 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 1039 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 1040 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 1041 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 1042 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 1043 block->lfreset_reg = TIM_AF_LF_RST; 1044 block->rvu = rvu; 1045 sprintf(block->name, "TIM"); 1046 err = rvu_alloc_bitmap(&block->lf); 1047 if (err) { 1048 dev_err(rvu->dev, 1049 "%s: Failed to allocate TIM LF bitmap\n", __func__); 1050 return err; 1051 } 1052 1053 cpt: 1054 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); 1055 if (err) { 1056 dev_err(rvu->dev, 1057 "%s: Failed to allocate CPT0 LF bitmap\n", __func__); 1058 return err; 1059 } 1060 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1); 1061 if (err) { 1062 dev_err(rvu->dev, 1063 "%s: Failed to allocate CPT1 LF bitmap\n", __func__); 1064 return err; 1065 } 1066 1067 /* Allocate memory for PFVF data */ 1068 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 1069 sizeof(struct rvu_pfvf), GFP_KERNEL); 1070 if (!rvu->pf) { 1071 dev_err(rvu->dev, 1072 "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__); 1073 return -ENOMEM; 1074 } 1075 1076 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 1077 sizeof(struct rvu_pfvf), GFP_KERNEL); 1078 if (!rvu->hwvf) { 1079 dev_err(rvu->dev, 1080 "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__); 1081 return -ENOMEM; 1082 } 1083 1084 mutex_init(&rvu->rsrc_lock); 1085 1086 rvu_fwdata_init(rvu); 1087 1088 err = rvu_setup_msix_resources(rvu); 1089 if (err) { 1090 dev_err(rvu->dev, 1091 "%s: Failed to setup MSIX resources\n", __func__); 1092 return err; 1093 } 1094 1095 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1096 block = &hw->block[blkid]; 1097 if (!block->lf.bmap) 1098 continue; 1099 1100 /* Allocate memory for block LF/slot to pcifunc mapping info */ 1101 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 1102 sizeof(u16), GFP_KERNEL); 1103 if (!block->fn_map) { 1104 err = -ENOMEM; 1105 goto msix_err; 1106 } 1107 1108 /* Scan all blocks to check if low level firmware has 1109 * already provisioned any of the resources to a PF/VF. 1110 */ 1111 rvu_scan_block(rvu, block); 1112 } 1113 1114 err = rvu_set_channels_base(rvu); 1115 if (err) 1116 goto msix_err; 1117 1118 err = rvu_npc_init(rvu); 1119 if (err) { 1120 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__); 1121 goto npc_err; 1122 } 1123 1124 err = rvu_cgx_init(rvu); 1125 if (err) { 1126 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__); 1127 goto cgx_err; 1128 } 1129 1130 err = rvu_npc_exact_init(rvu); 1131 if (err) { 1132 dev_err(rvu->dev, "failed to initialize exact match table\n"); 1133 return err; 1134 } 1135 1136 /* Assign MACs for CGX mapped functions */ 1137 rvu_setup_pfvf_macaddress(rvu); 1138 1139 err = rvu_npa_init(rvu); 1140 if (err) { 1141 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__); 1142 goto npa_err; 1143 } 1144 1145 rvu_get_lbk_bufsize(rvu); 1146 1147 err = rvu_nix_init(rvu); 1148 if (err) { 1149 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__); 1150 goto nix_err; 1151 } 1152 1153 err = rvu_sdp_init(rvu); 1154 if (err) { 1155 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__); 1156 goto nix_err; 1157 } 1158 1159 rvu_program_channels(rvu); 1160 cgx_start_linkup(rvu); 1161 1162 err = rvu_mcs_init(rvu); 1163 if (err) { 1164 dev_err(rvu->dev, "%s: Failed to initialize mcs\n", __func__); 1165 goto nix_err; 1166 } 1167 1168 err = rvu_cpt_init(rvu); 1169 if (err) { 1170 dev_err(rvu->dev, "%s: Failed to initialize cpt\n", __func__); 1171 goto mcs_err; 1172 } 1173 1174 return 0; 1175 1176 mcs_err: 1177 rvu_mcs_exit(rvu); 1178 nix_err: 1179 rvu_nix_freemem(rvu); 1180 npa_err: 1181 rvu_npa_freemem(rvu); 1182 cgx_err: 1183 rvu_cgx_exit(rvu); 1184 npc_err: 1185 rvu_npc_freemem(rvu); 1186 rvu_fwdata_exit(rvu); 1187 msix_err: 1188 rvu_reset_msix(rvu); 1189 return err; 1190 } 1191 1192 /* NPA and NIX admin queue APIs */ 1193 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 1194 { 1195 if (!aq) 1196 return; 1197 1198 qmem_free(rvu->dev, aq->inst); 1199 qmem_free(rvu->dev, aq->res); 1200 devm_kfree(rvu->dev, aq); 1201 } 1202 1203 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 1204 int qsize, int inst_size, int res_size) 1205 { 1206 struct admin_queue *aq; 1207 int err; 1208 1209 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 1210 if (!*ad_queue) 1211 return -ENOMEM; 1212 aq = *ad_queue; 1213 1214 /* Alloc memory for instructions i.e AQ */ 1215 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 1216 if (err) { 1217 devm_kfree(rvu->dev, aq); 1218 return err; 1219 } 1220 1221 /* Alloc memory for results */ 1222 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1223 if (err) { 1224 rvu_aq_free(rvu, aq); 1225 return err; 1226 } 1227 1228 spin_lock_init(&aq->lock); 1229 return 0; 1230 } 1231 1232 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1233 struct ready_msg_rsp *rsp) 1234 { 1235 if (rvu->fwdata) { 1236 rsp->rclk_freq = rvu->fwdata->rclk; 1237 rsp->sclk_freq = rvu->fwdata->sclk; 1238 } 1239 return 0; 1240 } 1241 1242 /* Get current count of a RVU block's LF/slots 1243 * provisioned to a given RVU func. 1244 */ 1245 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr) 1246 { 1247 switch (blkaddr) { 1248 case BLKADDR_NPA: 1249 return pfvf->npalf ? 1 : 0; 1250 case BLKADDR_NIX0: 1251 case BLKADDR_NIX1: 1252 return pfvf->nixlf ? 1 : 0; 1253 case BLKADDR_SSO: 1254 return pfvf->sso; 1255 case BLKADDR_SSOW: 1256 return pfvf->ssow; 1257 case BLKADDR_TIM: 1258 return pfvf->timlfs; 1259 case BLKADDR_CPT0: 1260 return pfvf->cptlfs; 1261 case BLKADDR_CPT1: 1262 return pfvf->cpt1_lfs; 1263 } 1264 return 0; 1265 } 1266 1267 /* Return true if LFs of block type are attached to pcifunc */ 1268 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype) 1269 { 1270 switch (blktype) { 1271 case BLKTYPE_NPA: 1272 return pfvf->npalf ? 1 : 0; 1273 case BLKTYPE_NIX: 1274 return pfvf->nixlf ? 1 : 0; 1275 case BLKTYPE_SSO: 1276 return !!pfvf->sso; 1277 case BLKTYPE_SSOW: 1278 return !!pfvf->ssow; 1279 case BLKTYPE_TIM: 1280 return !!pfvf->timlfs; 1281 case BLKTYPE_CPT: 1282 return pfvf->cptlfs || pfvf->cpt1_lfs; 1283 } 1284 1285 return false; 1286 } 1287 1288 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1289 { 1290 struct rvu_pfvf *pfvf; 1291 1292 if (!is_pf_func_valid(rvu, pcifunc)) 1293 return false; 1294 1295 pfvf = rvu_get_pfvf(rvu, pcifunc); 1296 1297 /* Check if this PFFUNC has a LF of type blktype attached */ 1298 if (!is_blktype_attached(pfvf, blktype)) 1299 return false; 1300 1301 return true; 1302 } 1303 1304 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1305 int pcifunc, int slot) 1306 { 1307 u64 val; 1308 1309 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1310 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1311 /* Wait for the lookup to finish */ 1312 /* TODO: put some timeout here */ 1313 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1314 ; 1315 1316 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1317 1318 /* Check LF valid bit */ 1319 if (!(val & (1ULL << 12))) 1320 return -1; 1321 1322 return (val & 0xFFF); 1323 } 1324 1325 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 1326 u16 global_slot, u16 *slot_in_block) 1327 { 1328 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1329 int numlfs, total_lfs = 0, nr_blocks = 0; 1330 int i, num_blkaddr[BLK_COUNT] = { 0 }; 1331 struct rvu_block *block; 1332 int blkaddr; 1333 u16 start_slot; 1334 1335 if (!is_blktype_attached(pfvf, blktype)) 1336 return -ENODEV; 1337 1338 /* Get all the block addresses from which LFs are attached to 1339 * the given pcifunc in num_blkaddr[]. 1340 */ 1341 for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) { 1342 block = &rvu->hw->block[blkaddr]; 1343 if (block->type != blktype) 1344 continue; 1345 if (!is_block_implemented(rvu->hw, blkaddr)) 1346 continue; 1347 1348 numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr); 1349 if (numlfs) { 1350 total_lfs += numlfs; 1351 num_blkaddr[nr_blocks] = blkaddr; 1352 nr_blocks++; 1353 } 1354 } 1355 1356 if (global_slot >= total_lfs) 1357 return -ENODEV; 1358 1359 /* Based on the given global slot number retrieve the 1360 * correct block address out of all attached block 1361 * addresses and slot number in that block. 1362 */ 1363 total_lfs = 0; 1364 blkaddr = -ENODEV; 1365 for (i = 0; i < nr_blocks; i++) { 1366 numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]); 1367 total_lfs += numlfs; 1368 if (global_slot < total_lfs) { 1369 blkaddr = num_blkaddr[i]; 1370 start_slot = total_lfs - numlfs; 1371 *slot_in_block = global_slot - start_slot; 1372 break; 1373 } 1374 } 1375 1376 return blkaddr; 1377 } 1378 1379 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1380 { 1381 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1382 struct rvu_hwinfo *hw = rvu->hw; 1383 struct rvu_block *block; 1384 int slot, lf, num_lfs; 1385 int blkaddr; 1386 1387 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1388 if (blkaddr < 0) 1389 return; 1390 1391 if (blktype == BLKTYPE_NIX) 1392 rvu_nix_reset_mac(pfvf, pcifunc); 1393 1394 block = &hw->block[blkaddr]; 1395 1396 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1397 if (!num_lfs) 1398 return; 1399 1400 for (slot = 0; slot < num_lfs; slot++) { 1401 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1402 if (lf < 0) /* This should never happen */ 1403 continue; 1404 1405 /* Disable the LF */ 1406 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1407 (lf << block->lfshift), 0x00ULL); 1408 1409 /* Update SW maintained mapping info as well */ 1410 rvu_update_rsrc_map(rvu, pfvf, block, 1411 pcifunc, lf, false); 1412 1413 /* Free the resource */ 1414 rvu_free_rsrc(&block->lf, lf); 1415 1416 /* Clear MSIX vector offset for this LF */ 1417 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1418 } 1419 } 1420 1421 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1422 u16 pcifunc) 1423 { 1424 struct rvu_hwinfo *hw = rvu->hw; 1425 bool detach_all = true; 1426 struct rvu_block *block; 1427 int blkid; 1428 1429 mutex_lock(&rvu->rsrc_lock); 1430 1431 /* Check for partial resource detach */ 1432 if (detach && detach->partial) 1433 detach_all = false; 1434 1435 /* Check for RVU block's LFs attached to this func, 1436 * if so, detach them. 1437 */ 1438 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1439 block = &hw->block[blkid]; 1440 if (!block->lf.bmap) 1441 continue; 1442 if (!detach_all && detach) { 1443 if (blkid == BLKADDR_NPA && !detach->npalf) 1444 continue; 1445 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1446 continue; 1447 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) 1448 continue; 1449 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1450 continue; 1451 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1452 continue; 1453 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1454 continue; 1455 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1456 continue; 1457 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) 1458 continue; 1459 } 1460 rvu_detach_block(rvu, pcifunc, block->type); 1461 } 1462 1463 mutex_unlock(&rvu->rsrc_lock); 1464 return 0; 1465 } 1466 1467 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1468 struct rsrc_detach *detach, 1469 struct msg_rsp *rsp) 1470 { 1471 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1472 } 1473 1474 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 1475 { 1476 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1477 int blkaddr = BLKADDR_NIX0, vf; 1478 struct rvu_pfvf *pf; 1479 1480 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1481 1482 /* All CGX mapped PFs are set with assigned NIX block during init */ 1483 if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 1484 blkaddr = pf->nix_blkaddr; 1485 } else if (is_afvf(pcifunc)) { 1486 vf = pcifunc - 1; 1487 /* Assign NIX based on VF number. All even numbered VFs get 1488 * NIX0 and odd numbered gets NIX1 1489 */ 1490 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0; 1491 /* NIX1 is not present on all silicons */ 1492 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1493 blkaddr = BLKADDR_NIX0; 1494 } 1495 1496 /* if SDP1 then the blkaddr is NIX1 */ 1497 if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1) 1498 blkaddr = BLKADDR_NIX1; 1499 1500 switch (blkaddr) { 1501 case BLKADDR_NIX1: 1502 pfvf->nix_blkaddr = BLKADDR_NIX1; 1503 pfvf->nix_rx_intf = NIX_INTFX_RX(1); 1504 pfvf->nix_tx_intf = NIX_INTFX_TX(1); 1505 break; 1506 case BLKADDR_NIX0: 1507 default: 1508 pfvf->nix_blkaddr = BLKADDR_NIX0; 1509 pfvf->nix_rx_intf = NIX_INTFX_RX(0); 1510 pfvf->nix_tx_intf = NIX_INTFX_TX(0); 1511 break; 1512 } 1513 1514 return pfvf->nix_blkaddr; 1515 } 1516 1517 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype, 1518 u16 pcifunc, struct rsrc_attach *attach) 1519 { 1520 int blkaddr; 1521 1522 switch (blktype) { 1523 case BLKTYPE_NIX: 1524 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc); 1525 break; 1526 case BLKTYPE_CPT: 1527 if (attach->hdr.ver < RVU_MULTI_BLK_VER) 1528 return rvu_get_blkaddr(rvu, blktype, 0); 1529 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : 1530 BLKADDR_CPT0; 1531 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 1532 return -ENODEV; 1533 break; 1534 default: 1535 return rvu_get_blkaddr(rvu, blktype, 0); 1536 } 1537 1538 if (is_block_implemented(rvu->hw, blkaddr)) 1539 return blkaddr; 1540 1541 return -ENODEV; 1542 } 1543 1544 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype, 1545 int num_lfs, struct rsrc_attach *attach) 1546 { 1547 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1548 struct rvu_hwinfo *hw = rvu->hw; 1549 struct rvu_block *block; 1550 int slot, lf; 1551 int blkaddr; 1552 u64 cfg; 1553 1554 if (!num_lfs) 1555 return; 1556 1557 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach); 1558 if (blkaddr < 0) 1559 return; 1560 1561 block = &hw->block[blkaddr]; 1562 if (!block->lf.bmap) 1563 return; 1564 1565 for (slot = 0; slot < num_lfs; slot++) { 1566 /* Allocate the resource */ 1567 lf = rvu_alloc_rsrc(&block->lf); 1568 if (lf < 0) 1569 return; 1570 1571 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1572 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1573 (lf << block->lfshift), cfg); 1574 rvu_update_rsrc_map(rvu, pfvf, block, 1575 pcifunc, lf, true); 1576 1577 /* Set start MSIX vector for this LF within this PF/VF */ 1578 rvu_set_msix_offset(rvu, pfvf, block, lf); 1579 } 1580 } 1581 1582 static int rvu_check_rsrc_availability(struct rvu *rvu, 1583 struct rsrc_attach *req, u16 pcifunc) 1584 { 1585 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1586 int free_lfs, mappedlfs, blkaddr; 1587 struct rvu_hwinfo *hw = rvu->hw; 1588 struct rvu_block *block; 1589 1590 /* Only one NPA LF can be attached */ 1591 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { 1592 block = &hw->block[BLKADDR_NPA]; 1593 free_lfs = rvu_rsrc_free_count(&block->lf); 1594 if (!free_lfs) 1595 goto fail; 1596 } else if (req->npalf) { 1597 dev_err(&rvu->pdev->dev, 1598 "Func 0x%x: Invalid req, already has NPA\n", 1599 pcifunc); 1600 return -EINVAL; 1601 } 1602 1603 /* Only one NIX LF can be attached */ 1604 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { 1605 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX, 1606 pcifunc, req); 1607 if (blkaddr < 0) 1608 return blkaddr; 1609 block = &hw->block[blkaddr]; 1610 free_lfs = rvu_rsrc_free_count(&block->lf); 1611 if (!free_lfs) 1612 goto fail; 1613 } else if (req->nixlf) { 1614 dev_err(&rvu->pdev->dev, 1615 "Func 0x%x: Invalid req, already has NIX\n", 1616 pcifunc); 1617 return -EINVAL; 1618 } 1619 1620 if (req->sso) { 1621 block = &hw->block[BLKADDR_SSO]; 1622 /* Is request within limits ? */ 1623 if (req->sso > block->lf.max) { 1624 dev_err(&rvu->pdev->dev, 1625 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1626 pcifunc, req->sso, block->lf.max); 1627 return -EINVAL; 1628 } 1629 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1630 free_lfs = rvu_rsrc_free_count(&block->lf); 1631 /* Check if additional resources are available */ 1632 if (req->sso > mappedlfs && 1633 ((req->sso - mappedlfs) > free_lfs)) 1634 goto fail; 1635 } 1636 1637 if (req->ssow) { 1638 block = &hw->block[BLKADDR_SSOW]; 1639 if (req->ssow > block->lf.max) { 1640 dev_err(&rvu->pdev->dev, 1641 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1642 pcifunc, req->ssow, block->lf.max); 1643 return -EINVAL; 1644 } 1645 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1646 free_lfs = rvu_rsrc_free_count(&block->lf); 1647 if (req->ssow > mappedlfs && 1648 ((req->ssow - mappedlfs) > free_lfs)) 1649 goto fail; 1650 } 1651 1652 if (req->timlfs) { 1653 block = &hw->block[BLKADDR_TIM]; 1654 if (req->timlfs > block->lf.max) { 1655 dev_err(&rvu->pdev->dev, 1656 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1657 pcifunc, req->timlfs, block->lf.max); 1658 return -EINVAL; 1659 } 1660 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1661 free_lfs = rvu_rsrc_free_count(&block->lf); 1662 if (req->timlfs > mappedlfs && 1663 ((req->timlfs - mappedlfs) > free_lfs)) 1664 goto fail; 1665 } 1666 1667 if (req->cptlfs) { 1668 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT, 1669 pcifunc, req); 1670 if (blkaddr < 0) 1671 return blkaddr; 1672 block = &hw->block[blkaddr]; 1673 if (req->cptlfs > block->lf.max) { 1674 dev_err(&rvu->pdev->dev, 1675 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1676 pcifunc, req->cptlfs, block->lf.max); 1677 return -EINVAL; 1678 } 1679 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1680 free_lfs = rvu_rsrc_free_count(&block->lf); 1681 if (req->cptlfs > mappedlfs && 1682 ((req->cptlfs - mappedlfs) > free_lfs)) 1683 goto fail; 1684 } 1685 1686 return 0; 1687 1688 fail: 1689 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1690 return -ENOSPC; 1691 } 1692 1693 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype, 1694 struct rsrc_attach *attach) 1695 { 1696 int blkaddr, num_lfs; 1697 1698 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, 1699 attach->hdr.pcifunc, attach); 1700 if (blkaddr < 0) 1701 return false; 1702 1703 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), 1704 blkaddr); 1705 /* Requester already has LFs from given block ? */ 1706 return !!num_lfs; 1707 } 1708 1709 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1710 struct rsrc_attach *attach, 1711 struct msg_rsp *rsp) 1712 { 1713 u16 pcifunc = attach->hdr.pcifunc; 1714 int err; 1715 1716 /* If first request, detach all existing attached resources */ 1717 if (!attach->modify) 1718 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1719 1720 mutex_lock(&rvu->rsrc_lock); 1721 1722 /* Check if the request can be accommodated */ 1723 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1724 if (err) 1725 goto exit; 1726 1727 /* Now attach the requested resources */ 1728 if (attach->npalf) 1729 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach); 1730 1731 if (attach->nixlf) 1732 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach); 1733 1734 if (attach->sso) { 1735 /* RVU func doesn't know which exact LF or slot is attached 1736 * to it, it always sees as slot 0,1,2. So for a 'modify' 1737 * request, simply detach all existing attached LFs/slots 1738 * and attach a fresh. 1739 */ 1740 if (attach->modify) 1741 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1742 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, 1743 attach->sso, attach); 1744 } 1745 1746 if (attach->ssow) { 1747 if (attach->modify) 1748 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1749 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, 1750 attach->ssow, attach); 1751 } 1752 1753 if (attach->timlfs) { 1754 if (attach->modify) 1755 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1756 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, 1757 attach->timlfs, attach); 1758 } 1759 1760 if (attach->cptlfs) { 1761 if (attach->modify && 1762 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach)) 1763 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1764 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, 1765 attach->cptlfs, attach); 1766 } 1767 1768 exit: 1769 mutex_unlock(&rvu->rsrc_lock); 1770 return err; 1771 } 1772 1773 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1774 int blkaddr, int lf) 1775 { 1776 u16 vec; 1777 1778 if (lf < 0) 1779 return MSIX_VECTOR_INVALID; 1780 1781 for (vec = 0; vec < pfvf->msix.max; vec++) { 1782 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1783 return vec; 1784 } 1785 return MSIX_VECTOR_INVALID; 1786 } 1787 1788 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1789 struct rvu_block *block, int lf) 1790 { 1791 u16 nvecs, vec, offset; 1792 u64 cfg; 1793 1794 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1795 (lf << block->lfshift)); 1796 nvecs = (cfg >> 12) & 0xFF; 1797 1798 /* Check and alloc MSIX vectors, must be contiguous */ 1799 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1800 return; 1801 1802 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1803 1804 /* Config MSIX offset in LF */ 1805 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1806 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1807 1808 /* Update the bitmap as well */ 1809 for (vec = 0; vec < nvecs; vec++) 1810 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1811 } 1812 1813 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1814 struct rvu_block *block, int lf) 1815 { 1816 u16 nvecs, vec, offset; 1817 u64 cfg; 1818 1819 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1820 (lf << block->lfshift)); 1821 nvecs = (cfg >> 12) & 0xFF; 1822 1823 /* Clear MSIX offset in LF */ 1824 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1825 (lf << block->lfshift), cfg & ~0x7FFULL); 1826 1827 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1828 1829 /* Update the mapping */ 1830 for (vec = 0; vec < nvecs; vec++) 1831 pfvf->msix_lfmap[offset + vec] = 0; 1832 1833 /* Free the same in MSIX bitmap */ 1834 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1835 } 1836 1837 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1838 struct msix_offset_rsp *rsp) 1839 { 1840 struct rvu_hwinfo *hw = rvu->hw; 1841 u16 pcifunc = req->hdr.pcifunc; 1842 struct rvu_pfvf *pfvf; 1843 int lf, slot, blkaddr; 1844 1845 pfvf = rvu_get_pfvf(rvu, pcifunc); 1846 if (!pfvf->msix.bmap) 1847 return 0; 1848 1849 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1850 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1851 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1852 1853 /* Get BLKADDR from which LFs are attached to pcifunc */ 1854 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1855 if (blkaddr < 0) { 1856 rsp->nix_msixoff = MSIX_VECTOR_INVALID; 1857 } else { 1858 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 1859 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); 1860 } 1861 1862 rsp->sso = pfvf->sso; 1863 for (slot = 0; slot < rsp->sso; slot++) { 1864 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1865 rsp->sso_msixoff[slot] = 1866 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1867 } 1868 1869 rsp->ssow = pfvf->ssow; 1870 for (slot = 0; slot < rsp->ssow; slot++) { 1871 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1872 rsp->ssow_msixoff[slot] = 1873 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1874 } 1875 1876 rsp->timlfs = pfvf->timlfs; 1877 for (slot = 0; slot < rsp->timlfs; slot++) { 1878 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1879 rsp->timlf_msixoff[slot] = 1880 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1881 } 1882 1883 rsp->cptlfs = pfvf->cptlfs; 1884 for (slot = 0; slot < rsp->cptlfs; slot++) { 1885 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1886 rsp->cptlf_msixoff[slot] = 1887 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1888 } 1889 1890 rsp->cpt1_lfs = pfvf->cpt1_lfs; 1891 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { 1892 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); 1893 rsp->cpt1_lf_msixoff[slot] = 1894 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf); 1895 } 1896 1897 return 0; 1898 } 1899 1900 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req, 1901 struct free_rsrcs_rsp *rsp) 1902 { 1903 struct rvu_hwinfo *hw = rvu->hw; 1904 struct rvu_block *block; 1905 struct nix_txsch *txsch; 1906 struct nix_hw *nix_hw; 1907 1908 mutex_lock(&rvu->rsrc_lock); 1909 1910 block = &hw->block[BLKADDR_NPA]; 1911 rsp->npa = rvu_rsrc_free_count(&block->lf); 1912 1913 block = &hw->block[BLKADDR_NIX0]; 1914 rsp->nix = rvu_rsrc_free_count(&block->lf); 1915 1916 block = &hw->block[BLKADDR_NIX1]; 1917 rsp->nix1 = rvu_rsrc_free_count(&block->lf); 1918 1919 block = &hw->block[BLKADDR_SSO]; 1920 rsp->sso = rvu_rsrc_free_count(&block->lf); 1921 1922 block = &hw->block[BLKADDR_SSOW]; 1923 rsp->ssow = rvu_rsrc_free_count(&block->lf); 1924 1925 block = &hw->block[BLKADDR_TIM]; 1926 rsp->tim = rvu_rsrc_free_count(&block->lf); 1927 1928 block = &hw->block[BLKADDR_CPT0]; 1929 rsp->cpt = rvu_rsrc_free_count(&block->lf); 1930 1931 block = &hw->block[BLKADDR_CPT1]; 1932 rsp->cpt1 = rvu_rsrc_free_count(&block->lf); 1933 1934 if (rvu->hw->cap.nix_fixed_txschq_mapping) { 1935 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1; 1936 rsp->schq[NIX_TXSCH_LVL_TL4] = 1; 1937 rsp->schq[NIX_TXSCH_LVL_TL3] = 1; 1938 rsp->schq[NIX_TXSCH_LVL_TL2] = 1; 1939 /* NIX1 */ 1940 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1941 goto out; 1942 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1; 1943 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1; 1944 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1; 1945 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1; 1946 } else { 1947 nix_hw = get_nix_hw(hw, BLKADDR_NIX0); 1948 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1949 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1950 rvu_rsrc_free_count(&txsch->schq); 1951 1952 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1953 rsp->schq[NIX_TXSCH_LVL_TL4] = 1954 rvu_rsrc_free_count(&txsch->schq); 1955 1956 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1957 rsp->schq[NIX_TXSCH_LVL_TL3] = 1958 rvu_rsrc_free_count(&txsch->schq); 1959 1960 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1961 rsp->schq[NIX_TXSCH_LVL_TL2] = 1962 rvu_rsrc_free_count(&txsch->schq); 1963 1964 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1965 goto out; 1966 1967 nix_hw = get_nix_hw(hw, BLKADDR_NIX1); 1968 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1969 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1970 rvu_rsrc_free_count(&txsch->schq); 1971 1972 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1973 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1974 rvu_rsrc_free_count(&txsch->schq); 1975 1976 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1977 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1978 rvu_rsrc_free_count(&txsch->schq); 1979 1980 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1981 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1982 rvu_rsrc_free_count(&txsch->schq); 1983 } 1984 1985 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1; 1986 out: 1987 rsp->schq[NIX_TXSCH_LVL_TL1] = 1; 1988 mutex_unlock(&rvu->rsrc_lock); 1989 1990 return 0; 1991 } 1992 1993 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1994 struct msg_rsp *rsp) 1995 { 1996 u16 pcifunc = req->hdr.pcifunc; 1997 u16 vf, numvfs; 1998 u64 cfg; 1999 2000 vf = pcifunc & RVU_PFVF_FUNC_MASK; 2001 cfg = rvu_read64(rvu, BLKADDR_RVUM, 2002 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 2003 numvfs = (cfg >> 12) & 0xFF; 2004 2005 if (vf && vf <= numvfs) 2006 __rvu_flr_handler(rvu, pcifunc); 2007 else 2008 return RVU_INVALID_VF_ID; 2009 2010 return 0; 2011 } 2012 2013 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 2014 struct get_hw_cap_rsp *rsp) 2015 { 2016 struct rvu_hwinfo *hw = rvu->hw; 2017 2018 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 2019 rsp->nix_shaping = hw->cap.nix_shaping; 2020 rsp->npc_hash_extract = hw->cap.npc_hash_extract; 2021 2022 return 0; 2023 } 2024 2025 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req, 2026 struct msg_rsp *rsp) 2027 { 2028 struct rvu_hwinfo *hw = rvu->hw; 2029 u16 pcifunc = req->hdr.pcifunc; 2030 struct rvu_pfvf *pfvf; 2031 int blkaddr, nixlf; 2032 u16 target; 2033 2034 /* Only PF can add VF permissions */ 2035 if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc)) 2036 return -EOPNOTSUPP; 2037 2038 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1); 2039 pfvf = rvu_get_pfvf(rvu, target); 2040 2041 if (req->flags & RESET_VF_PERM) { 2042 pfvf->flags &= RVU_CLEAR_VF_PERM; 2043 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^ 2044 (req->flags & VF_TRUSTED)) { 2045 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags); 2046 /* disable multicast and promisc entries */ 2047 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) { 2048 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target); 2049 if (blkaddr < 0) 2050 return 0; 2051 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 2052 target, 0); 2053 if (nixlf < 0) 2054 return 0; 2055 npc_enadis_default_mce_entry(rvu, target, nixlf, 2056 NIXLF_ALLMULTI_ENTRY, 2057 false); 2058 npc_enadis_default_mce_entry(rvu, target, nixlf, 2059 NIXLF_PROMISC_ENTRY, 2060 false); 2061 } 2062 } 2063 2064 return 0; 2065 } 2066 2067 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 2068 struct mbox_msghdr *req) 2069 { 2070 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 2071 2072 /* Check if valid, if not reply with a invalid msg */ 2073 if (req->sig != OTX2_MBOX_REQ_SIG) 2074 goto bad_message; 2075 2076 switch (req->id) { 2077 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 2078 case _id: { \ 2079 struct _rsp_type *rsp; \ 2080 int err; \ 2081 \ 2082 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 2083 mbox, devid, \ 2084 sizeof(struct _rsp_type)); \ 2085 /* some handlers should complete even if reply */ \ 2086 /* could not be allocated */ \ 2087 if (!rsp && \ 2088 _id != MBOX_MSG_DETACH_RESOURCES && \ 2089 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 2090 _id != MBOX_MSG_VF_FLR) \ 2091 return -ENOMEM; \ 2092 if (rsp) { \ 2093 rsp->hdr.id = _id; \ 2094 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 2095 rsp->hdr.pcifunc = req->pcifunc; \ 2096 rsp->hdr.rc = 0; \ 2097 } \ 2098 \ 2099 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 2100 (struct _req_type *)req, \ 2101 rsp); \ 2102 if (rsp && err) \ 2103 rsp->hdr.rc = err; \ 2104 \ 2105 trace_otx2_msg_process(mbox->pdev, _id, err); \ 2106 return rsp ? err : -ENOMEM; \ 2107 } 2108 MBOX_MESSAGES 2109 #undef M 2110 2111 bad_message: 2112 default: 2113 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 2114 return -ENODEV; 2115 } 2116 } 2117 2118 static void __rvu_mbox_handler(struct rvu_work *mwork, int type, bool poll) 2119 { 2120 struct rvu *rvu = mwork->rvu; 2121 int offset, err, id, devid; 2122 struct otx2_mbox_dev *mdev; 2123 struct mbox_hdr *req_hdr; 2124 struct mbox_msghdr *msg; 2125 struct mbox_wq_info *mw; 2126 struct otx2_mbox *mbox; 2127 2128 switch (type) { 2129 case TYPE_AFPF: 2130 mw = &rvu->afpf_wq_info; 2131 break; 2132 case TYPE_AFVF: 2133 mw = &rvu->afvf_wq_info; 2134 break; 2135 default: 2136 return; 2137 } 2138 2139 devid = mwork - mw->mbox_wrk; 2140 mbox = &mw->mbox; 2141 mdev = &mbox->dev[devid]; 2142 2143 /* Process received mbox messages */ 2144 req_hdr = mdev->mbase + mbox->rx_start; 2145 if (mw->mbox_wrk[devid].num_msgs == 0) 2146 return; 2147 2148 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 2149 2150 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 2151 msg = mdev->mbase + offset; 2152 2153 /* Set which PF/VF sent this message based on mbox IRQ */ 2154 switch (type) { 2155 case TYPE_AFPF: 2156 msg->pcifunc &= 2157 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 2158 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 2159 break; 2160 case TYPE_AFVF: 2161 msg->pcifunc &= 2162 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 2163 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 2164 break; 2165 } 2166 2167 err = rvu_process_mbox_msg(mbox, devid, msg); 2168 if (!err) { 2169 offset = mbox->rx_start + msg->next_msgoff; 2170 continue; 2171 } 2172 2173 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 2174 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 2175 err, otx2_mbox_id2name(msg->id), 2176 msg->id, rvu_get_pf(msg->pcifunc), 2177 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 2178 else 2179 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 2180 err, otx2_mbox_id2name(msg->id), 2181 msg->id, devid); 2182 } 2183 mw->mbox_wrk[devid].num_msgs = 0; 2184 2185 if (poll) 2186 otx2_mbox_wait_for_zero(mbox, devid); 2187 2188 /* Send mbox responses to VF/PF */ 2189 otx2_mbox_msg_send(mbox, devid); 2190 } 2191 2192 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 2193 { 2194 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2195 struct rvu *rvu = mwork->rvu; 2196 2197 mutex_lock(&rvu->mbox_lock); 2198 __rvu_mbox_handler(mwork, TYPE_AFPF, true); 2199 mutex_unlock(&rvu->mbox_lock); 2200 } 2201 2202 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 2203 { 2204 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2205 2206 __rvu_mbox_handler(mwork, TYPE_AFVF, false); 2207 } 2208 2209 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 2210 { 2211 struct rvu *rvu = mwork->rvu; 2212 struct otx2_mbox_dev *mdev; 2213 struct mbox_hdr *rsp_hdr; 2214 struct mbox_msghdr *msg; 2215 struct mbox_wq_info *mw; 2216 struct otx2_mbox *mbox; 2217 int offset, id, devid; 2218 2219 switch (type) { 2220 case TYPE_AFPF: 2221 mw = &rvu->afpf_wq_info; 2222 break; 2223 case TYPE_AFVF: 2224 mw = &rvu->afvf_wq_info; 2225 break; 2226 default: 2227 return; 2228 } 2229 2230 devid = mwork - mw->mbox_wrk_up; 2231 mbox = &mw->mbox_up; 2232 mdev = &mbox->dev[devid]; 2233 2234 rsp_hdr = mdev->mbase + mbox->rx_start; 2235 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 2236 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 2237 return; 2238 } 2239 2240 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 2241 2242 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 2243 msg = mdev->mbase + offset; 2244 2245 if (msg->id >= MBOX_MSG_MAX) { 2246 dev_err(rvu->dev, 2247 "Mbox msg with unknown ID 0x%x\n", msg->id); 2248 goto end; 2249 } 2250 2251 if (msg->sig != OTX2_MBOX_RSP_SIG) { 2252 dev_err(rvu->dev, 2253 "Mbox msg with wrong signature %x, ID 0x%x\n", 2254 msg->sig, msg->id); 2255 goto end; 2256 } 2257 2258 switch (msg->id) { 2259 case MBOX_MSG_CGX_LINK_EVENT: 2260 break; 2261 default: 2262 if (msg->rc) 2263 dev_err(rvu->dev, 2264 "Mbox msg response has err %d, ID 0x%x\n", 2265 msg->rc, msg->id); 2266 break; 2267 } 2268 end: 2269 offset = mbox->rx_start + msg->next_msgoff; 2270 mdev->msgs_acked++; 2271 } 2272 mw->mbox_wrk_up[devid].up_num_msgs = 0; 2273 2274 otx2_mbox_reset(mbox, devid); 2275 } 2276 2277 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 2278 { 2279 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2280 2281 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 2282 } 2283 2284 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 2285 { 2286 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2287 2288 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 2289 } 2290 2291 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr, 2292 int num, int type, unsigned long *pf_bmap) 2293 { 2294 struct rvu_hwinfo *hw = rvu->hw; 2295 int region; 2296 u64 bar4; 2297 2298 /* For cn10k platform VF mailbox regions of a PF follows after the 2299 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from 2300 * RVU_PF_VF_BAR4_ADDR register. 2301 */ 2302 if (type == TYPE_AFVF) { 2303 for (region = 0; region < num; region++) { 2304 if (!test_bit(region, pf_bmap)) 2305 continue; 2306 2307 if (hw->cap.per_pf_mbox_regs) { 2308 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2309 RVU_AF_PFX_BAR4_ADDR(0)) + 2310 MBOX_SIZE; 2311 bar4 += region * MBOX_SIZE; 2312 } else { 2313 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 2314 bar4 += region * MBOX_SIZE; 2315 } 2316 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2317 if (!mbox_addr[region]) 2318 goto error; 2319 } 2320 return 0; 2321 } 2322 2323 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per 2324 * PF registers. Whereas for Octeontx2 it is read from 2325 * RVU_AF_PF_BAR4_ADDR register. 2326 */ 2327 for (region = 0; region < num; region++) { 2328 if (!test_bit(region, pf_bmap)) 2329 continue; 2330 2331 if (hw->cap.per_pf_mbox_regs) { 2332 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2333 RVU_AF_PFX_BAR4_ADDR(region)); 2334 } else { 2335 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2336 RVU_AF_PF_BAR4_ADDR); 2337 bar4 += region * MBOX_SIZE; 2338 } 2339 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2340 if (!mbox_addr[region]) 2341 goto error; 2342 } 2343 return 0; 2344 2345 error: 2346 while (region--) 2347 iounmap((void __iomem *)mbox_addr[region]); 2348 return -ENOMEM; 2349 } 2350 2351 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 2352 int type, int num, 2353 void (mbox_handler)(struct work_struct *), 2354 void (mbox_up_handler)(struct work_struct *)) 2355 { 2356 int err = -EINVAL, i, dir, dir_up; 2357 void __iomem *reg_base; 2358 struct rvu_work *mwork; 2359 unsigned long *pf_bmap; 2360 void **mbox_regions; 2361 const char *name; 2362 u64 cfg; 2363 2364 pf_bmap = bitmap_zalloc(num, GFP_KERNEL); 2365 if (!pf_bmap) 2366 return -ENOMEM; 2367 2368 /* RVU VFs */ 2369 if (type == TYPE_AFVF) 2370 bitmap_set(pf_bmap, 0, num); 2371 2372 if (type == TYPE_AFPF) { 2373 /* Mark enabled PFs in bitmap */ 2374 for (i = 0; i < num; i++) { 2375 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(i)); 2376 if (cfg & BIT_ULL(20)) 2377 set_bit(i, pf_bmap); 2378 } 2379 } 2380 2381 mutex_init(&rvu->mbox_lock); 2382 2383 mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL); 2384 if (!mbox_regions) { 2385 err = -ENOMEM; 2386 goto free_bitmap; 2387 } 2388 2389 switch (type) { 2390 case TYPE_AFPF: 2391 name = "rvu_afpf_mailbox"; 2392 dir = MBOX_DIR_AFPF; 2393 dir_up = MBOX_DIR_AFPF_UP; 2394 reg_base = rvu->afreg_base; 2395 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF, pf_bmap); 2396 if (err) 2397 goto free_regions; 2398 break; 2399 case TYPE_AFVF: 2400 name = "rvu_afvf_mailbox"; 2401 dir = MBOX_DIR_PFVF; 2402 dir_up = MBOX_DIR_PFVF_UP; 2403 reg_base = rvu->pfreg_base; 2404 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF, pf_bmap); 2405 if (err) 2406 goto free_regions; 2407 break; 2408 default: 2409 goto free_regions; 2410 } 2411 2412 mw->mbox_wq = alloc_workqueue(name, 2413 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2414 num); 2415 if (!mw->mbox_wq) { 2416 err = -ENOMEM; 2417 goto unmap_regions; 2418 } 2419 2420 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 2421 sizeof(struct rvu_work), GFP_KERNEL); 2422 if (!mw->mbox_wrk) { 2423 err = -ENOMEM; 2424 goto exit; 2425 } 2426 2427 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 2428 sizeof(struct rvu_work), GFP_KERNEL); 2429 if (!mw->mbox_wrk_up) { 2430 err = -ENOMEM; 2431 goto exit; 2432 } 2433 2434 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, 2435 reg_base, dir, num, pf_bmap); 2436 if (err) 2437 goto exit; 2438 2439 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, 2440 reg_base, dir_up, num, pf_bmap); 2441 if (err) 2442 goto exit; 2443 2444 for (i = 0; i < num; i++) { 2445 if (!test_bit(i, pf_bmap)) 2446 continue; 2447 2448 mwork = &mw->mbox_wrk[i]; 2449 mwork->rvu = rvu; 2450 INIT_WORK(&mwork->work, mbox_handler); 2451 2452 mwork = &mw->mbox_wrk_up[i]; 2453 mwork->rvu = rvu; 2454 INIT_WORK(&mwork->work, mbox_up_handler); 2455 } 2456 goto free_regions; 2457 2458 exit: 2459 destroy_workqueue(mw->mbox_wq); 2460 unmap_regions: 2461 while (num--) 2462 iounmap((void __iomem *)mbox_regions[num]); 2463 free_regions: 2464 kfree(mbox_regions); 2465 free_bitmap: 2466 bitmap_free(pf_bmap); 2467 return err; 2468 } 2469 2470 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 2471 { 2472 struct otx2_mbox *mbox = &mw->mbox; 2473 struct otx2_mbox_dev *mdev; 2474 int devid; 2475 2476 if (mw->mbox_wq) { 2477 destroy_workqueue(mw->mbox_wq); 2478 mw->mbox_wq = NULL; 2479 } 2480 2481 for (devid = 0; devid < mbox->ndevs; devid++) { 2482 mdev = &mbox->dev[devid]; 2483 if (mdev->hwbase) 2484 iounmap((void __iomem *)mdev->hwbase); 2485 } 2486 2487 otx2_mbox_destroy(&mw->mbox); 2488 otx2_mbox_destroy(&mw->mbox_up); 2489 } 2490 2491 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 2492 int mdevs, u64 intr) 2493 { 2494 struct otx2_mbox_dev *mdev; 2495 struct otx2_mbox *mbox; 2496 struct mbox_hdr *hdr; 2497 int i; 2498 2499 for (i = first; i < mdevs; i++) { 2500 /* start from 0 */ 2501 if (!(intr & BIT_ULL(i - first))) 2502 continue; 2503 2504 mbox = &mw->mbox; 2505 mdev = &mbox->dev[i]; 2506 hdr = mdev->mbase + mbox->rx_start; 2507 2508 /*The hdr->num_msgs is set to zero immediately in the interrupt 2509 * handler to ensure that it holds a correct value next time 2510 * when the interrupt handler is called. 2511 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 2512 * pf>mbox.up_num_msgs holds the data for use in 2513 * pfaf_mbox_up_handler. 2514 */ 2515 2516 if (hdr->num_msgs) { 2517 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 2518 hdr->num_msgs = 0; 2519 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 2520 } 2521 mbox = &mw->mbox_up; 2522 mdev = &mbox->dev[i]; 2523 hdr = mdev->mbase + mbox->rx_start; 2524 if (hdr->num_msgs) { 2525 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 2526 hdr->num_msgs = 0; 2527 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 2528 } 2529 } 2530 } 2531 2532 static irqreturn_t rvu_mbox_pf_intr_handler(int irq, void *rvu_irq) 2533 { 2534 struct rvu *rvu = (struct rvu *)rvu_irq; 2535 u64 intr; 2536 2537 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 2538 /* Clear interrupts */ 2539 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 2540 if (intr) 2541 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); 2542 2543 /* Sync with mbox memory region */ 2544 rmb(); 2545 2546 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 2547 2548 return IRQ_HANDLED; 2549 } 2550 2551 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 2552 { 2553 struct rvu *rvu = (struct rvu *)rvu_irq; 2554 int vfs = rvu->vfs; 2555 u64 intr; 2556 2557 /* Sync with mbox memory region */ 2558 rmb(); 2559 2560 /* Handle VF interrupts */ 2561 if (vfs > 64) { 2562 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 2563 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 2564 2565 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 2566 vfs -= 64; 2567 } 2568 2569 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 2570 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 2571 if (intr) 2572 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); 2573 2574 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 2575 2576 return IRQ_HANDLED; 2577 } 2578 2579 static void rvu_enable_mbox_intr(struct rvu *rvu) 2580 { 2581 struct rvu_hwinfo *hw = rvu->hw; 2582 2583 /* Clear spurious irqs, if any */ 2584 rvu_write64(rvu, BLKADDR_RVUM, 2585 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 2586 2587 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 2588 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 2589 INTR_MASK(hw->total_pfs) & ~1ULL); 2590 } 2591 2592 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 2593 { 2594 struct rvu_block *block; 2595 int slot, lf, num_lfs; 2596 int err; 2597 2598 block = &rvu->hw->block[blkaddr]; 2599 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 2600 block->addr); 2601 if (!num_lfs) 2602 return; 2603 for (slot = 0; slot < num_lfs; slot++) { 2604 lf = rvu_get_lf(rvu, block, pcifunc, slot); 2605 if (lf < 0) 2606 continue; 2607 2608 /* Cleanup LF and reset it */ 2609 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) 2610 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 2611 else if (block->addr == BLKADDR_NPA) 2612 rvu_npa_lf_teardown(rvu, pcifunc, lf); 2613 else if ((block->addr == BLKADDR_CPT0) || 2614 (block->addr == BLKADDR_CPT1)) 2615 rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf, 2616 slot); 2617 2618 err = rvu_lf_reset(rvu, block, lf); 2619 if (err) { 2620 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 2621 block->addr, lf); 2622 } 2623 } 2624 } 2625 2626 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 2627 { 2628 if (rvu_npc_exact_has_match_table(rvu)) 2629 rvu_npc_exact_reset(rvu, pcifunc); 2630 2631 mutex_lock(&rvu->flr_lock); 2632 /* Reset order should reflect inter-block dependencies: 2633 * 1. Reset any packet/work sources (NIX, CPT, TIM) 2634 * 2. Flush and reset SSO/SSOW 2635 * 3. Cleanup pools (NPA) 2636 */ 2637 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 2638 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1); 2639 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 2640 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1); 2641 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 2642 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 2643 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 2644 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 2645 rvu_reset_lmt_map_tbl(rvu, pcifunc); 2646 rvu_detach_rsrcs(rvu, NULL, pcifunc); 2647 /* In scenarios where PF/VF drivers detach NIXLF without freeing MCAM 2648 * entries, check and free the MCAM entries explicitly to avoid leak. 2649 * Since LF is detached use LF number as -1. 2650 */ 2651 rvu_npc_free_mcam_entries(rvu, pcifunc, -1); 2652 rvu_mac_reset(rvu, pcifunc); 2653 2654 if (rvu->mcs_blk_cnt) 2655 rvu_mcs_flr_handler(rvu, pcifunc); 2656 2657 mutex_unlock(&rvu->flr_lock); 2658 } 2659 2660 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 2661 { 2662 int reg = 0; 2663 2664 /* pcifunc = 0(PF0) | (vf + 1) */ 2665 __rvu_flr_handler(rvu, vf + 1); 2666 2667 if (vf >= 64) { 2668 reg = 1; 2669 vf = vf - 64; 2670 } 2671 2672 /* Signal FLR finish and enable IRQ */ 2673 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 2674 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 2675 } 2676 2677 static void rvu_flr_handler(struct work_struct *work) 2678 { 2679 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 2680 struct rvu *rvu = flrwork->rvu; 2681 u16 pcifunc, numvfs, vf; 2682 u64 cfg; 2683 int pf; 2684 2685 pf = flrwork - rvu->flr_wrk; 2686 if (pf >= rvu->hw->total_pfs) { 2687 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 2688 return; 2689 } 2690 2691 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2692 numvfs = (cfg >> 12) & 0xFF; 2693 pcifunc = pf << RVU_PFVF_PF_SHIFT; 2694 2695 for (vf = 0; vf < numvfs; vf++) 2696 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2697 2698 __rvu_flr_handler(rvu, pcifunc); 2699 2700 /* Signal FLR finish */ 2701 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2702 2703 /* Enable interrupt */ 2704 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2705 } 2706 2707 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2708 { 2709 int dev, vf, reg = 0; 2710 u64 intr; 2711 2712 if (start_vf >= 64) 2713 reg = 1; 2714 2715 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2716 if (!intr) 2717 return; 2718 2719 for (vf = 0; vf < numvfs; vf++) { 2720 if (!(intr & BIT_ULL(vf))) 2721 continue; 2722 /* Clear and disable the interrupt */ 2723 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2724 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2725 2726 dev = vf + start_vf + rvu->hw->total_pfs; 2727 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2728 } 2729 } 2730 2731 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2732 { 2733 struct rvu *rvu = (struct rvu *)rvu_irq; 2734 u64 intr; 2735 u8 pf; 2736 2737 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2738 if (!intr) 2739 goto afvf_flr; 2740 2741 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2742 if (intr & (1ULL << pf)) { 2743 /* clear interrupt */ 2744 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2745 BIT_ULL(pf)); 2746 /* Disable the interrupt */ 2747 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2748 BIT_ULL(pf)); 2749 /* PF is already dead do only AF related operations */ 2750 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2751 } 2752 } 2753 2754 afvf_flr: 2755 rvu_afvf_queue_flr_work(rvu, 0, 64); 2756 if (rvu->vfs > 64) 2757 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2758 2759 return IRQ_HANDLED; 2760 } 2761 2762 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2763 { 2764 int vf; 2765 2766 /* Nothing to be done here other than clearing the 2767 * TRPEND bit. 2768 */ 2769 for (vf = 0; vf < 64; vf++) { 2770 if (intr & (1ULL << vf)) { 2771 /* clear the trpend due to ME(master enable) */ 2772 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2773 /* clear interrupt */ 2774 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2775 } 2776 } 2777 } 2778 2779 /* Handles ME interrupts from VFs of AF */ 2780 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2781 { 2782 struct rvu *rvu = (struct rvu *)rvu_irq; 2783 int vfset; 2784 u64 intr; 2785 2786 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2787 2788 for (vfset = 0; vfset <= 1; vfset++) { 2789 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2790 if (intr) 2791 rvu_me_handle_vfset(rvu, vfset, intr); 2792 } 2793 2794 return IRQ_HANDLED; 2795 } 2796 2797 /* Handles ME interrupts from PFs */ 2798 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2799 { 2800 struct rvu *rvu = (struct rvu *)rvu_irq; 2801 u64 intr; 2802 u8 pf; 2803 2804 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2805 2806 /* Nothing to be done here other than clearing the 2807 * TRPEND bit. 2808 */ 2809 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2810 if (intr & (1ULL << pf)) { 2811 /* clear the trpend due to ME(master enable) */ 2812 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2813 BIT_ULL(pf)); 2814 /* clear interrupt */ 2815 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2816 BIT_ULL(pf)); 2817 } 2818 } 2819 2820 return IRQ_HANDLED; 2821 } 2822 2823 static void rvu_unregister_interrupts(struct rvu *rvu) 2824 { 2825 int irq; 2826 2827 rvu_cpt_unregister_interrupts(rvu); 2828 2829 /* Disable the Mbox interrupt */ 2830 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2831 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2832 2833 /* Disable the PF FLR interrupt */ 2834 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2835 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2836 2837 /* Disable the PF ME interrupt */ 2838 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2839 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2840 2841 for (irq = 0; irq < rvu->num_vec; irq++) { 2842 if (rvu->irq_allocated[irq]) { 2843 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2844 rvu->irq_allocated[irq] = false; 2845 } 2846 } 2847 2848 pci_free_irq_vectors(rvu->pdev); 2849 rvu->num_vec = 0; 2850 } 2851 2852 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 2853 { 2854 struct rvu_pfvf *pfvf = &rvu->pf[0]; 2855 int offset; 2856 2857 pfvf = &rvu->pf[0]; 2858 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2859 2860 /* Make sure there are enough MSIX vectors configured so that 2861 * VF interrupts can be handled. Offset equal to zero means 2862 * that PF vectors are not configured and overlapping AF vectors. 2863 */ 2864 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2865 offset; 2866 } 2867 2868 static int rvu_register_interrupts(struct rvu *rvu) 2869 { 2870 int ret, offset, pf_vec_start; 2871 2872 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2873 2874 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2875 NAME_SIZE, GFP_KERNEL); 2876 if (!rvu->irq_name) 2877 return -ENOMEM; 2878 2879 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2880 sizeof(bool), GFP_KERNEL); 2881 if (!rvu->irq_allocated) 2882 return -ENOMEM; 2883 2884 /* Enable MSI-X */ 2885 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2886 rvu->num_vec, PCI_IRQ_MSIX); 2887 if (ret < 0) { 2888 dev_err(rvu->dev, 2889 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2890 rvu->num_vec, ret); 2891 return ret; 2892 } 2893 2894 /* Register mailbox interrupt handler */ 2895 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2896 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2897 rvu_mbox_pf_intr_handler, 0, 2898 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2899 if (ret) { 2900 dev_err(rvu->dev, 2901 "RVUAF: IRQ registration failed for mbox irq\n"); 2902 goto fail; 2903 } 2904 2905 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2906 2907 /* Enable mailbox interrupts from all PFs */ 2908 rvu_enable_mbox_intr(rvu); 2909 2910 /* Register FLR interrupt handler */ 2911 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2912 "RVUAF FLR"); 2913 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2914 rvu_flr_intr_handler, 0, 2915 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2916 rvu); 2917 if (ret) { 2918 dev_err(rvu->dev, 2919 "RVUAF: IRQ registration failed for FLR\n"); 2920 goto fail; 2921 } 2922 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 2923 2924 /* Enable FLR interrupt for all PFs*/ 2925 rvu_write64(rvu, BLKADDR_RVUM, 2926 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 2927 2928 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 2929 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2930 2931 /* Register ME interrupt handler */ 2932 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2933 "RVUAF ME"); 2934 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 2935 rvu_me_pf_intr_handler, 0, 2936 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2937 rvu); 2938 if (ret) { 2939 dev_err(rvu->dev, 2940 "RVUAF: IRQ registration failed for ME\n"); 2941 } 2942 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 2943 2944 /* Clear TRPEND bit for all PF */ 2945 rvu_write64(rvu, BLKADDR_RVUM, 2946 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 2947 /* Enable ME interrupt for all PFs*/ 2948 rvu_write64(rvu, BLKADDR_RVUM, 2949 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 2950 2951 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 2952 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2953 2954 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 2955 return 0; 2956 2957 /* Get PF MSIX vectors offset. */ 2958 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 2959 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2960 2961 /* Register MBOX0 interrupt. */ 2962 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 2963 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 2964 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2965 rvu_mbox_intr_handler, 0, 2966 &rvu->irq_name[offset * NAME_SIZE], 2967 rvu); 2968 if (ret) 2969 dev_err(rvu->dev, 2970 "RVUAF: IRQ registration failed for Mbox0\n"); 2971 2972 rvu->irq_allocated[offset] = true; 2973 2974 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 2975 * simply increment current offset by 1. 2976 */ 2977 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 2978 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 2979 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2980 rvu_mbox_intr_handler, 0, 2981 &rvu->irq_name[offset * NAME_SIZE], 2982 rvu); 2983 if (ret) 2984 dev_err(rvu->dev, 2985 "RVUAF: IRQ registration failed for Mbox1\n"); 2986 2987 rvu->irq_allocated[offset] = true; 2988 2989 /* Register FLR interrupt handler for AF's VFs */ 2990 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 2991 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 2992 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2993 rvu_flr_intr_handler, 0, 2994 &rvu->irq_name[offset * NAME_SIZE], rvu); 2995 if (ret) { 2996 dev_err(rvu->dev, 2997 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 2998 goto fail; 2999 } 3000 rvu->irq_allocated[offset] = true; 3001 3002 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 3003 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 3004 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3005 rvu_flr_intr_handler, 0, 3006 &rvu->irq_name[offset * NAME_SIZE], rvu); 3007 if (ret) { 3008 dev_err(rvu->dev, 3009 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 3010 goto fail; 3011 } 3012 rvu->irq_allocated[offset] = true; 3013 3014 /* Register ME interrupt handler for AF's VFs */ 3015 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 3016 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 3017 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3018 rvu_me_vf_intr_handler, 0, 3019 &rvu->irq_name[offset * NAME_SIZE], rvu); 3020 if (ret) { 3021 dev_err(rvu->dev, 3022 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 3023 goto fail; 3024 } 3025 rvu->irq_allocated[offset] = true; 3026 3027 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 3028 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 3029 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 3030 rvu_me_vf_intr_handler, 0, 3031 &rvu->irq_name[offset * NAME_SIZE], rvu); 3032 if (ret) { 3033 dev_err(rvu->dev, 3034 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 3035 goto fail; 3036 } 3037 rvu->irq_allocated[offset] = true; 3038 3039 ret = rvu_cpt_register_interrupts(rvu); 3040 if (ret) 3041 goto fail; 3042 3043 return 0; 3044 3045 fail: 3046 rvu_unregister_interrupts(rvu); 3047 return ret; 3048 } 3049 3050 static void rvu_flr_wq_destroy(struct rvu *rvu) 3051 { 3052 if (rvu->flr_wq) { 3053 destroy_workqueue(rvu->flr_wq); 3054 rvu->flr_wq = NULL; 3055 } 3056 } 3057 3058 static int rvu_flr_init(struct rvu *rvu) 3059 { 3060 int dev, num_devs; 3061 u64 cfg; 3062 int pf; 3063 3064 /* Enable FLR for all PFs*/ 3065 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 3066 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 3067 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 3068 cfg | BIT_ULL(22)); 3069 } 3070 3071 rvu->flr_wq = alloc_ordered_workqueue("rvu_afpf_flr", 3072 WQ_HIGHPRI | WQ_MEM_RECLAIM); 3073 if (!rvu->flr_wq) 3074 return -ENOMEM; 3075 3076 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 3077 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 3078 sizeof(struct rvu_work), GFP_KERNEL); 3079 if (!rvu->flr_wrk) { 3080 destroy_workqueue(rvu->flr_wq); 3081 return -ENOMEM; 3082 } 3083 3084 for (dev = 0; dev < num_devs; dev++) { 3085 rvu->flr_wrk[dev].rvu = rvu; 3086 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 3087 } 3088 3089 mutex_init(&rvu->flr_lock); 3090 3091 return 0; 3092 } 3093 3094 static void rvu_disable_afvf_intr(struct rvu *rvu) 3095 { 3096 int vfs = rvu->vfs; 3097 3098 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3099 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3100 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3101 if (vfs <= 64) 3102 return; 3103 3104 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 3105 INTR_MASK(vfs - 64)); 3106 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3107 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3108 } 3109 3110 static void rvu_enable_afvf_intr(struct rvu *rvu) 3111 { 3112 int vfs = rvu->vfs; 3113 3114 /* Clear any pending interrupts and enable AF VF interrupts for 3115 * the first 64 VFs. 3116 */ 3117 /* Mbox */ 3118 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 3119 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3120 3121 /* FLR */ 3122 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 3123 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3124 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3125 3126 /* Same for remaining VFs, if any. */ 3127 if (vfs <= 64) 3128 return; 3129 3130 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 3131 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 3132 INTR_MASK(vfs - 64)); 3133 3134 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 3135 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3136 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3137 } 3138 3139 int rvu_get_num_lbk_chans(void) 3140 { 3141 struct pci_dev *pdev; 3142 void __iomem *base; 3143 int ret = -EIO; 3144 3145 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 3146 NULL); 3147 if (!pdev) 3148 goto err; 3149 3150 base = pci_ioremap_bar(pdev, 0); 3151 if (!base) 3152 goto err_put; 3153 3154 /* Read number of available LBK channels from LBK(0)_CONST register. */ 3155 ret = (readq(base + 0x10) >> 32) & 0xffff; 3156 iounmap(base); 3157 err_put: 3158 pci_dev_put(pdev); 3159 err: 3160 return ret; 3161 } 3162 3163 static int rvu_enable_sriov(struct rvu *rvu) 3164 { 3165 struct pci_dev *pdev = rvu->pdev; 3166 int err, chans, vfs; 3167 3168 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 3169 dev_warn(&pdev->dev, 3170 "Skipping SRIOV enablement since not enough IRQs are available\n"); 3171 return 0; 3172 } 3173 3174 chans = rvu_get_num_lbk_chans(); 3175 if (chans < 0) 3176 return chans; 3177 3178 vfs = pci_sriov_get_totalvfs(pdev); 3179 3180 /* Limit VFs in case we have more VFs than LBK channels available. */ 3181 if (vfs > chans) 3182 vfs = chans; 3183 3184 if (!vfs) 3185 return 0; 3186 3187 /* LBK channel number 63 is used for switching packets between 3188 * CGX mapped VFs. Hence limit LBK pairs till 62 only. 3189 */ 3190 if (vfs > 62) 3191 vfs = 62; 3192 3193 /* Save VFs number for reference in VF interrupts handlers. 3194 * Since interrupts might start arriving during SRIOV enablement 3195 * ordinary API cannot be used to get number of enabled VFs. 3196 */ 3197 rvu->vfs = vfs; 3198 3199 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 3200 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 3201 if (err) 3202 return err; 3203 3204 rvu_enable_afvf_intr(rvu); 3205 /* Make sure IRQs are enabled before SRIOV. */ 3206 mb(); 3207 3208 err = pci_enable_sriov(pdev, vfs); 3209 if (err) { 3210 rvu_disable_afvf_intr(rvu); 3211 rvu_mbox_destroy(&rvu->afvf_wq_info); 3212 return err; 3213 } 3214 3215 return 0; 3216 } 3217 3218 static void rvu_disable_sriov(struct rvu *rvu) 3219 { 3220 rvu_disable_afvf_intr(rvu); 3221 rvu_mbox_destroy(&rvu->afvf_wq_info); 3222 pci_disable_sriov(rvu->pdev); 3223 } 3224 3225 static void rvu_update_module_params(struct rvu *rvu) 3226 { 3227 const char *default_pfl_name = "default"; 3228 3229 strscpy(rvu->mkex_pfl_name, 3230 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 3231 strscpy(rvu->kpu_pfl_name, 3232 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN); 3233 } 3234 3235 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3236 { 3237 struct device *dev = &pdev->dev; 3238 struct rvu *rvu; 3239 int err; 3240 3241 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 3242 if (!rvu) 3243 return -ENOMEM; 3244 3245 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 3246 if (!rvu->hw) { 3247 devm_kfree(dev, rvu); 3248 return -ENOMEM; 3249 } 3250 3251 pci_set_drvdata(pdev, rvu); 3252 rvu->pdev = pdev; 3253 rvu->dev = &pdev->dev; 3254 3255 err = pci_enable_device(pdev); 3256 if (err) { 3257 dev_err(dev, "Failed to enable PCI device\n"); 3258 goto err_freemem; 3259 } 3260 3261 err = pci_request_regions(pdev, DRV_NAME); 3262 if (err) { 3263 dev_err(dev, "PCI request regions failed 0x%x\n", err); 3264 goto err_disable_device; 3265 } 3266 3267 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3268 if (err) { 3269 dev_err(dev, "DMA mask config failed, abort\n"); 3270 goto err_release_regions; 3271 } 3272 3273 pci_set_master(pdev); 3274 3275 rvu->ptp = ptp_get(); 3276 if (IS_ERR(rvu->ptp)) { 3277 err = PTR_ERR(rvu->ptp); 3278 if (err) 3279 goto err_release_regions; 3280 rvu->ptp = NULL; 3281 } 3282 3283 /* Map Admin function CSRs */ 3284 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 3285 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 3286 if (!rvu->afreg_base || !rvu->pfreg_base) { 3287 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 3288 err = -ENOMEM; 3289 goto err_put_ptp; 3290 } 3291 3292 /* Store module params in rvu structure */ 3293 rvu_update_module_params(rvu); 3294 3295 /* Check which blocks the HW supports */ 3296 rvu_check_block_implemented(rvu); 3297 3298 rvu_reset_all_blocks(rvu); 3299 3300 rvu_setup_hw_capabilities(rvu); 3301 3302 err = rvu_setup_hw_resources(rvu); 3303 if (err) 3304 goto err_put_ptp; 3305 3306 /* Init mailbox btw AF and PFs */ 3307 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 3308 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 3309 rvu_afpf_mbox_up_handler); 3310 if (err) { 3311 dev_err(dev, "%s: Failed to initialize mbox\n", __func__); 3312 goto err_hwsetup; 3313 } 3314 3315 err = rvu_flr_init(rvu); 3316 if (err) { 3317 dev_err(dev, "%s: Failed to initialize flr\n", __func__); 3318 goto err_mbox; 3319 } 3320 3321 err = rvu_register_interrupts(rvu); 3322 if (err) { 3323 dev_err(dev, "%s: Failed to register interrupts\n", __func__); 3324 goto err_flr; 3325 } 3326 3327 err = rvu_register_dl(rvu); 3328 if (err) { 3329 dev_err(dev, "%s: Failed to register devlink\n", __func__); 3330 goto err_irq; 3331 } 3332 3333 rvu_setup_rvum_blk_revid(rvu); 3334 3335 /* Enable AF's VFs (if any) */ 3336 err = rvu_enable_sriov(rvu); 3337 if (err) { 3338 dev_err(dev, "%s: Failed to enable sriov\n", __func__); 3339 goto err_dl; 3340 } 3341 3342 /* Initialize debugfs */ 3343 rvu_dbg_init(rvu); 3344 3345 mutex_init(&rvu->rswitch.switch_lock); 3346 3347 if (rvu->fwdata) 3348 ptp_start(rvu, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate, 3349 rvu->fwdata->ptp_ext_tstamp); 3350 3351 return 0; 3352 err_dl: 3353 rvu_unregister_dl(rvu); 3354 err_irq: 3355 rvu_unregister_interrupts(rvu); 3356 err_flr: 3357 rvu_flr_wq_destroy(rvu); 3358 err_mbox: 3359 rvu_mbox_destroy(&rvu->afpf_wq_info); 3360 err_hwsetup: 3361 rvu_cgx_exit(rvu); 3362 rvu_fwdata_exit(rvu); 3363 rvu_mcs_exit(rvu); 3364 rvu_reset_all_blocks(rvu); 3365 rvu_free_hw_resources(rvu); 3366 rvu_clear_rvum_blk_revid(rvu); 3367 err_put_ptp: 3368 ptp_put(rvu->ptp); 3369 err_release_regions: 3370 pci_release_regions(pdev); 3371 err_disable_device: 3372 pci_disable_device(pdev); 3373 err_freemem: 3374 pci_set_drvdata(pdev, NULL); 3375 devm_kfree(&pdev->dev, rvu->hw); 3376 devm_kfree(dev, rvu); 3377 return err; 3378 } 3379 3380 static void rvu_remove(struct pci_dev *pdev) 3381 { 3382 struct rvu *rvu = pci_get_drvdata(pdev); 3383 3384 rvu_dbg_exit(rvu); 3385 rvu_unregister_dl(rvu); 3386 rvu_unregister_interrupts(rvu); 3387 rvu_flr_wq_destroy(rvu); 3388 rvu_cgx_exit(rvu); 3389 rvu_fwdata_exit(rvu); 3390 rvu_mcs_exit(rvu); 3391 rvu_mbox_destroy(&rvu->afpf_wq_info); 3392 rvu_disable_sriov(rvu); 3393 rvu_reset_all_blocks(rvu); 3394 rvu_free_hw_resources(rvu); 3395 rvu_clear_rvum_blk_revid(rvu); 3396 ptp_put(rvu->ptp); 3397 pci_release_regions(pdev); 3398 pci_disable_device(pdev); 3399 pci_set_drvdata(pdev, NULL); 3400 3401 devm_kfree(&pdev->dev, rvu->hw); 3402 devm_kfree(&pdev->dev, rvu); 3403 } 3404 3405 static struct pci_driver rvu_driver = { 3406 .name = DRV_NAME, 3407 .id_table = rvu_id_table, 3408 .probe = rvu_probe, 3409 .remove = rvu_remove, 3410 }; 3411 3412 static int __init rvu_init_module(void) 3413 { 3414 int err; 3415 3416 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3417 3418 err = pci_register_driver(&cgx_driver); 3419 if (err < 0) 3420 return err; 3421 3422 err = pci_register_driver(&ptp_driver); 3423 if (err < 0) 3424 goto ptp_err; 3425 3426 err = pci_register_driver(&mcs_driver); 3427 if (err < 0) 3428 goto mcs_err; 3429 3430 err = pci_register_driver(&rvu_driver); 3431 if (err < 0) 3432 goto rvu_err; 3433 3434 return 0; 3435 rvu_err: 3436 pci_unregister_driver(&mcs_driver); 3437 mcs_err: 3438 pci_unregister_driver(&ptp_driver); 3439 ptp_err: 3440 pci_unregister_driver(&cgx_driver); 3441 3442 return err; 3443 } 3444 3445 static void __exit rvu_cleanup_module(void) 3446 { 3447 pci_unregister_driver(&rvu_driver); 3448 pci_unregister_driver(&mcs_driver); 3449 pci_unregister_driver(&ptp_driver); 3450 pci_unregister_driver(&cgx_driver); 3451 } 3452 3453 module_init(rvu_init_module); 3454 module_exit(rvu_cleanup_module); 3455